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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DTS file for AMD Seattle XGBE (RevB)
4 *
5 * Copyright (C) 2015 Advanced Micro Devices, Inc.
6 */
7
8 xgmacclk0_dma_250mhz: clk250mhz_0 {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <250000000>;
12 clock-output-names = "xgmacclk0_dma_250mhz";
13 };
14
15 xgmacclk0_ptp_250mhz: clk250mhz_1 {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <250000000>;
19 clock-output-names = "xgmacclk0_ptp_250mhz";
20 };
21
22 xgmacclk1_dma_250mhz: clk250mhz_2 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <250000000>;
26 clock-output-names = "xgmacclk1_dma_250mhz";
27 };
28
29 xgmacclk1_ptp_250mhz: clk250mhz_3 {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <250000000>;
33 clock-output-names = "xgmacclk1_ptp_250mhz";
34 };
35
36 xgmac0: xgmac@e0700000 {
37 compatible = "amd,xgbe-seattle-v1a";
38 reg = <0 0xe0700000 0 0x80000>,
39 <0 0xe0780000 0 0x80000>,
40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
43 interrupts = <0 325 4>,
44 <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>,
45 <0 323 4>;
46 amd,per-channel-interrupt;
47 amd,speed-set = <0>;
48 amd,serdes-blwc = <1>, <1>, <0>;
49 amd,serdes-cdr-rate = <2>, <2>, <7>;
50 amd,serdes-pq-skew = <10>, <10>, <18>;
51 amd,serdes-tx-amp = <0>, <0>, <0>;
52 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
53 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
54 mac-address = [ 02 A1 A2 A3 A4 A5 ];
55 clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
56 clock-names = "dma_clk", "ptp_clk";
57 phy-mode = "xgmii";
58 #stream-id-cells = <16>;
59 dma-coherent;
60 };
61
62 xgmac1: xgmac@e0900000 {
63 compatible = "amd,xgbe-seattle-v1a";
64 reg = <0 0xe0900000 0 0x80000>,
65 <0 0xe0980000 0 0x80000>,
66 <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
67 <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */
68 <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */
69 interrupts = <0 324 4>,
70 <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>,
71 <0 322 4>;
72 amd,per-channel-interrupt;
73 amd,speed-set = <0>;
74 amd,serdes-blwc = <1>, <1>, <0>;
75 amd,serdes-cdr-rate = <2>, <2>, <7>;
76 amd,serdes-pq-skew = <10>, <10>, <18>;
77 amd,serdes-tx-amp = <0>, <0>, <0>;
78 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
79 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
80 mac-address = [ 02 B1 B2 B3 B4 B5 ];
81 clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
82 clock-names = "dma_clk", "ptp_clk";
83 phy-mode = "xgmii";
84 #stream-id-cells = <16>;
85 dma-coherent;
86 };
87
88 xgmac0_smmu: smmu@e0600000 {
89 compatible = "arm,mmu-401";
90 reg = <0 0xe0600000 0 0x10000>;
91 #global-interrupts = <1>;
92 interrupts = /* Uses combined intr for both
93 * global and context
94 */
95 <0 336 4>,
96 <0 336 4>;
97
98 mmu-masters = <&xgmac0
99 0 1 2 3 4 5 6 7
100 16 17 18 19 20 21 22 23
101 >;
102 };
103
104 xgmac1_smmu: smmu@e0800000 {
105 compatible = "arm,mmu-401";
106 reg = <0 0xe0800000 0 0x10000>;
107 #global-interrupts = <1>;
108 interrupts = /* Uses combined intr for both
109 * global and context
110 */
111 <0 335 4>,
112 <0 335 4>;
113
114 mmu-masters = <&xgmac1
115 0 1 2 3 4 5 6 7
116 16 17 18 19 20 21 22 23
117 >;
118 };
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * DTS file for AMD Seattle XGBE (RevB)
4 *
5 * Copyright (C) 2015 Advanced Micro Devices, Inc.
6 */
7
8 xgmacclk0_dma_250mhz: clk250mhz_0 {
9 compatible = "fixed-clock";
10 #clock-cells = <0>;
11 clock-frequency = <250000000>;
12 clock-output-names = "xgmacclk0_dma_250mhz";
13 };
14
15 xgmacclk0_ptp_250mhz: clk250mhz_1 {
16 compatible = "fixed-clock";
17 #clock-cells = <0>;
18 clock-frequency = <250000000>;
19 clock-output-names = "xgmacclk0_ptp_250mhz";
20 };
21
22 xgmacclk1_dma_250mhz: clk250mhz_2 {
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <250000000>;
26 clock-output-names = "xgmacclk1_dma_250mhz";
27 };
28
29 xgmacclk1_ptp_250mhz: clk250mhz_3 {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <250000000>;
33 clock-output-names = "xgmacclk1_ptp_250mhz";
34 };
35
36 xgmac0: xgmac@e0700000 {
37 compatible = "amd,xgbe-seattle-v1a";
38 reg = <0 0xe0700000 0 0x80000>,
39 <0 0xe0780000 0 0x80000>,
40 <0 0xe1240800 0 0x00400>, /* SERDES RX/TX0 */
41 <0 0xe1250000 0 0x00060>, /* SERDES IR 1/2 */
42 <0 0xe12500f8 0 0x00004>; /* SERDES IR 2/2 */
43 interrupts = <0 325 4>,
44 <0 346 1>, <0 347 1>, <0 348 1>, <0 349 1>,
45 <0 323 4>;
46 amd,per-channel-interrupt;
47 amd,speed-set = <0>;
48 amd,serdes-blwc = <1>, <1>, <0>;
49 amd,serdes-cdr-rate = <2>, <2>, <7>;
50 amd,serdes-pq-skew = <10>, <10>, <18>;
51 amd,serdes-tx-amp = <0>, <0>, <0>;
52 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
53 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
54 mac-address = [ 02 A1 A2 A3 A4 A5 ];
55 clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
56 clock-names = "dma_clk", "ptp_clk";
57 phy-mode = "xgmii";
58 iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
59 dma-coherent;
60 };
61
62 xgmac1: xgmac@e0900000 {
63 compatible = "amd,xgbe-seattle-v1a";
64 reg = <0 0xe0900000 0 0x80000>,
65 <0 0xe0980000 0 0x80000>,
66 <0 0xe1240c00 0 0x00400>, /* SERDES RX/TX1 */
67 <0 0xe1250080 0 0x00060>, /* SERDES IR 1/2 */
68 <0 0xe12500fc 0 0x00004>; /* SERDES IR 2/2 */
69 interrupts = <0 324 4>,
70 <0 341 1>, <0 342 1>, <0 343 1>, <0 344 1>,
71 <0 322 4>;
72 amd,per-channel-interrupt;
73 amd,speed-set = <0>;
74 amd,serdes-blwc = <1>, <1>, <0>;
75 amd,serdes-cdr-rate = <2>, <2>, <7>;
76 amd,serdes-pq-skew = <10>, <10>, <18>;
77 amd,serdes-tx-amp = <0>, <0>, <0>;
78 amd,serdes-dfe-tap-config = <3>, <3>, <3>;
79 amd,serdes-dfe-tap-enable = <0>, <0>, <7>;
80 mac-address = [ 02 B1 B2 B3 B4 B5 ];
81 clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
82 clock-names = "dma_clk", "ptp_clk";
83 phy-mode = "xgmii";
84 iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
85 dma-coherent;
86 };
87
88 xgmac0_smmu: iommu@e0600000 {
89 compatible = "arm,mmu-401";
90 reg = <0 0xe0600000 0 0x10000>;
91 #global-interrupts = <1>;
92 interrupts = /* Uses combined intr for both
93 * global and context
94 */
95 <0 336 4>,
96 <0 336 4>;
97 #iommu-cells = <2>;
98 dma-coherent;
99 };
100
101 xgmac1_smmu: iommu@e0800000 {
102 compatible = "arm,mmu-401";
103 reg = <0 0xe0800000 0 0x10000>;
104 #global-interrupts = <1>;
105 interrupts = /* Uses combined intr for both
106 * global and context
107 */
108 <0 335 4>,
109 <0 335 4>;
110 #iommu-cells = <2>;
111 dma-coherent;
112 };