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1/*
2 * Copyright 2016-2018 Toradex AG
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * version 2 as published by the Free Software Foundation.
12 *
13 * This file is distributed in the hope that it will be useful
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * Or, alternatively
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include "tegra124.dtsi"
43#include "tegra124-apalis-emc.dtsi"
44
45/*
46 * Toradex Apalis TK1 Module Device Tree
47 * Compatible for Revisions 2GB: V1.0A, V1.0B, V1.1A
48 */
49/ {
50 model = "Toradex Apalis TK1";
51 compatible = "toradex,apalis-tk1", "nvidia,tegra124";
52
53 memory {
54 reg = <0x0 0x80000000 0x0 0x80000000>;
55 };
56
57 pcie@1003000 {
58 status = "okay";
59 avddio-pex-supply = <&vdd_1v05>;
60 avdd-pex-pll-supply = <&vdd_1v05>;
61 avdd-pll-erefe-supply = <&avdd_1v05>;
62 dvddio-pex-supply = <&vdd_1v05>;
63 hvdd-pex-pll-e-supply = <®_3v3>;
64 hvdd-pex-supply = <®_3v3>;
65 vddio-pex-ctl-supply = <®_3v3>;
66
67 /* Apalis PCIe (additional lane Apalis type specific) */
68 pci@1,0 {
69 /* PCIE1_RX/TX and TS_DIFF1/2 */
70 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-4}>,
71 <&{/padctl@7009f000/pads/pcie/lanes/pcie-3}>;
72 phy-names = "pcie-0", "pcie-1";
73 };
74
75 /* I210 Gigabit Ethernet Controller (On-module) */
76 pci@2,0 {
77 phys = <&{/padctl@7009f000/pads/pcie/lanes/pcie-2}>;
78 phy-names = "pcie-0";
79 status = "okay";
80 };
81 };
82
83 host1x@50000000 {
84 hdmi@54280000 {
85 pll-supply = <®_1v05_avdd_hdmi_pll>;
86 vdd-supply = <®_3v3_avdd_hdmi>;
87 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
88 nvidia,hpd-gpio =
89 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
90 };
91 };
92
93 gpu@0,57000000 {
94 /*
95 * Node left disabled on purpose - the bootloader will enable
96 * it after having set the VPR up
97 */
98 vdd-supply = <&vdd_gpu>;
99 };
100
101 pinmux: pinmux@70000868 {
102 pinctrl-names = "default";
103 pinctrl-0 = <&state_default>;
104
105 state_default: pinmux {
106 /* Analogue Audio (On-module) */
107 dap3_fs_pp0 {
108 nvidia,pins = "dap3_fs_pp0";
109 nvidia,function = "i2s2";
110 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
111 nvidia,tristate = <TEGRA_PIN_DISABLE>;
112 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
113 };
114 dap3_din_pp1 {
115 nvidia,pins = "dap3_din_pp1";
116 nvidia,function = "i2s2";
117 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
118 nvidia,tristate = <TEGRA_PIN_ENABLE>;
119 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
120 };
121 dap3_dout_pp2 {
122 nvidia,pins = "dap3_dout_pp2";
123 nvidia,function = "i2s2";
124 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
125 nvidia,tristate = <TEGRA_PIN_DISABLE>;
126 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
127 };
128 dap3_sclk_pp3 {
129 nvidia,pins = "dap3_sclk_pp3";
130 nvidia,function = "i2s2";
131 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
132 nvidia,tristate = <TEGRA_PIN_DISABLE>;
133 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
134 };
135 dap_mclk1_pw4 {
136 nvidia,pins = "dap_mclk1_pw4";
137 nvidia,function = "extperiph1";
138 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
139 nvidia,tristate = <TEGRA_PIN_DISABLE>;
140 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
141 };
142
143 /* Apalis BKL1_ON */
144 pbb5 {
145 nvidia,pins = "pbb5";
146 nvidia,function = "vgp5";
147 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
148 nvidia,tristate = <TEGRA_PIN_DISABLE>;
149 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
150 };
151
152 /* Apalis BKL1_PWM */
153 pu6 {
154 nvidia,pins = "pu6";
155 nvidia,function = "pwm3";
156 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
157 nvidia,tristate = <TEGRA_PIN_DISABLE>;
158 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
159 };
160
161 /* Apalis CAM1_MCLK */
162 cam_mclk_pcc0 {
163 nvidia,pins = "cam_mclk_pcc0";
164 nvidia,function = "vi_alt3";
165 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
166 nvidia,tristate = <TEGRA_PIN_DISABLE>;
167 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
168 };
169
170 /* Apalis Digital Audio */
171 dap2_fs_pa2 {
172 nvidia,pins = "dap2_fs_pa2";
173 nvidia,function = "hda";
174 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
175 nvidia,tristate = <TEGRA_PIN_DISABLE>;
176 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
177 };
178 dap2_sclk_pa3 {
179 nvidia,pins = "dap2_sclk_pa3";
180 nvidia,function = "hda";
181 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
182 nvidia,tristate = <TEGRA_PIN_DISABLE>;
183 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
184 };
185 dap2_din_pa4 {
186 nvidia,pins = "dap2_din_pa4";
187 nvidia,function = "hda";
188 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
189 nvidia,tristate = <TEGRA_PIN_ENABLE>;
190 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
191 };
192 dap2_dout_pa5 {
193 nvidia,pins = "dap2_dout_pa5";
194 nvidia,function = "hda";
195 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
196 nvidia,tristate = <TEGRA_PIN_DISABLE>;
197 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
198 };
199 pbb3 { /* DAP1_RESET */
200 nvidia,pins = "pbb3";
201 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <TEGRA_PIN_DISABLE>;
203 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
204 };
205 clk3_out_pee0 {
206 nvidia,pins = "clk3_out_pee0";
207 nvidia,function = "extperiph3";
208 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
209 nvidia,tristate = <TEGRA_PIN_DISABLE>;
210 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
211 };
212
213 /* Apalis GPIO */
214 ddc_scl_pv4 {
215 nvidia,pins = "ddc_scl_pv4";
216 nvidia,function = "rsvd2";
217 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
218 nvidia,tristate = <TEGRA_PIN_DISABLE>;
219 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
220 };
221 ddc_sda_pv5 {
222 nvidia,pins = "ddc_sda_pv5";
223 nvidia,function = "rsvd2";
224 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
225 nvidia,tristate = <TEGRA_PIN_DISABLE>;
226 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
227 };
228 pex_l0_rst_n_pdd1 {
229 nvidia,pins = "pex_l0_rst_n_pdd1";
230 nvidia,function = "rsvd2";
231 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
232 nvidia,tristate = <TEGRA_PIN_DISABLE>;
233 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
234 };
235 pex_l0_clkreq_n_pdd2 {
236 nvidia,pins = "pex_l0_clkreq_n_pdd2";
237 nvidia,function = "rsvd2";
238 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
239 nvidia,tristate = <TEGRA_PIN_DISABLE>;
240 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
241 };
242 pex_l1_rst_n_pdd5 {
243 nvidia,pins = "pex_l1_rst_n_pdd5";
244 nvidia,function = "rsvd2";
245 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
246 nvidia,tristate = <TEGRA_PIN_DISABLE>;
247 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
248 };
249 pex_l1_clkreq_n_pdd6 {
250 nvidia,pins = "pex_l1_clkreq_n_pdd6";
251 nvidia,function = "rsvd2";
252 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
253 nvidia,tristate = <TEGRA_PIN_DISABLE>;
254 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
255 };
256 dp_hpd_pff0 {
257 nvidia,pins = "dp_hpd_pff0";
258 nvidia,function = "dp";
259 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
260 nvidia,tristate = <TEGRA_PIN_DISABLE>;
261 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
262 };
263 pff2 {
264 nvidia,pins = "pff2";
265 nvidia,function = "rsvd2";
266 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
267 nvidia,tristate = <TEGRA_PIN_DISABLE>;
268 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
269 };
270 owr { /* PEX_L1_CLKREQ_N multiplexed GPIO6 */
271 nvidia,pins = "owr";
272 nvidia,function = "rsvd2";
273 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
274 nvidia,tristate = <TEGRA_PIN_ENABLE>;
275 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
276 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
277 };
278
279 /* Apalis HDMI1_CEC */
280 hdmi_cec_pee3 {
281 nvidia,pins = "hdmi_cec_pee3";
282 nvidia,function = "cec";
283 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
284 nvidia,tristate = <TEGRA_PIN_DISABLE>;
285 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
286 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
287 };
288
289 /* Apalis HDMI1_HPD */
290 hdmi_int_pn7 {
291 nvidia,pins = "hdmi_int_pn7";
292 nvidia,function = "rsvd1";
293 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
294 nvidia,tristate = <TEGRA_PIN_ENABLE>;
295 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
296 nvidia,rcv-sel = <TEGRA_PIN_DISABLE>;
297 };
298
299 /* Apalis I2C1 */
300 gen1_i2c_scl_pc4 {
301 nvidia,pins = "gen1_i2c_scl_pc4";
302 nvidia,function = "i2c1";
303 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
304 nvidia,tristate = <TEGRA_PIN_DISABLE>;
305 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
306 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
307 };
308 gen1_i2c_sda_pc5 {
309 nvidia,pins = "gen1_i2c_sda_pc5";
310 nvidia,function = "i2c1";
311 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
312 nvidia,tristate = <TEGRA_PIN_DISABLE>;
313 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
314 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
315 };
316
317 /* Apalis I2C2 (DDC) */
318 gen2_i2c_scl_pt5 {
319 nvidia,pins = "gen2_i2c_scl_pt5";
320 nvidia,function = "i2c2";
321 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
322 nvidia,tristate = <TEGRA_PIN_DISABLE>;
323 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
324 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
325 };
326 gen2_i2c_sda_pt6 {
327 nvidia,pins = "gen2_i2c_sda_pt6";
328 nvidia,function = "i2c2";
329 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
330 nvidia,tristate = <TEGRA_PIN_DISABLE>;
331 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
332 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
333 };
334
335 /* Apalis I2C3 (CAM) */
336 cam_i2c_scl_pbb1 {
337 nvidia,pins = "cam_i2c_scl_pbb1";
338 nvidia,function = "i2c3";
339 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
340 nvidia,tristate = <TEGRA_PIN_DISABLE>;
341 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
342 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
343 };
344 cam_i2c_sda_pbb2 {
345 nvidia,pins = "cam_i2c_sda_pbb2";
346 nvidia,function = "i2c3";
347 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
348 nvidia,tristate = <TEGRA_PIN_DISABLE>;
349 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
350 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
351 };
352
353 /* Apalis MMC1 */
354 sdmmc1_cd_n_pv3 { /* CD# GPIO */
355 nvidia,pins = "sdmmc1_wp_n_pv3";
356 nvidia,function = "sdmmc1";
357 nvidia,pull = <TEGRA_PIN_PULL_UP>;
358 nvidia,tristate = <TEGRA_PIN_ENABLE>;
359 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
360 };
361 clk2_out_pw5 { /* D5 GPIO */
362 nvidia,pins = "clk2_out_pw5";
363 nvidia,function = "rsvd2";
364 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
365 nvidia,tristate = <TEGRA_PIN_DISABLE>;
366 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
367 };
368 sdmmc1_dat3_py4 {
369 nvidia,pins = "sdmmc1_dat3_py4";
370 nvidia,function = "sdmmc1";
371 nvidia,pull = <TEGRA_PIN_PULL_UP>;
372 nvidia,tristate = <TEGRA_PIN_DISABLE>;
373 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
374 };
375 sdmmc1_dat2_py5 {
376 nvidia,pins = "sdmmc1_dat2_py5";
377 nvidia,function = "sdmmc1";
378 nvidia,pull = <TEGRA_PIN_PULL_UP>;
379 nvidia,tristate = <TEGRA_PIN_DISABLE>;
380 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
381 };
382 sdmmc1_dat1_py6 {
383 nvidia,pins = "sdmmc1_dat1_py6";
384 nvidia,function = "sdmmc1";
385 nvidia,pull = <TEGRA_PIN_PULL_UP>;
386 nvidia,tristate = <TEGRA_PIN_DISABLE>;
387 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
388 };
389 sdmmc1_dat0_py7 {
390 nvidia,pins = "sdmmc1_dat0_py7";
391 nvidia,function = "sdmmc1";
392 nvidia,pull = <TEGRA_PIN_PULL_UP>;
393 nvidia,tristate = <TEGRA_PIN_DISABLE>;
394 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
395 };
396 sdmmc1_clk_pz0 {
397 nvidia,pins = "sdmmc1_clk_pz0";
398 nvidia,function = "sdmmc1";
399 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
400 nvidia,tristate = <TEGRA_PIN_DISABLE>;
401 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
402 };
403 sdmmc1_cmd_pz1 {
404 nvidia,pins = "sdmmc1_cmd_pz1";
405 nvidia,function = "sdmmc1";
406 nvidia,pull = <TEGRA_PIN_PULL_UP>;
407 nvidia,tristate = <TEGRA_PIN_DISABLE>;
408 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
409 };
410 clk2_req_pcc5 { /* D4 GPIO */
411 nvidia,pins = "clk2_req_pcc5";
412 nvidia,function = "rsvd2";
413 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
414 nvidia,tristate = <TEGRA_PIN_DISABLE>;
415 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
416 };
417 sdmmc3_clk_lb_in_pee5 { /* D6 GPIO */
418 nvidia,pins = "sdmmc3_clk_lb_in_pee5";
419 nvidia,function = "rsvd2";
420 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
421 nvidia,tristate = <TEGRA_PIN_DISABLE>;
422 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
423 };
424 usb_vbus_en2_pff1 { /* D7 GPIO */
425 nvidia,pins = "usb_vbus_en2_pff1";
426 nvidia,function = "rsvd2";
427 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
428 nvidia,tristate = <TEGRA_PIN_DISABLE>;
429 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
430 };
431
432 /* Apalis PWM */
433 ph0 {
434 nvidia,pins = "ph0";
435 nvidia,function = "pwm0";
436 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
437 nvidia,tristate = <TEGRA_PIN_DISABLE>;
438 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
439 };
440 ph1 {
441 nvidia,pins = "ph1";
442 nvidia,function = "pwm1";
443 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
444 nvidia,tristate = <TEGRA_PIN_DISABLE>;
445 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
446 };
447 ph2 {
448 nvidia,pins = "ph2";
449 nvidia,function = "pwm2";
450 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
451 nvidia,tristate = <TEGRA_PIN_DISABLE>;
452 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
453 };
454 /* PWM3 active on pu6 being Apalis BKL1_PWM as well */
455 ph3 {
456 nvidia,pins = "ph3";
457 nvidia,function = "pwm3";
458 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
459 nvidia,tristate = <TEGRA_PIN_DISABLE>;
460 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
461 };
462
463 /* Apalis SATA1_ACT# */
464 dap1_dout_pn2 {
465 nvidia,pins = "dap1_dout_pn2";
466 nvidia,function = "gmi";
467 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
468 nvidia,tristate = <TEGRA_PIN_DISABLE>;
469 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
470 };
471
472 /* Apalis SD1 */
473 sdmmc3_clk_pa6 {
474 nvidia,pins = "sdmmc3_clk_pa6";
475 nvidia,function = "sdmmc3";
476 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
477 nvidia,tristate = <TEGRA_PIN_DISABLE>;
478 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
479 };
480 sdmmc3_cmd_pa7 {
481 nvidia,pins = "sdmmc3_cmd_pa7";
482 nvidia,function = "sdmmc3";
483 nvidia,pull = <TEGRA_PIN_PULL_UP>;
484 nvidia,tristate = <TEGRA_PIN_DISABLE>;
485 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
486 };
487 sdmmc3_dat3_pb4 {
488 nvidia,pins = "sdmmc3_dat3_pb4";
489 nvidia,function = "sdmmc3";
490 nvidia,pull = <TEGRA_PIN_PULL_UP>;
491 nvidia,tristate = <TEGRA_PIN_DISABLE>;
492 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
493 };
494 sdmmc3_dat2_pb5 {
495 nvidia,pins = "sdmmc3_dat2_pb5";
496 nvidia,function = "sdmmc3";
497 nvidia,pull = <TEGRA_PIN_PULL_UP>;
498 nvidia,tristate = <TEGRA_PIN_DISABLE>;
499 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
500 };
501 sdmmc3_dat1_pb6 {
502 nvidia,pins = "sdmmc3_dat1_pb6";
503 nvidia,function = "sdmmc3";
504 nvidia,pull = <TEGRA_PIN_PULL_UP>;
505 nvidia,tristate = <TEGRA_PIN_DISABLE>;
506 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
507 };
508 sdmmc3_dat0_pb7 {
509 nvidia,pins = "sdmmc3_dat0_pb7";
510 nvidia,function = "sdmmc3";
511 nvidia,pull = <TEGRA_PIN_PULL_UP>;
512 nvidia,tristate = <TEGRA_PIN_DISABLE>;
513 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
514 };
515 sdmmc3_cd_n_pv2 { /* CD# GPIO */
516 nvidia,pins = "sdmmc3_cd_n_pv2";
517 nvidia,function = "rsvd3";
518 nvidia,pull = <TEGRA_PIN_PULL_UP>;
519 nvidia,tristate = <TEGRA_PIN_ENABLE>;
520 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
521 };
522
523 /* Apalis SPDIF */
524 spdif_out_pk5 {
525 nvidia,pins = "spdif_out_pk5";
526 nvidia,function = "spdif";
527 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
528 nvidia,tristate = <TEGRA_PIN_DISABLE>;
529 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
530 };
531 spdif_in_pk6 {
532 nvidia,pins = "spdif_in_pk6";
533 nvidia,function = "spdif";
534 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
535 nvidia,tristate = <TEGRA_PIN_ENABLE>;
536 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
537 };
538
539 /* Apalis SPI1 */
540 ulpi_clk_py0 {
541 nvidia,pins = "ulpi_clk_py0";
542 nvidia,function = "spi1";
543 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
544 nvidia,tristate = <TEGRA_PIN_DISABLE>;
545 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
546 };
547 ulpi_dir_py1 {
548 nvidia,pins = "ulpi_dir_py1";
549 nvidia,function = "spi1";
550 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
551 nvidia,tristate = <TEGRA_PIN_ENABLE>;
552 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
553 };
554 ulpi_nxt_py2 {
555 nvidia,pins = "ulpi_nxt_py2";
556 nvidia,function = "spi1";
557 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
558 nvidia,tristate = <TEGRA_PIN_DISABLE>;
559 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
560 };
561 ulpi_stp_py3 {
562 nvidia,pins = "ulpi_stp_py3";
563 nvidia,function = "spi1";
564 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
565 nvidia,tristate = <TEGRA_PIN_DISABLE>;
566 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
567 };
568
569 /* Apalis SPI2 */
570 pg5 {
571 nvidia,pins = "pg5";
572 nvidia,function = "spi4";
573 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
574 nvidia,tristate = <TEGRA_PIN_DISABLE>;
575 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
576 };
577 pg6 {
578 nvidia,pins = "pg6";
579 nvidia,function = "spi4";
580 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
581 nvidia,tristate = <TEGRA_PIN_DISABLE>;
582 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
583 };
584 pg7 {
585 nvidia,pins = "pg7";
586 nvidia,function = "spi4";
587 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
588 nvidia,tristate = <TEGRA_PIN_ENABLE>;
589 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
590 };
591 pi3 {
592 nvidia,pins = "pi3";
593 nvidia,function = "spi4";
594 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
595 nvidia,tristate = <TEGRA_PIN_DISABLE>;
596 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
597 };
598
599 /* Apalis UART1 */
600 pb1 { /* DCD GPIO */
601 nvidia,pins = "pb1";
602 nvidia,function = "rsvd2";
603 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
604 nvidia,tristate = <TEGRA_PIN_ENABLE>;
605 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
606 };
607 pk7 { /* RI GPIO */
608 nvidia,pins = "pk7";
609 nvidia,function = "rsvd2";
610 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
611 nvidia,tristate = <TEGRA_PIN_ENABLE>;
612 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
613 };
614 uart1_txd_pu0 {
615 nvidia,pins = "pu0";
616 nvidia,function = "uarta";
617 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
618 nvidia,tristate = <TEGRA_PIN_DISABLE>;
619 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
620 };
621 uart1_rxd_pu1 {
622 nvidia,pins = "pu1";
623 nvidia,function = "uarta";
624 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
625 nvidia,tristate = <TEGRA_PIN_ENABLE>;
626 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
627 };
628 uart1_cts_n_pu2 {
629 nvidia,pins = "pu2";
630 nvidia,function = "uarta";
631 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
632 nvidia,tristate = <TEGRA_PIN_ENABLE>;
633 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
634 };
635 uart1_rts_n_pu3 {
636 nvidia,pins = "pu3";
637 nvidia,function = "uarta";
638 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
639 nvidia,tristate = <TEGRA_PIN_DISABLE>;
640 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
641 };
642 uart3_cts_n_pa1 { /* DSR GPIO */
643 nvidia,pins = "uart3_cts_n_pa1";
644 nvidia,function = "gmi";
645 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
646 nvidia,tristate = <TEGRA_PIN_ENABLE>;
647 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
648 };
649 uart3_rts_n_pc0 { /* DTR GPIO */
650 nvidia,pins = "uart3_rts_n_pc0";
651 nvidia,function = "gmi";
652 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
653 nvidia,tristate = <TEGRA_PIN_DISABLE>;
654 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
655 };
656
657 /* Apalis UART2 */
658 uart2_txd_pc2 {
659 nvidia,pins = "uart2_txd_pc2";
660 nvidia,function = "irda";
661 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
662 nvidia,tristate = <TEGRA_PIN_DISABLE>;
663 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
664 };
665 uart2_rxd_pc3 {
666 nvidia,pins = "uart2_rxd_pc3";
667 nvidia,function = "irda";
668 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
669 nvidia,tristate = <TEGRA_PIN_ENABLE>;
670 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
671 };
672 uart2_cts_n_pj5 {
673 nvidia,pins = "uart2_cts_n_pj5";
674 nvidia,function = "uartb";
675 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
676 nvidia,tristate = <TEGRA_PIN_ENABLE>;
677 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
678 };
679 uart2_rts_n_pj6 {
680 nvidia,pins = "uart2_rts_n_pj6";
681 nvidia,function = "uartb";
682 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
683 nvidia,tristate = <TEGRA_PIN_DISABLE>;
684 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
685 };
686
687 /* Apalis UART3 */
688 uart3_txd_pw6 {
689 nvidia,pins = "uart3_txd_pw6";
690 nvidia,function = "uartc";
691 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
692 nvidia,tristate = <TEGRA_PIN_DISABLE>;
693 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
694 };
695 uart3_rxd_pw7 {
696 nvidia,pins = "uart3_rxd_pw7";
697 nvidia,function = "uartc";
698 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
699 nvidia,tristate = <TEGRA_PIN_ENABLE>;
700 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
701 };
702
703 /* Apalis UART4 */
704 uart4_rxd_pb0 {
705 nvidia,pins = "pb0";
706 nvidia,function = "uartd";
707 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
708 nvidia,tristate = <TEGRA_PIN_ENABLE>;
709 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
710 };
711 uart4_txd_pj7 {
712 nvidia,pins = "pj7";
713 nvidia,function = "uartd";
714 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
715 nvidia,tristate = <TEGRA_PIN_DISABLE>;
716 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
717 };
718
719 /* Apalis USBH_EN */
720 usb_vbus_en1_pn5 {
721 nvidia,pins = "usb_vbus_en1_pn5";
722 nvidia,function = "rsvd2";
723 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
724 nvidia,tristate = <TEGRA_PIN_DISABLE>;
725 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
726 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
727 };
728
729 /* Apalis USBH_OC# */
730 pbb0 {
731 nvidia,pins = "pbb0";
732 nvidia,function = "vgp6";
733 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
734 nvidia,tristate = <TEGRA_PIN_ENABLE>;
735 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
736 };
737
738 /* Apalis USBO1_EN */
739 usb_vbus_en0_pn4 {
740 nvidia,pins = "usb_vbus_en0_pn4";
741 nvidia,function = "rsvd2";
742 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
743 nvidia,tristate = <TEGRA_PIN_DISABLE>;
744 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
745 nvidia,open-drain = <TEGRA_PIN_DISABLE>;
746 };
747
748 /* Apalis USBO1_OC# */
749 pbb4 {
750 nvidia,pins = "pbb4";
751 nvidia,function = "vgp4";
752 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
753 nvidia,tristate = <TEGRA_PIN_ENABLE>;
754 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
755 };
756
757 /* Apalis WAKE1_MICO */
758 pex_wake_n_pdd3 {
759 nvidia,pins = "pex_wake_n_pdd3";
760 nvidia,function = "rsvd2";
761 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
762 nvidia,tristate = <TEGRA_PIN_ENABLE>;
763 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
764 };
765
766 /* CORE_PWR_REQ */
767 core_pwr_req {
768 nvidia,pins = "core_pwr_req";
769 nvidia,function = "pwron";
770 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
771 nvidia,tristate = <TEGRA_PIN_DISABLE>;
772 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
773 };
774
775 /* CPU_PWR_REQ */
776 cpu_pwr_req {
777 nvidia,pins = "cpu_pwr_req";
778 nvidia,function = "cpu";
779 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
780 nvidia,tristate = <TEGRA_PIN_DISABLE>;
781 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
782 };
783
784 /* DVFS */
785 dvfs_pwm_px0 {
786 nvidia,pins = "dvfs_pwm_px0";
787 nvidia,function = "cldvfs";
788 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
789 nvidia,tristate = <TEGRA_PIN_DISABLE>;
790 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
791 };
792 dvfs_clk_px2 {
793 nvidia,pins = "dvfs_clk_px2";
794 nvidia,function = "cldvfs";
795 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
796 nvidia,tristate = <TEGRA_PIN_DISABLE>;
797 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
798 };
799
800 /* eMMC */
801 sdmmc4_dat0_paa0 {
802 nvidia,pins = "sdmmc4_dat0_paa0";
803 nvidia,function = "sdmmc4";
804 nvidia,pull = <TEGRA_PIN_PULL_UP>;
805 nvidia,tristate = <TEGRA_PIN_DISABLE>;
806 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
807 };
808 sdmmc4_dat1_paa1 {
809 nvidia,pins = "sdmmc4_dat1_paa1";
810 nvidia,function = "sdmmc4";
811 nvidia,pull = <TEGRA_PIN_PULL_UP>;
812 nvidia,tristate = <TEGRA_PIN_DISABLE>;
813 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
814 };
815 sdmmc4_dat2_paa2 {
816 nvidia,pins = "sdmmc4_dat2_paa2";
817 nvidia,function = "sdmmc4";
818 nvidia,pull = <TEGRA_PIN_PULL_UP>;
819 nvidia,tristate = <TEGRA_PIN_DISABLE>;
820 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
821 };
822 sdmmc4_dat3_paa3 {
823 nvidia,pins = "sdmmc4_dat3_paa3";
824 nvidia,function = "sdmmc4";
825 nvidia,pull = <TEGRA_PIN_PULL_UP>;
826 nvidia,tristate = <TEGRA_PIN_DISABLE>;
827 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
828 };
829 sdmmc4_dat4_paa4 {
830 nvidia,pins = "sdmmc4_dat4_paa4";
831 nvidia,function = "sdmmc4";
832 nvidia,pull = <TEGRA_PIN_PULL_UP>;
833 nvidia,tristate = <TEGRA_PIN_DISABLE>;
834 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
835 };
836 sdmmc4_dat5_paa5 {
837 nvidia,pins = "sdmmc4_dat5_paa5";
838 nvidia,function = "sdmmc4";
839 nvidia,pull = <TEGRA_PIN_PULL_UP>;
840 nvidia,tristate = <TEGRA_PIN_DISABLE>;
841 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
842 };
843 sdmmc4_dat6_paa6 {
844 nvidia,pins = "sdmmc4_dat6_paa6";
845 nvidia,function = "sdmmc4";
846 nvidia,pull = <TEGRA_PIN_PULL_UP>;
847 nvidia,tristate = <TEGRA_PIN_DISABLE>;
848 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
849 };
850 sdmmc4_dat7_paa7 {
851 nvidia,pins = "sdmmc4_dat7_paa7";
852 nvidia,function = "sdmmc4";
853 nvidia,pull = <TEGRA_PIN_PULL_UP>;
854 nvidia,tristate = <TEGRA_PIN_DISABLE>;
855 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
856 };
857 sdmmc4_clk_pcc4 {
858 nvidia,pins = "sdmmc4_clk_pcc4";
859 nvidia,function = "sdmmc4";
860 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
861 nvidia,tristate = <TEGRA_PIN_DISABLE>;
862 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
863 };
864 sdmmc4_cmd_pt7 {
865 nvidia,pins = "sdmmc4_cmd_pt7";
866 nvidia,function = "sdmmc4";
867 nvidia,pull = <TEGRA_PIN_PULL_UP>;
868 nvidia,tristate = <TEGRA_PIN_DISABLE>;
869 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
870 };
871
872 /* JTAG_RTCK */
873 jtag_rtck {
874 nvidia,pins = "jtag_rtck";
875 nvidia,function = "rtck";
876 nvidia,pull = <TEGRA_PIN_PULL_UP>;
877 nvidia,tristate = <TEGRA_PIN_DISABLE>;
878 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
879 };
880
881 /* LAN_DEV_OFF# */
882 ulpi_data5_po6 {
883 nvidia,pins = "ulpi_data5_po6";
884 nvidia,function = "ulpi";
885 nvidia,pull = <TEGRA_PIN_PULL_UP>;
886 nvidia,tristate = <TEGRA_PIN_DISABLE>;
887 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
888 };
889
890 /* LAN_RESET# */
891 kb_row10_ps2 {
892 nvidia,pins = "kb_row10_ps2";
893 nvidia,function = "rsvd2";
894 nvidia,pull = <TEGRA_PIN_PULL_UP>;
895 nvidia,tristate = <TEGRA_PIN_DISABLE>;
896 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
897 };
898
899 /* LAN_WAKE# */
900 ulpi_data4_po5 {
901 nvidia,pins = "ulpi_data4_po5";
902 nvidia,function = "ulpi";
903 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
904 nvidia,tristate = <TEGRA_PIN_ENABLE>;
905 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
906 };
907
908 /* MCU_INT1# */
909 pk2 {
910 nvidia,pins = "pk2";
911 nvidia,function = "rsvd1";
912 nvidia,pull = <TEGRA_PIN_PULL_UP>;
913 nvidia,tristate = <TEGRA_PIN_ENABLE>;
914 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
915 };
916
917 /* MCU_INT2# */
918 pj2 {
919 nvidia,pins = "pj2";
920 nvidia,function = "rsvd1";
921 nvidia,pull = <TEGRA_PIN_PULL_UP>;
922 nvidia,tristate = <TEGRA_PIN_ENABLE>;
923 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
924 };
925
926 /* MCU_INT3# */
927 pi5 {
928 nvidia,pins = "pi5";
929 nvidia,function = "rsvd2";
930 nvidia,pull = <TEGRA_PIN_PULL_UP>;
931 nvidia,tristate = <TEGRA_PIN_ENABLE>;
932 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
933 };
934
935 /* MCU_INT4# */
936 pj0 {
937 nvidia,pins = "pj0";
938 nvidia,function = "rsvd1";
939 nvidia,pull = <TEGRA_PIN_PULL_UP>;
940 nvidia,tristate = <TEGRA_PIN_ENABLE>;
941 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
942 };
943
944 /* MCU_RESET */
945 pbb6 {
946 nvidia,pins = "pbb6";
947 nvidia,function = "rsvd2";
948 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
949 nvidia,tristate = <TEGRA_PIN_DISABLE>;
950 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
951 };
952
953 /* MCU SPI */
954 gpio_x4_aud_px4 {
955 nvidia,pins = "gpio_x4_aud_px4";
956 nvidia,function = "spi2";
957 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
958 nvidia,tristate = <TEGRA_PIN_DISABLE>;
959 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
960 };
961 gpio_x5_aud_px5 {
962 nvidia,pins = "gpio_x5_aud_px5";
963 nvidia,function = "spi2";
964 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
965 nvidia,tristate = <TEGRA_PIN_DISABLE>;
966 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
967 };
968 gpio_x6_aud_px6 { /* MCU_CS */
969 nvidia,pins = "gpio_x6_aud_px6";
970 nvidia,function = "spi2";
971 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
972 nvidia,tristate = <TEGRA_PIN_DISABLE>;
973 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
974 };
975 gpio_x7_aud_px7 {
976 nvidia,pins = "gpio_x7_aud_px7";
977 nvidia,function = "spi2";
978 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
979 nvidia,tristate = <TEGRA_PIN_ENABLE>;
980 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
981 };
982 gpio_w2_aud_pw2 { /* MCU_CSEZP */
983 nvidia,pins = "gpio_w2_aud_pw2";
984 nvidia,function = "spi2";
985 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
986 nvidia,tristate = <TEGRA_PIN_DISABLE>;
987 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
988 };
989
990 /* PMIC_CLK_32K */
991 clk_32k_in {
992 nvidia,pins = "clk_32k_in";
993 nvidia,function = "clk";
994 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
995 nvidia,tristate = <TEGRA_PIN_ENABLE>;
996 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
997 };
998
999 /* PMIC_CPU_OC_INT */
1000 clk_32k_out_pa0 {
1001 nvidia,pins = "clk_32k_out_pa0";
1002 nvidia,function = "soc";
1003 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1004 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1005 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1006 };
1007
1008 /* PWR_I2C */
1009 pwr_i2c_scl_pz6 {
1010 nvidia,pins = "pwr_i2c_scl_pz6";
1011 nvidia,function = "i2cpwr";
1012 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1013 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1014 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1015 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1016 };
1017 pwr_i2c_sda_pz7 {
1018 nvidia,pins = "pwr_i2c_sda_pz7";
1019 nvidia,function = "i2cpwr";
1020 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1021 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1022 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1023 nvidia,open-drain = <TEGRA_PIN_ENABLE>;
1024 };
1025
1026 /* PWR_INT_N */
1027 pwr_int_n {
1028 nvidia,pins = "pwr_int_n";
1029 nvidia,function = "pmi";
1030 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1031 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1032 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1033 };
1034
1035 /* RESET_MOCI_CTRL */
1036 pu4 {
1037 nvidia,pins = "pu4";
1038 nvidia,function = "gmi";
1039 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1040 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1041 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1042 };
1043
1044 /* RESET_OUT_N */
1045 reset_out_n {
1046 nvidia,pins = "reset_out_n";
1047 nvidia,function = "reset_out_n";
1048 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1049 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1050 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1051 };
1052
1053 /* SHIFT_CTRL_DIR_IN */
1054 kb_row0_pr0 {
1055 nvidia,pins = "kb_row0_pr0";
1056 nvidia,function = "rsvd2";
1057 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1058 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1059 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1060 };
1061 kb_row1_pr1 {
1062 nvidia,pins = "kb_row1_pr1";
1063 nvidia,function = "rsvd2";
1064 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1065 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1066 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1067 };
1068
1069 /* Configure level-shifter as output for HDA */
1070 kb_row11_ps3 {
1071 nvidia,pins = "kb_row11_ps3";
1072 nvidia,function = "rsvd2";
1073 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1074 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1075 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1076 };
1077
1078 /* SHIFT_CTRL_DIR_OUT */
1079 kb_col5_pq5 {
1080 nvidia,pins = "kb_col5_pq5";
1081 nvidia,function = "rsvd2";
1082 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1083 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1084 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1085 };
1086 kb_col6_pq6 {
1087 nvidia,pins = "kb_col6_pq6";
1088 nvidia,function = "rsvd2";
1089 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1090 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1091 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1092 };
1093 kb_col7_pq7 {
1094 nvidia,pins = "kb_col7_pq7";
1095 nvidia,function = "rsvd2";
1096 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1097 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1098 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1099 };
1100
1101 /* SHIFT_CTRL_OE */
1102 kb_col0_pq0 {
1103 nvidia,pins = "kb_col0_pq0";
1104 nvidia,function = "rsvd2";
1105 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1106 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1107 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1108 };
1109 kb_col1_pq1 {
1110 nvidia,pins = "kb_col1_pq1";
1111 nvidia,function = "rsvd2";
1112 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1113 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1114 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1115 };
1116 kb_col2_pq2 {
1117 nvidia,pins = "kb_col2_pq2";
1118 nvidia,function = "rsvd2";
1119 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1120 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1121 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1122 };
1123 kb_col4_pq4 {
1124 nvidia,pins = "kb_col4_pq4";
1125 nvidia,function = "kbc";
1126 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1127 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1128 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1129 };
1130 kb_row2_pr2 {
1131 nvidia,pins = "kb_row2_pr2";
1132 nvidia,function = "rsvd2";
1133 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1134 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1135 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1136 };
1137
1138 /* GPIO_PI6 aka TMP451 ALERT#/THERM2# */
1139 pi6 {
1140 nvidia,pins = "pi6";
1141 nvidia,function = "rsvd1";
1142 nvidia,pull = <TEGRA_PIN_PULL_UP>;
1143 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1144 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1145 };
1146
1147 /* TOUCH_INT */
1148 gpio_w3_aud_pw3 {
1149 nvidia,pins = "gpio_w3_aud_pw3";
1150 nvidia,function = "spi6";
1151 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1152 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1153 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1154 };
1155
1156 pc7 { /* NC */
1157 nvidia,pins = "pc7";
1158 nvidia,function = "rsvd1";
1159 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1160 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1161 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1162 };
1163 pg0 { /* NC */
1164 nvidia,pins = "pg0";
1165 nvidia,function = "rsvd1";
1166 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1167 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1168 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1169 };
1170 pg1 { /* NC */
1171 nvidia,pins = "pg1";
1172 nvidia,function = "rsvd1";
1173 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1174 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1175 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1176 };
1177 pg2 { /* NC */
1178 nvidia,pins = "pg2";
1179 nvidia,function = "rsvd1";
1180 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1181 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1182 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1183 };
1184 pg3 { /* NC */
1185 nvidia,pins = "pg3";
1186 nvidia,function = "rsvd1";
1187 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1188 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1189 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1190 };
1191 pg4 { /* NC */
1192 nvidia,pins = "pg4";
1193 nvidia,function = "rsvd1";
1194 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1195 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1196 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1197 };
1198 ph4 { /* NC */
1199 nvidia,pins = "ph4";
1200 nvidia,function = "rsvd2";
1201 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1202 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1203 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1204 };
1205 ph5 { /* NC */
1206 nvidia,pins = "ph5";
1207 nvidia,function = "rsvd2";
1208 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1209 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1210 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1211 };
1212 ph6 { /* NC */
1213 nvidia,pins = "ph6";
1214 nvidia,function = "gmi";
1215 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1216 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1217 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1218 };
1219 ph7 { /* NC */
1220 nvidia,pins = "ph7";
1221 nvidia,function = "gmi";
1222 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1223 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1224 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1225 };
1226 pi0 { /* NC */
1227 nvidia,pins = "pi0";
1228 nvidia,function = "rsvd1";
1229 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1230 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1231 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1232 };
1233 pi1 { /* NC */
1234 nvidia,pins = "pi1";
1235 nvidia,function = "rsvd1";
1236 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1237 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1238 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1239 };
1240 pi2 { /* NC */
1241 nvidia,pins = "pi2";
1242 nvidia,function = "rsvd4";
1243 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1244 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1245 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1246 };
1247 pi4 { /* NC */
1248 nvidia,pins = "pi4";
1249 nvidia,function = "gmi";
1250 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1251 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1252 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1253 };
1254 pi7 { /* NC */
1255 nvidia,pins = "pi7";
1256 nvidia,function = "rsvd1";
1257 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1258 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1259 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1260 };
1261 pk0 { /* NC */
1262 nvidia,pins = "pk0";
1263 nvidia,function = "rsvd1";
1264 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1265 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1266 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1267 };
1268 pk1 { /* NC */
1269 nvidia,pins = "pk1";
1270 nvidia,function = "rsvd4";
1271 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1272 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1273 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1274 };
1275 pk3 { /* NC */
1276 nvidia,pins = "pk3";
1277 nvidia,function = "gmi";
1278 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1279 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1280 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1281 };
1282 pk4 { /* NC */
1283 nvidia,pins = "pk4";
1284 nvidia,function = "rsvd2";
1285 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1286 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1287 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1288 };
1289 dap1_fs_pn0 { /* NC */
1290 nvidia,pins = "dap1_fs_pn0";
1291 nvidia,function = "rsvd4";
1292 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1293 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1294 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1295 };
1296 dap1_din_pn1 { /* NC */
1297 nvidia,pins = "dap1_din_pn1";
1298 nvidia,function = "rsvd4";
1299 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1300 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1301 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1302 };
1303 dap1_sclk_pn3 { /* NC */
1304 nvidia,pins = "dap1_sclk_pn3";
1305 nvidia,function = "rsvd4";
1306 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1307 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1308 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1309 };
1310 ulpi_data7_po0 { /* NC */
1311 nvidia,pins = "ulpi_data7_po0";
1312 nvidia,function = "ulpi";
1313 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1314 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1315 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1316 };
1317 ulpi_data0_po1 { /* NC */
1318 nvidia,pins = "ulpi_data0_po1";
1319 nvidia,function = "ulpi";
1320 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1321 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1322 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1323 };
1324 ulpi_data1_po2 { /* NC */
1325 nvidia,pins = "ulpi_data1_po2";
1326 nvidia,function = "ulpi";
1327 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1328 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1329 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1330 };
1331 ulpi_data2_po3 { /* NC */
1332 nvidia,pins = "ulpi_data2_po3";
1333 nvidia,function = "ulpi";
1334 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1335 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1336 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1337 };
1338 ulpi_data3_po4 { /* NC */
1339 nvidia,pins = "ulpi_data3_po4";
1340 nvidia,function = "ulpi";
1341 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1342 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1343 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1344 };
1345 ulpi_data6_po7 { /* NC */
1346 nvidia,pins = "ulpi_data6_po7";
1347 nvidia,function = "ulpi";
1348 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1349 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1350 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1351 };
1352 dap4_fs_pp4 { /* NC */
1353 nvidia,pins = "dap4_fs_pp4";
1354 nvidia,function = "rsvd4";
1355 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1356 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1357 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1358 };
1359 dap4_din_pp5 { /* NC */
1360 nvidia,pins = "dap4_din_pp5";
1361 nvidia,function = "rsvd3";
1362 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1363 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1364 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1365 };
1366 dap4_dout_pp6 { /* NC */
1367 nvidia,pins = "dap4_dout_pp6";
1368 nvidia,function = "rsvd4";
1369 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1370 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1371 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1372 };
1373 dap4_sclk_pp7 { /* NC */
1374 nvidia,pins = "dap4_sclk_pp7";
1375 nvidia,function = "rsvd3";
1376 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1377 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1378 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1379 };
1380 kb_col3_pq3 { /* NC */
1381 nvidia,pins = "kb_col3_pq3";
1382 nvidia,function = "kbc";
1383 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1384 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1385 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1386 };
1387 kb_row3_pr3 { /* NC */
1388 nvidia,pins = "kb_row3_pr3";
1389 nvidia,function = "kbc";
1390 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1391 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1392 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1393 };
1394 kb_row4_pr4 { /* NC */
1395 nvidia,pins = "kb_row4_pr4";
1396 nvidia,function = "rsvd3";
1397 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1398 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1399 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1400 };
1401 kb_row5_pr5 { /* NC */
1402 nvidia,pins = "kb_row5_pr5";
1403 nvidia,function = "rsvd3";
1404 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1405 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1406 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1407 };
1408 kb_row6_pr6 { /* NC */
1409 nvidia,pins = "kb_row6_pr6";
1410 nvidia,function = "kbc";
1411 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1412 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1413 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1414 };
1415 kb_row7_pr7 { /* NC */
1416 nvidia,pins = "kb_row7_pr7";
1417 nvidia,function = "rsvd2";
1418 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1419 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1420 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1421 };
1422 kb_row8_ps0 { /* NC */
1423 nvidia,pins = "kb_row8_ps0";
1424 nvidia,function = "rsvd2";
1425 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1426 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1427 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1428 };
1429 kb_row9_ps1 { /* NC */
1430 nvidia,pins = "kb_row9_ps1";
1431 nvidia,function = "rsvd2";
1432 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1433 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1434 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1435 };
1436 kb_row12_ps4 { /* NC */
1437 nvidia,pins = "kb_row12_ps4";
1438 nvidia,function = "rsvd2";
1439 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1440 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1441 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1442 };
1443 kb_row13_ps5 { /* NC */
1444 nvidia,pins = "kb_row13_ps5";
1445 nvidia,function = "rsvd2";
1446 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1447 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1448 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1449 };
1450 kb_row14_ps6 { /* NC */
1451 nvidia,pins = "kb_row14_ps6";
1452 nvidia,function = "rsvd2";
1453 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1454 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1455 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1456 };
1457 kb_row15_ps7 { /* NC */
1458 nvidia,pins = "kb_row15_ps7";
1459 nvidia,function = "rsvd3";
1460 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1461 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1462 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1463 };
1464 kb_row16_pt0 { /* NC */
1465 nvidia,pins = "kb_row16_pt0";
1466 nvidia,function = "rsvd2";
1467 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1468 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1469 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1470 };
1471 kb_row17_pt1 { /* NC */
1472 nvidia,pins = "kb_row17_pt1";
1473 nvidia,function = "rsvd2";
1474 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1475 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1476 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1477 };
1478 pu5 { /* NC */
1479 nvidia,pins = "pu5";
1480 nvidia,function = "gmi";
1481 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1482 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1483 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1484 };
1485 pv0 { /* NC */
1486 nvidia,pins = "pv0";
1487 nvidia,function = "rsvd1";
1488 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1489 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1490 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1491 };
1492 pv1 { /* NC */
1493 nvidia,pins = "pv1";
1494 nvidia,function = "rsvd1";
1495 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1496 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1497 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1498 };
1499 gpio_x1_aud_px1 { /* NC */
1500 nvidia,pins = "gpio_x1_aud_px1";
1501 nvidia,function = "rsvd2";
1502 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1503 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1504 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1505 };
1506 gpio_x3_aud_px3 { /* NC */
1507 nvidia,pins = "gpio_x3_aud_px3";
1508 nvidia,function = "rsvd4";
1509 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1510 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1511 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1512 };
1513 pbb7 { /* NC */
1514 nvidia,pins = "pbb7";
1515 nvidia,function = "rsvd2";
1516 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1517 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1518 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1519 };
1520 pcc1 { /* NC */
1521 nvidia,pins = "pcc1";
1522 nvidia,function = "rsvd2";
1523 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1524 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1525 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1526 };
1527 pcc2 { /* NC */
1528 nvidia,pins = "pcc2";
1529 nvidia,function = "rsvd2";
1530 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1531 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1532 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1533 };
1534 clk3_req_pee1 { /* NC */
1535 nvidia,pins = "clk3_req_pee1";
1536 nvidia,function = "rsvd2";
1537 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1538 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1539 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1540 };
1541 dap_mclk1_req_pee2 { /* NC */
1542 nvidia,pins = "dap_mclk1_req_pee2";
1543 nvidia,function = "rsvd4";
1544 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
1545 nvidia,tristate = <TEGRA_PIN_ENABLE>;
1546 nvidia,enable-input = <TEGRA_PIN_DISABLE>;
1547 };
1548 /*
1549 * Leave SDMMC3_CLK_LB_OUT muxed as SDMMC3 with output
1550 * driver enabled aka not tristated and input driver
1551 * enabled as well as it features some magic properties
1552 * even though the external loopback is disabled and the
1553 * internal loopback used as per
1554 * SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
1555 * bits being set to 0xfffd according to the TRM!
1556 */
1557 sdmmc3_clk_lb_out_pee4 { /* NC */
1558 nvidia,pins = "sdmmc3_clk_lb_out_pee4";
1559 nvidia,function = "sdmmc3";
1560 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
1561 nvidia,tristate = <TEGRA_PIN_DISABLE>;
1562 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
1563 };
1564 };
1565 };
1566
1567 serial@70006040 {
1568 compatible = "nvidia,tegra124-hsuart";
1569 };
1570
1571 serial@70006200 {
1572 compatible = "nvidia,tegra124-hsuart";
1573 };
1574
1575 serial@70006300 {
1576 compatible = "nvidia,tegra124-hsuart";
1577 };
1578
1579 hdmi_ddc: i2c@7000c400 {
1580 clock-frequency = <10000>;
1581 };
1582
1583 /* PWR_I2C: power I2C to audio codec, PMIC and temperature sensor */
1584 i2c@7000d000 {
1585 status = "okay";
1586 clock-frequency = <400000>;
1587
1588 /* SGTL5000 audio codec */
1589 sgtl5000: codec@a {
1590 compatible = "fsl,sgtl5000";
1591 reg = <0x0a>;
1592 VDDA-supply = <®_3v3>;
1593 VDDIO-supply = <&vddio_1v8>;
1594 clocks = <&tegra_car TEGRA124_CLK_EXTERN1>;
1595 };
1596
1597 pmic: pmic@40 {
1598 compatible = "ams,as3722";
1599 reg = <0x40>;
1600 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
1601 ams,system-power-controller;
1602 #interrupt-cells = <2>;
1603 interrupt-controller;
1604 gpio-controller;
1605 #gpio-cells = <2>;
1606 pinctrl-names = "default";
1607 pinctrl-0 = <&as3722_default>;
1608
1609 as3722_default: pinmux {
1610 gpio2_7 {
1611 pins = "gpio2", /* PWR_EN_+V3.3 */
1612 "gpio7"; /* +V1.6_LPO */
1613 function = "gpio";
1614 bias-pull-up;
1615 };
1616
1617 gpio0_1_3_4_5_6 {
1618 pins = "gpio0", "gpio1", "gpio3",
1619 "gpio4", "gpio5", "gpio6";
1620 bias-high-impedance;
1621 };
1622 };
1623
1624 regulators {
1625 vsup-sd2-supply = <®_3v3>;
1626 vsup-sd3-supply = <®_3v3>;
1627 vsup-sd4-supply = <®_3v3>;
1628 vsup-sd5-supply = <®_3v3>;
1629 vin-ldo0-supply = <&vddio_ddr_1v35>;
1630 vin-ldo1-6-supply = <®_3v3>;
1631 vin-ldo2-5-7-supply = <&vddio_1v8>;
1632 vin-ldo3-4-supply = <®_3v3>;
1633 vin-ldo9-10-supply = <®_3v3>;
1634 vin-ldo11-supply = <®_3v3>;
1635
1636 vdd_cpu: sd0 {
1637 regulator-name = "+VDD_CPU_AP";
1638 regulator-min-microvolt = <700000>;
1639 regulator-max-microvolt = <1400000>;
1640 regulator-min-microamp = <3500000>;
1641 regulator-max-microamp = <3500000>;
1642 regulator-always-on;
1643 regulator-boot-on;
1644 ams,ext-control = <2>;
1645 };
1646
1647 sd1 {
1648 regulator-name = "+VDD_CORE";
1649 regulator-min-microvolt = <700000>;
1650 regulator-max-microvolt = <1350000>;
1651 regulator-min-microamp = <2500000>;
1652 regulator-max-microamp = <4000000>;
1653 regulator-always-on;
1654 regulator-boot-on;
1655 ams,ext-control = <1>;
1656 };
1657
1658 vddio_ddr_1v35: sd2 {
1659 regulator-name =
1660 "+V1.35_VDDIO_DDR(sd2)";
1661 regulator-min-microvolt = <1350000>;
1662 regulator-max-microvolt = <1350000>;
1663 regulator-always-on;
1664 regulator-boot-on;
1665 };
1666
1667 sd3 {
1668 regulator-name =
1669 "+V1.35_VDDIO_DDR(sd3)";
1670 regulator-min-microvolt = <1350000>;
1671 regulator-max-microvolt = <1350000>;
1672 regulator-always-on;
1673 regulator-boot-on;
1674 };
1675
1676 vdd_1v05: sd4 {
1677 regulator-name = "+V1.05";
1678 regulator-min-microvolt = <1050000>;
1679 regulator-max-microvolt = <1050000>;
1680 };
1681
1682 vddio_1v8: sd5 {
1683 regulator-name = "+V1.8";
1684 regulator-min-microvolt = <1800000>;
1685 regulator-max-microvolt = <1800000>;
1686 regulator-boot-on;
1687 regulator-always-on;
1688 };
1689
1690 vdd_gpu: sd6 {
1691 regulator-name = "+VDD_GPU_AP";
1692 regulator-min-microvolt = <650000>;
1693 regulator-max-microvolt = <1200000>;
1694 regulator-min-microamp = <3500000>;
1695 regulator-max-microamp = <3500000>;
1696 regulator-boot-on;
1697 regulator-always-on;
1698 };
1699
1700 avdd_1v05: ldo0 {
1701 regulator-name = "+V1.05_AVDD";
1702 regulator-min-microvolt = <1050000>;
1703 regulator-max-microvolt = <1050000>;
1704 regulator-boot-on;
1705 regulator-always-on;
1706 ams,ext-control = <1>;
1707 };
1708
1709 vddio_sdmmc1: ldo1 {
1710 regulator-name = "VDDIO_SDMMC1";
1711 regulator-min-microvolt = <1800000>;
1712 regulator-max-microvolt = <3300000>;
1713 };
1714
1715 ldo2 {
1716 regulator-name = "+V1.2";
1717 regulator-min-microvolt = <1200000>;
1718 regulator-max-microvolt = <1200000>;
1719 regulator-boot-on;
1720 regulator-always-on;
1721 };
1722
1723 ldo3 {
1724 regulator-name = "+V1.05_RTC";
1725 regulator-min-microvolt = <1000000>;
1726 regulator-max-microvolt = <1000000>;
1727 regulator-boot-on;
1728 regulator-always-on;
1729 ams,enable-tracking;
1730 };
1731
1732 /* 1.8V for LVDS, 3.3V for eDP */
1733 ldo4 {
1734 regulator-name = "AVDD_LVDS0_PLL";
1735 regulator-min-microvolt = <1800000>;
1736 regulator-max-microvolt = <1800000>;
1737 };
1738
1739 /* LDO5 not used */
1740
1741 vddio_sdmmc3: ldo6 {
1742 regulator-name = "VDDIO_SDMMC3";
1743 regulator-min-microvolt = <1800000>;
1744 regulator-max-microvolt = <3300000>;
1745 };
1746
1747 /* LDO7 not used */
1748
1749 ldo9 {
1750 regulator-name = "+V3.3_ETH(ldo9)";
1751 regulator-min-microvolt = <3300000>;
1752 regulator-max-microvolt = <3300000>;
1753 regulator-always-on;
1754 };
1755
1756 ldo10 {
1757 regulator-name = "+V3.3_ETH(ldo10)";
1758 regulator-min-microvolt = <3300000>;
1759 regulator-max-microvolt = <3300000>;
1760 regulator-always-on;
1761 };
1762
1763 ldo11 {
1764 regulator-name = "+V1.8_VPP_FUSE";
1765 regulator-min-microvolt = <1800000>;
1766 regulator-max-microvolt = <1800000>;
1767 };
1768 };
1769 };
1770
1771 /*
1772 * TMP451 temperature sensor
1773 * Note: THERM_N directly connected to AS3722 PMIC THERM
1774 */
1775 temperature-sensor@4c {
1776 compatible = "ti,tmp451";
1777 reg = <0x4c>;
1778 interrupt-parent = <&gpio>;
1779 interrupts = <TEGRA_GPIO(I, 6) IRQ_TYPE_LEVEL_LOW>;
1780 #thermal-sensor-cells = <1>;
1781 };
1782 };
1783
1784 /* SPI2: MCU SPI */
1785 spi@7000d600 {
1786 status = "okay";
1787 spi-max-frequency = <25000000>;
1788 };
1789
1790 pmc@7000e400 {
1791 nvidia,invert-interrupt;
1792 nvidia,suspend-mode = <1>;
1793 nvidia,cpu-pwr-good-time = <500>;
1794 nvidia,cpu-pwr-off-time = <300>;
1795 nvidia,core-pwr-good-time = <641 3845>;
1796 nvidia,core-pwr-off-time = <61036>;
1797 nvidia,core-power-req-active-high;
1798 nvidia,sys-clock-req-active-high;
1799
1800 /* Set power_off bit in ResetControl register of AS3722 PMIC */
1801 i2c-thermtrip {
1802 nvidia,i2c-controller-id = <4>;
1803 nvidia,bus-addr = <0x40>;
1804 nvidia,reg-addr = <0x36>;
1805 nvidia,reg-data = <0x2>;
1806 };
1807 };
1808
1809 sata@70020000 {
1810 phys = <&{/padctl@7009f000/pads/sata/lanes/sata-0}>;
1811 phy-names = "sata-0";
1812 avdd-supply = <&vdd_1v05>;
1813 hvdd-supply = <®_3v3>;
1814 vddio-supply = <&vdd_1v05>;
1815 };
1816
1817 usb@70090000 {
1818 /* USBO1, USBO1 (SS), USBH2, USBH4 and USBH4 (SS) */
1819 phys = <&{/padctl@7009f000/pads/usb2/lanes/usb2-0}>,
1820 <&{/padctl@7009f000/pads/pcie/lanes/pcie-1}>,
1821 <&{/padctl@7009f000/pads/usb2/lanes/usb2-1}>,
1822 <&{/padctl@7009f000/pads/usb2/lanes/usb2-2}>,
1823 <&{/padctl@7009f000/pads/pcie/lanes/pcie-0}>;
1824 phy-names = "usb2-0", "usb3-1", "usb2-1", "usb2-2", "usb3-0";
1825 avddio-pex-supply = <&vdd_1v05>;
1826 avdd-pll-erefe-supply = <&avdd_1v05>;
1827 avdd-pll-utmip-supply = <&vddio_1v8>;
1828 avdd-usb-ss-pll-supply = <&vdd_1v05>;
1829 avdd-usb-supply = <®_3v3>;
1830 dvddio-pex-supply = <&vdd_1v05>;
1831 hvdd-usb-ss-pll-e-supply = <®_3v3>;
1832 hvdd-usb-ss-supply = <®_3v3>;
1833 };
1834
1835 padctl@7009f000 {
1836 pads {
1837 usb2 {
1838 status = "okay";
1839
1840 lanes {
1841 usb2-0 {
1842 nvidia,function = "xusb";
1843 status = "okay";
1844 };
1845
1846 usb2-1 {
1847 nvidia,function = "xusb";
1848 status = "okay";
1849 };
1850
1851 usb2-2 {
1852 nvidia,function = "xusb";
1853 status = "okay";
1854 };
1855 };
1856 };
1857
1858 pcie {
1859 status = "okay";
1860
1861 lanes {
1862 pcie-0 {
1863 nvidia,function = "usb3-ss";
1864 status = "okay";
1865 };
1866
1867 pcie-1 {
1868 nvidia,function = "usb3-ss";
1869 status = "okay";
1870 };
1871
1872 pcie-2 {
1873 nvidia,function = "pcie";
1874 status = "okay";
1875 };
1876
1877 pcie-3 {
1878 nvidia,function = "pcie";
1879 status = "okay";
1880 };
1881
1882 pcie-4 {
1883 nvidia,function = "pcie";
1884 status = "okay";
1885 };
1886 };
1887 };
1888
1889 sata {
1890 status = "okay";
1891
1892 lanes {
1893 sata-0 {
1894 nvidia,function = "sata";
1895 status = "okay";
1896 };
1897 };
1898 };
1899 };
1900
1901 ports {
1902 /* USBO1 */
1903 usb2-0 {
1904 status = "okay";
1905 mode = "otg";
1906
1907 vbus-supply = <®_usbo1_vbus>;
1908 };
1909
1910 /* USBH2 */
1911 usb2-1 {
1912 status = "okay";
1913 mode = "host";
1914
1915 vbus-supply = <®_usbh_vbus>;
1916 };
1917
1918 /* USBH4 */
1919 usb2-2 {
1920 status = "okay";
1921 mode = "host";
1922
1923 vbus-supply = <®_usbh_vbus>;
1924 };
1925
1926 usb3-0 {
1927 nvidia,usb2-companion = <2>;
1928 status = "okay";
1929 };
1930
1931 usb3-1 {
1932 nvidia,usb2-companion = <0>;
1933 status = "okay";
1934 };
1935 };
1936 };
1937
1938 /* eMMC */
1939 sdhci@700b0600 {
1940 status = "okay";
1941 bus-width = <8>;
1942 non-removable;
1943 };
1944
1945 /* CPU DFLL clock */
1946 clock@70110000 {
1947 status = "okay";
1948 vdd-cpu-supply = <&vdd_cpu>;
1949 nvidia,i2c-fs-rate = <400000>;
1950 };
1951
1952 ahub@70300000 {
1953 i2s@70301200 {
1954 status = "okay";
1955 };
1956 };
1957
1958 clocks {
1959 compatible = "simple-bus";
1960 #address-cells = <1>;
1961 #size-cells = <0>;
1962
1963 clk32k_in: clock@0 {
1964 compatible = "fixed-clock";
1965 reg = <0>;
1966 #clock-cells = <0>;
1967 clock-frequency = <32768>;
1968 };
1969 };
1970
1971 cpus {
1972 cpu@0 {
1973 vdd-cpu-supply = <&vdd_cpu>;
1974 };
1975 };
1976
1977 reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll {
1978 compatible = "regulator-fixed";
1979 regulator-name = "+V1.05_AVDD_HDMI_PLL";
1980 regulator-min-microvolt = <1050000>;
1981 regulator-max-microvolt = <1050000>;
1982 gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>;
1983 vin-supply = <&vdd_1v05>;
1984 };
1985
1986 reg_3v3_mxm: regulator-3v3-mxm {
1987 compatible = "regulator-fixed";
1988 regulator-name = "+V3.3_MXM";
1989 regulator-min-microvolt = <3300000>;
1990 regulator-max-microvolt = <3300000>;
1991 regulator-always-on;
1992 regulator-boot-on;
1993 };
1994
1995 reg_3v3: regulator-3v3 {
1996 compatible = "regulator-fixed";
1997 regulator-name = "+V3.3";
1998 regulator-min-microvolt = <3300000>;
1999 regulator-max-microvolt = <3300000>;
2000 regulator-always-on;
2001 regulator-boot-on;
2002 /* PWR_EN_+V3.3 */
2003 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
2004 enable-active-high;
2005 vin-supply = <®_3v3_mxm>;
2006 };
2007
2008 reg_3v3_avdd_hdmi: regulator-3v3-avdd-hdmi {
2009 compatible = "regulator-fixed";
2010 regulator-name = "+V3.3_AVDD_HDMI";
2011 regulator-min-microvolt = <3300000>;
2012 regulator-max-microvolt = <3300000>;
2013 vin-supply = <&vdd_1v05>;
2014 };
2015
2016 sound {
2017 compatible = "toradex,tegra-audio-sgtl5000-apalis_tk1",
2018 "nvidia,tegra-audio-sgtl5000";
2019 nvidia,model = "Toradex Apalis TK1";
2020 nvidia,audio-routing =
2021 "Headphone Jack", "HP_OUT",
2022 "LINE_IN", "Line In Jack",
2023 "MIC_IN", "Mic Jack";
2024 nvidia,i2s-controller = <&tegra_i2s2>;
2025 nvidia,audio-codec = <&sgtl5000>;
2026 clocks = <&tegra_car TEGRA124_CLK_PLL_A>,
2027 <&tegra_car TEGRA124_CLK_PLL_A_OUT0>,
2028 <&tegra_car TEGRA124_CLK_EXTERN1>;
2029 clock-names = "pll_a", "pll_a_out0", "mclk";
2030 };
2031
2032 thermal-zones {
2033 cpu {
2034 trips {
2035 cpu-shutdown-trip {
2036 temperature = <101000>;
2037 hysteresis = <0>;
2038 type = "critical";
2039 };
2040 };
2041 };
2042
2043 mem {
2044 trips {
2045 mem-shutdown-trip {
2046 temperature = <101000>;
2047 hysteresis = <0>;
2048 type = "critical";
2049 };
2050 };
2051 };
2052
2053 gpu {
2054 trips {
2055 gpu-shutdown-trip {
2056 temperature = <101000>;
2057 hysteresis = <0>;
2058 type = "critical";
2059 };
2060 };
2061 };
2062 };
2063};
2064
2065&gpio {
2066 /* I210 Gigabit Ethernet Controller Reset */
2067 lan_reset_n {
2068 gpio-hog;
2069 gpios = <TEGRA_GPIO(S, 2) GPIO_ACTIVE_HIGH>;
2070 output-high;
2071 line-name = "LAN_RESET_N";
2072 };
2073
2074 /* Control MXM3 pin 26 Reset Module Output Carrier Input */
2075 reset_moci_ctrl {
2076 gpio-hog;
2077 gpios = <TEGRA_GPIO(U, 4) GPIO_ACTIVE_HIGH>;
2078 output-high;
2079 line-name = "RESET_MOCI_CTRL";
2080 };
2081};