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1/*
2 * Copyright 2015 - Maxime Coquelin <mcoquelin.stm32@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public
20 * License along with this file; if not, write to the Free
21 * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
22 * MA 02110-1301 USA
23 *
24 * Or, alternatively,
25 *
26 * b) Permission is hereby granted, free of charge, to any person
27 * obtaining a copy of this software and associated documentation
28 * files (the "Software"), to deal in the Software without
29 * restriction, including without limitation the rights to use,
30 * copy, modify, merge, publish, distribute, sublicense, and/or
31 * sell copies of the Software, and to permit persons to whom the
32 * Software is furnished to do so, subject to the following
33 * conditions:
34 *
35 * The above copyright notice and this permission notice shall be
36 * included in all copies or substantial portions of the Software.
37 *
38 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
39 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
43 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 * OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "skeleton.dtsi"
49#include "armv7-m.dtsi"
50#include <dt-bindings/clock/stm32fx-clock.h>
51#include <dt-bindings/mfd/stm32f4-rcc.h>
52
53/ {
54 clocks {
55 clk_hse: clk-hse {
56 #clock-cells = <0>;
57 compatible = "fixed-clock";
58 clock-frequency = <0>;
59 };
60
61 clk-lse {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 clock-frequency = <32768>;
65 };
66
67 clk_lsi: clk-lsi {
68 #clock-cells = <0>;
69 compatible = "fixed-clock";
70 clock-frequency = <32000>;
71 };
72
73 clk_i2s_ckin: i2s-ckin {
74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <0>;
77 };
78 };
79
80 soc {
81 timer2: timer@40000000 {
82 compatible = "st,stm32-timer";
83 reg = <0x40000000 0x400>;
84 interrupts = <28>;
85 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
86 status = "disabled";
87 };
88
89 timers2: timers@40000000 {
90 #address-cells = <1>;
91 #size-cells = <0>;
92 compatible = "st,stm32-timers";
93 reg = <0x40000000 0x400>;
94 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
95 clock-names = "int";
96 status = "disabled";
97
98 pwm {
99 compatible = "st,stm32-pwm";
100 status = "disabled";
101 };
102
103 timer@1 {
104 compatible = "st,stm32-timer-trigger";
105 reg = <1>;
106 status = "disabled";
107 };
108 };
109
110 timer3: timer@40000400 {
111 compatible = "st,stm32-timer";
112 reg = <0x40000400 0x400>;
113 interrupts = <29>;
114 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
115 status = "disabled";
116 };
117
118 timers3: timers@40000400 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "st,stm32-timers";
122 reg = <0x40000400 0x400>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
124 clock-names = "int";
125 status = "disabled";
126
127 pwm {
128 compatible = "st,stm32-pwm";
129 status = "disabled";
130 };
131
132 timer@2 {
133 compatible = "st,stm32-timer-trigger";
134 reg = <2>;
135 status = "disabled";
136 };
137 };
138
139 timer4: timer@40000800 {
140 compatible = "st,stm32-timer";
141 reg = <0x40000800 0x400>;
142 interrupts = <30>;
143 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
144 status = "disabled";
145 };
146
147 timers4: timers@40000800 {
148 #address-cells = <1>;
149 #size-cells = <0>;
150 compatible = "st,stm32-timers";
151 reg = <0x40000800 0x400>;
152 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
153 clock-names = "int";
154 status = "disabled";
155
156 pwm {
157 compatible = "st,stm32-pwm";
158 status = "disabled";
159 };
160
161 timer@3 {
162 compatible = "st,stm32-timer-trigger";
163 reg = <3>;
164 status = "disabled";
165 };
166 };
167
168 timer5: timer@40000c00 {
169 compatible = "st,stm32-timer";
170 reg = <0x40000c00 0x400>;
171 interrupts = <50>;
172 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
173 };
174
175 timers5: timers@40000c00 {
176 #address-cells = <1>;
177 #size-cells = <0>;
178 compatible = "st,stm32-timers";
179 reg = <0x40000C00 0x400>;
180 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
181 clock-names = "int";
182 status = "disabled";
183
184 pwm {
185 compatible = "st,stm32-pwm";
186 status = "disabled";
187 };
188
189 timer@4 {
190 compatible = "st,stm32-timer-trigger";
191 reg = <4>;
192 status = "disabled";
193 };
194 };
195
196 timer6: timer@40001000 {
197 compatible = "st,stm32-timer";
198 reg = <0x40001000 0x400>;
199 interrupts = <54>;
200 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
201 status = "disabled";
202 };
203
204 timers6: timers@40001000 {
205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "st,stm32-timers";
208 reg = <0x40001000 0x400>;
209 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
210 clock-names = "int";
211 status = "disabled";
212
213 timer@5 {
214 compatible = "st,stm32-timer-trigger";
215 reg = <5>;
216 status = "disabled";
217 };
218 };
219
220 timer7: timer@40001400 {
221 compatible = "st,stm32-timer";
222 reg = <0x40001400 0x400>;
223 interrupts = <55>;
224 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
225 status = "disabled";
226 };
227
228 timers7: timers@40001400 {
229 #address-cells = <1>;
230 #size-cells = <0>;
231 compatible = "st,stm32-timers";
232 reg = <0x40001400 0x400>;
233 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
234 clock-names = "int";
235 status = "disabled";
236
237 timer@6 {
238 compatible = "st,stm32-timer-trigger";
239 reg = <6>;
240 status = "disabled";
241 };
242 };
243
244 timers12: timers@40001800 {
245 #address-cells = <1>;
246 #size-cells = <0>;
247 compatible = "st,stm32-timers";
248 reg = <0x40001800 0x400>;
249 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
250 clock-names = "int";
251 status = "disabled";
252
253 pwm {
254 compatible = "st,stm32-pwm";
255 status = "disabled";
256 };
257
258 timer@11 {
259 compatible = "st,stm32-timer-trigger";
260 reg = <11>;
261 status = "disabled";
262 };
263 };
264
265 timers13: timers@40001c00 {
266 #address-cells = <1>;
267 #size-cells = <0>;
268 compatible = "st,stm32-timers";
269 reg = <0x40001C00 0x400>;
270 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
271 clock-names = "int";
272 status = "disabled";
273
274 pwm {
275 compatible = "st,stm32-pwm";
276 status = "disabled";
277 };
278 };
279
280 timers14: timers@40002000 {
281 #address-cells = <1>;
282 #size-cells = <0>;
283 compatible = "st,stm32-timers";
284 reg = <0x40002000 0x400>;
285 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
286 clock-names = "int";
287 status = "disabled";
288
289 pwm {
290 compatible = "st,stm32-pwm";
291 status = "disabled";
292 };
293 };
294
295 rtc: rtc@40002800 {
296 compatible = "st,stm32-rtc";
297 reg = <0x40002800 0x400>;
298 clocks = <&rcc 1 CLK_RTC>;
299 clock-names = "ck_rtc";
300 assigned-clocks = <&rcc 1 CLK_RTC>;
301 assigned-clock-parents = <&rcc 1 CLK_LSE>;
302 interrupt-parent = <&exti>;
303 interrupts = <17 1>;
304 interrupt-names = "alarm";
305 st,syscfg = <&pwrcfg>;
306 status = "disabled";
307 };
308
309 iwdg: watchdog@40003000 {
310 compatible = "st,stm32-iwdg";
311 reg = <0x40003000 0x400>;
312 clocks = <&clk_lsi>;
313 status = "disabled";
314 };
315
316 usart2: serial@40004400 {
317 compatible = "st,stm32-uart";
318 reg = <0x40004400 0x400>;
319 interrupts = <38>;
320 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART2)>;
321 status = "disabled";
322 };
323
324 usart3: serial@40004800 {
325 compatible = "st,stm32-uart";
326 reg = <0x40004800 0x400>;
327 interrupts = <39>;
328 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART3)>;
329 status = "disabled";
330 dmas = <&dma1 1 4 0x400 0x0>,
331 <&dma1 3 4 0x400 0x0>;
332 dma-names = "rx", "tx";
333 };
334
335 usart4: serial@40004c00 {
336 compatible = "st,stm32-uart";
337 reg = <0x40004c00 0x400>;
338 interrupts = <52>;
339 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART4)>;
340 status = "disabled";
341 };
342
343 usart5: serial@40005000 {
344 compatible = "st,stm32-uart";
345 reg = <0x40005000 0x400>;
346 interrupts = <53>;
347 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART5)>;
348 status = "disabled";
349 };
350
351 i2c1: i2c@40005400 {
352 compatible = "st,stm32f4-i2c";
353 reg = <0x40005400 0x400>;
354 interrupts = <31>,
355 <32>;
356 resets = <&rcc STM32F4_APB1_RESET(I2C1)>;
357 clocks = <&rcc 0 STM32F4_APB1_CLOCK(I2C1)>;
358 #address-cells = <1>;
359 #size-cells = <0>;
360 status = "disabled";
361 };
362
363 dac: dac@40007400 {
364 compatible = "st,stm32f4-dac-core";
365 reg = <0x40007400 0x400>;
366 resets = <&rcc STM32F4_APB1_RESET(DAC)>;
367 clocks = <&rcc 0 STM32F4_APB1_CLOCK(DAC)>;
368 clock-names = "pclk";
369 #address-cells = <1>;
370 #size-cells = <0>;
371 status = "disabled";
372
373 dac1: dac@1 {
374 compatible = "st,stm32-dac";
375 #io-channels-cells = <1>;
376 reg = <1>;
377 status = "disabled";
378 };
379
380 dac2: dac@2 {
381 compatible = "st,stm32-dac";
382 #io-channels-cells = <1>;
383 reg = <2>;
384 status = "disabled";
385 };
386 };
387
388 usart7: serial@40007800 {
389 compatible = "st,stm32-uart";
390 reg = <0x40007800 0x400>;
391 interrupts = <82>;
392 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART7)>;
393 status = "disabled";
394 };
395
396 usart8: serial@40007c00 {
397 compatible = "st,stm32-uart";
398 reg = <0x40007c00 0x400>;
399 interrupts = <83>;
400 clocks = <&rcc 0 STM32F4_APB1_CLOCK(UART8)>;
401 status = "disabled";
402 };
403
404 timers1: timers@40010000 {
405 #address-cells = <1>;
406 #size-cells = <0>;
407 compatible = "st,stm32-timers";
408 reg = <0x40010000 0x400>;
409 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM1)>;
410 clock-names = "int";
411 status = "disabled";
412
413 pwm {
414 compatible = "st,stm32-pwm";
415 status = "disabled";
416 };
417
418 timer@0 {
419 compatible = "st,stm32-timer-trigger";
420 reg = <0>;
421 status = "disabled";
422 };
423 };
424
425 timers8: timers@40010400 {
426 #address-cells = <1>;
427 #size-cells = <0>;
428 compatible = "st,stm32-timers";
429 reg = <0x40010400 0x400>;
430 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM8)>;
431 clock-names = "int";
432 status = "disabled";
433
434 pwm {
435 compatible = "st,stm32-pwm";
436 status = "disabled";
437 };
438
439 timer@7 {
440 compatible = "st,stm32-timer-trigger";
441 reg = <7>;
442 status = "disabled";
443 };
444 };
445
446 usart1: serial@40011000 {
447 compatible = "st,stm32-uart";
448 reg = <0x40011000 0x400>;
449 interrupts = <37>;
450 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART1)>;
451 status = "disabled";
452 dmas = <&dma2 2 4 0x400 0x0>,
453 <&dma2 7 4 0x400 0x0>;
454 dma-names = "rx", "tx";
455 };
456
457 usart6: serial@40011400 {
458 compatible = "st,stm32-uart";
459 reg = <0x40011400 0x400>;
460 interrupts = <71>;
461 clocks = <&rcc 0 STM32F4_APB2_CLOCK(USART6)>;
462 status = "disabled";
463 };
464
465 adc: adc@40012000 {
466 compatible = "st,stm32f4-adc-core";
467 reg = <0x40012000 0x400>;
468 interrupts = <18>;
469 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
470 clock-names = "adc";
471 interrupt-controller;
472 #interrupt-cells = <1>;
473 #address-cells = <1>;
474 #size-cells = <0>;
475 status = "disabled";
476
477 adc1: adc@0 {
478 compatible = "st,stm32f4-adc";
479 #io-channel-cells = <1>;
480 reg = <0x0>;
481 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC1)>;
482 interrupt-parent = <&adc>;
483 interrupts = <0>;
484 dmas = <&dma2 0 0 0x400 0x0>;
485 dma-names = "rx";
486 status = "disabled";
487 };
488
489 adc2: adc@100 {
490 compatible = "st,stm32f4-adc";
491 #io-channel-cells = <1>;
492 reg = <0x100>;
493 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC2)>;
494 interrupt-parent = <&adc>;
495 interrupts = <1>;
496 dmas = <&dma2 3 1 0x400 0x0>;
497 dma-names = "rx";
498 status = "disabled";
499 };
500
501 adc3: adc@200 {
502 compatible = "st,stm32f4-adc";
503 #io-channel-cells = <1>;
504 reg = <0x200>;
505 clocks = <&rcc 0 STM32F4_APB2_CLOCK(ADC3)>;
506 interrupt-parent = <&adc>;
507 interrupts = <2>;
508 dmas = <&dma2 1 2 0x400 0x0>;
509 dma-names = "rx";
510 status = "disabled";
511 };
512 };
513
514 sdio: sdio@40012c00 {
515 compatible = "arm,pl180", "arm,primecell";
516 arm,primecell-periphid = <0x00880180>;
517 reg = <0x40012c00 0x400>;
518 clocks = <&rcc 0 STM32F4_APB2_CLOCK(SDIO)>;
519 clock-names = "apb_pclk";
520 interrupts = <49>;
521 max-frequency = <48000000>;
522 status = "disabled";
523 };
524
525 syscfg: system-config@40013800 {
526 compatible = "syscon";
527 reg = <0x40013800 0x400>;
528 };
529
530 exti: interrupt-controller@40013c00 {
531 compatible = "st,stm32-exti";
532 interrupt-controller;
533 #interrupt-cells = <2>;
534 reg = <0x40013C00 0x400>;
535 interrupts = <1>, <2>, <3>, <6>, <7>, <8>, <9>, <10>, <23>, <40>, <41>, <42>, <62>, <76>;
536 };
537
538 timers9: timers@40014000 {
539 #address-cells = <1>;
540 #size-cells = <0>;
541 compatible = "st,stm32-timers";
542 reg = <0x40014000 0x400>;
543 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM9)>;
544 clock-names = "int";
545 status = "disabled";
546
547 pwm {
548 compatible = "st,stm32-pwm";
549 status = "disabled";
550 };
551
552 timer@8 {
553 compatible = "st,stm32-timer-trigger";
554 reg = <8>;
555 status = "disabled";
556 };
557 };
558
559 timers10: timers@40014400 {
560 #address-cells = <1>;
561 #size-cells = <0>;
562 compatible = "st,stm32-timers";
563 reg = <0x40014400 0x400>;
564 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM10)>;
565 clock-names = "int";
566 status = "disabled";
567
568 pwm {
569 compatible = "st,stm32-pwm";
570 status = "disabled";
571 };
572 };
573
574 timers11: timers@40014800 {
575 #address-cells = <1>;
576 #size-cells = <0>;
577 compatible = "st,stm32-timers";
578 reg = <0x40014800 0x400>;
579 clocks = <&rcc 0 STM32F4_APB2_CLOCK(TIM11)>;
580 clock-names = "int";
581 status = "disabled";
582
583 pwm {
584 compatible = "st,stm32-pwm";
585 status = "disabled";
586 };
587 };
588
589 pwrcfg: power-config@40007000 {
590 compatible = "syscon";
591 reg = <0x40007000 0x400>;
592 };
593
594 ltdc: display-controller@40016800 {
595 compatible = "st,stm32-ltdc";
596 reg = <0x40016800 0x200>;
597 interrupts = <88>, <89>;
598 resets = <&rcc STM32F4_APB2_RESET(LTDC)>;
599 clocks = <&rcc 1 CLK_LCD>;
600 clock-names = "lcd";
601 status = "disabled";
602 };
603
604 crc: crc@40023000 {
605 compatible = "st,stm32f4-crc";
606 reg = <0x40023000 0x400>;
607 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(CRC)>;
608 status = "disabled";
609 };
610
611 rcc: rcc@40023810 {
612 #reset-cells = <1>;
613 #clock-cells = <2>;
614 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
615 reg = <0x40023800 0x400>;
616 clocks = <&clk_hse>, <&clk_i2s_ckin>;
617 st,syscfg = <&pwrcfg>;
618 assigned-clocks = <&rcc 1 CLK_HSE_RTC>;
619 assigned-clock-rates = <1000000>;
620 };
621
622 dma1: dma-controller@40026000 {
623 compatible = "st,stm32-dma";
624 reg = <0x40026000 0x400>;
625 interrupts = <11>,
626 <12>,
627 <13>,
628 <14>,
629 <15>,
630 <16>,
631 <17>,
632 <47>;
633 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA1)>;
634 #dma-cells = <4>;
635 };
636
637 dma2: dma-controller@40026400 {
638 compatible = "st,stm32-dma";
639 reg = <0x40026400 0x400>;
640 interrupts = <56>,
641 <57>,
642 <58>,
643 <59>,
644 <60>,
645 <68>,
646 <69>,
647 <70>;
648 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(DMA2)>;
649 #dma-cells = <4>;
650 st,mem2mem;
651 };
652
653 mac: ethernet@40028000 {
654 compatible = "st,stm32-dwmac", "snps,dwmac-3.50a";
655 reg = <0x40028000 0x8000>;
656 reg-names = "stmmaceth";
657 interrupts = <61>;
658 interrupt-names = "macirq";
659 clock-names = "stmmaceth", "mac-clk-tx", "mac-clk-rx";
660 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(ETHMAC)>,
661 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACTX)>,
662 <&rcc 0 STM32F4_AHB1_CLOCK(ETHMACRX)>;
663 st,syscon = <&syscfg 0x4>;
664 snps,pbl = <8>;
665 snps,mixed-burst;
666 status = "disabled";
667 };
668
669 usbotg_hs: usb@40040000 {
670 compatible = "snps,dwc2";
671 reg = <0x40040000 0x40000>;
672 interrupts = <77>;
673 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(OTGHS)>;
674 clock-names = "otg";
675 status = "disabled";
676 };
677
678 usbotg_fs: usb@50000000 {
679 compatible = "st,stm32f4x9-fsotg";
680 reg = <0x50000000 0x40000>;
681 interrupts = <67>;
682 clocks = <&rcc 0 39>;
683 clock-names = "otg";
684 status = "disabled";
685 };
686
687 dcmi: dcmi@50050000 {
688 compatible = "st,stm32-dcmi";
689 reg = <0x50050000 0x400>;
690 interrupts = <78>;
691 resets = <&rcc STM32F4_AHB2_RESET(DCMI)>;
692 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(DCMI)>;
693 clock-names = "mclk";
694 pinctrl-names = "default";
695 pinctrl-0 = <&dcmi_pins>;
696 dmas = <&dma2 1 1 0x414 0x3>;
697 dma-names = "tx";
698 status = "disabled";
699 };
700
701 rng: rng@50060800 {
702 compatible = "st,stm32-rng";
703 reg = <0x50060800 0x400>;
704 interrupts = <80>;
705 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(RNG)>;
706
707 };
708 };
709};
710
711&systick {
712 clocks = <&rcc 1 SYSTICK>;
713 status = "okay";
714};