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1/*
2 * Device Tree Source for the SH73A0 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11#include <dt-bindings/clock/sh73a0-clock.h>
12#include <dt-bindings/interrupt-controller/arm-gic.h>
13#include <dt-bindings/interrupt-controller/irq.h>
14
15/ {
16 compatible = "renesas,sh73a0";
17 interrupt-parent = <&gic>;
18 #address-cells = <1>;
19 #size-cells = <1>;
20
21 cpus {
22 #address-cells = <1>;
23 #size-cells = <0>;
24
25 cpu@0 {
26 device_type = "cpu";
27 compatible = "arm,cortex-a9";
28 reg = <0>;
29 clock-frequency = <1196000000>;
30 clocks = <&cpg_clocks SH73A0_CLK_Z>;
31 power-domains = <&pd_a2sl>;
32 next-level-cache = <&L2>;
33 };
34 cpu@1 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a9";
37 reg = <1>;
38 clock-frequency = <1196000000>;
39 clocks = <&cpg_clocks SH73A0_CLK_Z>;
40 power-domains = <&pd_a2sl>;
41 next-level-cache = <&L2>;
42 };
43 };
44
45 timer@f0000600 {
46 compatible = "arm,cortex-a9-twd-timer";
47 reg = <0xf0000600 0x20>;
48 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
49 clocks = <&twd_clk>;
50 };
51
52 gic: interrupt-controller@f0001000 {
53 compatible = "arm,cortex-a9-gic";
54 #interrupt-cells = <3>;
55 interrupt-controller;
56 reg = <0xf0001000 0x1000>,
57 <0xf0000100 0x100>;
58 };
59
60 L2: cache-controller@f0100000 {
61 compatible = "arm,pl310-cache";
62 reg = <0xf0100000 0x1000>;
63 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
64 power-domains = <&pd_a3sm>;
65 arm,data-latency = <3 3 3>;
66 arm,tag-latency = <2 2 2>;
67 arm,shared-override;
68 cache-unified;
69 cache-level = <2>;
70 };
71
72 sbsc2: memory-controller@fb400000 {
73 compatible = "renesas,sbsc-sh73a0";
74 reg = <0xfb400000 0x400>;
75 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
76 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
77 interrupt-names = "sec", "temp";
78 power-domains = <&pd_a4bc1>;
79 };
80
81 sbsc1: memory-controller@fe400000 {
82 compatible = "renesas,sbsc-sh73a0";
83 reg = <0xfe400000 0x400>;
84 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
85 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
86 interrupt-names = "sec", "temp";
87 power-domains = <&pd_a4bc0>;
88 };
89
90 pmu {
91 compatible = "arm,cortex-a9-pmu";
92 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
93 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
94 };
95
96 cmt1: timer@e6138000 {
97 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
98 reg = <0xe6138000 0x200>;
99 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
100 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
101 clock-names = "fck";
102 power-domains = <&pd_c5>;
103 status = "disabled";
104 };
105
106 irqpin0: interrupt-controller@e6900000 {
107 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
108 #interrupt-cells = <2>;
109 interrupt-controller;
110 reg = <0xe6900000 4>,
111 <0xe6900010 4>,
112 <0xe6900020 1>,
113 <0xe6900040 1>,
114 <0xe6900060 1>;
115 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
116 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
117 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
118 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH
119 GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH
120 GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH
121 GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH
122 GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
124 power-domains = <&pd_a4s>;
125 control-parent;
126 };
127
128 irqpin1: interrupt-controller@e6900004 {
129 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
130 #interrupt-cells = <2>;
131 interrupt-controller;
132 reg = <0xe6900004 4>,
133 <0xe6900014 4>,
134 <0xe6900024 1>,
135 <0xe6900044 1>,
136 <0xe6900064 1>;
137 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH
138 GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH
139 GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH
140 GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH
141 GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH
142 GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH
143 GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH
144 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
146 power-domains = <&pd_a4s>;
147 control-parent;
148 };
149
150 irqpin2: interrupt-controller@e6900008 {
151 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
152 #interrupt-cells = <2>;
153 interrupt-controller;
154 reg = <0xe6900008 4>,
155 <0xe6900018 4>,
156 <0xe6900028 1>,
157 <0xe6900048 1>,
158 <0xe6900068 1>;
159 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH
160 GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
161 GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH
162 GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH
163 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH
164 GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH
165 GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH
166 GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
168 power-domains = <&pd_a4s>;
169 control-parent;
170 };
171
172 irqpin3: interrupt-controller@e690000c {
173 compatible = "renesas,intc-irqpin-sh73a0", "renesas,intc-irqpin";
174 #interrupt-cells = <2>;
175 interrupt-controller;
176 reg = <0xe690000c 4>,
177 <0xe690001c 4>,
178 <0xe690002c 1>,
179 <0xe690004c 1>,
180 <0xe690006c 1>;
181 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH
182 GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH
183 GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH
184 GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH
185 GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH
186 GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH
187 GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH
188 GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
189 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
190 power-domains = <&pd_a4s>;
191 control-parent;
192 };
193
194 i2c0: i2c@e6820000 {
195 #address-cells = <1>;
196 #size-cells = <0>;
197 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
198 reg = <0xe6820000 0x425>;
199 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH
200 GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH
201 GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH
202 GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
204 power-domains = <&pd_a3sp>;
205 status = "disabled";
206 };
207
208 i2c1: i2c@e6822000 {
209 #address-cells = <1>;
210 #size-cells = <0>;
211 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
212 reg = <0xe6822000 0x425>;
213 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH
214 GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH
215 GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH
216 GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
217 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
218 power-domains = <&pd_a3sp>;
219 status = "disabled";
220 };
221
222 i2c2: i2c@e6824000 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
226 reg = <0xe6824000 0x425>;
227 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH
228 GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH
229 GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH
230 GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
232 power-domains = <&pd_a3sp>;
233 status = "disabled";
234 };
235
236 i2c3: i2c@e6826000 {
237 #address-cells = <1>;
238 #size-cells = <0>;
239 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
240 reg = <0xe6826000 0x425>;
241 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH
242 GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH
243 GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH
244 GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
245 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
246 power-domains = <&pd_a3sp>;
247 status = "disabled";
248 };
249
250 i2c4: i2c@e6828000 {
251 #address-cells = <1>;
252 #size-cells = <0>;
253 compatible = "renesas,iic-sh73a0", "renesas,rmobile-iic";
254 reg = <0xe6828000 0x425>;
255 interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH
256 GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH
257 GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH
258 GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
260 power-domains = <&pd_c5>;
261 status = "disabled";
262 };
263
264 mmcif: mmc@e6bd0000 {
265 compatible = "renesas,mmcif-sh73a0", "renesas,sh-mmcif";
266 reg = <0xe6bd0000 0x100>;
267 interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
268 GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
269 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
270 power-domains = <&pd_a3sp>;
271 reg-io-width = <4>;
272 status = "disabled";
273 };
274
275 msiof0: spi@e6e20000 {
276 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
277 reg = <0xe6e20000 0x0064>;
278 interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&mstp0_clks SH73A0_CLK_MSIOF0>;
280 power-domains = <&pd_a3sp>;
281 #address-cells = <1>;
282 #size-cells = <0>;
283 status = "disabled";
284 };
285
286 msiof1: spi@e6e10000 {
287 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
288 reg = <0xe6e10000 0x0064>;
289 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
290 clocks = <&mstp2_clks SH73A0_CLK_MSIOF1>;
291 power-domains = <&pd_a3sp>;
292 #address-cells = <1>;
293 #size-cells = <0>;
294 status = "disabled";
295 };
296
297 msiof2: spi@e6e00000 {
298 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
299 reg = <0xe6e00000 0x0064>;
300 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
301 clocks = <&mstp2_clks SH73A0_CLK_MSIOF2>;
302 power-domains = <&pd_a3sp>;
303 #address-cells = <1>;
304 #size-cells = <0>;
305 status = "disabled";
306 };
307
308 msiof3: spi@e6c90000 {
309 compatible = "renesas,msiof-sh73a0", "renesas,sh-mobile-msiof";
310 reg = <0xe6c90000 0x0064>;
311 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
312 clocks = <&mstp2_clks SH73A0_CLK_MSIOF3>;
313 power-domains = <&pd_a3sp>;
314 #address-cells = <1>;
315 #size-cells = <0>;
316 status = "disabled";
317 };
318
319 sdhi0: sd@ee100000 {
320 compatible = "renesas,sdhi-sh73a0";
321 reg = <0xee100000 0x100>;
322 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH
323 GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH
324 GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
326 power-domains = <&pd_a3sp>;
327 cap-sd-highspeed;
328 status = "disabled";
329 };
330
331 /* SDHI1 and SDHI2 have no CD pins, no need for CD IRQ */
332 sdhi1: sd@ee120000 {
333 compatible = "renesas,sdhi-sh73a0";
334 reg = <0xee120000 0x100>;
335 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH
336 GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
338 power-domains = <&pd_a3sp>;
339 toshiba,mmc-wrprotect-disable;
340 cap-sd-highspeed;
341 status = "disabled";
342 };
343
344 sdhi2: sd@ee140000 {
345 compatible = "renesas,sdhi-sh73a0";
346 reg = <0xee140000 0x100>;
347 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH
348 GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
350 power-domains = <&pd_a3sp>;
351 toshiba,mmc-wrprotect-disable;
352 cap-sd-highspeed;
353 status = "disabled";
354 };
355
356 scifa0: serial@e6c40000 {
357 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
358 reg = <0xe6c40000 0x100>;
359 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
361 clock-names = "fck";
362 power-domains = <&pd_a3sp>;
363 status = "disabled";
364 };
365
366 scifa1: serial@e6c50000 {
367 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
368 reg = <0xe6c50000 0x100>;
369 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
370 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
371 clock-names = "fck";
372 power-domains = <&pd_a3sp>;
373 status = "disabled";
374 };
375
376 scifa2: serial@e6c60000 {
377 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
378 reg = <0xe6c60000 0x100>;
379 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
380 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
381 clock-names = "fck";
382 power-domains = <&pd_a3sp>;
383 status = "disabled";
384 };
385
386 scifa3: serial@e6c70000 {
387 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
388 reg = <0xe6c70000 0x100>;
389 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
390 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
391 clock-names = "fck";
392 power-domains = <&pd_a3sp>;
393 status = "disabled";
394 };
395
396 scifa4: serial@e6c80000 {
397 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
398 reg = <0xe6c80000 0x100>;
399 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
400 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
401 clock-names = "fck";
402 power-domains = <&pd_a3sp>;
403 status = "disabled";
404 };
405
406 scifa5: serial@e6cb0000 {
407 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
408 reg = <0xe6cb0000 0x100>;
409 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
410 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
411 clock-names = "fck";
412 power-domains = <&pd_a3sp>;
413 status = "disabled";
414 };
415
416 scifa6: serial@e6cc0000 {
417 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
418 reg = <0xe6cc0000 0x100>;
419 interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
420 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
421 clock-names = "fck";
422 power-domains = <&pd_a3sp>;
423 status = "disabled";
424 };
425
426 scifa7: serial@e6cd0000 {
427 compatible = "renesas,scifa-sh73a0", "renesas,scifa";
428 reg = <0xe6cd0000 0x100>;
429 interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
430 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
431 clock-names = "fck";
432 power-domains = <&pd_a3sp>;
433 status = "disabled";
434 };
435
436 scifb: serial@e6c30000 {
437 compatible = "renesas,scifb-sh73a0", "renesas,scifb";
438 reg = <0xe6c30000 0x100>;
439 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
440 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
441 clock-names = "fck";
442 power-domains = <&pd_a3sp>;
443 status = "disabled";
444 };
445
446 pfc: pin-controller@e6050000 {
447 compatible = "renesas,pfc-sh73a0";
448 reg = <0xe6050000 0x8000>,
449 <0xe605801c 0x1c>;
450 gpio-controller;
451 #gpio-cells = <2>;
452 gpio-ranges =
453 <&pfc 0 0 119>, <&pfc 128 128 37>, <&pfc 192 192 91>,
454 <&pfc 288 288 22>;
455 interrupts-extended =
456 <&irqpin0 0 0>, <&irqpin0 1 0>, <&irqpin0 2 0>, <&irqpin0 3 0>,
457 <&irqpin0 4 0>, <&irqpin0 5 0>, <&irqpin0 6 0>, <&irqpin0 7 0>,
458 <&irqpin1 0 0>, <&irqpin1 1 0>, <&irqpin1 2 0>, <&irqpin1 3 0>,
459 <&irqpin1 4 0>, <&irqpin1 5 0>, <&irqpin1 6 0>, <&irqpin1 7 0>,
460 <&irqpin2 0 0>, <&irqpin2 1 0>, <&irqpin2 2 0>, <&irqpin2 3 0>,
461 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
462 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
463 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
464 power-domains = <&pd_c5>;
465 };
466
467 sysc: system-controller@e6180000 {
468 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
469 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
470
471 pm-domains {
472 pd_c5: c5 {
473 #address-cells = <1>;
474 #size-cells = <0>;
475 #power-domain-cells = <0>;
476
477 pd_c4: c4@0 {
478 reg = <0>;
479 #power-domain-cells = <0>;
480 };
481
482 pd_d4: d4@1 {
483 reg = <1>;
484 #power-domain-cells = <0>;
485 };
486
487 pd_a4bc0: a4bc0@4 {
488 reg = <4>;
489 #power-domain-cells = <0>;
490 };
491
492 pd_a4bc1: a4bc1@5 {
493 reg = <5>;
494 #power-domain-cells = <0>;
495 };
496
497 pd_a4lc0: a4lc0@6 {
498 reg = <6>;
499 #power-domain-cells = <0>;
500 };
501
502 pd_a4lc1: a4lc1@7 {
503 reg = <7>;
504 #power-domain-cells = <0>;
505 };
506
507 pd_a4mp: a4mp@8 {
508 reg = <8>;
509 #address-cells = <1>;
510 #size-cells = <0>;
511 #power-domain-cells = <0>;
512
513 pd_a3mp: a3mp@9 {
514 reg = <9>;
515 #power-domain-cells = <0>;
516 };
517
518 pd_a3vc: a3vc@10 {
519 reg = <10>;
520 #power-domain-cells = <0>;
521 };
522 };
523
524 pd_a4rm: a4rm@12 {
525 reg = <12>;
526 #address-cells = <1>;
527 #size-cells = <0>;
528 #power-domain-cells = <0>;
529
530 pd_a3r: a3r@13 {
531 reg = <13>;
532 #address-cells = <1>;
533 #size-cells = <0>;
534 #power-domain-cells = <0>;
535
536 pd_a2rv: a2rv@14 {
537 reg = <14>;
538 #address-cells = <1>;
539 #size-cells = <0>;
540 #power-domain-cells = <0>;
541 };
542 };
543 };
544
545 pd_a4s: a4s@16 {
546 reg = <16>;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 #power-domain-cells = <0>;
550
551 pd_a3sp: a3sp@17 {
552 reg = <17>;
553 #power-domain-cells = <0>;
554 };
555
556 pd_a3sg: a3sg@18 {
557 reg = <18>;
558 #power-domain-cells = <0>;
559 };
560
561 pd_a3sm: a3sm@19 {
562 reg = <19>;
563 #address-cells = <1>;
564 #size-cells = <0>;
565 #power-domain-cells = <0>;
566
567 pd_a2sl: a2sl@20 {
568 reg = <20>;
569 #power-domain-cells = <0>;
570 };
571 };
572 };
573 };
574 };
575 };
576
577 sh_fsi2: sound@ec230000 {
578 #sound-dai-cells = <1>;
579 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
580 reg = <0xec230000 0x400>;
581 interrupts = <GIC_SPI 146 0x4>;
582 power-domains = <&pd_a4mp>;
583 status = "disabled";
584 };
585
586 bsc: bus@fec10000 {
587 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
588 "simple-pm-bus";
589 #address-cells = <1>;
590 #size-cells = <1>;
591 ranges = <0 0 0x20000000>;
592 reg = <0xfec10000 0x400>;
593 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&zb_clk>;
595 power-domains = <&pd_a4s>;
596 };
597
598 clocks {
599 #address-cells = <1>;
600 #size-cells = <1>;
601 ranges;
602
603 /* External root clocks */
604 extalr_clk: extalr {
605 compatible = "fixed-clock";
606 #clock-cells = <0>;
607 clock-frequency = <32768>;
608 };
609 extal1_clk: extal1 {
610 compatible = "fixed-clock";
611 #clock-cells = <0>;
612 clock-frequency = <26000000>;
613 };
614 extal2_clk: extal2 {
615 compatible = "fixed-clock";
616 #clock-cells = <0>;
617 };
618 extcki_clk: extcki {
619 compatible = "fixed-clock";
620 #clock-cells = <0>;
621 };
622 fsiack_clk: fsiack {
623 compatible = "fixed-clock";
624 #clock-cells = <0>;
625 clock-frequency = <0>;
626 };
627 fsibck_clk: fsibck {
628 compatible = "fixed-clock";
629 #clock-cells = <0>;
630 clock-frequency = <0>;
631 };
632
633 /* Special CPG clocks */
634 cpg_clocks: cpg_clocks@e6150000 {
635 compatible = "renesas,sh73a0-cpg-clocks";
636 reg = <0xe6150000 0x10000>;
637 clocks = <&extal1_clk>, <&extal2_clk>;
638 #clock-cells = <1>;
639 clock-output-names = "main", "pll0", "pll1", "pll2",
640 "pll3", "dsi0phy", "dsi1phy",
641 "zg", "m3", "b", "m1", "m2",
642 "z", "zx", "hp";
643 };
644
645 /* Variable factor clocks (DIV6) */
646 vclk1_clk: vclk1@e6150008 {
647 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
648 reg = <0xe6150008 4>;
649 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
650 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
651 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
652 <0>;
653 #clock-cells = <0>;
654 };
655 vclk2_clk: vclk2@e615000c {
656 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
657 reg = <0xe615000c 4>;
658 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
659 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
660 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
661 <0>;
662 #clock-cells = <0>;
663 };
664 vclk3_clk: vclk3@e615001c {
665 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
666 reg = <0xe615001c 4>;
667 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
668 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
669 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
670 <0>;
671 #clock-cells = <0>;
672 };
673 zb_clk: zb_clk@e6150010 {
674 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
675 reg = <0xe6150010 4>;
676 clocks = <&pll1_div2_clk>, <0>,
677 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
678 #clock-cells = <0>;
679 clock-output-names = "zb";
680 };
681 flctl_clk: flctlck@e6150014 {
682 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
683 reg = <0xe6150014 4>;
684 clocks = <&pll1_div2_clk>, <0>,
685 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
686 #clock-cells = <0>;
687 };
688 sdhi0_clk: sdhi0ck@e6150074 {
689 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
690 reg = <0xe6150074 4>;
691 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
692 <&pll1_div13_clk>, <0>;
693 #clock-cells = <0>;
694 };
695 sdhi1_clk: sdhi1ck@e6150078 {
696 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
697 reg = <0xe6150078 4>;
698 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
699 <&pll1_div13_clk>, <0>;
700 #clock-cells = <0>;
701 };
702 sdhi2_clk: sdhi2ck@e615007c {
703 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
704 reg = <0xe615007c 4>;
705 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
706 <&pll1_div13_clk>, <0>;
707 #clock-cells = <0>;
708 };
709 fsia_clk: fsia@e6150018 {
710 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
711 reg = <0xe6150018 4>;
712 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
713 <&fsiack_clk>, <&fsiack_clk>;
714 #clock-cells = <0>;
715 };
716 fsib_clk: fsib@e6150090 {
717 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
718 reg = <0xe6150090 4>;
719 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
720 <&fsibck_clk>, <&fsibck_clk>;
721 #clock-cells = <0>;
722 };
723 sub_clk: sub@e6150080 {
724 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
725 reg = <0xe6150080 4>;
726 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
727 <&extal2_clk>, <&extal2_clk>;
728 #clock-cells = <0>;
729 };
730 spua_clk: spua@e6150084 {
731 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
732 reg = <0xe6150084 4>;
733 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
734 <&extal2_clk>, <&extal2_clk>;
735 #clock-cells = <0>;
736 };
737 spuv_clk: spuv@e6150094 {
738 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
739 reg = <0xe6150094 4>;
740 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
741 <&extal2_clk>, <&extal2_clk>;
742 #clock-cells = <0>;
743 };
744 msu_clk: msu@e6150088 {
745 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
746 reg = <0xe6150088 4>;
747 clocks = <&pll1_div2_clk>, <0>,
748 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
749 #clock-cells = <0>;
750 };
751 hsi_clk: hsi@e615008c {
752 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
753 reg = <0xe615008c 4>;
754 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
755 <&pll1_div7_clk>, <0>;
756 #clock-cells = <0>;
757 };
758 mfg1_clk: mfg1@e6150098 {
759 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
760 reg = <0xe6150098 4>;
761 clocks = <&pll1_div2_clk>, <0>,
762 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
763 #clock-cells = <0>;
764 };
765 mfg2_clk: mfg2@e615009c {
766 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
767 reg = <0xe615009c 4>;
768 clocks = <&pll1_div2_clk>, <0>,
769 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
770 #clock-cells = <0>;
771 };
772 dsit_clk: dsit@e6150060 {
773 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
774 reg = <0xe6150060 4>;
775 clocks = <&pll1_div2_clk>, <0>,
776 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
777 #clock-cells = <0>;
778 };
779 dsi0p_clk: dsi0pck@e6150064 {
780 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
781 reg = <0xe6150064 4>;
782 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
783 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
784 <&extcki_clk>, <0>, <0>, <0>;
785 #clock-cells = <0>;
786 };
787
788 /* Fixed factor clocks */
789 main_div2_clk: main_div2 {
790 compatible = "fixed-factor-clock";
791 clocks = <&cpg_clocks SH73A0_CLK_MAIN>;
792 #clock-cells = <0>;
793 clock-div = <2>;
794 clock-mult = <1>;
795 };
796 pll1_div2_clk: pll1_div2 {
797 compatible = "fixed-factor-clock";
798 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
799 #clock-cells = <0>;
800 clock-div = <2>;
801 clock-mult = <1>;
802 };
803 pll1_div7_clk: pll1_div7 {
804 compatible = "fixed-factor-clock";
805 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
806 #clock-cells = <0>;
807 clock-div = <7>;
808 clock-mult = <1>;
809 };
810 pll1_div13_clk: pll1_div13 {
811 compatible = "fixed-factor-clock";
812 clocks = <&cpg_clocks SH73A0_CLK_PLL1>;
813 #clock-cells = <0>;
814 clock-div = <13>;
815 clock-mult = <1>;
816 };
817 twd_clk: twd {
818 compatible = "fixed-factor-clock";
819 clocks = <&cpg_clocks SH73A0_CLK_Z>;
820 #clock-cells = <0>;
821 clock-div = <4>;
822 clock-mult = <1>;
823 };
824
825 /* Gate clocks */
826 mstp0_clks: mstp0_clks@e6150130 {
827 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
828 reg = <0xe6150130 4>, <0xe6150030 4>;
829 clocks = <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>;
830 #clock-cells = <1>;
831 clock-indices = <
832 SH73A0_CLK_IIC2 SH73A0_CLK_MSIOF0
833 >;
834 clock-output-names =
835 "iic2", "msiof0";
836 };
837 mstp1_clks: mstp1_clks@e6150134 {
838 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
839 reg = <0xe6150134 4>, <0xe6150038 4>;
840 clocks = <&cpg_clocks SH73A0_CLK_B>,
841 <&cpg_clocks SH73A0_CLK_B>,
842 <&cpg_clocks SH73A0_CLK_B>,
843 <&cpg_clocks SH73A0_CLK_B>,
844 <&sub_clk>, <&cpg_clocks SH73A0_CLK_B>,
845 <&cpg_clocks SH73A0_CLK_HP>,
846 <&cpg_clocks SH73A0_CLK_ZG>,
847 <&cpg_clocks SH73A0_CLK_B>;
848 #clock-cells = <1>;
849 clock-indices = <
850 SH73A0_CLK_CEU1 SH73A0_CLK_CSI2_RX1
851 SH73A0_CLK_CEU0 SH73A0_CLK_CSI2_RX0
852 SH73A0_CLK_TMU0 SH73A0_CLK_DSITX0
853 SH73A0_CLK_IIC0 SH73A0_CLK_SGX
854 SH73A0_CLK_LCDC0
855 >;
856 clock-output-names =
857 "ceu1", "csi2_rx1", "ceu0", "csi2_rx0",
858 "tmu0", "dsitx0", "iic0", "sgx", "lcdc0";
859 };
860 mstp2_clks: mstp2_clks@e6150138 {
861 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
862 reg = <0xe6150138 4>, <0xe6150040 4>;
863 clocks = <&sub_clk>, <&cpg_clocks SH73A0_CLK_HP>,
864 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
865 <&sub_clk>, <&sub_clk>, <&sub_clk>,
866 <&sub_clk>, <&sub_clk>, <&sub_clk>,
867 <&sub_clk>, <&sub_clk>, <&sub_clk>;
868 #clock-cells = <1>;
869 clock-indices = <
870 SH73A0_CLK_SCIFA7 SH73A0_CLK_SY_DMAC
871 SH73A0_CLK_MP_DMAC SH73A0_CLK_MSIOF3
872 SH73A0_CLK_MSIOF1 SH73A0_CLK_SCIFA5
873 SH73A0_CLK_SCIFB SH73A0_CLK_MSIOF2
874 SH73A0_CLK_SCIFA0 SH73A0_CLK_SCIFA1
875 SH73A0_CLK_SCIFA2 SH73A0_CLK_SCIFA3
876 SH73A0_CLK_SCIFA4
877 >;
878 clock-output-names =
879 "scifa7", "sy_dmac", "mp_dmac", "msiof3",
880 "msiof1", "scifa5", "scifb", "msiof2",
881 "scifa0", "scifa1", "scifa2", "scifa3",
882 "scifa4";
883 };
884 mstp3_clks: mstp3_clks@e615013c {
885 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
886 reg = <0xe615013c 4>, <0xe6150048 4>;
887 clocks = <&sub_clk>, <&extalr_clk>,
888 <&cpg_clocks SH73A0_CLK_HP>, <&sub_clk>,
889 <&cpg_clocks SH73A0_CLK_HP>,
890 <&cpg_clocks SH73A0_CLK_HP>, <&flctl_clk>,
891 <&sdhi0_clk>, <&sdhi1_clk>,
892 <&cpg_clocks SH73A0_CLK_HP>, <&sdhi2_clk>,
893 <&main_div2_clk>, <&main_div2_clk>,
894 <&main_div2_clk>, <&main_div2_clk>,
895 <&main_div2_clk>;
896 #clock-cells = <1>;
897 clock-indices = <
898 SH73A0_CLK_SCIFA6 SH73A0_CLK_CMT1
899 SH73A0_CLK_FSI SH73A0_CLK_IRDA
900 SH73A0_CLK_IIC1 SH73A0_CLK_USB SH73A0_CLK_FLCTL
901 SH73A0_CLK_SDHI0 SH73A0_CLK_SDHI1
902 SH73A0_CLK_MMCIF0 SH73A0_CLK_SDHI2
903 SH73A0_CLK_TPU0 SH73A0_CLK_TPU1
904 SH73A0_CLK_TPU2 SH73A0_CLK_TPU3
905 SH73A0_CLK_TPU4
906 >;
907 clock-output-names =
908 "scifa6", "cmt1", "fsi", "irda", "iic1",
909 "usb", "flctl", "sdhi0", "sdhi1", "mmcif0", "sdhi2",
910 "tpu0", "tpu1", "tpu2", "tpu3", "tpu4";
911 };
912 mstp4_clks: mstp4_clks@e6150140 {
913 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
914 reg = <0xe6150140 4>, <0xe615004c 4>;
915 clocks = <&cpg_clocks SH73A0_CLK_HP>,
916 <&cpg_clocks SH73A0_CLK_HP>, <&extalr_clk>;
917 #clock-cells = <1>;
918 clock-indices = <
919 SH73A0_CLK_IIC3 SH73A0_CLK_IIC4
920 SH73A0_CLK_KEYSC
921 >;
922 clock-output-names =
923 "iic3", "iic4", "keysc";
924 };
925 mstp5_clks: mstp5_clks@e6150144 {
926 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
927 reg = <0xe6150144 4>, <0xe615003c 4>;
928 clocks = <&cpg_clocks SH73A0_CLK_HP>;
929 #clock-cells = <1>;
930 clock-indices = <
931 SH73A0_CLK_INTCA0
932 >;
933 clock-output-names =
934 "intca0";
935 };
936 };
937};