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1/*
2 * Device Tree Include file for Marvell Armada 1500 (Berlin BG2) SoC
3 *
4 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
5 *
6 * based on GPL'ed 2.6 kernel sources
7 * (c) Marvell International Ltd.
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 * a) This file is licensed under the terms of the GNU General Public
15 * License version 2. This program is licensed "as is" without any
16 * warranty of any kind, whether express or implied.
17 *
18 * Or, alternatively,
19 *
20 * b) Permission is hereby granted, free of charge, to any person
21 * obtaining a copy of this software and associated documentation
22 * files (the "Software"), to deal in the Software without
23 * restriction, including without limitation the rights to use,
24 * copy, modify, merge, publish, distribute, sublicense, and/or
25 * sell copies of the Software, and to permit persons to whom the
26 * Software is furnished to do so, subject to the following
27 * conditions:
28 *
29 * The above copyright notice and this permission notice shall be
30 * included in all copies or substantial portions of the Software.
31 *
32 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
33 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
34 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
35 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
36 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
37 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
38 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
39 * OTHER DEALINGS IN THE SOFTWARE.
40 */
41
42#include <dt-bindings/clock/berlin2.h>
43#include <dt-bindings/interrupt-controller/arm-gic.h>
44
45/ {
46 model = "Marvell Armada 1500 (BG2) SoC";
47 compatible = "marvell,berlin2", "marvell,berlin";
48 #address-cells = <1>;
49 #size-cells = <1>;
50
51 aliases {
52 serial0 = &uart0;
53 serial1 = &uart1;
54 serial2 = &uart2;
55 };
56
57 cpus {
58 #address-cells = <1>;
59 #size-cells = <0>;
60 enable-method = "marvell,berlin-smp";
61
62 cpu@0 {
63 compatible = "marvell,pj4b";
64 device_type = "cpu";
65 next-level-cache = <&l2>;
66 reg = <0>;
67
68 clocks = <&chip_clk CLKID_CPU>;
69 clock-latency = <100000>;
70 operating-points = <
71 /* kHz uV */
72 1200000 1200000
73 1000000 1200000
74 800000 1200000
75 600000 1200000
76 >;
77 };
78
79 cpu@1 {
80 compatible = "marvell,pj4b";
81 device_type = "cpu";
82 next-level-cache = <&l2>;
83 reg = <1>;
84 };
85 };
86
87 refclk: oscillator {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <25000000>;
91 };
92
93 soc@f7000000 {
94 compatible = "simple-bus";
95 #address-cells = <1>;
96 #size-cells = <1>;
97 interrupt-parent = <&gic>;
98
99 ranges = <0 0xf7000000 0x1000000>;
100
101 sdhci0: sdhci@ab0000 {
102 compatible = "mrvl,pxav3-mmc";
103 reg = <0xab0000 0x200>;
104 clocks = <&chip_clk CLKID_SDIO0XIN>, <&chip_clk CLKID_SDIO0>;
105 clock-names = "io", "core";
106 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
107 status = "disabled";
108 };
109
110 sdhci1: sdhci@ab0800 {
111 compatible = "mrvl,pxav3-mmc";
112 reg = <0xab0800 0x200>;
113 clocks = <&chip_clk CLKID_SDIO1XIN>, <&chip_clk CLKID_SDIO1>;
114 clock-names = "io", "core";
115 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
116 status = "disabled";
117 };
118
119 sdhci2: sdhci@ab1000 {
120 compatible = "mrvl,pxav3-mmc";
121 reg = <0xab1000 0x200>;
122 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
123 clocks = <&chip_clk CLKID_NFC_ECC>, <&chip_clk CLKID_NFC>;
124 clock-names = "io", "core";
125 pinctrl-0 = <&emmc_pmux>;
126 pinctrl-names = "default";
127 status = "disabled";
128 };
129
130 l2: l2-cache-controller@ac0000 {
131 compatible = "marvell,tauros3-cache", "arm,pl310-cache";
132 reg = <0xac0000 0x1000>;
133 cache-unified;
134 cache-level = <2>;
135 };
136
137 scu: snoop-control-unit@ad0000 {
138 compatible = "arm,cortex-a9-scu";
139 reg = <0xad0000 0x58>;
140 };
141
142 gic: interrupt-controller@ad1000 {
143 compatible = "arm,cortex-a9-gic";
144 reg = <0xad1000 0x1000>, <0xad0100 0x0100>;
145 interrupt-controller;
146 #interrupt-cells = <3>;
147 };
148
149 local-timer@ad0600 {
150 compatible = "arm,cortex-a9-twd-timer";
151 reg = <0xad0600 0x20>;
152 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
153 clocks = <&chip_clk CLKID_TWD>;
154 };
155
156 eth1: ethernet@b90000 {
157 compatible = "marvell,pxa168-eth";
158 reg = <0xb90000 0x10000>;
159 clocks = <&chip_clk CLKID_GETH1>;
160 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
161 /* set by bootloader */
162 local-mac-address = [00 00 00 00 00 00];
163 #address-cells = <1>;
164 #size-cells = <0>;
165 phy-connection-type = "mii";
166 phy-handle = <ðphy1>;
167 status = "disabled";
168
169 ethphy1: ethernet-phy@0 {
170 reg = <0>;
171 };
172 };
173
174 cpu-ctrl@dd0000 {
175 compatible = "marvell,berlin-cpu-ctrl";
176 reg = <0xdd0000 0x10000>;
177 };
178
179 eth0: ethernet@e50000 {
180 compatible = "marvell,pxa168-eth";
181 reg = <0xe50000 0x10000>;
182 clocks = <&chip_clk CLKID_GETH0>;
183 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
184 /* set by bootloader */
185 local-mac-address = [00 00 00 00 00 00];
186 #address-cells = <1>;
187 #size-cells = <0>;
188 phy-connection-type = "mii";
189 phy-handle = <ðphy0>;
190 status = "disabled";
191
192 ethphy0: ethernet-phy@0 {
193 reg = <0>;
194 };
195 };
196
197 apb@e80000 {
198 compatible = "simple-bus";
199 #address-cells = <1>;
200 #size-cells = <1>;
201
202 ranges = <0 0xe80000 0x10000>;
203 interrupt-parent = <&aic>;
204
205 gpio0: gpio@400 {
206 compatible = "snps,dw-apb-gpio";
207 reg = <0x0400 0x400>;
208 #address-cells = <1>;
209 #size-cells = <0>;
210
211 porta: gpio-port@0 {
212 compatible = "snps,dw-apb-gpio-port";
213 gpio-controller;
214 #gpio-cells = <2>;
215 snps,nr-gpios = <8>;
216 reg = <0>;
217 interrupt-controller;
218 #interrupt-cells = <2>;
219 interrupts = <0>;
220 };
221 };
222
223 gpio1: gpio@800 {
224 compatible = "snps,dw-apb-gpio";
225 reg = <0x0800 0x400>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228
229 portb: gpio-port@1 {
230 compatible = "snps,dw-apb-gpio-port";
231 gpio-controller;
232 #gpio-cells = <2>;
233 snps,nr-gpios = <8>;
234 reg = <0>;
235 interrupt-controller;
236 #interrupt-cells = <2>;
237 interrupts = <1>;
238 };
239 };
240
241 gpio2: gpio@c00 {
242 compatible = "snps,dw-apb-gpio";
243 reg = <0x0c00 0x400>;
244 #address-cells = <1>;
245 #size-cells = <0>;
246
247 portc: gpio-port@2 {
248 compatible = "snps,dw-apb-gpio-port";
249 gpio-controller;
250 #gpio-cells = <2>;
251 snps,nr-gpios = <8>;
252 reg = <0>;
253 interrupt-controller;
254 #interrupt-cells = <2>;
255 interrupts = <2>;
256 };
257 };
258
259 gpio3: gpio@1000 {
260 compatible = "snps,dw-apb-gpio";
261 reg = <0x1000 0x400>;
262 #address-cells = <1>;
263 #size-cells = <0>;
264
265 portd: gpio-port@3 {
266 compatible = "snps,dw-apb-gpio-port";
267 gpio-controller;
268 #gpio-cells = <2>;
269 snps,nr-gpios = <8>;
270 reg = <0>;
271 interrupt-controller;
272 #interrupt-cells = <2>;
273 interrupts = <3>;
274 };
275 };
276
277 timer0: timer@2c00 {
278 compatible = "snps,dw-apb-timer";
279 reg = <0x2c00 0x14>;
280 interrupts = <8>;
281 clocks = <&chip_clk CLKID_CFG>;
282 clock-names = "timer";
283 status = "okay";
284 };
285
286 timer1: timer@2c14 {
287 compatible = "snps,dw-apb-timer";
288 reg = <0x2c14 0x14>;
289 interrupts = <9>;
290 clocks = <&chip_clk CLKID_CFG>;
291 clock-names = "timer";
292 status = "okay";
293 };
294
295 timer2: timer@2c28 {
296 compatible = "snps,dw-apb-timer";
297 reg = <0x2c28 0x14>;
298 interrupts = <10>;
299 clocks = <&chip_clk CLKID_CFG>;
300 clock-names = "timer";
301 status = "disabled";
302 };
303
304 timer3: timer@2c3c {
305 compatible = "snps,dw-apb-timer";
306 reg = <0x2c3c 0x14>;
307 interrupts = <11>;
308 clocks = <&chip_clk CLKID_CFG>;
309 clock-names = "timer";
310 status = "disabled";
311 };
312
313 timer4: timer@2c50 {
314 compatible = "snps,dw-apb-timer";
315 reg = <0x2c50 0x14>;
316 interrupts = <12>;
317 clocks = <&chip_clk CLKID_CFG>;
318 clock-names = "timer";
319 status = "disabled";
320 };
321
322 timer5: timer@2c64 {
323 compatible = "snps,dw-apb-timer";
324 reg = <0x2c64 0x14>;
325 interrupts = <13>;
326 clocks = <&chip_clk CLKID_CFG>;
327 clock-names = "timer";
328 status = "disabled";
329 };
330
331 timer6: timer@2c78 {
332 compatible = "snps,dw-apb-timer";
333 reg = <0x2c78 0x14>;
334 interrupts = <14>;
335 clocks = <&chip_clk CLKID_CFG>;
336 clock-names = "timer";
337 status = "disabled";
338 };
339
340 timer7: timer@2c8c {
341 compatible = "snps,dw-apb-timer";
342 reg = <0x2c8c 0x14>;
343 interrupts = <15>;
344 clocks = <&chip_clk CLKID_CFG>;
345 clock-names = "timer";
346 status = "disabled";
347 };
348
349 aic: interrupt-controller@3000 {
350 compatible = "snps,dw-apb-ictl";
351 reg = <0x3000 0xc00>;
352 interrupt-controller;
353 #interrupt-cells = <1>;
354 interrupt-parent = <&gic>;
355 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
356 };
357 };
358
359 ahci: sata@e90000 {
360 compatible = "marvell,berlin2-ahci", "generic-ahci";
361 reg = <0xe90000 0x1000>;
362 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&chip_clk CLKID_SATA>;
364 #address-cells = <1>;
365 #size-cells = <0>;
366
367 sata0: sata-port@0 {
368 reg = <0>;
369 phys = <&sata_phy 0>;
370 status = "disabled";
371 };
372
373 sata1: sata-port@1 {
374 reg = <1>;
375 phys = <&sata_phy 1>;
376 status = "disabled";
377 };
378 };
379
380 sata_phy: phy@e900a0 {
381 compatible = "marvell,berlin2-sata-phy";
382 reg = <0xe900a0 0x200>;
383 clocks = <&chip_clk CLKID_SATA>;
384 #address-cells = <1>;
385 #size-cells = <0>;
386 #phy-cells = <1>;
387 status = "disabled";
388
389 sata-phy@0 {
390 reg = <0>;
391 };
392
393 sata-phy@1 {
394 reg = <1>;
395 };
396 };
397
398 chip: chip-control@ea0000 {
399 compatible = "simple-mfd", "syscon";
400 reg = <0xea0000 0x400>;
401
402 chip_clk: clock {
403 compatible = "marvell,berlin2-clk";
404 #clock-cells = <1>;
405 clocks = <&refclk>;
406 clock-names = "refclk";
407 };
408
409 soc_pinctrl: pin-controller {
410 compatible = "marvell,berlin2-soc-pinctrl";
411
412 emmc_pmux: emmc-pmux {
413 groups = "G26";
414 function = "emmc";
415 };
416 };
417
418 chip_rst: reset {
419 compatible = "marvell,berlin2-reset";
420 #reset-cells = <2>;
421 };
422 };
423
424 pwm: pwm@f20000 {
425 compatible = "marvell,berlin-pwm";
426 reg = <0xf20000 0x40>;
427 clocks = <&chip_clk CLKID_CFG>;
428 #pwm-cells = <3>;
429 };
430
431 apb@fc0000 {
432 compatible = "simple-bus";
433 #address-cells = <1>;
434 #size-cells = <1>;
435
436 ranges = <0 0xfc0000 0x10000>;
437 interrupt-parent = <&sic>;
438
439 wdt0: watchdog@1000 {
440 compatible = "snps,dw-wdt";
441 reg = <0x1000 0x100>;
442 clocks = <&refclk>;
443 interrupts = <0>;
444 };
445
446 wdt1: watchdog@2000 {
447 compatible = "snps,dw-wdt";
448 reg = <0x2000 0x100>;
449 clocks = <&refclk>;
450 interrupts = <1>;
451 };
452
453 wdt2: watchdog@3000 {
454 compatible = "snps,dw-wdt";
455 reg = <0x3000 0x100>;
456 clocks = <&refclk>;
457 interrupts = <2>;
458 };
459
460 sm_gpio1: gpio@5000 {
461 compatible = "snps,dw-apb-gpio";
462 reg = <0x5000 0x400>;
463 #address-cells = <1>;
464 #size-cells = <0>;
465
466 portf: gpio-port@5 {
467 compatible = "snps,dw-apb-gpio-port";
468 gpio-controller;
469 #gpio-cells = <2>;
470 snps,nr-gpios = <8>;
471 reg = <0>;
472 };
473 };
474
475 sm_gpio0: gpio@c000 {
476 compatible = "snps,dw-apb-gpio";
477 reg = <0xc000 0x400>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480
481 porte: gpio-port@4 {
482 compatible = "snps,dw-apb-gpio-port";
483 gpio-controller;
484 #gpio-cells = <2>;
485 snps,nr-gpios = <8>;
486 reg = <0>;
487 interrupt-controller;
488 #interrupt-cells = <2>;
489 interrupts = <11>;
490 };
491 };
492
493 uart0: serial@9000 {
494 compatible = "snps,dw-apb-uart";
495 reg = <0x9000 0x100>;
496 reg-shift = <2>;
497 reg-io-width = <1>;
498 interrupts = <8>;
499 clocks = <&refclk>;
500 pinctrl-0 = <&uart0_pmux>;
501 pinctrl-names = "default";
502 status = "disabled";
503 };
504
505 uart1: serial@a000 {
506 compatible = "snps,dw-apb-uart";
507 reg = <0xa000 0x100>;
508 reg-shift = <2>;
509 reg-io-width = <1>;
510 interrupts = <9>;
511 clocks = <&refclk>;
512 pinctrl-0 = <&uart1_pmux>;
513 pinctrl-names = "default";
514 status = "disabled";
515 };
516
517 uart2: serial@b000 {
518 compatible = "snps,dw-apb-uart";
519 reg = <0xb000 0x100>;
520 reg-shift = <2>;
521 reg-io-width = <1>;
522 interrupts = <10>;
523 clocks = <&refclk>;
524 pinctrl-0 = <&uart2_pmux>;
525 pinctrl-names = "default";
526 status = "disabled";
527 };
528
529 sysctrl: system-controller@d000 {
530 compatible = "simple-mfd", "syscon";
531 reg = <0xd000 0x100>;
532
533 sys_pinctrl: pin-controller {
534 compatible = "marvell,berlin2-system-pinctrl";
535 uart0_pmux: uart0-pmux {
536 groups = "GSM4";
537 function = "uart0";
538 };
539
540 uart1_pmux: uart1-pmux {
541 groups = "GSM5";
542 function = "uart1";
543 };
544 uart2_pmux: uart2-pmux {
545 groups = "GSM3";
546 function = "uart2";
547 };
548 };
549 };
550
551 sic: interrupt-controller@e000 {
552 compatible = "snps,dw-apb-ictl";
553 reg = <0xe000 0x400>;
554 interrupt-controller;
555 #interrupt-cells = <1>;
556 interrupt-parent = <&gic>;
557 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
558 };
559 };
560 };
561};