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1// SPDX-License-Identifier: GPL-2.0 OR MIT
2/*
3 * Copyright 2014 Carlo Caione <carlo@caione.org>
4 */
5
6#include <dt-bindings/clock/meson8-ddr-clkc.h>
7#include <dt-bindings/clock/meson8b-clkc.h>
8#include <dt-bindings/gpio/meson8-gpio.h>
9#include <dt-bindings/power/meson8-power.h>
10#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
11#include <dt-bindings/reset/amlogic,meson8b-reset.h>
12#include <dt-bindings/thermal/thermal.h>
13#include "meson.dtsi"
14
15/ {
16 model = "Amlogic Meson8 SoC";
17 compatible = "amlogic,meson8";
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu0: cpu@200 {
24 device_type = "cpu";
25 compatible = "arm,cortex-a9";
26 next-level-cache = <&L2>;
27 reg = <0x200>;
28 enable-method = "amlogic,meson8-smp";
29 resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
30 operating-points-v2 = <&cpu_opp_table>;
31 clocks = <&clkc CLKID_CPUCLK>;
32 #cooling-cells = <2>; /* min followed by max */
33 };
34
35 cpu1: cpu@201 {
36 device_type = "cpu";
37 compatible = "arm,cortex-a9";
38 next-level-cache = <&L2>;
39 reg = <0x201>;
40 enable-method = "amlogic,meson8-smp";
41 resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
42 operating-points-v2 = <&cpu_opp_table>;
43 clocks = <&clkc CLKID_CPUCLK>;
44 #cooling-cells = <2>; /* min followed by max */
45 };
46
47 cpu2: cpu@202 {
48 device_type = "cpu";
49 compatible = "arm,cortex-a9";
50 next-level-cache = <&L2>;
51 reg = <0x202>;
52 enable-method = "amlogic,meson8-smp";
53 resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
54 operating-points-v2 = <&cpu_opp_table>;
55 clocks = <&clkc CLKID_CPUCLK>;
56 #cooling-cells = <2>; /* min followed by max */
57 };
58
59 cpu3: cpu@203 {
60 device_type = "cpu";
61 compatible = "arm,cortex-a9";
62 next-level-cache = <&L2>;
63 reg = <0x203>;
64 enable-method = "amlogic,meson8-smp";
65 resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
66 operating-points-v2 = <&cpu_opp_table>;
67 clocks = <&clkc CLKID_CPUCLK>;
68 #cooling-cells = <2>; /* min followed by max */
69 };
70 };
71
72 cpu_opp_table: opp-table {
73 compatible = "operating-points-v2";
74 opp-shared;
75
76 opp-96000000 {
77 opp-hz = /bits/ 64 <96000000>;
78 opp-microvolt = <825000>;
79 };
80 opp-192000000 {
81 opp-hz = /bits/ 64 <192000000>;
82 opp-microvolt = <825000>;
83 };
84 opp-312000000 {
85 opp-hz = /bits/ 64 <312000000>;
86 opp-microvolt = <825000>;
87 };
88 opp-408000000 {
89 opp-hz = /bits/ 64 <408000000>;
90 opp-microvolt = <825000>;
91 };
92 opp-504000000 {
93 opp-hz = /bits/ 64 <504000000>;
94 opp-microvolt = <825000>;
95 };
96 opp-600000000 {
97 opp-hz = /bits/ 64 <600000000>;
98 opp-microvolt = <850000>;
99 };
100 opp-720000000 {
101 opp-hz = /bits/ 64 <720000000>;
102 opp-microvolt = <850000>;
103 };
104 opp-816000000 {
105 opp-hz = /bits/ 64 <816000000>;
106 opp-microvolt = <875000>;
107 };
108 opp-1008000000 {
109 opp-hz = /bits/ 64 <1008000000>;
110 opp-microvolt = <925000>;
111 };
112 opp-1200000000 {
113 opp-hz = /bits/ 64 <1200000000>;
114 opp-microvolt = <975000>;
115 };
116 opp-1416000000 {
117 opp-hz = /bits/ 64 <1416000000>;
118 opp-microvolt = <1025000>;
119 };
120 opp-1608000000 {
121 opp-hz = /bits/ 64 <1608000000>;
122 opp-microvolt = <1100000>;
123 };
124 opp-1800000000 {
125 status = "disabled";
126 opp-hz = /bits/ 64 <1800000000>;
127 opp-microvolt = <1125000>;
128 };
129 opp-1992000000 {
130 status = "disabled";
131 opp-hz = /bits/ 64 <1992000000>;
132 opp-microvolt = <1150000>;
133 };
134 };
135
136 gpu_opp_table: opp-table-gpu {
137 compatible = "operating-points-v2";
138
139 opp-182142857 {
140 opp-hz = /bits/ 64 <182142857>;
141 opp-microvolt = <1150000>;
142 };
143 opp-318750000 {
144 opp-hz = /bits/ 64 <318750000>;
145 opp-microvolt = <1150000>;
146 };
147 opp-425000000 {
148 opp-hz = /bits/ 64 <425000000>;
149 opp-microvolt = <1150000>;
150 };
151 opp-510000000 {
152 opp-hz = /bits/ 64 <510000000>;
153 opp-microvolt = <1150000>;
154 };
155 opp-637500000 {
156 opp-hz = /bits/ 64 <637500000>;
157 opp-microvolt = <1150000>;
158 turbo-mode;
159 };
160 };
161
162 pmu {
163 compatible = "arm,cortex-a9-pmu";
164 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
165 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
166 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
167 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
168 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
169 };
170
171 reserved-memory {
172 #address-cells = <1>;
173 #size-cells = <1>;
174 ranges;
175
176 /* 2 MiB reserved for Hardware ROM Firmware? */
177 hwrom@0 {
178 reg = <0x0 0x200000>;
179 no-map;
180 };
181
182 /*
183 * 1 MiB reserved for the "ARM Power Firmware": this is ARM
184 * code which is responsible for system suspend. It loads a
185 * piece of ARC code ("arc_power" in the vendor u-boot tree)
186 * into SRAM, executes that and shuts down the (last) ARM core.
187 * The arc_power firmware then checks various wakeup sources
188 * (IR remote receiver, HDMI CEC, WIFI and Bluetooth wakeup or
189 * simply the power key) and re-starts the ARM core once it
190 * detects a wakeup request.
191 */
192 power-firmware@4f00000 {
193 reg = <0x4f00000 0x100000>;
194 no-map;
195 };
196 };
197
198 thermal-zones {
199 soc-thermal {
200 polling-delay-passive = <250>; /* milliseconds */
201 polling-delay = <1000>; /* milliseconds */
202 thermal-sensors = <&thermal_sensor>;
203
204 cooling-maps {
205 map0 {
206 trip = <&soc_passive>;
207 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
208 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
209 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
210 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
211 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
212 };
213
214 map1 {
215 trip = <&soc_hot>;
216 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
217 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
218 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
219 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
220 <&mali THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
221 };
222 };
223
224 trips {
225 soc_passive: soc-passive {
226 temperature = <80000>; /* millicelsius */
227 hysteresis = <2000>; /* millicelsius */
228 type = "passive";
229 };
230
231 soc_hot: soc-hot {
232 temperature = <90000>; /* millicelsius */
233 hysteresis = <2000>; /* millicelsius */
234 type = "hot";
235 };
236
237 soc_critical: soc-critical {
238 temperature = <110000>; /* millicelsius */
239 hysteresis = <2000>; /* millicelsius */
240 type = "critical";
241 };
242 };
243 };
244 };
245
246 mmcbus: bus@c8000000 {
247 compatible = "simple-bus";
248 reg = <0xc8000000 0x8000>;
249 #address-cells = <1>;
250 #size-cells = <1>;
251 ranges = <0x0 0xc8000000 0x8000>;
252
253 ddr_clkc: clock-controller@400 {
254 compatible = "amlogic,meson8-ddr-clkc";
255 reg = <0x400 0x20>;
256 clocks = <&xtal>;
257 clock-names = "xtal";
258 #clock-cells = <1>;
259 };
260
261 dmcbus: bus@6000 {
262 compatible = "simple-bus";
263 reg = <0x6000 0x400>;
264 #address-cells = <1>;
265 #size-cells = <1>;
266 ranges = <0x0 0x6000 0x400>;
267
268 canvas: video-lut@20 {
269 compatible = "amlogic,meson8-canvas",
270 "amlogic,canvas";
271 reg = <0x20 0x14>;
272 };
273 };
274 };
275
276 apb: bus@d0000000 {
277 compatible = "simple-bus";
278 reg = <0xd0000000 0x200000>;
279 #address-cells = <1>;
280 #size-cells = <1>;
281 ranges = <0x0 0xd0000000 0x200000>;
282
283 mali: gpu@c0000 {
284 compatible = "amlogic,meson8-mali", "arm,mali-450";
285 reg = <0xc0000 0x40000>;
286 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
302 interrupt-names = "gp", "gpmmu", "pp", "pmu",
303 "pp0", "ppmmu0", "pp1", "ppmmu1",
304 "pp2", "ppmmu2", "pp4", "ppmmu4",
305 "pp5", "ppmmu5", "pp6", "ppmmu6";
306 resets = <&reset RESET_MALI>;
307
308 clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;
309 clock-names = "bus", "core";
310
311 assigned-clocks = <&clkc CLKID_MALI>;
312 assigned-clock-rates = <318750000>;
313
314 operating-points-v2 = <&gpu_opp_table>;
315 #cooling-cells = <2>; /* min followed by max */
316 };
317 };
318}; /* end of / */
319
320&aiu {
321 compatible = "amlogic,aiu-meson8", "amlogic,aiu";
322 clocks = <&clkc CLKID_AIU_GLUE>,
323 <&clkc CLKID_I2S_OUT>,
324 <&clkc CLKID_AOCLK_GATE>,
325 <&clkc CLKID_CTS_AMCLK>,
326 <&clkc CLKID_MIXER_IFACE>,
327 <&clkc CLKID_IEC958>,
328 <&clkc CLKID_IEC958_GATE>,
329 <&clkc CLKID_CTS_MCLK_I958>,
330 <&clkc CLKID_CTS_I958>;
331 clock-names = "pclk",
332 "i2s_pclk",
333 "i2s_aoclk",
334 "i2s_mclk",
335 "i2s_mixer",
336 "spdif_pclk",
337 "spdif_aoclk",
338 "spdif_mclk",
339 "spdif_mclk_sel";
340 resets = <&reset RESET_AIU>;
341};
342
343&aobus {
344 pmu: pmu@e0 {
345 compatible = "amlogic,meson8-pmu", "syscon";
346 reg = <0xe0 0x18>;
347 };
348
349 pinctrl_aobus: pinctrl@14 {
350 compatible = "amlogic,meson8-aobus-pinctrl";
351 #address-cells = <1>;
352 #size-cells = <1>;
353 ranges = <0x0 0x14 0x1c>;
354
355 gpio_ao: bank@0 {
356 reg = <0x0 0x4>,
357 <0x18 0x4>,
358 <0x10 0x8>;
359 reg-names = "mux", "pull", "gpio";
360 gpio-controller;
361 #gpio-cells = <2>;
362 gpio-ranges = <&pinctrl_aobus 0 0 16>;
363 };
364
365 i2s_am_clk_pins: i2s-am-clk-out {
366 mux {
367 groups = "i2s_am_clk_out_ao";
368 function = "i2s_ao";
369 bias-disable;
370 };
371 };
372
373 i2s_out_ao_clk_pins: i2s-ao-clk-out {
374 mux {
375 groups = "i2s_ao_clk_out_ao";
376 function = "i2s_ao";
377 bias-disable;
378 };
379 };
380
381 i2s_out_lr_clk_pins: i2s-lr-clk-out {
382 mux {
383 groups = "i2s_lr_clk_out_ao";
384 function = "i2s_ao";
385 bias-disable;
386 };
387 };
388
389 i2s_out_ch01_ao_pins: i2s-out-ch01 {
390 mux {
391 groups = "i2s_out_ch01_ao";
392 function = "i2s_ao";
393 bias-disable;
394 };
395 };
396
397 uart_ao_a_pins: uart_ao_a {
398 mux {
399 groups = "uart_tx_ao_a", "uart_rx_ao_a";
400 function = "uart_ao";
401 bias-disable;
402 };
403 };
404
405 i2c_ao_pins: i2c_mst_ao {
406 mux {
407 groups = "i2c_mst_sck_ao", "i2c_mst_sda_ao";
408 function = "i2c_mst_ao";
409 bias-disable;
410 };
411 };
412
413 ir_recv_pins: remote {
414 mux {
415 groups = "remote_input";
416 function = "remote";
417 bias-disable;
418 };
419 };
420
421 pwm_f_ao_pins: pwm-f-ao {
422 mux {
423 groups = "pwm_f_ao";
424 function = "pwm_f_ao";
425 bias-disable;
426 };
427 };
428 };
429};
430
431&ao_arc_rproc {
432 compatible = "amlogic,meson8-ao-arc", "amlogic,meson-mx-ao-arc";
433 amlogic,secbus2 = <&secbus2>;
434 sram = <&ao_arc_sram>;
435 resets = <&reset RESET_MEDIA_CPU>;
436 clocks = <&clkc CLKID_AO_MEDIA_CPU>;
437};
438
439&cbus {
440 reset: reset-controller@4404 {
441 compatible = "amlogic,meson8b-reset";
442 reg = <0x4404 0x9c>;
443 #reset-cells = <1>;
444 };
445
446 analog_top: analog-top@81a8 {
447 compatible = "amlogic,meson8-analog-top", "syscon";
448 reg = <0x81a8 0x14>;
449 };
450
451 pwm_ef: pwm@86c0 {
452 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
453 reg = <0x86c0 0x10>;
454 #pwm-cells = <3>;
455 status = "disabled";
456 };
457
458 clock-measure@8758 {
459 compatible = "amlogic,meson8-clk-measure";
460 reg = <0x8758 0x1c>;
461 };
462
463 pinctrl_cbus: pinctrl@8030 {
464 compatible = "amlogic,meson8-cbus-pinctrl";
465 #address-cells = <1>;
466 #size-cells = <1>;
467 ranges = <0x0 0x8030 0x108>;
468
469 gpio: bank@80 {
470 reg = <0x80 0x28>,
471 <0xb8 0x18>,
472 <0xf0 0x18>,
473 <0x00 0x30>;
474 reg-names = "mux", "pull", "pull-enable", "gpio";
475 gpio-controller;
476 #gpio-cells = <2>;
477 gpio-ranges = <&pinctrl_cbus 0 0 120>;
478 };
479
480 sd_a_pins: sd-a {
481 mux {
482 groups = "sd_d0_a", "sd_d1_a", "sd_d2_a",
483 "sd_d3_a", "sd_clk_a", "sd_cmd_a";
484 function = "sd_a";
485 bias-disable;
486 };
487 };
488
489 sd_b_pins: sd-b {
490 mux {
491 groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
492 "sd_d3_b", "sd_clk_b", "sd_cmd_b";
493 function = "sd_b";
494 bias-disable;
495 };
496 };
497
498 sd_c_pins: sd-c {
499 mux {
500 groups = "sd_d0_c", "sd_d1_c", "sd_d2_c",
501 "sd_d3_c", "sd_clk_c", "sd_cmd_c";
502 function = "sd_c";
503 bias-disable;
504 };
505 };
506
507 sdxc_a_pins: sdxc-a {
508 mux {
509 groups = "sdxc_d0_a", "sdxc_d13_a",
510 "sdxc_clk_a", "sdxc_cmd_a";
511 function = "sdxc_a";
512 bias-pull-up;
513 };
514 };
515
516 sdxc_b_pins: sdxc-b {
517 mux {
518 groups = "sdxc_d0_b", "sdxc_d13_b",
519 "sdxc_clk_b", "sdxc_cmd_b";
520 function = "sdxc_b";
521 bias-pull-up;
522 };
523 };
524
525 spdif_out_pins: spdif-out {
526 mux {
527 groups = "spdif_out";
528 function = "spdif";
529 bias-disable;
530 };
531 };
532
533 spi_nor_pins: nor {
534 mux {
535 groups = "nor_d", "nor_q", "nor_c", "nor_cs";
536 function = "nor";
537 bias-disable;
538 };
539 };
540
541 eth_pins: ethernet {
542 mux {
543 groups = "eth_tx_clk_50m", "eth_tx_en",
544 "eth_txd1", "eth_txd0",
545 "eth_rx_clk_in", "eth_rx_dv",
546 "eth_rxd1", "eth_rxd0", "eth_mdio",
547 "eth_mdc";
548 function = "ethernet";
549 bias-disable;
550 };
551 };
552
553 pwm_e_pins: pwm-e {
554 mux {
555 groups = "pwm_e";
556 function = "pwm_e";
557 bias-disable;
558 };
559 };
560
561 uart_a1_pins: uart-a1 {
562 mux {
563 groups = "uart_tx_a1",
564 "uart_rx_a1";
565 function = "uart_a";
566 bias-disable;
567 };
568 };
569
570 uart_a1_cts_rts_pins: uart-a1-cts-rts {
571 mux {
572 groups = "uart_cts_a1",
573 "uart_rts_a1";
574 function = "uart_a";
575 bias-disable;
576 };
577 };
578
579 xtal_32k_out_pins: xtal-32k-out {
580 mux {
581 groups = "xtal_32k_out";
582 function = "xtal";
583 bias-disable;
584 };
585 };
586 };
587};
588
589&ahb_sram {
590 ao_arc_sram: aoarc-sram@0 {
591 compatible = "amlogic,meson8-ao-arc-sram";
592 reg = <0x0 0x8000>;
593 pool;
594 };
595
596 smp-sram@1ff80 {
597 compatible = "amlogic,meson8-smp-sram";
598 reg = <0x1ff80 0x8>;
599 };
600};
601
602&efuse {
603 compatible = "amlogic,meson8-efuse";
604 clocks = <&clkc CLKID_EFUSE>;
605 clock-names = "core";
606
607 temperature_calib: calib@1f4 {
608 /* only the upper two bytes are relevant */
609 reg = <0x1f4 0x4>;
610 };
611};
612
613ðmac {
614 clocks = <&clkc CLKID_ETH>;
615 clock-names = "stmmaceth";
616
617 power-domains = <&pwrc PWRC_MESON8_ETHERNET_MEM_ID>;
618};
619
620&gpio_intc {
621 compatible = "amlogic,meson8-gpio-intc", "amlogic,meson-gpio-intc";
622 status = "okay";
623};
624
625&hhi {
626 clkc: clock-controller {
627 compatible = "amlogic,meson8-clkc";
628 clocks = <&xtal>, <&ddr_clkc DDR_CLKID_DDR_PLL>;
629 clock-names = "xtal", "ddr_pll";
630 #clock-cells = <1>;
631 #reset-cells = <1>;
632 };
633
634 pwrc: power-controller {
635 compatible = "amlogic,meson8-pwrc";
636 #power-domain-cells = <1>;
637 amlogic,ao-sysctrl = <&pmu>;
638 clocks = <&clkc CLKID_VPU>;
639 clock-names = "vpu";
640 assigned-clocks = <&clkc CLKID_VPU>;
641 assigned-clock-rates = <364285714>;
642 };
643};
644
645&hwrng {
646 clocks = <&clkc CLKID_RNG0>;
647 clock-names = "core";
648};
649
650&i2c_AO {
651 clocks = <&clkc CLKID_CLK81>;
652};
653
654&i2c_A {
655 clocks = <&clkc CLKID_CLK81>;
656};
657
658&i2c_B {
659 clocks = <&clkc CLKID_CLK81>;
660};
661
662&L2 {
663 arm,data-latency = <3 3 3>;
664 arm,tag-latency = <2 2 2>;
665 arm,filter-ranges = <0x100000 0xc0000000>;
666 prefetch-data = <1>;
667 prefetch-instr = <1>;
668 arm,prefetch-offset = <7>;
669 arm,double-linefill = <1>;
670 arm,prefetch-drop = <1>;
671 arm,shared-override;
672};
673
674&periph {
675 scu@0 {
676 compatible = "arm,cortex-a9-scu";
677 reg = <0x0 0x100>;
678 };
679
680 timer@200 {
681 compatible = "arm,cortex-a9-global-timer";
682 reg = <0x200 0x20>;
683 interrupts = <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
684 clocks = <&clkc CLKID_PERIPH>;
685
686 /*
687 * the arm_global_timer driver currently does not handle clock
688 * rate changes. Keep it disabled for now.
689 */
690 status = "disabled";
691 };
692
693 timer@600 {
694 compatible = "arm,cortex-a9-twd-timer";
695 reg = <0x600 0x20>;
696 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
697 clocks = <&clkc CLKID_PERIPH>;
698 };
699};
700
701&pwm_ab {
702 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
703};
704
705&pwm_cd {
706 compatible = "amlogic,meson8-pwm", "amlogic,meson8b-pwm";
707};
708
709&rtc {
710 compatible = "amlogic,meson8-rtc";
711 resets = <&reset RESET_RTC>;
712};
713
714&saradc {
715 compatible = "amlogic,meson8-saradc", "amlogic,meson-saradc";
716 clocks = <&xtal>, <&clkc CLKID_SAR_ADC>;
717 clock-names = "clkin", "core";
718 amlogic,hhi-sysctrl = <&hhi>;
719 nvmem-cells = <&temperature_calib>;
720 nvmem-cell-names = "temperature_calib";
721};
722
723&sdhc {
724 compatible = "amlogic,meson8-sdhc", "amlogic,meson-mx-sdhc";
725 clocks = <&xtal>,
726 <&clkc CLKID_FCLK_DIV4>,
727 <&clkc CLKID_FCLK_DIV3>,
728 <&clkc CLKID_FCLK_DIV5>,
729 <&clkc CLKID_SDHC>;
730 clock-names = "clkin0", "clkin1", "clkin2", "clkin3", "pclk";
731};
732
733&secbus {
734 secbus2: system-controller@4000 {
735 compatible = "amlogic,meson8-secbus2", "syscon";
736 reg = <0x4000 0x2000>;
737 };
738};
739
740&sdio {
741 compatible = "amlogic,meson8-sdio", "amlogic,meson-mx-sdio";
742 clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
743 clock-names = "core", "clkin";
744};
745
746&spifc {
747 clocks = <&clkc CLKID_CLK81>;
748};
749
750&timer_abcde {
751 clocks = <&xtal>, <&clkc CLKID_CLK81>;
752 clock-names = "xtal", "pclk";
753};
754
755&uart_AO {
756 compatible = "amlogic,meson8-uart", "amlogic,meson-ao-uart";
757 clocks = <&xtal>, <&clkc CLKID_CLK81>, <&clkc CLKID_CLK81>;
758 clock-names = "xtal", "pclk", "baud";
759};
760
761&uart_A {
762 compatible = "amlogic,meson8-uart";
763 clocks = <&xtal>, <&clkc CLKID_UART0>, <&clkc CLKID_CLK81>;
764 clock-names = "xtal", "pclk", "baud";
765};
766
767&uart_B {
768 compatible = "amlogic,meson8-uart";
769 clocks = <&xtal>, <&clkc CLKID_UART1>, <&clkc CLKID_CLK81>;
770 clock-names = "xtal", "pclk", "baud";
771};
772
773&uart_C {
774 compatible = "amlogic,meson8-uart";
775 clocks = <&xtal>, <&clkc CLKID_UART2>, <&clkc CLKID_CLK81>;
776 clock-names = "xtal", "pclk", "baud";
777};
778
779&usb0 {
780 compatible = "amlogic,meson8-usb", "snps,dwc2";
781 clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
782 clock-names = "otg";
783};
784
785&usb1 {
786 compatible = "amlogic,meson8-usb", "snps,dwc2";
787 clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
788 clock-names = "otg";
789};
790
791&usb0_phy {
792 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
793 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
794 clock-names = "usb_general", "usb";
795 resets = <&reset RESET_USB_OTG>;
796};
797
798&usb1_phy {
799 compatible = "amlogic,meson8-usb2-phy", "amlogic,meson-mx-usb2-phy";
800 clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
801 clock-names = "usb_general", "usb";
802 resets = <&reset RESET_USB_OTG>;
803};