1/*
 2 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
 3 *
 4 * This program is free software; you can redistribute it and/or modify
 5 * it under the terms of the GNU General Public License version 2 as
 6 * published by the Free Software Foundation.
 7 */
 8/dts-v1/;
 9
10/include/ "skeleton_hs_idu.dtsi"
11
12/ {
13	model = "snps,zebu_hs-smp";
14	compatible = "snps,zebu_hs";
15	#address-cells = <1>;
16	#size-cells = <1>;
17	interrupt-parent = <&core_intc>;
18
19	memory {
20		device_type = "memory";
21		reg = <0x80000000 0x20000000>;	/* 512 */
22	};
23
24	chosen {
25		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
26	};
27
28	aliases {
29		serial0 = &uart0;
30	};
31
32	fpga {
33		compatible = "simple-bus";
34		#address-cells = <1>;
35		#size-cells = <1>;
36
37		/* child and parent address space 1:1 mapped */
38		ranges;
39
40		core_clk: core_clk {
41			#clock-cells = <0>;
42			compatible = "fixed-clock";
43			clock-frequency = <50000000>;	/* 50 MHZ */
44		};
45
46		core_intc: interrupt-controller {
47			compatible = "snps,archs-intc";
48			interrupt-controller;
49			#interrupt-cells = <1>;
50		};
51
52		idu_intc: idu-interrupt-controller {
53			compatible = "snps,archs-idu-intc";
54			interrupt-controller;
55			interrupt-parent = <&core_intc>;
56			#interrupt-cells = <1>;
57		};
58
59		uart0: serial@f0000000 {
60			/* compatible = "ns8250"; Doesn't use FIFOs */
61			compatible = "ns16550a";
62			reg = <0xf0000000 0x2000>;
63			interrupt-parent = <&idu_intc>;
64			interrupts = <0>;
65			clock-frequency = <50000000>;
66			baud = <115200>;
67			reg-shift = <2>;
68			reg-io-width = <4>;
69			no-loopback-test = <1>;
70		};
71
72		arcpct0: pct {
73			compatible = "snps,archs-pct";
74			#interrupt-cells = <1>;
75			interrupts = <20>;
76		};
77	};
78};

 1// SPDX-License-Identifier: GPL-2.0-only
 2/*
 3 * Copyright (C) 2016-2014 Synopsys, Inc. (www.synopsys.com)
 
 
 
 
 4 */
 5/dts-v1/;
 6
 7/include/ "skeleton_hs_idu.dtsi"
 8
 9/ {
10	model = "snps,zebu_hs-smp";
11	compatible = "snps,zebu_hs";
12	#address-cells = <1>;
13	#size-cells = <1>;
14	interrupt-parent = <&core_intc>;
15
16	memory {
17		device_type = "memory";
18		reg = <0x80000000 0x20000000>;	/* 512 */
19	};
20
21	chosen {
22		bootargs = "earlycon=uart8250,mmio32,0xf0000000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1";
23	};
24
25	aliases {
26		serial0 = &uart0;
27	};
28
29	fpga {
30		compatible = "simple-bus";
31		#address-cells = <1>;
32		#size-cells = <1>;
33
34		/* child and parent address space 1:1 mapped */
35		ranges;
36
37		core_clk: core_clk {
38			#clock-cells = <0>;
39			compatible = "fixed-clock";
40			clock-frequency = <50000000>;	/* 50 MHZ */
41		};
42
43		core_intc: interrupt-controller {
44			compatible = "snps,archs-intc";
45			interrupt-controller;
46			#interrupt-cells = <1>;
47		};
48
49		idu_intc: idu-interrupt-controller {
50			compatible = "snps,archs-idu-intc";
51			interrupt-controller;
52			interrupt-parent = <&core_intc>;
53			#interrupt-cells = <1>;
54		};
55
56		uart0: serial@f0000000 {
 
57			compatible = "ns16550a";
58			reg = <0xf0000000 0x2000>;
59			interrupt-parent = <&idu_intc>;
60			interrupts = <0>;
61			clock-frequency = <50000000>;
62			baud = <115200>;
63			reg-shift = <2>;
64			reg-io-width = <4>;
65			no-loopback-test = <1>;
66		};
67
68		arcpct0: pct {
69			compatible = "snps,archs-pct";
70			#interrupt-cells = <1>;
71			interrupts = <20>;
72		};
73	};
74};