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1/*
2 * User-space Probes (UProbes) for x86
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 *
18 * Copyright (C) IBM Corporation, 2008-2011
19 * Authors:
20 * Srikar Dronamraju
21 * Jim Keniston
22 */
23#include <linux/kernel.h>
24#include <linux/sched.h>
25#include <linux/ptrace.h>
26#include <linux/uprobes.h>
27#include <linux/uaccess.h>
28
29#include <linux/kdebug.h>
30#include <asm/processor.h>
31#include <asm/insn.h>
32#include <asm/mmu_context.h>
33
34/* Post-execution fixups. */
35
36/* Adjust IP back to vicinity of actual insn */
37#define UPROBE_FIX_IP 0x01
38
39/* Adjust the return address of a call insn */
40#define UPROBE_FIX_CALL 0x02
41
42/* Instruction will modify TF, don't change it */
43#define UPROBE_FIX_SETF 0x04
44
45#define UPROBE_FIX_RIP_SI 0x08
46#define UPROBE_FIX_RIP_DI 0x10
47#define UPROBE_FIX_RIP_BX 0x20
48#define UPROBE_FIX_RIP_MASK \
49 (UPROBE_FIX_RIP_SI | UPROBE_FIX_RIP_DI | UPROBE_FIX_RIP_BX)
50
51#define UPROBE_TRAP_NR UINT_MAX
52
53/* Adaptations for mhiramat x86 decoder v14. */
54#define OPCODE1(insn) ((insn)->opcode.bytes[0])
55#define OPCODE2(insn) ((insn)->opcode.bytes[1])
56#define OPCODE3(insn) ((insn)->opcode.bytes[2])
57#define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value)
58
59#define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\
60 (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \
61 (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \
62 (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \
63 (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \
64 << (row % 32))
65
66/*
67 * Good-instruction tables for 32-bit apps. This is non-const and volatile
68 * to keep gcc from statically optimizing it out, as variable_test_bit makes
69 * some versions of gcc to think only *(unsigned long*) is used.
70 *
71 * Opcodes we'll probably never support:
72 * 6c-6f - ins,outs. SEGVs if used in userspace
73 * e4-e7 - in,out imm. SEGVs if used in userspace
74 * ec-ef - in,out acc. SEGVs if used in userspace
75 * cc - int3. SIGTRAP if used in userspace
76 * ce - into. Not used in userspace - no kernel support to make it useful. SEGVs
77 * (why we support bound (62) then? it's similar, and similarly unused...)
78 * f1 - int1. SIGTRAP if used in userspace
79 * f4 - hlt. SEGVs if used in userspace
80 * fa - cli. SEGVs if used in userspace
81 * fb - sti. SEGVs if used in userspace
82 *
83 * Opcodes which need some work to be supported:
84 * 07,17,1f - pop es/ss/ds
85 * Normally not used in userspace, but would execute if used.
86 * Can cause GP or stack exception if tries to load wrong segment descriptor.
87 * We hesitate to run them under single step since kernel's handling
88 * of userspace single-stepping (TF flag) is fragile.
89 * We can easily refuse to support push es/cs/ss/ds (06/0e/16/1e)
90 * on the same grounds that they are never used.
91 * cd - int N.
92 * Used by userspace for "int 80" syscall entry. (Other "int N"
93 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
94 * Not supported since kernel's handling of userspace single-stepping
95 * (TF flag) is fragile.
96 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
97 */
98#if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)
99static volatile u32 good_insns_32[256 / 32] = {
100 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
101 /* ---------------------------------------------- */
102 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 00 */
103 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */
104 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
105 W(0x30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
106 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
107 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
108 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
109 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
110 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
111 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
112 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
113 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
114 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
115 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
116 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
117 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
118 /* ---------------------------------------------- */
119 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
120};
121#else
122#define good_insns_32 NULL
123#endif
124
125/* Good-instruction tables for 64-bit apps.
126 *
127 * Genuinely invalid opcodes:
128 * 06,07 - formerly push/pop es
129 * 0e - formerly push cs
130 * 16,17 - formerly push/pop ss
131 * 1e,1f - formerly push/pop ds
132 * 27,2f,37,3f - formerly daa/das/aaa/aas
133 * 60,61 - formerly pusha/popa
134 * 62 - formerly bound. EVEX prefix for AVX512 (not yet supported)
135 * 82 - formerly redundant encoding of Group1
136 * 9a - formerly call seg:ofs
137 * ce - formerly into
138 * d4,d5 - formerly aam/aad
139 * d6 - formerly undocumented salc
140 * ea - formerly jmp seg:ofs
141 *
142 * Opcodes we'll probably never support:
143 * 6c-6f - ins,outs. SEGVs if used in userspace
144 * e4-e7 - in,out imm. SEGVs if used in userspace
145 * ec-ef - in,out acc. SEGVs if used in userspace
146 * cc - int3. SIGTRAP if used in userspace
147 * f1 - int1. SIGTRAP if used in userspace
148 * f4 - hlt. SEGVs if used in userspace
149 * fa - cli. SEGVs if used in userspace
150 * fb - sti. SEGVs if used in userspace
151 *
152 * Opcodes which need some work to be supported:
153 * cd - int N.
154 * Used by userspace for "int 80" syscall entry. (Other "int N"
155 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
156 * Not supported since kernel's handling of userspace single-stepping
157 * (TF flag) is fragile.
158 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
159 */
160#if defined(CONFIG_X86_64)
161static volatile u32 good_insns_64[256 / 32] = {
162 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
163 /* ---------------------------------------------- */
164 W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* 00 */
165 W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */
166 W(0x20, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 20 */
167 W(0x30, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 30 */
168 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
169 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
170 W(0x60, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
171 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
172 W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
173 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1) , /* 90 */
174 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
175 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
176 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
177 W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
178 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0) | /* e0 */
179 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
180 /* ---------------------------------------------- */
181 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
182};
183#else
184#define good_insns_64 NULL
185#endif
186
187/* Using this for both 64-bit and 32-bit apps.
188 * Opcodes we don't support:
189 * 0f 00 - SLDT/STR/LLDT/LTR/VERR/VERW/-/- group. System insns
190 * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group.
191 * Also encodes tons of other system insns if mod=11.
192 * Some are in fact non-system: xend, xtest, rdtscp, maybe more
193 * 0f 05 - syscall
194 * 0f 06 - clts (CPL0 insn)
195 * 0f 07 - sysret
196 * 0f 08 - invd (CPL0 insn)
197 * 0f 09 - wbinvd (CPL0 insn)
198 * 0f 0b - ud2
199 * 0f 30 - wrmsr (CPL0 insn) (then why rdmsr is allowed, it's also CPL0 insn?)
200 * 0f 34 - sysenter
201 * 0f 35 - sysexit
202 * 0f 37 - getsec
203 * 0f 78 - vmread (Intel VMX. CPL0 insn)
204 * 0f 79 - vmwrite (Intel VMX. CPL0 insn)
205 * Note: with prefixes, these two opcodes are
206 * extrq/insertq/AVX512 convert vector ops.
207 * 0f ae - group15: [f]xsave,[f]xrstor,[v]{ld,st}mxcsr,clflush[opt],
208 * {rd,wr}{fs,gs}base,{s,l,m}fence.
209 * Why? They are all user-executable.
210 */
211static volatile u32 good_2byte_insns[256 / 32] = {
212 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
213 /* ---------------------------------------------- */
214 W(0x00, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1) | /* 00 */
215 W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 10 */
216 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
217 W(0x30, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
218 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
219 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
220 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */
221 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1) , /* 70 */
222 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
223 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
224 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */
225 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
226 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */
227 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
228 W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */
229 W(0xf0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) /* f0 */
230 /* ---------------------------------------------- */
231 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
232};
233#undef W
234
235/*
236 * opcodes we may need to refine support for:
237 *
238 * 0f - 2-byte instructions: For many of these instructions, the validity
239 * depends on the prefix and/or the reg field. On such instructions, we
240 * just consider the opcode combination valid if it corresponds to any
241 * valid instruction.
242 *
243 * 8f - Group 1 - only reg = 0 is OK
244 * c6-c7 - Group 11 - only reg = 0 is OK
245 * d9-df - fpu insns with some illegal encodings
246 * f2, f3 - repnz, repz prefixes. These are also the first byte for
247 * certain floating-point instructions, such as addsd.
248 *
249 * fe - Group 4 - only reg = 0 or 1 is OK
250 * ff - Group 5 - only reg = 0-6 is OK
251 *
252 * others -- Do we need to support these?
253 *
254 * 0f - (floating-point?) prefetch instructions
255 * 07, 17, 1f - pop es, pop ss, pop ds
256 * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes --
257 * but 64 and 65 (fs: and gs:) seem to be used, so we support them
258 * 67 - addr16 prefix
259 * ce - into
260 * f0 - lock prefix
261 */
262
263/*
264 * TODO:
265 * - Where necessary, examine the modrm byte and allow only valid instructions
266 * in the different Groups and fpu instructions.
267 */
268
269static bool is_prefix_bad(struct insn *insn)
270{
271 int i;
272
273 for (i = 0; i < insn->prefixes.nbytes; i++) {
274 insn_attr_t attr;
275
276 attr = inat_get_opcode_attribute(insn->prefixes.bytes[i]);
277 switch (attr) {
278 case INAT_MAKE_PREFIX(INAT_PFX_ES):
279 case INAT_MAKE_PREFIX(INAT_PFX_CS):
280 case INAT_MAKE_PREFIX(INAT_PFX_DS):
281 case INAT_MAKE_PREFIX(INAT_PFX_SS):
282 case INAT_MAKE_PREFIX(INAT_PFX_LOCK):
283 return true;
284 }
285 }
286 return false;
287}
288
289static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64)
290{
291 u32 volatile *good_insns;
292
293 insn_init(insn, auprobe->insn, sizeof(auprobe->insn), x86_64);
294 /* has the side-effect of processing the entire instruction */
295 insn_get_length(insn);
296 if (WARN_ON_ONCE(!insn_complete(insn)))
297 return -ENOEXEC;
298
299 if (is_prefix_bad(insn))
300 return -ENOTSUPP;
301
302 /* We should not singlestep on the exception masking instructions */
303 if (insn_masking_exception(insn))
304 return -ENOTSUPP;
305
306 if (x86_64)
307 good_insns = good_insns_64;
308 else
309 good_insns = good_insns_32;
310
311 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns))
312 return 0;
313
314 if (insn->opcode.nbytes == 2) {
315 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
316 return 0;
317 }
318
319 return -ENOTSUPP;
320}
321
322#ifdef CONFIG_X86_64
323/*
324 * If arch_uprobe->insn doesn't use rip-relative addressing, return
325 * immediately. Otherwise, rewrite the instruction so that it accesses
326 * its memory operand indirectly through a scratch register. Set
327 * defparam->fixups accordingly. (The contents of the scratch register
328 * will be saved before we single-step the modified instruction,
329 * and restored afterward).
330 *
331 * We do this because a rip-relative instruction can access only a
332 * relatively small area (+/- 2 GB from the instruction), and the XOL
333 * area typically lies beyond that area. At least for instructions
334 * that store to memory, we can't execute the original instruction
335 * and "fix things up" later, because the misdirected store could be
336 * disastrous.
337 *
338 * Some useful facts about rip-relative instructions:
339 *
340 * - There's always a modrm byte with bit layout "00 reg 101".
341 * - There's never a SIB byte.
342 * - The displacement is always 4 bytes.
343 * - REX.B=1 bit in REX prefix, which normally extends r/m field,
344 * has no effect on rip-relative mode. It doesn't make modrm byte
345 * with r/m=101 refer to register 1101 = R13.
346 */
347static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
348{
349 u8 *cursor;
350 u8 reg;
351 u8 reg2;
352
353 if (!insn_rip_relative(insn))
354 return;
355
356 /*
357 * insn_rip_relative() would have decoded rex_prefix, vex_prefix, modrm.
358 * Clear REX.b bit (extension of MODRM.rm field):
359 * we want to encode low numbered reg, not r8+.
360 */
361 if (insn->rex_prefix.nbytes) {
362 cursor = auprobe->insn + insn_offset_rex_prefix(insn);
363 /* REX byte has 0100wrxb layout, clearing REX.b bit */
364 *cursor &= 0xfe;
365 }
366 /*
367 * Similar treatment for VEX3/EVEX prefix.
368 * TODO: add XOP treatment when insn decoder supports them
369 */
370 if (insn->vex_prefix.nbytes >= 3) {
371 /*
372 * vex2: c5 rvvvvLpp (has no b bit)
373 * vex3/xop: c4/8f rxbmmmmm wvvvvLpp
374 * evex: 62 rxbR00mm wvvvv1pp zllBVaaa
375 * Setting VEX3.b (setting because it has inverted meaning).
376 * Setting EVEX.x since (in non-SIB encoding) EVEX.x
377 * is the 4th bit of MODRM.rm, and needs the same treatment.
378 * For VEX3-encoded insns, VEX3.x value has no effect in
379 * non-SIB encoding, the change is superfluous but harmless.
380 */
381 cursor = auprobe->insn + insn_offset_vex_prefix(insn) + 1;
382 *cursor |= 0x60;
383 }
384
385 /*
386 * Convert from rip-relative addressing to register-relative addressing
387 * via a scratch register.
388 *
389 * This is tricky since there are insns with modrm byte
390 * which also use registers not encoded in modrm byte:
391 * [i]div/[i]mul: implicitly use dx:ax
392 * shift ops: implicitly use cx
393 * cmpxchg: implicitly uses ax
394 * cmpxchg8/16b: implicitly uses dx:ax and bx:cx
395 * Encoding: 0f c7/1 modrm
396 * The code below thinks that reg=1 (cx), chooses si as scratch.
397 * mulx: implicitly uses dx: mulx r/m,r1,r2 does r1:r2 = dx * r/m.
398 * First appeared in Haswell (BMI2 insn). It is vex-encoded.
399 * Example where none of bx,cx,dx can be used as scratch reg:
400 * c4 e2 63 f6 0d disp32 mulx disp32(%rip),%ebx,%ecx
401 * [v]pcmpistri: implicitly uses cx, xmm0
402 * [v]pcmpistrm: implicitly uses xmm0
403 * [v]pcmpestri: implicitly uses ax, dx, cx, xmm0
404 * [v]pcmpestrm: implicitly uses ax, dx, xmm0
405 * Evil SSE4.2 string comparison ops from hell.
406 * maskmovq/[v]maskmovdqu: implicitly uses (ds:rdi) as destination.
407 * Encoding: 0f f7 modrm, 66 0f f7 modrm, vex-encoded: c5 f9 f7 modrm.
408 * Store op1, byte-masked by op2 msb's in each byte, to (ds:rdi).
409 * AMD says it has no 3-operand form (vex.vvvv must be 1111)
410 * and that it can have only register operands, not mem
411 * (its modrm byte must have mode=11).
412 * If these restrictions will ever be lifted,
413 * we'll need code to prevent selection of di as scratch reg!
414 *
415 * Summary: I don't know any insns with modrm byte which
416 * use SI register implicitly. DI register is used only
417 * by one insn (maskmovq) and BX register is used
418 * only by one too (cmpxchg8b).
419 * BP is stack-segment based (may be a problem?).
420 * AX, DX, CX are off-limits (many implicit users).
421 * SP is unusable (it's stack pointer - think about "pop mem";
422 * also, rsp+disp32 needs sib encoding -> insn length change).
423 */
424
425 reg = MODRM_REG(insn); /* Fetch modrm.reg */
426 reg2 = 0xff; /* Fetch vex.vvvv */
427 if (insn->vex_prefix.nbytes)
428 reg2 = insn->vex_prefix.bytes[2];
429 /*
430 * TODO: add XOP vvvv reading.
431 *
432 * vex.vvvv field is in bits 6-3, bits are inverted.
433 * But in 32-bit mode, high-order bit may be ignored.
434 * Therefore, let's consider only 3 low-order bits.
435 */
436 reg2 = ((reg2 >> 3) & 0x7) ^ 0x7;
437 /*
438 * Register numbering is ax,cx,dx,bx, sp,bp,si,di, r8..r15.
439 *
440 * Choose scratch reg. Order is important: must not select bx
441 * if we can use si (cmpxchg8b case!)
442 */
443 if (reg != 6 && reg2 != 6) {
444 reg2 = 6;
445 auprobe->defparam.fixups |= UPROBE_FIX_RIP_SI;
446 } else if (reg != 7 && reg2 != 7) {
447 reg2 = 7;
448 auprobe->defparam.fixups |= UPROBE_FIX_RIP_DI;
449 /* TODO (paranoia): force maskmovq to not use di */
450 } else {
451 reg2 = 3;
452 auprobe->defparam.fixups |= UPROBE_FIX_RIP_BX;
453 }
454 /*
455 * Point cursor at the modrm byte. The next 4 bytes are the
456 * displacement. Beyond the displacement, for some instructions,
457 * is the immediate operand.
458 */
459 cursor = auprobe->insn + insn_offset_modrm(insn);
460 /*
461 * Change modrm from "00 reg 101" to "10 reg reg2". Example:
462 * 89 05 disp32 mov %eax,disp32(%rip) becomes
463 * 89 86 disp32 mov %eax,disp32(%rsi)
464 */
465 *cursor = 0x80 | (reg << 3) | reg2;
466}
467
468static inline unsigned long *
469scratch_reg(struct arch_uprobe *auprobe, struct pt_regs *regs)
470{
471 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_SI)
472 return ®s->si;
473 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_DI)
474 return ®s->di;
475 return ®s->bx;
476}
477
478/*
479 * If we're emulating a rip-relative instruction, save the contents
480 * of the scratch register and store the target address in that register.
481 */
482static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
483{
484 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
485 struct uprobe_task *utask = current->utask;
486 unsigned long *sr = scratch_reg(auprobe, regs);
487
488 utask->autask.saved_scratch_register = *sr;
489 *sr = utask->vaddr + auprobe->defparam.ilen;
490 }
491}
492
493static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
494{
495 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
496 struct uprobe_task *utask = current->utask;
497 unsigned long *sr = scratch_reg(auprobe, regs);
498
499 *sr = utask->autask.saved_scratch_register;
500 }
501}
502#else /* 32-bit: */
503/*
504 * No RIP-relative addressing on 32-bit
505 */
506static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
507{
508}
509static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
510{
511}
512static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
513{
514}
515#endif /* CONFIG_X86_64 */
516
517struct uprobe_xol_ops {
518 bool (*emulate)(struct arch_uprobe *, struct pt_regs *);
519 int (*pre_xol)(struct arch_uprobe *, struct pt_regs *);
520 int (*post_xol)(struct arch_uprobe *, struct pt_regs *);
521 void (*abort)(struct arch_uprobe *, struct pt_regs *);
522};
523
524static inline int sizeof_long(void)
525{
526 return in_ia32_syscall() ? 4 : 8;
527}
528
529static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
530{
531 riprel_pre_xol(auprobe, regs);
532 return 0;
533}
534
535static int emulate_push_stack(struct pt_regs *regs, unsigned long val)
536{
537 unsigned long new_sp = regs->sp - sizeof_long();
538
539 if (copy_to_user((void __user *)new_sp, &val, sizeof_long()))
540 return -EFAULT;
541
542 regs->sp = new_sp;
543 return 0;
544}
545
546/*
547 * We have to fix things up as follows:
548 *
549 * Typically, the new ip is relative to the copied instruction. We need
550 * to make it relative to the original instruction (FIX_IP). Exceptions
551 * are return instructions and absolute or indirect jump or call instructions.
552 *
553 * If the single-stepped instruction was a call, the return address that
554 * is atop the stack is the address following the copied instruction. We
555 * need to make it the address following the original instruction (FIX_CALL).
556 *
557 * If the original instruction was a rip-relative instruction such as
558 * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent
559 * instruction using a scratch register -- e.g., "movl %edx,0xnnnn(%rsi)".
560 * We need to restore the contents of the scratch register
561 * (FIX_RIP_reg).
562 */
563static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
564{
565 struct uprobe_task *utask = current->utask;
566
567 riprel_post_xol(auprobe, regs);
568 if (auprobe->defparam.fixups & UPROBE_FIX_IP) {
569 long correction = utask->vaddr - utask->xol_vaddr;
570 regs->ip += correction;
571 } else if (auprobe->defparam.fixups & UPROBE_FIX_CALL) {
572 regs->sp += sizeof_long(); /* Pop incorrect return address */
573 if (emulate_push_stack(regs, utask->vaddr + auprobe->defparam.ilen))
574 return -ERESTART;
575 }
576 /* popf; tell the caller to not touch TF */
577 if (auprobe->defparam.fixups & UPROBE_FIX_SETF)
578 utask->autask.saved_tf = true;
579
580 return 0;
581}
582
583static void default_abort_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
584{
585 riprel_post_xol(auprobe, regs);
586}
587
588static const struct uprobe_xol_ops default_xol_ops = {
589 .pre_xol = default_pre_xol_op,
590 .post_xol = default_post_xol_op,
591 .abort = default_abort_op,
592};
593
594static bool branch_is_call(struct arch_uprobe *auprobe)
595{
596 return auprobe->branch.opc1 == 0xe8;
597}
598
599#define CASE_COND \
600 COND(70, 71, XF(OF)) \
601 COND(72, 73, XF(CF)) \
602 COND(74, 75, XF(ZF)) \
603 COND(78, 79, XF(SF)) \
604 COND(7a, 7b, XF(PF)) \
605 COND(76, 77, XF(CF) || XF(ZF)) \
606 COND(7c, 7d, XF(SF) != XF(OF)) \
607 COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF))
608
609#define COND(op_y, op_n, expr) \
610 case 0x ## op_y: DO((expr) != 0) \
611 case 0x ## op_n: DO((expr) == 0)
612
613#define XF(xf) (!!(flags & X86_EFLAGS_ ## xf))
614
615static bool is_cond_jmp_opcode(u8 opcode)
616{
617 switch (opcode) {
618 #define DO(expr) \
619 return true;
620 CASE_COND
621 #undef DO
622
623 default:
624 return false;
625 }
626}
627
628static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs)
629{
630 unsigned long flags = regs->flags;
631
632 switch (auprobe->branch.opc1) {
633 #define DO(expr) \
634 return expr;
635 CASE_COND
636 #undef DO
637
638 default: /* not a conditional jmp */
639 return true;
640 }
641}
642
643#undef XF
644#undef COND
645#undef CASE_COND
646
647static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
648{
649 unsigned long new_ip = regs->ip += auprobe->branch.ilen;
650 unsigned long offs = (long)auprobe->branch.offs;
651
652 if (branch_is_call(auprobe)) {
653 /*
654 * If it fails we execute this (mangled, see the comment in
655 * branch_clear_offset) insn out-of-line. In the likely case
656 * this should trigger the trap, and the probed application
657 * should die or restart the same insn after it handles the
658 * signal, arch_uprobe_post_xol() won't be even called.
659 *
660 * But there is corner case, see the comment in ->post_xol().
661 */
662 if (emulate_push_stack(regs, new_ip))
663 return false;
664 } else if (!check_jmp_cond(auprobe, regs)) {
665 offs = 0;
666 }
667
668 regs->ip = new_ip + offs;
669 return true;
670}
671
672static bool push_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
673{
674 unsigned long *src_ptr = (void *)regs + auprobe->push.reg_offset;
675
676 if (emulate_push_stack(regs, *src_ptr))
677 return false;
678 regs->ip += auprobe->push.ilen;
679 return true;
680}
681
682static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
683{
684 BUG_ON(!branch_is_call(auprobe));
685 /*
686 * We can only get here if branch_emulate_op() failed to push the ret
687 * address _and_ another thread expanded our stack before the (mangled)
688 * "call" insn was executed out-of-line. Just restore ->sp and restart.
689 * We could also restore ->ip and try to call branch_emulate_op() again.
690 */
691 regs->sp += sizeof_long();
692 return -ERESTART;
693}
694
695static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn)
696{
697 /*
698 * Turn this insn into "call 1f; 1:", this is what we will execute
699 * out-of-line if ->emulate() fails. We only need this to generate
700 * a trap, so that the probed task receives the correct signal with
701 * the properly filled siginfo.
702 *
703 * But see the comment in ->post_xol(), in the unlikely case it can
704 * succeed. So we need to ensure that the new ->ip can not fall into
705 * the non-canonical area and trigger #GP.
706 *
707 * We could turn it into (say) "pushf", but then we would need to
708 * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte
709 * of ->insn[] for set_orig_insn().
710 */
711 memset(auprobe->insn + insn_offset_immediate(insn),
712 0, insn->immediate.nbytes);
713}
714
715static const struct uprobe_xol_ops branch_xol_ops = {
716 .emulate = branch_emulate_op,
717 .post_xol = branch_post_xol_op,
718};
719
720static const struct uprobe_xol_ops push_xol_ops = {
721 .emulate = push_emulate_op,
722};
723
724/* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */
725static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
726{
727 u8 opc1 = OPCODE1(insn);
728 int i;
729
730 switch (opc1) {
731 case 0xeb: /* jmp 8 */
732 case 0xe9: /* jmp 32 */
733 case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */
734 break;
735
736 case 0xe8: /* call relative */
737 branch_clear_offset(auprobe, insn);
738 break;
739
740 case 0x0f:
741 if (insn->opcode.nbytes != 2)
742 return -ENOSYS;
743 /*
744 * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches
745 * OPCODE1() of the "short" jmp which checks the same condition.
746 */
747 opc1 = OPCODE2(insn) - 0x10;
748 default:
749 if (!is_cond_jmp_opcode(opc1))
750 return -ENOSYS;
751 }
752
753 /*
754 * 16-bit overrides such as CALLW (66 e8 nn nn) are not supported.
755 * Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix.
756 * No one uses these insns, reject any branch insns with such prefix.
757 */
758 for (i = 0; i < insn->prefixes.nbytes; i++) {
759 if (insn->prefixes.bytes[i] == 0x66)
760 return -ENOTSUPP;
761 }
762
763 auprobe->branch.opc1 = opc1;
764 auprobe->branch.ilen = insn->length;
765 auprobe->branch.offs = insn->immediate.value;
766
767 auprobe->ops = &branch_xol_ops;
768 return 0;
769}
770
771/* Returns -ENOSYS if push_xol_ops doesn't handle this insn */
772static int push_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
773{
774 u8 opc1 = OPCODE1(insn), reg_offset = 0;
775
776 if (opc1 < 0x50 || opc1 > 0x57)
777 return -ENOSYS;
778
779 if (insn->length > 2)
780 return -ENOSYS;
781 if (insn->length == 2) {
782 /* only support rex_prefix 0x41 (x64 only) */
783#ifdef CONFIG_X86_64
784 if (insn->rex_prefix.nbytes != 1 ||
785 insn->rex_prefix.bytes[0] != 0x41)
786 return -ENOSYS;
787
788 switch (opc1) {
789 case 0x50:
790 reg_offset = offsetof(struct pt_regs, r8);
791 break;
792 case 0x51:
793 reg_offset = offsetof(struct pt_regs, r9);
794 break;
795 case 0x52:
796 reg_offset = offsetof(struct pt_regs, r10);
797 break;
798 case 0x53:
799 reg_offset = offsetof(struct pt_regs, r11);
800 break;
801 case 0x54:
802 reg_offset = offsetof(struct pt_regs, r12);
803 break;
804 case 0x55:
805 reg_offset = offsetof(struct pt_regs, r13);
806 break;
807 case 0x56:
808 reg_offset = offsetof(struct pt_regs, r14);
809 break;
810 case 0x57:
811 reg_offset = offsetof(struct pt_regs, r15);
812 break;
813 }
814#else
815 return -ENOSYS;
816#endif
817 } else {
818 switch (opc1) {
819 case 0x50:
820 reg_offset = offsetof(struct pt_regs, ax);
821 break;
822 case 0x51:
823 reg_offset = offsetof(struct pt_regs, cx);
824 break;
825 case 0x52:
826 reg_offset = offsetof(struct pt_regs, dx);
827 break;
828 case 0x53:
829 reg_offset = offsetof(struct pt_regs, bx);
830 break;
831 case 0x54:
832 reg_offset = offsetof(struct pt_regs, sp);
833 break;
834 case 0x55:
835 reg_offset = offsetof(struct pt_regs, bp);
836 break;
837 case 0x56:
838 reg_offset = offsetof(struct pt_regs, si);
839 break;
840 case 0x57:
841 reg_offset = offsetof(struct pt_regs, di);
842 break;
843 }
844 }
845
846 auprobe->push.reg_offset = reg_offset;
847 auprobe->push.ilen = insn->length;
848 auprobe->ops = &push_xol_ops;
849 return 0;
850}
851
852/**
853 * arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
854 * @mm: the probed address space.
855 * @arch_uprobe: the probepoint information.
856 * @addr: virtual address at which to install the probepoint
857 * Return 0 on success or a -ve number on error.
858 */
859int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr)
860{
861 struct insn insn;
862 u8 fix_ip_or_call = UPROBE_FIX_IP;
863 int ret;
864
865 ret = uprobe_init_insn(auprobe, &insn, is_64bit_mm(mm));
866 if (ret)
867 return ret;
868
869 ret = branch_setup_xol_ops(auprobe, &insn);
870 if (ret != -ENOSYS)
871 return ret;
872
873 ret = push_setup_xol_ops(auprobe, &insn);
874 if (ret != -ENOSYS)
875 return ret;
876
877 /*
878 * Figure out which fixups default_post_xol_op() will need to perform,
879 * and annotate defparam->fixups accordingly.
880 */
881 switch (OPCODE1(&insn)) {
882 case 0x9d: /* popf */
883 auprobe->defparam.fixups |= UPROBE_FIX_SETF;
884 break;
885 case 0xc3: /* ret or lret -- ip is correct */
886 case 0xcb:
887 case 0xc2:
888 case 0xca:
889 case 0xea: /* jmp absolute -- ip is correct */
890 fix_ip_or_call = 0;
891 break;
892 case 0x9a: /* call absolute - Fix return addr, not ip */
893 fix_ip_or_call = UPROBE_FIX_CALL;
894 break;
895 case 0xff:
896 switch (MODRM_REG(&insn)) {
897 case 2: case 3: /* call or lcall, indirect */
898 fix_ip_or_call = UPROBE_FIX_CALL;
899 break;
900 case 4: case 5: /* jmp or ljmp, indirect */
901 fix_ip_or_call = 0;
902 break;
903 }
904 /* fall through */
905 default:
906 riprel_analyze(auprobe, &insn);
907 }
908
909 auprobe->defparam.ilen = insn.length;
910 auprobe->defparam.fixups |= fix_ip_or_call;
911
912 auprobe->ops = &default_xol_ops;
913 return 0;
914}
915
916/*
917 * arch_uprobe_pre_xol - prepare to execute out of line.
918 * @auprobe: the probepoint information.
919 * @regs: reflects the saved user state of current task.
920 */
921int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
922{
923 struct uprobe_task *utask = current->utask;
924
925 if (auprobe->ops->pre_xol) {
926 int err = auprobe->ops->pre_xol(auprobe, regs);
927 if (err)
928 return err;
929 }
930
931 regs->ip = utask->xol_vaddr;
932 utask->autask.saved_trap_nr = current->thread.trap_nr;
933 current->thread.trap_nr = UPROBE_TRAP_NR;
934
935 utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF);
936 regs->flags |= X86_EFLAGS_TF;
937 if (test_tsk_thread_flag(current, TIF_BLOCKSTEP))
938 set_task_blockstep(current, false);
939
940 return 0;
941}
942
943/*
944 * If xol insn itself traps and generates a signal(Say,
945 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
946 * instruction jumps back to its own address. It is assumed that anything
947 * like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
948 *
949 * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
950 * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
951 * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
952 */
953bool arch_uprobe_xol_was_trapped(struct task_struct *t)
954{
955 if (t->thread.trap_nr != UPROBE_TRAP_NR)
956 return true;
957
958 return false;
959}
960
961/*
962 * Called after single-stepping. To avoid the SMP problems that can
963 * occur when we temporarily put back the original opcode to
964 * single-step, we single-stepped a copy of the instruction.
965 *
966 * This function prepares to resume execution after the single-step.
967 */
968int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
969{
970 struct uprobe_task *utask = current->utask;
971 bool send_sigtrap = utask->autask.saved_tf;
972 int err = 0;
973
974 WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR);
975 current->thread.trap_nr = utask->autask.saved_trap_nr;
976
977 if (auprobe->ops->post_xol) {
978 err = auprobe->ops->post_xol(auprobe, regs);
979 if (err) {
980 /*
981 * Restore ->ip for restart or post mortem analysis.
982 * ->post_xol() must not return -ERESTART unless this
983 * is really possible.
984 */
985 regs->ip = utask->vaddr;
986 if (err == -ERESTART)
987 err = 0;
988 send_sigtrap = false;
989 }
990 }
991 /*
992 * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP
993 * so we can get an extra SIGTRAP if we do not clear TF. We need
994 * to examine the opcode to make it right.
995 */
996 if (send_sigtrap)
997 send_sig(SIGTRAP, current, 0);
998
999 if (!utask->autask.saved_tf)
1000 regs->flags &= ~X86_EFLAGS_TF;
1001
1002 return err;
1003}
1004
1005/* callback routine for handling exceptions. */
1006int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data)
1007{
1008 struct die_args *args = data;
1009 struct pt_regs *regs = args->regs;
1010 int ret = NOTIFY_DONE;
1011
1012 /* We are only interested in userspace traps */
1013 if (regs && !user_mode(regs))
1014 return NOTIFY_DONE;
1015
1016 switch (val) {
1017 case DIE_INT3:
1018 if (uprobe_pre_sstep_notifier(regs))
1019 ret = NOTIFY_STOP;
1020
1021 break;
1022
1023 case DIE_DEBUG:
1024 if (uprobe_post_sstep_notifier(regs))
1025 ret = NOTIFY_STOP;
1026
1027 default:
1028 break;
1029 }
1030
1031 return ret;
1032}
1033
1034/*
1035 * This function gets called when XOL instruction either gets trapped or
1036 * the thread has a fatal signal. Reset the instruction pointer to its
1037 * probed address for the potential restart or for post mortem analysis.
1038 */
1039void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
1040{
1041 struct uprobe_task *utask = current->utask;
1042
1043 if (auprobe->ops->abort)
1044 auprobe->ops->abort(auprobe, regs);
1045
1046 current->thread.trap_nr = utask->autask.saved_trap_nr;
1047 regs->ip = utask->vaddr;
1048 /* clear TF if it was set by us in arch_uprobe_pre_xol() */
1049 if (!utask->autask.saved_tf)
1050 regs->flags &= ~X86_EFLAGS_TF;
1051}
1052
1053static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
1054{
1055 if (auprobe->ops->emulate)
1056 return auprobe->ops->emulate(auprobe, regs);
1057 return false;
1058}
1059
1060bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
1061{
1062 bool ret = __skip_sstep(auprobe, regs);
1063 if (ret && (regs->flags & X86_EFLAGS_TF))
1064 send_sig(SIGTRAP, current, 0);
1065 return ret;
1066}
1067
1068unsigned long
1069arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs)
1070{
1071 int rasize = sizeof_long(), nleft;
1072 unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */
1073
1074 if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize))
1075 return -1;
1076
1077 /* check whether address has been already hijacked */
1078 if (orig_ret_vaddr == trampoline_vaddr)
1079 return orig_ret_vaddr;
1080
1081 nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize);
1082 if (likely(!nleft))
1083 return orig_ret_vaddr;
1084
1085 if (nleft != rasize) {
1086 pr_err("uprobe: return address clobbered: pid=%d, %%sp=%#lx, "
1087 "%%ip=%#lx\n", current->pid, regs->sp, regs->ip);
1088
1089 force_sig_info(SIGSEGV, SEND_SIG_FORCED, current);
1090 }
1091
1092 return -1;
1093}
1094
1095bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx,
1096 struct pt_regs *regs)
1097{
1098 if (ctx == RP_CHECK_CALL) /* sp was just decremented by "call" insn */
1099 return regs->sp < ret->stack;
1100 else
1101 return regs->sp <= ret->stack;
1102}
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * User-space Probes (UProbes) for x86
4 *
5 * Copyright (C) IBM Corporation, 2008-2011
6 * Authors:
7 * Srikar Dronamraju
8 * Jim Keniston
9 */
10#include <linux/kernel.h>
11#include <linux/sched.h>
12#include <linux/ptrace.h>
13#include <linux/uprobes.h>
14#include <linux/uaccess.h>
15#include <linux/syscalls.h>
16
17#include <linux/kdebug.h>
18#include <asm/processor.h>
19#include <asm/insn.h>
20#include <asm/mmu_context.h>
21
22/* Post-execution fixups. */
23
24/* Adjust IP back to vicinity of actual insn */
25#define UPROBE_FIX_IP 0x01
26
27/* Adjust the return address of a call insn */
28#define UPROBE_FIX_CALL 0x02
29
30/* Instruction will modify TF, don't change it */
31#define UPROBE_FIX_SETF 0x04
32
33#define UPROBE_FIX_RIP_SI 0x08
34#define UPROBE_FIX_RIP_DI 0x10
35#define UPROBE_FIX_RIP_BX 0x20
36#define UPROBE_FIX_RIP_MASK \
37 (UPROBE_FIX_RIP_SI | UPROBE_FIX_RIP_DI | UPROBE_FIX_RIP_BX)
38
39#define UPROBE_TRAP_NR UINT_MAX
40
41/* Adaptations for mhiramat x86 decoder v14. */
42#define OPCODE1(insn) ((insn)->opcode.bytes[0])
43#define OPCODE2(insn) ((insn)->opcode.bytes[1])
44#define OPCODE3(insn) ((insn)->opcode.bytes[2])
45#define MODRM_REG(insn) X86_MODRM_REG((insn)->modrm.value)
46
47#define W(row, b0, b1, b2, b3, b4, b5, b6, b7, b8, b9, ba, bb, bc, bd, be, bf)\
48 (((b0##UL << 0x0)|(b1##UL << 0x1)|(b2##UL << 0x2)|(b3##UL << 0x3) | \
49 (b4##UL << 0x4)|(b5##UL << 0x5)|(b6##UL << 0x6)|(b7##UL << 0x7) | \
50 (b8##UL << 0x8)|(b9##UL << 0x9)|(ba##UL << 0xa)|(bb##UL << 0xb) | \
51 (bc##UL << 0xc)|(bd##UL << 0xd)|(be##UL << 0xe)|(bf##UL << 0xf)) \
52 << (row % 32))
53
54/*
55 * Good-instruction tables for 32-bit apps. This is non-const and volatile
56 * to keep gcc from statically optimizing it out, as variable_test_bit makes
57 * some versions of gcc to think only *(unsigned long*) is used.
58 *
59 * Opcodes we'll probably never support:
60 * 6c-6f - ins,outs. SEGVs if used in userspace
61 * e4-e7 - in,out imm. SEGVs if used in userspace
62 * ec-ef - in,out acc. SEGVs if used in userspace
63 * cc - int3. SIGTRAP if used in userspace
64 * ce - into. Not used in userspace - no kernel support to make it useful. SEGVs
65 * (why we support bound (62) then? it's similar, and similarly unused...)
66 * f1 - int1. SIGTRAP if used in userspace
67 * f4 - hlt. SEGVs if used in userspace
68 * fa - cli. SEGVs if used in userspace
69 * fb - sti. SEGVs if used in userspace
70 *
71 * Opcodes which need some work to be supported:
72 * 07,17,1f - pop es/ss/ds
73 * Normally not used in userspace, but would execute if used.
74 * Can cause GP or stack exception if tries to load wrong segment descriptor.
75 * We hesitate to run them under single step since kernel's handling
76 * of userspace single-stepping (TF flag) is fragile.
77 * We can easily refuse to support push es/cs/ss/ds (06/0e/16/1e)
78 * on the same grounds that they are never used.
79 * cd - int N.
80 * Used by userspace for "int 80" syscall entry. (Other "int N"
81 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
82 * Not supported since kernel's handling of userspace single-stepping
83 * (TF flag) is fragile.
84 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
85 */
86#if defined(CONFIG_X86_32) || defined(CONFIG_IA32_EMULATION)
87static volatile u32 good_insns_32[256 / 32] = {
88 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
89 /* ---------------------------------------------- */
90 W(0x00, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) | /* 00 */
91 W(0x10, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 10 */
92 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
93 W(0x30, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
94 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
95 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
96 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
97 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
98 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
99 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
100 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
101 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
102 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
103 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
104 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 1, 1, 0, 0, 0, 0) | /* e0 */
105 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
106 /* ---------------------------------------------- */
107 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
108};
109#else
110#define good_insns_32 NULL
111#endif
112
113/* Good-instruction tables for 64-bit apps.
114 *
115 * Genuinely invalid opcodes:
116 * 06,07 - formerly push/pop es
117 * 0e - formerly push cs
118 * 16,17 - formerly push/pop ss
119 * 1e,1f - formerly push/pop ds
120 * 27,2f,37,3f - formerly daa/das/aaa/aas
121 * 60,61 - formerly pusha/popa
122 * 62 - formerly bound. EVEX prefix for AVX512 (not yet supported)
123 * 82 - formerly redundant encoding of Group1
124 * 9a - formerly call seg:ofs
125 * ce - formerly into
126 * d4,d5 - formerly aam/aad
127 * d6 - formerly undocumented salc
128 * ea - formerly jmp seg:ofs
129 *
130 * Opcodes we'll probably never support:
131 * 6c-6f - ins,outs. SEGVs if used in userspace
132 * e4-e7 - in,out imm. SEGVs if used in userspace
133 * ec-ef - in,out acc. SEGVs if used in userspace
134 * cc - int3. SIGTRAP if used in userspace
135 * f1 - int1. SIGTRAP if used in userspace
136 * f4 - hlt. SEGVs if used in userspace
137 * fa - cli. SEGVs if used in userspace
138 * fb - sti. SEGVs if used in userspace
139 *
140 * Opcodes which need some work to be supported:
141 * cd - int N.
142 * Used by userspace for "int 80" syscall entry. (Other "int N"
143 * cause GP -> SEGV since their IDT gates don't allow calls from CPL 3).
144 * Not supported since kernel's handling of userspace single-stepping
145 * (TF flag) is fragile.
146 * cf - iret. Normally not used in userspace. Doesn't SEGV unless arguments are bad
147 */
148#if defined(CONFIG_X86_64)
149static volatile u32 good_insns_64[256 / 32] = {
150 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
151 /* ---------------------------------------------- */
152 W(0x00, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 1) | /* 00 */
153 W(0x10, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1, 0, 0) , /* 10 */
154 W(0x20, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) | /* 20 */
155 W(0x30, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 0) , /* 30 */
156 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
157 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
158 W(0x60, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* 60 */
159 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 70 */
160 W(0x80, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
161 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1, 1, 1, 1, 1) , /* 90 */
162 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* a0 */
163 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
164 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 0, 0) | /* c0 */
165 W(0xd0, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
166 W(0xe0, 1, 1, 1, 1, 0, 0, 0, 0, 1, 1, 0, 1, 0, 0, 0, 0) | /* e0 */
167 W(0xf0, 1, 0, 1, 1, 0, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1) /* f0 */
168 /* ---------------------------------------------- */
169 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
170};
171#else
172#define good_insns_64 NULL
173#endif
174
175/* Using this for both 64-bit and 32-bit apps.
176 * Opcodes we don't support:
177 * 0f 00 - SLDT/STR/LLDT/LTR/VERR/VERW/-/- group. System insns
178 * 0f 01 - SGDT/SIDT/LGDT/LIDT/SMSW/-/LMSW/INVLPG group.
179 * Also encodes tons of other system insns if mod=11.
180 * Some are in fact non-system: xend, xtest, rdtscp, maybe more
181 * 0f 05 - syscall
182 * 0f 06 - clts (CPL0 insn)
183 * 0f 07 - sysret
184 * 0f 08 - invd (CPL0 insn)
185 * 0f 09 - wbinvd (CPL0 insn)
186 * 0f 0b - ud2
187 * 0f 30 - wrmsr (CPL0 insn) (then why rdmsr is allowed, it's also CPL0 insn?)
188 * 0f 34 - sysenter
189 * 0f 35 - sysexit
190 * 0f 37 - getsec
191 * 0f 78 - vmread (Intel VMX. CPL0 insn)
192 * 0f 79 - vmwrite (Intel VMX. CPL0 insn)
193 * Note: with prefixes, these two opcodes are
194 * extrq/insertq/AVX512 convert vector ops.
195 * 0f ae - group15: [f]xsave,[f]xrstor,[v]{ld,st}mxcsr,clflush[opt],
196 * {rd,wr}{fs,gs}base,{s,l,m}fence.
197 * Why? They are all user-executable.
198 */
199static volatile u32 good_2byte_insns[256 / 32] = {
200 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
201 /* ---------------------------------------------- */
202 W(0x00, 0, 0, 1, 1, 1, 0, 0, 0, 0, 0, 1, 0, 1, 1, 1, 1) | /* 00 */
203 W(0x10, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 10 */
204 W(0x20, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 20 */
205 W(0x30, 0, 1, 1, 1, 0, 0, 1, 0, 1, 1, 1, 1, 1, 1, 1, 1) , /* 30 */
206 W(0x40, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 40 */
207 W(0x50, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 50 */
208 W(0x60, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 60 */
209 W(0x70, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, 1, 1, 1, 1, 1, 1) , /* 70 */
210 W(0x80, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* 80 */
211 W(0x90, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* 90 */
212 W(0xa0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 1) | /* a0 */
213 W(0xb0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* b0 */
214 W(0xc0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* c0 */
215 W(0xd0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) , /* d0 */
216 W(0xe0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) | /* e0 */
217 W(0xf0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) /* f0 */
218 /* ---------------------------------------------- */
219 /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */
220};
221#undef W
222
223/*
224 * opcodes we may need to refine support for:
225 *
226 * 0f - 2-byte instructions: For many of these instructions, the validity
227 * depends on the prefix and/or the reg field. On such instructions, we
228 * just consider the opcode combination valid if it corresponds to any
229 * valid instruction.
230 *
231 * 8f - Group 1 - only reg = 0 is OK
232 * c6-c7 - Group 11 - only reg = 0 is OK
233 * d9-df - fpu insns with some illegal encodings
234 * f2, f3 - repnz, repz prefixes. These are also the first byte for
235 * certain floating-point instructions, such as addsd.
236 *
237 * fe - Group 4 - only reg = 0 or 1 is OK
238 * ff - Group 5 - only reg = 0-6 is OK
239 *
240 * others -- Do we need to support these?
241 *
242 * 0f - (floating-point?) prefetch instructions
243 * 07, 17, 1f - pop es, pop ss, pop ds
244 * 26, 2e, 36, 3e - es:, cs:, ss:, ds: segment prefixes --
245 * but 64 and 65 (fs: and gs:) seem to be used, so we support them
246 * 67 - addr16 prefix
247 * ce - into
248 * f0 - lock prefix
249 */
250
251/*
252 * TODO:
253 * - Where necessary, examine the modrm byte and allow only valid instructions
254 * in the different Groups and fpu instructions.
255 */
256
257static bool is_prefix_bad(struct insn *insn)
258{
259 insn_byte_t p;
260 int i;
261
262 for_each_insn_prefix(insn, i, p) {
263 insn_attr_t attr;
264
265 attr = inat_get_opcode_attribute(p);
266 switch (attr) {
267 case INAT_MAKE_PREFIX(INAT_PFX_ES):
268 case INAT_MAKE_PREFIX(INAT_PFX_CS):
269 case INAT_MAKE_PREFIX(INAT_PFX_DS):
270 case INAT_MAKE_PREFIX(INAT_PFX_SS):
271 case INAT_MAKE_PREFIX(INAT_PFX_LOCK):
272 return true;
273 }
274 }
275 return false;
276}
277
278static int uprobe_init_insn(struct arch_uprobe *auprobe, struct insn *insn, bool x86_64)
279{
280 enum insn_mode m = x86_64 ? INSN_MODE_64 : INSN_MODE_32;
281 u32 volatile *good_insns;
282 int ret;
283
284 ret = insn_decode(insn, auprobe->insn, sizeof(auprobe->insn), m);
285 if (ret < 0)
286 return -ENOEXEC;
287
288 if (is_prefix_bad(insn))
289 return -ENOTSUPP;
290
291 /* We should not singlestep on the exception masking instructions */
292 if (insn_masking_exception(insn))
293 return -ENOTSUPP;
294
295 if (x86_64)
296 good_insns = good_insns_64;
297 else
298 good_insns = good_insns_32;
299
300 if (test_bit(OPCODE1(insn), (unsigned long *)good_insns))
301 return 0;
302
303 if (insn->opcode.nbytes == 2) {
304 if (test_bit(OPCODE2(insn), (unsigned long *)good_2byte_insns))
305 return 0;
306 }
307
308 return -ENOTSUPP;
309}
310
311#ifdef CONFIG_X86_64
312
313asm (
314 ".pushsection .rodata\n"
315 ".global uretprobe_trampoline_entry\n"
316 "uretprobe_trampoline_entry:\n"
317 "pushq %rax\n"
318 "pushq %rcx\n"
319 "pushq %r11\n"
320 "movq $" __stringify(__NR_uretprobe) ", %rax\n"
321 "syscall\n"
322 ".global uretprobe_syscall_check\n"
323 "uretprobe_syscall_check:\n"
324 "popq %r11\n"
325 "popq %rcx\n"
326
327 /* The uretprobe syscall replaces stored %rax value with final
328 * return address, so we don't restore %rax in here and just
329 * call ret.
330 */
331 "retq\n"
332 ".global uretprobe_trampoline_end\n"
333 "uretprobe_trampoline_end:\n"
334 ".popsection\n"
335);
336
337extern u8 uretprobe_trampoline_entry[];
338extern u8 uretprobe_trampoline_end[];
339extern u8 uretprobe_syscall_check[];
340
341void *arch_uprobe_trampoline(unsigned long *psize)
342{
343 static uprobe_opcode_t insn = UPROBE_SWBP_INSN;
344 struct pt_regs *regs = task_pt_regs(current);
345
346 /*
347 * At the moment the uretprobe syscall trampoline is supported
348 * only for native 64-bit process, the compat process still uses
349 * standard breakpoint.
350 */
351 if (user_64bit_mode(regs)) {
352 *psize = uretprobe_trampoline_end - uretprobe_trampoline_entry;
353 return uretprobe_trampoline_entry;
354 }
355
356 *psize = UPROBE_SWBP_INSN_SIZE;
357 return &insn;
358}
359
360static unsigned long trampoline_check_ip(void)
361{
362 unsigned long tramp = uprobe_get_trampoline_vaddr();
363
364 return tramp + (uretprobe_syscall_check - uretprobe_trampoline_entry);
365}
366
367SYSCALL_DEFINE0(uretprobe)
368{
369 struct pt_regs *regs = task_pt_regs(current);
370 unsigned long err, ip, sp, r11_cx_ax[3];
371
372 if (regs->ip != trampoline_check_ip())
373 goto sigill;
374
375 err = copy_from_user(r11_cx_ax, (void __user *)regs->sp, sizeof(r11_cx_ax));
376 if (err)
377 goto sigill;
378
379 /* expose the "right" values of r11/cx/ax/sp to uprobe_consumer/s */
380 regs->r11 = r11_cx_ax[0];
381 regs->cx = r11_cx_ax[1];
382 regs->ax = r11_cx_ax[2];
383 regs->sp += sizeof(r11_cx_ax);
384 regs->orig_ax = -1;
385
386 ip = regs->ip;
387 sp = regs->sp;
388
389 uprobe_handle_trampoline(regs);
390
391 /*
392 * Some of the uprobe consumers has changed sp, we can do nothing,
393 * just return via iret.
394 * .. or shadow stack is enabled, in which case we need to skip
395 * return through the user space stack address.
396 */
397 if (regs->sp != sp || shstk_is_enabled())
398 return regs->ax;
399 regs->sp -= sizeof(r11_cx_ax);
400
401 /* for the case uprobe_consumer has changed r11/cx */
402 r11_cx_ax[0] = regs->r11;
403 r11_cx_ax[1] = regs->cx;
404
405 /*
406 * ax register is passed through as return value, so we can use
407 * its space on stack for ip value and jump to it through the
408 * trampoline's ret instruction
409 */
410 r11_cx_ax[2] = regs->ip;
411 regs->ip = ip;
412
413 err = copy_to_user((void __user *)regs->sp, r11_cx_ax, sizeof(r11_cx_ax));
414 if (err)
415 goto sigill;
416
417 /* ensure sysret, see do_syscall_64() */
418 regs->r11 = regs->flags;
419 regs->cx = regs->ip;
420
421 return regs->ax;
422
423sigill:
424 force_sig(SIGILL);
425 return -1;
426}
427
428/*
429 * If arch_uprobe->insn doesn't use rip-relative addressing, return
430 * immediately. Otherwise, rewrite the instruction so that it accesses
431 * its memory operand indirectly through a scratch register. Set
432 * defparam->fixups accordingly. (The contents of the scratch register
433 * will be saved before we single-step the modified instruction,
434 * and restored afterward).
435 *
436 * We do this because a rip-relative instruction can access only a
437 * relatively small area (+/- 2 GB from the instruction), and the XOL
438 * area typically lies beyond that area. At least for instructions
439 * that store to memory, we can't execute the original instruction
440 * and "fix things up" later, because the misdirected store could be
441 * disastrous.
442 *
443 * Some useful facts about rip-relative instructions:
444 *
445 * - There's always a modrm byte with bit layout "00 reg 101".
446 * - There's never a SIB byte.
447 * - The displacement is always 4 bytes.
448 * - REX.B=1 bit in REX prefix, which normally extends r/m field,
449 * has no effect on rip-relative mode. It doesn't make modrm byte
450 * with r/m=101 refer to register 1101 = R13.
451 */
452static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
453{
454 u8 *cursor;
455 u8 reg;
456 u8 reg2;
457
458 if (!insn_rip_relative(insn))
459 return;
460
461 /*
462 * insn_rip_relative() would have decoded rex_prefix, vex_prefix, modrm.
463 * Clear REX.b bit (extension of MODRM.rm field):
464 * we want to encode low numbered reg, not r8+.
465 */
466 if (insn->rex_prefix.nbytes) {
467 cursor = auprobe->insn + insn_offset_rex_prefix(insn);
468 /* REX byte has 0100wrxb layout, clearing REX.b bit */
469 *cursor &= 0xfe;
470 }
471 /*
472 * Similar treatment for VEX3/EVEX prefix.
473 * TODO: add XOP treatment when insn decoder supports them
474 */
475 if (insn->vex_prefix.nbytes >= 3) {
476 /*
477 * vex2: c5 rvvvvLpp (has no b bit)
478 * vex3/xop: c4/8f rxbmmmmm wvvvvLpp
479 * evex: 62 rxbR00mm wvvvv1pp zllBVaaa
480 * Setting VEX3.b (setting because it has inverted meaning).
481 * Setting EVEX.x since (in non-SIB encoding) EVEX.x
482 * is the 4th bit of MODRM.rm, and needs the same treatment.
483 * For VEX3-encoded insns, VEX3.x value has no effect in
484 * non-SIB encoding, the change is superfluous but harmless.
485 */
486 cursor = auprobe->insn + insn_offset_vex_prefix(insn) + 1;
487 *cursor |= 0x60;
488 }
489
490 /*
491 * Convert from rip-relative addressing to register-relative addressing
492 * via a scratch register.
493 *
494 * This is tricky since there are insns with modrm byte
495 * which also use registers not encoded in modrm byte:
496 * [i]div/[i]mul: implicitly use dx:ax
497 * shift ops: implicitly use cx
498 * cmpxchg: implicitly uses ax
499 * cmpxchg8/16b: implicitly uses dx:ax and bx:cx
500 * Encoding: 0f c7/1 modrm
501 * The code below thinks that reg=1 (cx), chooses si as scratch.
502 * mulx: implicitly uses dx: mulx r/m,r1,r2 does r1:r2 = dx * r/m.
503 * First appeared in Haswell (BMI2 insn). It is vex-encoded.
504 * Example where none of bx,cx,dx can be used as scratch reg:
505 * c4 e2 63 f6 0d disp32 mulx disp32(%rip),%ebx,%ecx
506 * [v]pcmpistri: implicitly uses cx, xmm0
507 * [v]pcmpistrm: implicitly uses xmm0
508 * [v]pcmpestri: implicitly uses ax, dx, cx, xmm0
509 * [v]pcmpestrm: implicitly uses ax, dx, xmm0
510 * Evil SSE4.2 string comparison ops from hell.
511 * maskmovq/[v]maskmovdqu: implicitly uses (ds:rdi) as destination.
512 * Encoding: 0f f7 modrm, 66 0f f7 modrm, vex-encoded: c5 f9 f7 modrm.
513 * Store op1, byte-masked by op2 msb's in each byte, to (ds:rdi).
514 * AMD says it has no 3-operand form (vex.vvvv must be 1111)
515 * and that it can have only register operands, not mem
516 * (its modrm byte must have mode=11).
517 * If these restrictions will ever be lifted,
518 * we'll need code to prevent selection of di as scratch reg!
519 *
520 * Summary: I don't know any insns with modrm byte which
521 * use SI register implicitly. DI register is used only
522 * by one insn (maskmovq) and BX register is used
523 * only by one too (cmpxchg8b).
524 * BP is stack-segment based (may be a problem?).
525 * AX, DX, CX are off-limits (many implicit users).
526 * SP is unusable (it's stack pointer - think about "pop mem";
527 * also, rsp+disp32 needs sib encoding -> insn length change).
528 */
529
530 reg = MODRM_REG(insn); /* Fetch modrm.reg */
531 reg2 = 0xff; /* Fetch vex.vvvv */
532 if (insn->vex_prefix.nbytes)
533 reg2 = insn->vex_prefix.bytes[2];
534 /*
535 * TODO: add XOP vvvv reading.
536 *
537 * vex.vvvv field is in bits 6-3, bits are inverted.
538 * But in 32-bit mode, high-order bit may be ignored.
539 * Therefore, let's consider only 3 low-order bits.
540 */
541 reg2 = ((reg2 >> 3) & 0x7) ^ 0x7;
542 /*
543 * Register numbering is ax,cx,dx,bx, sp,bp,si,di, r8..r15.
544 *
545 * Choose scratch reg. Order is important: must not select bx
546 * if we can use si (cmpxchg8b case!)
547 */
548 if (reg != 6 && reg2 != 6) {
549 reg2 = 6;
550 auprobe->defparam.fixups |= UPROBE_FIX_RIP_SI;
551 } else if (reg != 7 && reg2 != 7) {
552 reg2 = 7;
553 auprobe->defparam.fixups |= UPROBE_FIX_RIP_DI;
554 /* TODO (paranoia): force maskmovq to not use di */
555 } else {
556 reg2 = 3;
557 auprobe->defparam.fixups |= UPROBE_FIX_RIP_BX;
558 }
559 /*
560 * Point cursor at the modrm byte. The next 4 bytes are the
561 * displacement. Beyond the displacement, for some instructions,
562 * is the immediate operand.
563 */
564 cursor = auprobe->insn + insn_offset_modrm(insn);
565 /*
566 * Change modrm from "00 reg 101" to "10 reg reg2". Example:
567 * 89 05 disp32 mov %eax,disp32(%rip) becomes
568 * 89 86 disp32 mov %eax,disp32(%rsi)
569 */
570 *cursor = 0x80 | (reg << 3) | reg2;
571}
572
573static inline unsigned long *
574scratch_reg(struct arch_uprobe *auprobe, struct pt_regs *regs)
575{
576 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_SI)
577 return ®s->si;
578 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_DI)
579 return ®s->di;
580 return ®s->bx;
581}
582
583/*
584 * If we're emulating a rip-relative instruction, save the contents
585 * of the scratch register and store the target address in that register.
586 */
587static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
588{
589 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
590 struct uprobe_task *utask = current->utask;
591 unsigned long *sr = scratch_reg(auprobe, regs);
592
593 utask->autask.saved_scratch_register = *sr;
594 *sr = utask->vaddr + auprobe->defparam.ilen;
595 }
596}
597
598static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
599{
600 if (auprobe->defparam.fixups & UPROBE_FIX_RIP_MASK) {
601 struct uprobe_task *utask = current->utask;
602 unsigned long *sr = scratch_reg(auprobe, regs);
603
604 *sr = utask->autask.saved_scratch_register;
605 }
606}
607#else /* 32-bit: */
608/*
609 * No RIP-relative addressing on 32-bit
610 */
611static void riprel_analyze(struct arch_uprobe *auprobe, struct insn *insn)
612{
613}
614static void riprel_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
615{
616}
617static void riprel_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
618{
619}
620#endif /* CONFIG_X86_64 */
621
622struct uprobe_xol_ops {
623 bool (*emulate)(struct arch_uprobe *, struct pt_regs *);
624 int (*pre_xol)(struct arch_uprobe *, struct pt_regs *);
625 int (*post_xol)(struct arch_uprobe *, struct pt_regs *);
626 void (*abort)(struct arch_uprobe *, struct pt_regs *);
627};
628
629static inline int sizeof_long(struct pt_regs *regs)
630{
631 /*
632 * Check registers for mode as in_xxx_syscall() does not apply here.
633 */
634 return user_64bit_mode(regs) ? 8 : 4;
635}
636
637static int default_pre_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
638{
639 riprel_pre_xol(auprobe, regs);
640 return 0;
641}
642
643static int emulate_push_stack(struct pt_regs *regs, unsigned long val)
644{
645 unsigned long new_sp = regs->sp - sizeof_long(regs);
646
647 if (copy_to_user((void __user *)new_sp, &val, sizeof_long(regs)))
648 return -EFAULT;
649
650 regs->sp = new_sp;
651 return 0;
652}
653
654/*
655 * We have to fix things up as follows:
656 *
657 * Typically, the new ip is relative to the copied instruction. We need
658 * to make it relative to the original instruction (FIX_IP). Exceptions
659 * are return instructions and absolute or indirect jump or call instructions.
660 *
661 * If the single-stepped instruction was a call, the return address that
662 * is atop the stack is the address following the copied instruction. We
663 * need to make it the address following the original instruction (FIX_CALL).
664 *
665 * If the original instruction was a rip-relative instruction such as
666 * "movl %edx,0xnnnn(%rip)", we have instead executed an equivalent
667 * instruction using a scratch register -- e.g., "movl %edx,0xnnnn(%rsi)".
668 * We need to restore the contents of the scratch register
669 * (FIX_RIP_reg).
670 */
671static int default_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
672{
673 struct uprobe_task *utask = current->utask;
674
675 riprel_post_xol(auprobe, regs);
676 if (auprobe->defparam.fixups & UPROBE_FIX_IP) {
677 long correction = utask->vaddr - utask->xol_vaddr;
678 regs->ip += correction;
679 } else if (auprobe->defparam.fixups & UPROBE_FIX_CALL) {
680 regs->sp += sizeof_long(regs); /* Pop incorrect return address */
681 if (emulate_push_stack(regs, utask->vaddr + auprobe->defparam.ilen))
682 return -ERESTART;
683 }
684 /* popf; tell the caller to not touch TF */
685 if (auprobe->defparam.fixups & UPROBE_FIX_SETF)
686 utask->autask.saved_tf = true;
687
688 return 0;
689}
690
691static void default_abort_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
692{
693 riprel_post_xol(auprobe, regs);
694}
695
696static const struct uprobe_xol_ops default_xol_ops = {
697 .pre_xol = default_pre_xol_op,
698 .post_xol = default_post_xol_op,
699 .abort = default_abort_op,
700};
701
702static bool branch_is_call(struct arch_uprobe *auprobe)
703{
704 return auprobe->branch.opc1 == 0xe8;
705}
706
707#define CASE_COND \
708 COND(70, 71, XF(OF)) \
709 COND(72, 73, XF(CF)) \
710 COND(74, 75, XF(ZF)) \
711 COND(78, 79, XF(SF)) \
712 COND(7a, 7b, XF(PF)) \
713 COND(76, 77, XF(CF) || XF(ZF)) \
714 COND(7c, 7d, XF(SF) != XF(OF)) \
715 COND(7e, 7f, XF(ZF) || XF(SF) != XF(OF))
716
717#define COND(op_y, op_n, expr) \
718 case 0x ## op_y: DO((expr) != 0) \
719 case 0x ## op_n: DO((expr) == 0)
720
721#define XF(xf) (!!(flags & X86_EFLAGS_ ## xf))
722
723static bool is_cond_jmp_opcode(u8 opcode)
724{
725 switch (opcode) {
726 #define DO(expr) \
727 return true;
728 CASE_COND
729 #undef DO
730
731 default:
732 return false;
733 }
734}
735
736static bool check_jmp_cond(struct arch_uprobe *auprobe, struct pt_regs *regs)
737{
738 unsigned long flags = regs->flags;
739
740 switch (auprobe->branch.opc1) {
741 #define DO(expr) \
742 return expr;
743 CASE_COND
744 #undef DO
745
746 default: /* not a conditional jmp */
747 return true;
748 }
749}
750
751#undef XF
752#undef COND
753#undef CASE_COND
754
755static bool branch_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
756{
757 unsigned long new_ip = regs->ip += auprobe->branch.ilen;
758 unsigned long offs = (long)auprobe->branch.offs;
759
760 if (branch_is_call(auprobe)) {
761 /*
762 * If it fails we execute this (mangled, see the comment in
763 * branch_clear_offset) insn out-of-line. In the likely case
764 * this should trigger the trap, and the probed application
765 * should die or restart the same insn after it handles the
766 * signal, arch_uprobe_post_xol() won't be even called.
767 *
768 * But there is corner case, see the comment in ->post_xol().
769 */
770 if (emulate_push_stack(regs, new_ip))
771 return false;
772 } else if (!check_jmp_cond(auprobe, regs)) {
773 offs = 0;
774 }
775
776 regs->ip = new_ip + offs;
777 return true;
778}
779
780static bool push_emulate_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
781{
782 unsigned long *src_ptr = (void *)regs + auprobe->push.reg_offset;
783
784 if (emulate_push_stack(regs, *src_ptr))
785 return false;
786 regs->ip += auprobe->push.ilen;
787 return true;
788}
789
790static int branch_post_xol_op(struct arch_uprobe *auprobe, struct pt_regs *regs)
791{
792 BUG_ON(!branch_is_call(auprobe));
793 /*
794 * We can only get here if branch_emulate_op() failed to push the ret
795 * address _and_ another thread expanded our stack before the (mangled)
796 * "call" insn was executed out-of-line. Just restore ->sp and restart.
797 * We could also restore ->ip and try to call branch_emulate_op() again.
798 */
799 regs->sp += sizeof_long(regs);
800 return -ERESTART;
801}
802
803static void branch_clear_offset(struct arch_uprobe *auprobe, struct insn *insn)
804{
805 /*
806 * Turn this insn into "call 1f; 1:", this is what we will execute
807 * out-of-line if ->emulate() fails. We only need this to generate
808 * a trap, so that the probed task receives the correct signal with
809 * the properly filled siginfo.
810 *
811 * But see the comment in ->post_xol(), in the unlikely case it can
812 * succeed. So we need to ensure that the new ->ip can not fall into
813 * the non-canonical area and trigger #GP.
814 *
815 * We could turn it into (say) "pushf", but then we would need to
816 * divorce ->insn[] and ->ixol[]. We need to preserve the 1st byte
817 * of ->insn[] for set_orig_insn().
818 */
819 memset(auprobe->insn + insn_offset_immediate(insn),
820 0, insn->immediate.nbytes);
821}
822
823static const struct uprobe_xol_ops branch_xol_ops = {
824 .emulate = branch_emulate_op,
825 .post_xol = branch_post_xol_op,
826};
827
828static const struct uprobe_xol_ops push_xol_ops = {
829 .emulate = push_emulate_op,
830};
831
832/* Returns -ENOSYS if branch_xol_ops doesn't handle this insn */
833static int branch_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
834{
835 u8 opc1 = OPCODE1(insn);
836 insn_byte_t p;
837 int i;
838
839 switch (opc1) {
840 case 0xeb: /* jmp 8 */
841 case 0xe9: /* jmp 32 */
842 break;
843 case 0x90: /* prefix* + nop; same as jmp with .offs = 0 */
844 goto setup;
845
846 case 0xe8: /* call relative */
847 branch_clear_offset(auprobe, insn);
848 break;
849
850 case 0x0f:
851 if (insn->opcode.nbytes != 2)
852 return -ENOSYS;
853 /*
854 * If it is a "near" conditional jmp, OPCODE2() - 0x10 matches
855 * OPCODE1() of the "short" jmp which checks the same condition.
856 */
857 opc1 = OPCODE2(insn) - 0x10;
858 fallthrough;
859 default:
860 if (!is_cond_jmp_opcode(opc1))
861 return -ENOSYS;
862 }
863
864 /*
865 * 16-bit overrides such as CALLW (66 e8 nn nn) are not supported.
866 * Intel and AMD behavior differ in 64-bit mode: Intel ignores 66 prefix.
867 * No one uses these insns, reject any branch insns with such prefix.
868 */
869 for_each_insn_prefix(insn, i, p) {
870 if (p == 0x66)
871 return -ENOTSUPP;
872 }
873
874setup:
875 auprobe->branch.opc1 = opc1;
876 auprobe->branch.ilen = insn->length;
877 auprobe->branch.offs = insn->immediate.value;
878
879 auprobe->ops = &branch_xol_ops;
880 return 0;
881}
882
883/* Returns -ENOSYS if push_xol_ops doesn't handle this insn */
884static int push_setup_xol_ops(struct arch_uprobe *auprobe, struct insn *insn)
885{
886 u8 opc1 = OPCODE1(insn), reg_offset = 0;
887
888 if (opc1 < 0x50 || opc1 > 0x57)
889 return -ENOSYS;
890
891 if (insn->length > 2)
892 return -ENOSYS;
893 if (insn->length == 2) {
894 /* only support rex_prefix 0x41 (x64 only) */
895#ifdef CONFIG_X86_64
896 if (insn->rex_prefix.nbytes != 1 ||
897 insn->rex_prefix.bytes[0] != 0x41)
898 return -ENOSYS;
899
900 switch (opc1) {
901 case 0x50:
902 reg_offset = offsetof(struct pt_regs, r8);
903 break;
904 case 0x51:
905 reg_offset = offsetof(struct pt_regs, r9);
906 break;
907 case 0x52:
908 reg_offset = offsetof(struct pt_regs, r10);
909 break;
910 case 0x53:
911 reg_offset = offsetof(struct pt_regs, r11);
912 break;
913 case 0x54:
914 reg_offset = offsetof(struct pt_regs, r12);
915 break;
916 case 0x55:
917 reg_offset = offsetof(struct pt_regs, r13);
918 break;
919 case 0x56:
920 reg_offset = offsetof(struct pt_regs, r14);
921 break;
922 case 0x57:
923 reg_offset = offsetof(struct pt_regs, r15);
924 break;
925 }
926#else
927 return -ENOSYS;
928#endif
929 } else {
930 switch (opc1) {
931 case 0x50:
932 reg_offset = offsetof(struct pt_regs, ax);
933 break;
934 case 0x51:
935 reg_offset = offsetof(struct pt_regs, cx);
936 break;
937 case 0x52:
938 reg_offset = offsetof(struct pt_regs, dx);
939 break;
940 case 0x53:
941 reg_offset = offsetof(struct pt_regs, bx);
942 break;
943 case 0x54:
944 reg_offset = offsetof(struct pt_regs, sp);
945 break;
946 case 0x55:
947 reg_offset = offsetof(struct pt_regs, bp);
948 break;
949 case 0x56:
950 reg_offset = offsetof(struct pt_regs, si);
951 break;
952 case 0x57:
953 reg_offset = offsetof(struct pt_regs, di);
954 break;
955 }
956 }
957
958 auprobe->push.reg_offset = reg_offset;
959 auprobe->push.ilen = insn->length;
960 auprobe->ops = &push_xol_ops;
961 return 0;
962}
963
964/**
965 * arch_uprobe_analyze_insn - instruction analysis including validity and fixups.
966 * @auprobe: the probepoint information.
967 * @mm: the probed address space.
968 * @addr: virtual address at which to install the probepoint
969 * Return 0 on success or a -ve number on error.
970 */
971int arch_uprobe_analyze_insn(struct arch_uprobe *auprobe, struct mm_struct *mm, unsigned long addr)
972{
973 struct insn insn;
974 u8 fix_ip_or_call = UPROBE_FIX_IP;
975 int ret;
976
977 ret = uprobe_init_insn(auprobe, &insn, is_64bit_mm(mm));
978 if (ret)
979 return ret;
980
981 ret = branch_setup_xol_ops(auprobe, &insn);
982 if (ret != -ENOSYS)
983 return ret;
984
985 ret = push_setup_xol_ops(auprobe, &insn);
986 if (ret != -ENOSYS)
987 return ret;
988
989 /*
990 * Figure out which fixups default_post_xol_op() will need to perform,
991 * and annotate defparam->fixups accordingly.
992 */
993 switch (OPCODE1(&insn)) {
994 case 0x9d: /* popf */
995 auprobe->defparam.fixups |= UPROBE_FIX_SETF;
996 break;
997 case 0xc3: /* ret or lret -- ip is correct */
998 case 0xcb:
999 case 0xc2:
1000 case 0xca:
1001 case 0xea: /* jmp absolute -- ip is correct */
1002 fix_ip_or_call = 0;
1003 break;
1004 case 0x9a: /* call absolute - Fix return addr, not ip */
1005 fix_ip_or_call = UPROBE_FIX_CALL;
1006 break;
1007 case 0xff:
1008 switch (MODRM_REG(&insn)) {
1009 case 2: case 3: /* call or lcall, indirect */
1010 fix_ip_or_call = UPROBE_FIX_CALL;
1011 break;
1012 case 4: case 5: /* jmp or ljmp, indirect */
1013 fix_ip_or_call = 0;
1014 break;
1015 }
1016 fallthrough;
1017 default:
1018 riprel_analyze(auprobe, &insn);
1019 }
1020
1021 auprobe->defparam.ilen = insn.length;
1022 auprobe->defparam.fixups |= fix_ip_or_call;
1023
1024 auprobe->ops = &default_xol_ops;
1025 return 0;
1026}
1027
1028/*
1029 * arch_uprobe_pre_xol - prepare to execute out of line.
1030 * @auprobe: the probepoint information.
1031 * @regs: reflects the saved user state of current task.
1032 */
1033int arch_uprobe_pre_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
1034{
1035 struct uprobe_task *utask = current->utask;
1036
1037 if (auprobe->ops->pre_xol) {
1038 int err = auprobe->ops->pre_xol(auprobe, regs);
1039 if (err)
1040 return err;
1041 }
1042
1043 regs->ip = utask->xol_vaddr;
1044 utask->autask.saved_trap_nr = current->thread.trap_nr;
1045 current->thread.trap_nr = UPROBE_TRAP_NR;
1046
1047 utask->autask.saved_tf = !!(regs->flags & X86_EFLAGS_TF);
1048 regs->flags |= X86_EFLAGS_TF;
1049 if (test_tsk_thread_flag(current, TIF_BLOCKSTEP))
1050 set_task_blockstep(current, false);
1051
1052 return 0;
1053}
1054
1055/*
1056 * If xol insn itself traps and generates a signal(Say,
1057 * SIGILL/SIGSEGV/etc), then detect the case where a singlestepped
1058 * instruction jumps back to its own address. It is assumed that anything
1059 * like do_page_fault/do_trap/etc sets thread.trap_nr != -1.
1060 *
1061 * arch_uprobe_pre_xol/arch_uprobe_post_xol save/restore thread.trap_nr,
1062 * arch_uprobe_xol_was_trapped() simply checks that ->trap_nr is not equal to
1063 * UPROBE_TRAP_NR == -1 set by arch_uprobe_pre_xol().
1064 */
1065bool arch_uprobe_xol_was_trapped(struct task_struct *t)
1066{
1067 if (t->thread.trap_nr != UPROBE_TRAP_NR)
1068 return true;
1069
1070 return false;
1071}
1072
1073/*
1074 * Called after single-stepping. To avoid the SMP problems that can
1075 * occur when we temporarily put back the original opcode to
1076 * single-step, we single-stepped a copy of the instruction.
1077 *
1078 * This function prepares to resume execution after the single-step.
1079 */
1080int arch_uprobe_post_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
1081{
1082 struct uprobe_task *utask = current->utask;
1083 bool send_sigtrap = utask->autask.saved_tf;
1084 int err = 0;
1085
1086 WARN_ON_ONCE(current->thread.trap_nr != UPROBE_TRAP_NR);
1087 current->thread.trap_nr = utask->autask.saved_trap_nr;
1088
1089 if (auprobe->ops->post_xol) {
1090 err = auprobe->ops->post_xol(auprobe, regs);
1091 if (err) {
1092 /*
1093 * Restore ->ip for restart or post mortem analysis.
1094 * ->post_xol() must not return -ERESTART unless this
1095 * is really possible.
1096 */
1097 regs->ip = utask->vaddr;
1098 if (err == -ERESTART)
1099 err = 0;
1100 send_sigtrap = false;
1101 }
1102 }
1103 /*
1104 * arch_uprobe_pre_xol() doesn't save the state of TIF_BLOCKSTEP
1105 * so we can get an extra SIGTRAP if we do not clear TF. We need
1106 * to examine the opcode to make it right.
1107 */
1108 if (send_sigtrap)
1109 send_sig(SIGTRAP, current, 0);
1110
1111 if (!utask->autask.saved_tf)
1112 regs->flags &= ~X86_EFLAGS_TF;
1113
1114 return err;
1115}
1116
1117/* callback routine for handling exceptions. */
1118int arch_uprobe_exception_notify(struct notifier_block *self, unsigned long val, void *data)
1119{
1120 struct die_args *args = data;
1121 struct pt_regs *regs = args->regs;
1122 int ret = NOTIFY_DONE;
1123
1124 /* We are only interested in userspace traps */
1125 if (regs && !user_mode(regs))
1126 return NOTIFY_DONE;
1127
1128 switch (val) {
1129 case DIE_INT3:
1130 if (uprobe_pre_sstep_notifier(regs))
1131 ret = NOTIFY_STOP;
1132
1133 break;
1134
1135 case DIE_DEBUG:
1136 if (uprobe_post_sstep_notifier(regs))
1137 ret = NOTIFY_STOP;
1138
1139 break;
1140
1141 default:
1142 break;
1143 }
1144
1145 return ret;
1146}
1147
1148/*
1149 * This function gets called when XOL instruction either gets trapped or
1150 * the thread has a fatal signal. Reset the instruction pointer to its
1151 * probed address for the potential restart or for post mortem analysis.
1152 */
1153void arch_uprobe_abort_xol(struct arch_uprobe *auprobe, struct pt_regs *regs)
1154{
1155 struct uprobe_task *utask = current->utask;
1156
1157 if (auprobe->ops->abort)
1158 auprobe->ops->abort(auprobe, regs);
1159
1160 current->thread.trap_nr = utask->autask.saved_trap_nr;
1161 regs->ip = utask->vaddr;
1162 /* clear TF if it was set by us in arch_uprobe_pre_xol() */
1163 if (!utask->autask.saved_tf)
1164 regs->flags &= ~X86_EFLAGS_TF;
1165}
1166
1167static bool __skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
1168{
1169 if (auprobe->ops->emulate)
1170 return auprobe->ops->emulate(auprobe, regs);
1171 return false;
1172}
1173
1174bool arch_uprobe_skip_sstep(struct arch_uprobe *auprobe, struct pt_regs *regs)
1175{
1176 bool ret = __skip_sstep(auprobe, regs);
1177 if (ret && (regs->flags & X86_EFLAGS_TF))
1178 send_sig(SIGTRAP, current, 0);
1179 return ret;
1180}
1181
1182unsigned long
1183arch_uretprobe_hijack_return_addr(unsigned long trampoline_vaddr, struct pt_regs *regs)
1184{
1185 int rasize = sizeof_long(regs), nleft;
1186 unsigned long orig_ret_vaddr = 0; /* clear high bits for 32-bit apps */
1187
1188 if (copy_from_user(&orig_ret_vaddr, (void __user *)regs->sp, rasize))
1189 return -1;
1190
1191 /* check whether address has been already hijacked */
1192 if (orig_ret_vaddr == trampoline_vaddr)
1193 return orig_ret_vaddr;
1194
1195 nleft = copy_to_user((void __user *)regs->sp, &trampoline_vaddr, rasize);
1196 if (likely(!nleft)) {
1197 if (shstk_update_last_frame(trampoline_vaddr)) {
1198 force_sig(SIGSEGV);
1199 return -1;
1200 }
1201 return orig_ret_vaddr;
1202 }
1203
1204 if (nleft != rasize) {
1205 pr_err("return address clobbered: pid=%d, %%sp=%#lx, %%ip=%#lx\n",
1206 current->pid, regs->sp, regs->ip);
1207
1208 force_sig(SIGSEGV);
1209 }
1210
1211 return -1;
1212}
1213
1214bool arch_uretprobe_is_alive(struct return_instance *ret, enum rp_check ctx,
1215 struct pt_regs *regs)
1216{
1217 if (ctx == RP_CHECK_CALL) /* sp was just decremented by "call" insn */
1218 return regs->sp < ret->stack;
1219 else
1220 return regs->sp <= ret->stack;
1221}