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1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DRIVERS_PCI_H
3#define DRIVERS_PCI_H
4
5#define PCI_FIND_CAP_TTL 48
6
7#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
8
9extern const unsigned char pcie_link_speed[];
10
11bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
12
13/* Functions internal to the PCI core code */
14
15int pci_create_sysfs_dev_files(struct pci_dev *pdev);
16void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
17#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
18static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
19{ return; }
20static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
21{ return; }
22#else
23void pci_create_firmware_label_files(struct pci_dev *pdev);
24void pci_remove_firmware_label_files(struct pci_dev *pdev);
25#endif
26void pci_cleanup_rom(struct pci_dev *dev);
27
28enum pci_mmap_api {
29 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
30 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
31};
32int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
33 enum pci_mmap_api mmap_api);
34
35int pci_probe_reset_function(struct pci_dev *dev);
36
37/**
38 * struct pci_platform_pm_ops - Firmware PM callbacks
39 *
40 * @is_manageable: returns 'true' if given device is power manageable by the
41 * platform firmware
42 *
43 * @set_state: invokes the platform firmware to set the device's power state
44 *
45 * @get_state: queries the platform firmware for a device's current power state
46 *
47 * @choose_state: returns PCI power state of given device preferred by the
48 * platform; to be used during system-wide transitions from a
49 * sleeping state to the working state and vice versa
50 *
51 * @set_wakeup: enables/disables wakeup capability for the device
52 *
53 * @need_resume: returns 'true' if the given device (which is currently
54 * suspended) needs to be resumed to be configured for system
55 * wakeup.
56 *
57 * If given platform is generally capable of power managing PCI devices, all of
58 * these callbacks are mandatory.
59 */
60struct pci_platform_pm_ops {
61 bool (*is_manageable)(struct pci_dev *dev);
62 int (*set_state)(struct pci_dev *dev, pci_power_t state);
63 pci_power_t (*get_state)(struct pci_dev *dev);
64 pci_power_t (*choose_state)(struct pci_dev *dev);
65 int (*set_wakeup)(struct pci_dev *dev, bool enable);
66 bool (*need_resume)(struct pci_dev *dev);
67};
68
69int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
70void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
71void pci_power_up(struct pci_dev *dev);
72void pci_disable_enabled_device(struct pci_dev *dev);
73int pci_finish_runtime_suspend(struct pci_dev *dev);
74void pcie_clear_root_pme_status(struct pci_dev *dev);
75int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
76void pci_pme_restore(struct pci_dev *dev);
77bool pci_dev_keep_suspended(struct pci_dev *dev);
78void pci_dev_complete_resume(struct pci_dev *pci_dev);
79void pci_config_pm_runtime_get(struct pci_dev *dev);
80void pci_config_pm_runtime_put(struct pci_dev *dev);
81void pci_pm_init(struct pci_dev *dev);
82void pci_ea_init(struct pci_dev *dev);
83void pci_allocate_cap_save_buffers(struct pci_dev *dev);
84void pci_free_cap_save_buffers(struct pci_dev *dev);
85bool pci_bridge_d3_possible(struct pci_dev *dev);
86void pci_bridge_d3_update(struct pci_dev *dev);
87
88static inline void pci_wakeup_event(struct pci_dev *dev)
89{
90 /* Wait 100 ms before the system can be put into a sleep state. */
91 pm_wakeup_event(&dev->dev, 100);
92}
93
94static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
95{
96 return !!(pci_dev->subordinate);
97}
98
99static inline bool pci_power_manageable(struct pci_dev *pci_dev)
100{
101 /*
102 * Currently we allow normal PCI devices and PCI bridges transition
103 * into D3 if their bridge_d3 is set.
104 */
105 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
106}
107
108int pci_vpd_init(struct pci_dev *dev);
109void pci_vpd_release(struct pci_dev *dev);
110void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
111void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
112
113/* PCI /proc functions */
114#ifdef CONFIG_PROC_FS
115int pci_proc_attach_device(struct pci_dev *dev);
116int pci_proc_detach_device(struct pci_dev *dev);
117int pci_proc_detach_bus(struct pci_bus *bus);
118#else
119static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
120static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
121static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
122#endif
123
124/* Functions for PCI Hotplug drivers to use */
125int pci_hp_add_bridge(struct pci_dev *dev);
126
127#ifdef HAVE_PCI_LEGACY
128void pci_create_legacy_files(struct pci_bus *bus);
129void pci_remove_legacy_files(struct pci_bus *bus);
130#else
131static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
132static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
133#endif
134
135/* Lock for read/write access to pci device and bus lists */
136extern struct rw_semaphore pci_bus_sem;
137
138extern raw_spinlock_t pci_lock;
139
140extern unsigned int pci_pm_d3_delay;
141
142#ifdef CONFIG_PCI_MSI
143void pci_no_msi(void);
144#else
145static inline void pci_no_msi(void) { }
146#endif
147
148static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
149{
150 u16 control;
151
152 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
153 control &= ~PCI_MSI_FLAGS_ENABLE;
154 if (enable)
155 control |= PCI_MSI_FLAGS_ENABLE;
156 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
157}
158
159static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
160{
161 u16 ctrl;
162
163 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
164 ctrl &= ~clear;
165 ctrl |= set;
166 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
167}
168
169void pci_realloc_get_opt(char *);
170
171static inline int pci_no_d1d2(struct pci_dev *dev)
172{
173 unsigned int parent_dstates = 0;
174
175 if (dev->bus->self)
176 parent_dstates = dev->bus->self->no_d1d2;
177 return (dev->no_d1d2 || parent_dstates);
178
179}
180extern const struct attribute_group *pci_dev_groups[];
181extern const struct attribute_group *pcibus_groups[];
182extern const struct device_type pci_dev_type;
183extern const struct attribute_group *pci_bus_groups[];
184
185
186/**
187 * pci_match_one_device - Tell if a PCI device structure has a matching
188 * PCI device id structure
189 * @id: single PCI device id structure to match
190 * @dev: the PCI device structure to match against
191 *
192 * Returns the matching pci_device_id structure or %NULL if there is no match.
193 */
194static inline const struct pci_device_id *
195pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
196{
197 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
198 (id->device == PCI_ANY_ID || id->device == dev->device) &&
199 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
200 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
201 !((id->class ^ dev->class) & id->class_mask))
202 return id;
203 return NULL;
204}
205
206/* PCI slot sysfs helper code */
207#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
208
209extern struct kset *pci_slots_kset;
210
211struct pci_slot_attribute {
212 struct attribute attr;
213 ssize_t (*show)(struct pci_slot *, char *);
214 ssize_t (*store)(struct pci_slot *, const char *, size_t);
215};
216#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
217
218enum pci_bar_type {
219 pci_bar_unknown, /* Standard PCI BAR probe */
220 pci_bar_io, /* An I/O port BAR */
221 pci_bar_mem32, /* A 32-bit memory BAR */
222 pci_bar_mem64, /* A 64-bit memory BAR */
223};
224
225int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
226bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
227 int crs_timeout);
228int pci_setup_device(struct pci_dev *dev);
229int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
230 struct resource *res, unsigned int reg);
231void pci_configure_ari(struct pci_dev *dev);
232void __pci_bus_size_bridges(struct pci_bus *bus,
233 struct list_head *realloc_head);
234void __pci_bus_assign_resources(const struct pci_bus *bus,
235 struct list_head *realloc_head,
236 struct list_head *fail_head);
237bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
238
239void pci_reassigndev_resource_alignment(struct pci_dev *dev);
240void pci_disable_bridge_window(struct pci_dev *dev);
241
242/* PCIe link information */
243#define PCIE_SPEED2STR(speed) \
244 ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
245 (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
246 (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
247 (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
248 "Unknown speed")
249
250/* PCIe speed to Mb/s reduced by encoding overhead */
251#define PCIE_SPEED2MBS_ENC(speed) \
252 ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
253 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
254 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
255 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
256 0)
257
258enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
259enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
260u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
261 enum pcie_link_width *width);
262
263/* Single Root I/O Virtualization */
264struct pci_sriov {
265 int pos; /* Capability position */
266 int nres; /* Number of resources */
267 u32 cap; /* SR-IOV Capabilities */
268 u16 ctrl; /* SR-IOV Control */
269 u16 total_VFs; /* Total VFs associated with the PF */
270 u16 initial_VFs; /* Initial VFs associated with the PF */
271 u16 num_VFs; /* Number of VFs available */
272 u16 offset; /* First VF Routing ID offset */
273 u16 stride; /* Following VF stride */
274 u16 vf_device; /* VF device ID */
275 u32 pgsz; /* Page size for BAR alignment */
276 u8 link; /* Function Dependency Link */
277 u8 max_VF_buses; /* Max buses consumed by VFs */
278 u16 driver_max_VFs; /* Max num VFs driver supports */
279 struct pci_dev *dev; /* Lowest numbered PF */
280 struct pci_dev *self; /* This PF */
281 u32 class; /* VF device */
282 u8 hdr_type; /* VF header type */
283 u16 subsystem_vendor; /* VF subsystem vendor */
284 u16 subsystem_device; /* VF subsystem device */
285 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
286 bool drivers_autoprobe; /* Auto probing of VFs by driver */
287};
288
289/* pci_dev priv_flags */
290#define PCI_DEV_DISCONNECTED 0
291
292static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
293{
294 set_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
295 return 0;
296}
297
298static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
299{
300 return test_bit(PCI_DEV_DISCONNECTED, &dev->priv_flags);
301}
302
303#ifdef CONFIG_PCI_ATS
304void pci_restore_ats_state(struct pci_dev *dev);
305#else
306static inline void pci_restore_ats_state(struct pci_dev *dev)
307{
308}
309#endif /* CONFIG_PCI_ATS */
310
311#ifdef CONFIG_PCI_IOV
312int pci_iov_init(struct pci_dev *dev);
313void pci_iov_release(struct pci_dev *dev);
314void pci_iov_update_resource(struct pci_dev *dev, int resno);
315resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
316void pci_restore_iov_state(struct pci_dev *dev);
317int pci_iov_bus_range(struct pci_bus *bus);
318
319#else
320static inline int pci_iov_init(struct pci_dev *dev)
321{
322 return -ENODEV;
323}
324static inline void pci_iov_release(struct pci_dev *dev)
325
326{
327}
328static inline void pci_restore_iov_state(struct pci_dev *dev)
329{
330}
331static inline int pci_iov_bus_range(struct pci_bus *bus)
332{
333 return 0;
334}
335
336#endif /* CONFIG_PCI_IOV */
337
338unsigned long pci_cardbus_resource_alignment(struct resource *);
339
340static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
341 struct resource *res)
342{
343#ifdef CONFIG_PCI_IOV
344 int resno = res - dev->resource;
345
346 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
347 return pci_sriov_resource_alignment(dev, resno);
348#endif
349 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
350 return pci_cardbus_resource_alignment(res);
351 return resource_alignment(res);
352}
353
354void pci_enable_acs(struct pci_dev *dev);
355
356#ifdef CONFIG_PCIEASPM
357void pcie_aspm_init_link_state(struct pci_dev *pdev);
358void pcie_aspm_exit_link_state(struct pci_dev *pdev);
359void pcie_aspm_pm_state_change(struct pci_dev *pdev);
360void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
361#else
362static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
363static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
364static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
365static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
366#endif
367
368#ifdef CONFIG_PCIEASPM_DEBUG
369void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
370void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
371#else
372static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
373static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
374#endif
375
376#ifdef CONFIG_PCIE_PTM
377void pci_ptm_init(struct pci_dev *dev);
378#else
379static inline void pci_ptm_init(struct pci_dev *dev) { }
380#endif
381
382struct pci_dev_reset_methods {
383 u16 vendor;
384 u16 device;
385 int (*reset)(struct pci_dev *dev, int probe);
386};
387
388#ifdef CONFIG_PCI_QUIRKS
389int pci_dev_specific_reset(struct pci_dev *dev, int probe);
390#else
391static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
392{
393 return -ENOTTY;
394}
395#endif
396
397#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
398int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
399 struct resource *res);
400#endif
401
402u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
403int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
404int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
405static inline u64 pci_rebar_size_to_bytes(int size)
406{
407 return 1ULL << (size + 20);
408}
409
410#endif /* DRIVERS_PCI_H */
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef DRIVERS_PCI_H
3#define DRIVERS_PCI_H
4
5#include <linux/pci.h>
6
7/* Number of possible devfns: 0.0 to 1f.7 inclusive */
8#define MAX_NR_DEVFNS 256
9
10#define PCI_FIND_CAP_TTL 48
11
12#define PCI_VSEC_ID_INTEL_TBT 0x1234 /* Thunderbolt */
13
14extern const unsigned char pcie_link_speed[];
15extern bool pci_early_dump;
16
17bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
18bool pcie_cap_has_rtctl(const struct pci_dev *dev);
19
20/* Functions internal to the PCI core code */
21
22int pci_create_sysfs_dev_files(struct pci_dev *pdev);
23void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
24#if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
25static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
26{ return; }
27static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
28{ return; }
29#else
30void pci_create_firmware_label_files(struct pci_dev *pdev);
31void pci_remove_firmware_label_files(struct pci_dev *pdev);
32#endif
33void pci_cleanup_rom(struct pci_dev *dev);
34
35enum pci_mmap_api {
36 PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
37 PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
38};
39int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
40 enum pci_mmap_api mmap_api);
41
42int pci_probe_reset_function(struct pci_dev *dev);
43int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
44int pci_bus_error_reset(struct pci_dev *dev);
45
46#define PCI_PM_D2_DELAY 200
47#define PCI_PM_D3_WAIT 10
48#define PCI_PM_D3COLD_WAIT 100
49#define PCI_PM_BUS_WAIT 50
50
51/**
52 * struct pci_platform_pm_ops - Firmware PM callbacks
53 *
54 * @bridge_d3: Does the bridge allow entering into D3
55 *
56 * @is_manageable: returns 'true' if given device is power manageable by the
57 * platform firmware
58 *
59 * @set_state: invokes the platform firmware to set the device's power state
60 *
61 * @get_state: queries the platform firmware for a device's current power state
62 *
63 * @refresh_state: asks the platform to refresh the device's power state data
64 *
65 * @choose_state: returns PCI power state of given device preferred by the
66 * platform; to be used during system-wide transitions from a
67 * sleeping state to the working state and vice versa
68 *
69 * @set_wakeup: enables/disables wakeup capability for the device
70 *
71 * @need_resume: returns 'true' if the given device (which is currently
72 * suspended) needs to be resumed to be configured for system
73 * wakeup.
74 *
75 * If given platform is generally capable of power managing PCI devices, all of
76 * these callbacks are mandatory.
77 */
78struct pci_platform_pm_ops {
79 bool (*bridge_d3)(struct pci_dev *dev);
80 bool (*is_manageable)(struct pci_dev *dev);
81 int (*set_state)(struct pci_dev *dev, pci_power_t state);
82 pci_power_t (*get_state)(struct pci_dev *dev);
83 void (*refresh_state)(struct pci_dev *dev);
84 pci_power_t (*choose_state)(struct pci_dev *dev);
85 int (*set_wakeup)(struct pci_dev *dev, bool enable);
86 bool (*need_resume)(struct pci_dev *dev);
87};
88
89int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
90void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
91void pci_refresh_power_state(struct pci_dev *dev);
92int pci_power_up(struct pci_dev *dev);
93void pci_disable_enabled_device(struct pci_dev *dev);
94int pci_finish_runtime_suspend(struct pci_dev *dev);
95void pcie_clear_device_status(struct pci_dev *dev);
96void pcie_clear_root_pme_status(struct pci_dev *dev);
97bool pci_check_pme_status(struct pci_dev *dev);
98void pci_pme_wakeup_bus(struct pci_bus *bus);
99int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
100void pci_pme_restore(struct pci_dev *dev);
101bool pci_dev_need_resume(struct pci_dev *dev);
102void pci_dev_adjust_pme(struct pci_dev *dev);
103void pci_dev_complete_resume(struct pci_dev *pci_dev);
104void pci_config_pm_runtime_get(struct pci_dev *dev);
105void pci_config_pm_runtime_put(struct pci_dev *dev);
106void pci_pm_init(struct pci_dev *dev);
107void pci_ea_init(struct pci_dev *dev);
108void pci_allocate_cap_save_buffers(struct pci_dev *dev);
109void pci_free_cap_save_buffers(struct pci_dev *dev);
110bool pci_bridge_d3_possible(struct pci_dev *dev);
111void pci_bridge_d3_update(struct pci_dev *dev);
112void pci_bridge_wait_for_secondary_bus(struct pci_dev *dev);
113
114static inline void pci_wakeup_event(struct pci_dev *dev)
115{
116 /* Wait 100 ms before the system can be put into a sleep state. */
117 pm_wakeup_event(&dev->dev, 100);
118}
119
120static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
121{
122 return !!(pci_dev->subordinate);
123}
124
125static inline bool pci_power_manageable(struct pci_dev *pci_dev)
126{
127 /*
128 * Currently we allow normal PCI devices and PCI bridges transition
129 * into D3 if their bridge_d3 is set.
130 */
131 return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
132}
133
134static inline bool pcie_downstream_port(const struct pci_dev *dev)
135{
136 int type = pci_pcie_type(dev);
137
138 return type == PCI_EXP_TYPE_ROOT_PORT ||
139 type == PCI_EXP_TYPE_DOWNSTREAM ||
140 type == PCI_EXP_TYPE_PCIE_BRIDGE;
141}
142
143int pci_vpd_init(struct pci_dev *dev);
144void pci_vpd_release(struct pci_dev *dev);
145void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
146void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
147
148/* PCI Virtual Channel */
149int pci_save_vc_state(struct pci_dev *dev);
150void pci_restore_vc_state(struct pci_dev *dev);
151void pci_allocate_vc_save_buffers(struct pci_dev *dev);
152
153/* PCI /proc functions */
154#ifdef CONFIG_PROC_FS
155int pci_proc_attach_device(struct pci_dev *dev);
156int pci_proc_detach_device(struct pci_dev *dev);
157int pci_proc_detach_bus(struct pci_bus *bus);
158#else
159static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
160static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
161static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
162#endif
163
164/* Functions for PCI Hotplug drivers to use */
165int pci_hp_add_bridge(struct pci_dev *dev);
166
167#ifdef HAVE_PCI_LEGACY
168void pci_create_legacy_files(struct pci_bus *bus);
169void pci_remove_legacy_files(struct pci_bus *bus);
170#else
171static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
172static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
173#endif
174
175/* Lock for read/write access to pci device and bus lists */
176extern struct rw_semaphore pci_bus_sem;
177extern struct mutex pci_slot_mutex;
178
179extern raw_spinlock_t pci_lock;
180
181extern unsigned int pci_pm_d3_delay;
182
183#ifdef CONFIG_PCI_MSI
184void pci_no_msi(void);
185#else
186static inline void pci_no_msi(void) { }
187#endif
188
189static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
190{
191 u16 control;
192
193 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
194 control &= ~PCI_MSI_FLAGS_ENABLE;
195 if (enable)
196 control |= PCI_MSI_FLAGS_ENABLE;
197 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
198}
199
200static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
201{
202 u16 ctrl;
203
204 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
205 ctrl &= ~clear;
206 ctrl |= set;
207 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
208}
209
210void pci_realloc_get_opt(char *);
211
212static inline int pci_no_d1d2(struct pci_dev *dev)
213{
214 unsigned int parent_dstates = 0;
215
216 if (dev->bus->self)
217 parent_dstates = dev->bus->self->no_d1d2;
218 return (dev->no_d1d2 || parent_dstates);
219
220}
221extern const struct attribute_group *pci_dev_groups[];
222extern const struct attribute_group *pcibus_groups[];
223extern const struct device_type pci_dev_type;
224extern const struct attribute_group *pci_bus_groups[];
225
226extern unsigned long pci_hotplug_io_size;
227extern unsigned long pci_hotplug_mmio_size;
228extern unsigned long pci_hotplug_mmio_pref_size;
229extern unsigned long pci_hotplug_bus_size;
230
231/**
232 * pci_match_one_device - Tell if a PCI device structure has a matching
233 * PCI device id structure
234 * @id: single PCI device id structure to match
235 * @dev: the PCI device structure to match against
236 *
237 * Returns the matching pci_device_id structure or %NULL if there is no match.
238 */
239static inline const struct pci_device_id *
240pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
241{
242 if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
243 (id->device == PCI_ANY_ID || id->device == dev->device) &&
244 (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
245 (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
246 !((id->class ^ dev->class) & id->class_mask))
247 return id;
248 return NULL;
249}
250
251/* PCI slot sysfs helper code */
252#define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
253
254extern struct kset *pci_slots_kset;
255
256struct pci_slot_attribute {
257 struct attribute attr;
258 ssize_t (*show)(struct pci_slot *, char *);
259 ssize_t (*store)(struct pci_slot *, const char *, size_t);
260};
261#define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
262
263enum pci_bar_type {
264 pci_bar_unknown, /* Standard PCI BAR probe */
265 pci_bar_io, /* An I/O port BAR */
266 pci_bar_mem32, /* A 32-bit memory BAR */
267 pci_bar_mem64, /* A 64-bit memory BAR */
268};
269
270struct device *pci_get_host_bridge_device(struct pci_dev *dev);
271void pci_put_host_bridge_device(struct device *dev);
272
273int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
274bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
275 int crs_timeout);
276bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
277 int crs_timeout);
278int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
279
280int pci_setup_device(struct pci_dev *dev);
281int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
282 struct resource *res, unsigned int reg);
283void pci_configure_ari(struct pci_dev *dev);
284void __pci_bus_size_bridges(struct pci_bus *bus,
285 struct list_head *realloc_head);
286void __pci_bus_assign_resources(const struct pci_bus *bus,
287 struct list_head *realloc_head,
288 struct list_head *fail_head);
289bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
290
291void pci_reassigndev_resource_alignment(struct pci_dev *dev);
292void pci_disable_bridge_window(struct pci_dev *dev);
293struct pci_bus *pci_bus_get(struct pci_bus *bus);
294void pci_bus_put(struct pci_bus *bus);
295
296/* PCIe link information from Link Capabilities 2 */
297#define PCIE_LNKCAP2_SLS2SPEED(lnkcap2) \
298 ((lnkcap2) & PCI_EXP_LNKCAP2_SLS_32_0GB ? PCIE_SPEED_32_0GT : \
299 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_16_0GB ? PCIE_SPEED_16_0GT : \
300 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_8_0GB ? PCIE_SPEED_8_0GT : \
301 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_5_0GB ? PCIE_SPEED_5_0GT : \
302 (lnkcap2) & PCI_EXP_LNKCAP2_SLS_2_5GB ? PCIE_SPEED_2_5GT : \
303 PCI_SPEED_UNKNOWN)
304
305/* PCIe speed to Mb/s reduced by encoding overhead */
306#define PCIE_SPEED2MBS_ENC(speed) \
307 ((speed) == PCIE_SPEED_32_0GT ? 32000*128/130 : \
308 (speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
309 (speed) == PCIE_SPEED_8_0GT ? 8000*128/130 : \
310 (speed) == PCIE_SPEED_5_0GT ? 5000*8/10 : \
311 (speed) == PCIE_SPEED_2_5GT ? 2500*8/10 : \
312 0)
313
314const char *pci_speed_string(enum pci_bus_speed speed);
315enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
316enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
317u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
318 enum pcie_link_width *width);
319void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
320void pcie_report_downtraining(struct pci_dev *dev);
321void pcie_update_link_speed(struct pci_bus *bus, u16 link_status);
322
323/* Single Root I/O Virtualization */
324struct pci_sriov {
325 int pos; /* Capability position */
326 int nres; /* Number of resources */
327 u32 cap; /* SR-IOV Capabilities */
328 u16 ctrl; /* SR-IOV Control */
329 u16 total_VFs; /* Total VFs associated with the PF */
330 u16 initial_VFs; /* Initial VFs associated with the PF */
331 u16 num_VFs; /* Number of VFs available */
332 u16 offset; /* First VF Routing ID offset */
333 u16 stride; /* Following VF stride */
334 u16 vf_device; /* VF device ID */
335 u32 pgsz; /* Page size for BAR alignment */
336 u8 link; /* Function Dependency Link */
337 u8 max_VF_buses; /* Max buses consumed by VFs */
338 u16 driver_max_VFs; /* Max num VFs driver supports */
339 struct pci_dev *dev; /* Lowest numbered PF */
340 struct pci_dev *self; /* This PF */
341 u32 class; /* VF device */
342 u8 hdr_type; /* VF header type */
343 u16 subsystem_vendor; /* VF subsystem vendor */
344 u16 subsystem_device; /* VF subsystem device */
345 resource_size_t barsz[PCI_SRIOV_NUM_BARS]; /* VF BAR size */
346 bool drivers_autoprobe; /* Auto probing of VFs by driver */
347};
348
349/**
350 * pci_dev_set_io_state - Set the new error state if possible.
351 *
352 * @dev - pci device to set new error_state
353 * @new - the state we want dev to be in
354 *
355 * Must be called with device_lock held.
356 *
357 * Returns true if state has been changed to the requested state.
358 */
359static inline bool pci_dev_set_io_state(struct pci_dev *dev,
360 pci_channel_state_t new)
361{
362 bool changed = false;
363
364 device_lock_assert(&dev->dev);
365 switch (new) {
366 case pci_channel_io_perm_failure:
367 switch (dev->error_state) {
368 case pci_channel_io_frozen:
369 case pci_channel_io_normal:
370 case pci_channel_io_perm_failure:
371 changed = true;
372 break;
373 }
374 break;
375 case pci_channel_io_frozen:
376 switch (dev->error_state) {
377 case pci_channel_io_frozen:
378 case pci_channel_io_normal:
379 changed = true;
380 break;
381 }
382 break;
383 case pci_channel_io_normal:
384 switch (dev->error_state) {
385 case pci_channel_io_frozen:
386 case pci_channel_io_normal:
387 changed = true;
388 break;
389 }
390 break;
391 }
392 if (changed)
393 dev->error_state = new;
394 return changed;
395}
396
397static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
398{
399 device_lock(&dev->dev);
400 pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
401 device_unlock(&dev->dev);
402
403 return 0;
404}
405
406static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
407{
408 return dev->error_state == pci_channel_io_perm_failure;
409}
410
411/* pci_dev priv_flags */
412#define PCI_DEV_ADDED 0
413
414static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
415{
416 assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
417}
418
419static inline bool pci_dev_is_added(const struct pci_dev *dev)
420{
421 return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
422}
423
424#ifdef CONFIG_PCIEAER
425#include <linux/aer.h>
426
427#define AER_MAX_MULTI_ERR_DEVICES 5 /* Not likely to have more */
428
429struct aer_err_info {
430 struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
431 int error_dev_num;
432
433 unsigned int id:16;
434
435 unsigned int severity:2; /* 0:NONFATAL | 1:FATAL | 2:COR */
436 unsigned int __pad1:5;
437 unsigned int multi_error_valid:1;
438
439 unsigned int first_error:5;
440 unsigned int __pad2:2;
441 unsigned int tlp_header_valid:1;
442
443 unsigned int status; /* COR/UNCOR Error Status */
444 unsigned int mask; /* COR/UNCOR Error Mask */
445 struct aer_header_log_regs tlp; /* TLP Header */
446};
447
448int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
449void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
450#endif /* CONFIG_PCIEAER */
451
452#ifdef CONFIG_PCIE_DPC
453void pci_save_dpc_state(struct pci_dev *dev);
454void pci_restore_dpc_state(struct pci_dev *dev);
455void pci_dpc_init(struct pci_dev *pdev);
456void dpc_process_error(struct pci_dev *pdev);
457pci_ers_result_t dpc_reset_link(struct pci_dev *pdev);
458#else
459static inline void pci_save_dpc_state(struct pci_dev *dev) {}
460static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
461static inline void pci_dpc_init(struct pci_dev *pdev) {}
462#endif
463
464#ifdef CONFIG_PCI_ATS
465/* Address Translation Service */
466void pci_ats_init(struct pci_dev *dev);
467void pci_restore_ats_state(struct pci_dev *dev);
468#else
469static inline void pci_ats_init(struct pci_dev *d) { }
470static inline void pci_restore_ats_state(struct pci_dev *dev) { }
471#endif /* CONFIG_PCI_ATS */
472
473#ifdef CONFIG_PCI_PRI
474void pci_pri_init(struct pci_dev *dev);
475void pci_restore_pri_state(struct pci_dev *pdev);
476#else
477static inline void pci_pri_init(struct pci_dev *dev) { }
478static inline void pci_restore_pri_state(struct pci_dev *pdev) { }
479#endif
480
481#ifdef CONFIG_PCI_PASID
482void pci_pasid_init(struct pci_dev *dev);
483void pci_restore_pasid_state(struct pci_dev *pdev);
484#else
485static inline void pci_pasid_init(struct pci_dev *dev) { }
486static inline void pci_restore_pasid_state(struct pci_dev *pdev) { }
487#endif
488
489#ifdef CONFIG_PCI_IOV
490int pci_iov_init(struct pci_dev *dev);
491void pci_iov_release(struct pci_dev *dev);
492void pci_iov_remove(struct pci_dev *dev);
493void pci_iov_update_resource(struct pci_dev *dev, int resno);
494resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
495void pci_restore_iov_state(struct pci_dev *dev);
496int pci_iov_bus_range(struct pci_bus *bus);
497extern const struct attribute_group sriov_dev_attr_group;
498#else
499static inline int pci_iov_init(struct pci_dev *dev)
500{
501 return -ENODEV;
502}
503static inline void pci_iov_release(struct pci_dev *dev)
504
505{
506}
507static inline void pci_iov_remove(struct pci_dev *dev)
508{
509}
510static inline void pci_restore_iov_state(struct pci_dev *dev)
511{
512}
513static inline int pci_iov_bus_range(struct pci_bus *bus)
514{
515 return 0;
516}
517
518#endif /* CONFIG_PCI_IOV */
519
520unsigned long pci_cardbus_resource_alignment(struct resource *);
521
522static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
523 struct resource *res)
524{
525#ifdef CONFIG_PCI_IOV
526 int resno = res - dev->resource;
527
528 if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
529 return pci_sriov_resource_alignment(dev, resno);
530#endif
531 if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
532 return pci_cardbus_resource_alignment(res);
533 return resource_alignment(res);
534}
535
536void pci_acs_init(struct pci_dev *dev);
537#ifdef CONFIG_PCI_QUIRKS
538int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
539int pci_dev_specific_enable_acs(struct pci_dev *dev);
540int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
541#else
542static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
543 u16 acs_flags)
544{
545 return -ENOTTY;
546}
547static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
548{
549 return -ENOTTY;
550}
551static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
552{
553 return -ENOTTY;
554}
555#endif
556
557/* PCI error reporting and recovery */
558pci_ers_result_t pcie_do_recovery(struct pci_dev *dev,
559 pci_channel_state_t state,
560 pci_ers_result_t (*reset_link)(struct pci_dev *pdev));
561
562bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
563#ifdef CONFIG_PCIEASPM
564void pcie_aspm_init_link_state(struct pci_dev *pdev);
565void pcie_aspm_exit_link_state(struct pci_dev *pdev);
566void pcie_aspm_pm_state_change(struct pci_dev *pdev);
567void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
568#else
569static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
570static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
571static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
572static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
573#endif
574
575#ifdef CONFIG_PCIE_ECRC
576void pcie_set_ecrc_checking(struct pci_dev *dev);
577void pcie_ecrc_get_policy(char *str);
578#else
579static inline void pcie_set_ecrc_checking(struct pci_dev *dev) { }
580static inline void pcie_ecrc_get_policy(char *str) { }
581#endif
582
583#ifdef CONFIG_PCIE_PTM
584void pci_ptm_init(struct pci_dev *dev);
585int pci_enable_ptm(struct pci_dev *dev, u8 *granularity);
586#else
587static inline void pci_ptm_init(struct pci_dev *dev) { }
588static inline int pci_enable_ptm(struct pci_dev *dev, u8 *granularity)
589{ return -EINVAL; }
590#endif
591
592struct pci_dev_reset_methods {
593 u16 vendor;
594 u16 device;
595 int (*reset)(struct pci_dev *dev, int probe);
596};
597
598#ifdef CONFIG_PCI_QUIRKS
599int pci_dev_specific_reset(struct pci_dev *dev, int probe);
600#else
601static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
602{
603 return -ENOTTY;
604}
605#endif
606
607#if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
608int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
609 struct resource *res);
610#endif
611
612u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
613int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
614int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
615static inline u64 pci_rebar_size_to_bytes(int size)
616{
617 return 1ULL << (size + 20);
618}
619
620struct device_node;
621
622#ifdef CONFIG_OF
623int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
624int of_get_pci_domain_nr(struct device_node *node);
625int of_pci_get_max_link_speed(struct device_node *node);
626void pci_set_of_node(struct pci_dev *dev);
627void pci_release_of_node(struct pci_dev *dev);
628void pci_set_bus_of_node(struct pci_bus *bus);
629void pci_release_bus_of_node(struct pci_bus *bus);
630
631int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge);
632
633#else
634static inline int
635of_pci_parse_bus_range(struct device_node *node, struct resource *res)
636{
637 return -EINVAL;
638}
639
640static inline int
641of_get_pci_domain_nr(struct device_node *node)
642{
643 return -1;
644}
645
646static inline int
647of_pci_get_max_link_speed(struct device_node *node)
648{
649 return -EINVAL;
650}
651
652static inline void pci_set_of_node(struct pci_dev *dev) { }
653static inline void pci_release_of_node(struct pci_dev *dev) { }
654static inline void pci_set_bus_of_node(struct pci_bus *bus) { }
655static inline void pci_release_bus_of_node(struct pci_bus *bus) { }
656
657static inline int devm_of_pci_bridge_init(struct device *dev, struct pci_host_bridge *bridge)
658{
659 return 0;
660}
661
662#endif /* CONFIG_OF */
663
664#ifdef CONFIG_PCIEAER
665void pci_no_aer(void);
666void pci_aer_init(struct pci_dev *dev);
667void pci_aer_exit(struct pci_dev *dev);
668extern const struct attribute_group aer_stats_attr_group;
669void pci_aer_clear_fatal_status(struct pci_dev *dev);
670int pci_aer_clear_status(struct pci_dev *dev);
671int pci_aer_raw_clear_status(struct pci_dev *dev);
672#else
673static inline void pci_no_aer(void) { }
674static inline void pci_aer_init(struct pci_dev *d) { }
675static inline void pci_aer_exit(struct pci_dev *d) { }
676static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
677static inline int pci_aer_clear_status(struct pci_dev *dev) { return -EINVAL; }
678static inline int pci_aer_raw_clear_status(struct pci_dev *dev) { return -EINVAL; }
679#endif
680
681#ifdef CONFIG_ACPI
682int pci_acpi_program_hp_params(struct pci_dev *dev);
683#else
684static inline int pci_acpi_program_hp_params(struct pci_dev *dev)
685{
686 return -ENODEV;
687}
688#endif
689
690#ifdef CONFIG_PCIEASPM
691extern const struct attribute_group aspm_ctrl_attr_group;
692#endif
693
694#endif /* DRIVERS_PCI_H */