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1/*
2 * Qualcomm Atheros IPQ806x GMAC glue layer
3 *
4 * Copyright (C) 2015 The Linux Foundation
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/phy.h>
22#include <linux/regmap.h>
23#include <linux/clk.h>
24#include <linux/reset.h>
25#include <linux/of_net.h>
26#include <linux/mfd/syscon.h>
27#include <linux/stmmac.h>
28#include <linux/of_mdio.h>
29#include <linux/module.h>
30
31#include "stmmac_platform.h"
32
33#define NSS_COMMON_CLK_GATE 0x8
34#define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x)
35#define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2))
36#define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2))
37#define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x)
38#define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x)
39
40#define NSS_COMMON_CLK_DIV0 0xC
41#define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8)
42#define NSS_COMMON_CLK_DIV_MASK 0x7f
43
44#define NSS_COMMON_CLK_SRC_CTRL 0x14
45#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x)
46/* Mode is coded on 1 bit but is different depending on the MAC ID:
47 * MAC0: QSGMII=0 RGMII=1
48 * MAC1: QSGMII=0 SGMII=0 RGMII=1
49 * MAC2 & MAC3: QSGMII=0 SGMII=1
50 */
51#define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1
52#define NSS_COMMON_CLK_SRC_CTRL_SGMII(x) ((x >= 2) ? 1 : 0)
53
54#define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4))
55#define NSS_COMMON_GMAC_CTL_CSYS_REQ BIT(19)
56#define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL BIT(16)
57#define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET 8
58#define NSS_COMMON_GMAC_CTL_IFG_OFFSET 0
59
60#define NSS_COMMON_CLK_DIV_RGMII_1000 1
61#define NSS_COMMON_CLK_DIV_RGMII_100 9
62#define NSS_COMMON_CLK_DIV_RGMII_10 99
63#define NSS_COMMON_CLK_DIV_SGMII_1000 0
64#define NSS_COMMON_CLK_DIV_SGMII_100 4
65#define NSS_COMMON_CLK_DIV_SGMII_10 49
66
67#define QSGMII_PCS_CAL_LCKDT_CTL 0x120
68#define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19)
69
70/* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */
71#define QSGMII_PHY_SGMII_CTL(x) ((x == 1) ? 0x134 : \
72 (0x13c + (4 * (x - 2))))
73#define QSGMII_PHY_CDR_EN BIT(0)
74#define QSGMII_PHY_RX_FRONT_EN BIT(1)
75#define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2)
76#define QSGMII_PHY_TX_DRIVER_EN BIT(3)
77#define QSGMII_PHY_QSGMII_EN BIT(7)
78#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET 12
79#define QSGMII_PHY_RX_DC_BIAS_OFFSET 18
80#define QSGMII_PHY_RX_INPUT_EQU_OFFSET 20
81#define QSGMII_PHY_CDR_PI_SLEW_OFFSET 22
82#define QSGMII_PHY_TX_DRV_AMP_OFFSET 28
83
84struct ipq806x_gmac {
85 struct platform_device *pdev;
86 struct regmap *nss_common;
87 struct regmap *qsgmii_csr;
88 uint32_t id;
89 struct clk *core_clk;
90 phy_interface_t phy_mode;
91};
92
93static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed)
94{
95 struct device *dev = &gmac->pdev->dev;
96 int div;
97
98 switch (speed) {
99 case SPEED_1000:
100 div = NSS_COMMON_CLK_DIV_SGMII_1000;
101 break;
102
103 case SPEED_100:
104 div = NSS_COMMON_CLK_DIV_SGMII_100;
105 break;
106
107 case SPEED_10:
108 div = NSS_COMMON_CLK_DIV_SGMII_10;
109 break;
110
111 default:
112 dev_err(dev, "Speed %dMbps not supported in SGMII\n", speed);
113 return -EINVAL;
114 }
115
116 return div;
117}
118
119static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed)
120{
121 struct device *dev = &gmac->pdev->dev;
122 int div;
123
124 switch (speed) {
125 case SPEED_1000:
126 div = NSS_COMMON_CLK_DIV_RGMII_1000;
127 break;
128
129 case SPEED_100:
130 div = NSS_COMMON_CLK_DIV_RGMII_100;
131 break;
132
133 case SPEED_10:
134 div = NSS_COMMON_CLK_DIV_RGMII_10;
135 break;
136
137 default:
138 dev_err(dev, "Speed %dMbps not supported in RGMII\n", speed);
139 return -EINVAL;
140 }
141
142 return div;
143}
144
145static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed)
146{
147 uint32_t clk_bits, val;
148 int div;
149
150 switch (gmac->phy_mode) {
151 case PHY_INTERFACE_MODE_RGMII:
152 div = get_clk_div_rgmii(gmac, speed);
153 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
154 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
155 break;
156
157 case PHY_INTERFACE_MODE_SGMII:
158 div = get_clk_div_sgmii(gmac, speed);
159 clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
160 NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
161 break;
162
163 default:
164 dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n",
165 phy_modes(gmac->phy_mode));
166 return -EINVAL;
167 }
168
169 /* Disable the clocks */
170 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
171 val &= ~clk_bits;
172 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
173
174 /* Set the divider */
175 regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val);
176 val &= ~(NSS_COMMON_CLK_DIV_MASK
177 << NSS_COMMON_CLK_DIV_OFFSET(gmac->id));
178 val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id);
179 regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val);
180
181 /* Enable the clock back */
182 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
183 val |= clk_bits;
184 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
185
186 return 0;
187}
188
189static int ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac)
190{
191 struct device *dev = &gmac->pdev->dev;
192
193 gmac->phy_mode = of_get_phy_mode(dev->of_node);
194 if (gmac->phy_mode < 0) {
195 dev_err(dev, "missing phy mode property\n");
196 return -EINVAL;
197 }
198
199 if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) {
200 dev_err(dev, "missing qcom id property\n");
201 return -EINVAL;
202 }
203
204 /* The GMACs are called 1 to 4 in the documentation, but to simplify the
205 * code and keep it consistent with the Linux convention, we'll number
206 * them from 0 to 3 here.
207 */
208 if (gmac->id > 3) {
209 dev_err(dev, "invalid gmac id\n");
210 return -EINVAL;
211 }
212
213 gmac->core_clk = devm_clk_get(dev, "stmmaceth");
214 if (IS_ERR(gmac->core_clk)) {
215 dev_err(dev, "missing stmmaceth clk property\n");
216 return PTR_ERR(gmac->core_clk);
217 }
218 clk_set_rate(gmac->core_clk, 266000000);
219
220 /* Setup the register map for the nss common registers */
221 gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node,
222 "qcom,nss-common");
223 if (IS_ERR(gmac->nss_common)) {
224 dev_err(dev, "missing nss-common node\n");
225 return PTR_ERR(gmac->nss_common);
226 }
227
228 /* Setup the register map for the qsgmii csr registers */
229 gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node,
230 "qcom,qsgmii-csr");
231 if (IS_ERR(gmac->qsgmii_csr))
232 dev_err(dev, "missing qsgmii-csr node\n");
233
234 return PTR_ERR_OR_ZERO(gmac->qsgmii_csr);
235}
236
237static void ipq806x_gmac_fix_mac_speed(void *priv, unsigned int speed)
238{
239 struct ipq806x_gmac *gmac = priv;
240
241 ipq806x_gmac_set_speed(gmac, speed);
242}
243
244static int ipq806x_gmac_probe(struct platform_device *pdev)
245{
246 struct plat_stmmacenet_data *plat_dat;
247 struct stmmac_resources stmmac_res;
248 struct device *dev = &pdev->dev;
249 struct ipq806x_gmac *gmac;
250 int val;
251 int err;
252
253 val = stmmac_get_platform_resources(pdev, &stmmac_res);
254 if (val)
255 return val;
256
257 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
258 if (IS_ERR(plat_dat))
259 return PTR_ERR(plat_dat);
260
261 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
262 if (!gmac) {
263 err = -ENOMEM;
264 goto err_remove_config_dt;
265 }
266
267 gmac->pdev = pdev;
268
269 err = ipq806x_gmac_of_parse(gmac);
270 if (err) {
271 dev_err(dev, "device tree parsing error\n");
272 goto err_remove_config_dt;
273 }
274
275 regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL,
276 QSGMII_PCS_CAL_LCKDT_CTL_RST);
277
278 /* Inter frame gap is set to 12 */
279 val = 12 << NSS_COMMON_GMAC_CTL_IFG_OFFSET |
280 12 << NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET;
281 /* We also initiate an AXI low power exit request */
282 val |= NSS_COMMON_GMAC_CTL_CSYS_REQ;
283 switch (gmac->phy_mode) {
284 case PHY_INTERFACE_MODE_RGMII:
285 val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
286 break;
287 case PHY_INTERFACE_MODE_SGMII:
288 val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
289 break;
290 default:
291 dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
292 phy_modes(gmac->phy_mode));
293 err = -EINVAL;
294 goto err_remove_config_dt;
295 }
296 regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val);
297
298 /* Configure the clock src according to the mode */
299 regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);
300 val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
301 switch (gmac->phy_mode) {
302 case PHY_INTERFACE_MODE_RGMII:
303 val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
304 NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
305 break;
306 case PHY_INTERFACE_MODE_SGMII:
307 val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) <<
308 NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
309 break;
310 default:
311 dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
312 phy_modes(gmac->phy_mode));
313 err = -EINVAL;
314 goto err_remove_config_dt;
315 }
316 regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val);
317
318 /* Enable PTP clock */
319 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
320 val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id);
321 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
322
323 if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) {
324 regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),
325 QSGMII_PHY_CDR_EN |
326 QSGMII_PHY_RX_FRONT_EN |
327 QSGMII_PHY_RX_SIGNAL_DETECT_EN |
328 QSGMII_PHY_TX_DRIVER_EN |
329 QSGMII_PHY_QSGMII_EN |
330 0x4ul << QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET |
331 0x3ul << QSGMII_PHY_RX_DC_BIAS_OFFSET |
332 0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |
333 0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |
334 0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);
335 }
336
337 plat_dat->has_gmac = true;
338 plat_dat->bsp_priv = gmac;
339 plat_dat->fix_mac_speed = ipq806x_gmac_fix_mac_speed;
340
341 err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
342 if (err)
343 goto err_remove_config_dt;
344
345 return 0;
346
347err_remove_config_dt:
348 stmmac_remove_config_dt(pdev, plat_dat);
349
350 return err;
351}
352
353static const struct of_device_id ipq806x_gmac_dwmac_match[] = {
354 { .compatible = "qcom,ipq806x-gmac" },
355 { }
356};
357MODULE_DEVICE_TABLE(of, ipq806x_gmac_dwmac_match);
358
359static struct platform_driver ipq806x_gmac_dwmac_driver = {
360 .probe = ipq806x_gmac_probe,
361 .remove = stmmac_pltfr_remove,
362 .driver = {
363 .name = "ipq806x-gmac-dwmac",
364 .pm = &stmmac_pltfr_pm_ops,
365 .of_match_table = ipq806x_gmac_dwmac_match,
366 },
367};
368module_platform_driver(ipq806x_gmac_dwmac_driver);
369
370MODULE_AUTHOR("Mathieu Olivari <mathieu@codeaurora.org>");
371MODULE_DESCRIPTION("Qualcomm Atheros IPQ806x DWMAC specific glue layer");
372MODULE_LICENSE("Dual BSD/GPL");
1/*
2 * Qualcomm Atheros IPQ806x GMAC glue layer
3 *
4 * Copyright (C) 2015 The Linux Foundation
5 *
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#include <linux/device.h>
20#include <linux/platform_device.h>
21#include <linux/phy.h>
22#include <linux/regmap.h>
23#include <linux/clk.h>
24#include <linux/reset.h>
25#include <linux/of_net.h>
26#include <linux/mfd/syscon.h>
27#include <linux/stmmac.h>
28#include <linux/of_mdio.h>
29#include <linux/module.h>
30
31#include "stmmac_platform.h"
32
33#define NSS_COMMON_CLK_GATE 0x8
34#define NSS_COMMON_CLK_GATE_PTP_EN(x) BIT(0x10 + x)
35#define NSS_COMMON_CLK_GATE_RGMII_RX_EN(x) BIT(0x9 + (x * 2))
36#define NSS_COMMON_CLK_GATE_RGMII_TX_EN(x) BIT(0x8 + (x * 2))
37#define NSS_COMMON_CLK_GATE_GMII_RX_EN(x) BIT(0x4 + x)
38#define NSS_COMMON_CLK_GATE_GMII_TX_EN(x) BIT(0x0 + x)
39
40#define NSS_COMMON_CLK_DIV0 0xC
41#define NSS_COMMON_CLK_DIV_OFFSET(x) (x * 8)
42#define NSS_COMMON_CLK_DIV_MASK 0x7f
43
44#define NSS_COMMON_CLK_SRC_CTRL 0x14
45#define NSS_COMMON_CLK_SRC_CTRL_OFFSET(x) (x)
46/* Mode is coded on 1 bit but is different depending on the MAC ID:
47 * MAC0: QSGMII=0 RGMII=1
48 * MAC1: QSGMII=0 SGMII=0 RGMII=1
49 * MAC2 & MAC3: QSGMII=0 SGMII=1
50 */
51#define NSS_COMMON_CLK_SRC_CTRL_RGMII(x) 1
52#define NSS_COMMON_CLK_SRC_CTRL_SGMII(x) ((x >= 2) ? 1 : 0)
53
54#define NSS_COMMON_GMAC_CTL(x) (0x30 + (x * 4))
55#define NSS_COMMON_GMAC_CTL_CSYS_REQ BIT(19)
56#define NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL BIT(16)
57#define NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET 8
58#define NSS_COMMON_GMAC_CTL_IFG_OFFSET 0
59
60#define NSS_COMMON_CLK_DIV_RGMII_1000 1
61#define NSS_COMMON_CLK_DIV_RGMII_100 9
62#define NSS_COMMON_CLK_DIV_RGMII_10 99
63#define NSS_COMMON_CLK_DIV_SGMII_1000 0
64#define NSS_COMMON_CLK_DIV_SGMII_100 4
65#define NSS_COMMON_CLK_DIV_SGMII_10 49
66
67#define QSGMII_PCS_CAL_LCKDT_CTL 0x120
68#define QSGMII_PCS_CAL_LCKDT_CTL_RST BIT(19)
69
70/* Only GMAC1/2/3 support SGMII and their CTL register are not contiguous */
71#define QSGMII_PHY_SGMII_CTL(x) ((x == 1) ? 0x134 : \
72 (0x13c + (4 * (x - 2))))
73#define QSGMII_PHY_CDR_EN BIT(0)
74#define QSGMII_PHY_RX_FRONT_EN BIT(1)
75#define QSGMII_PHY_RX_SIGNAL_DETECT_EN BIT(2)
76#define QSGMII_PHY_TX_DRIVER_EN BIT(3)
77#define QSGMII_PHY_QSGMII_EN BIT(7)
78#define QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET 12
79#define QSGMII_PHY_RX_DC_BIAS_OFFSET 18
80#define QSGMII_PHY_RX_INPUT_EQU_OFFSET 20
81#define QSGMII_PHY_CDR_PI_SLEW_OFFSET 22
82#define QSGMII_PHY_TX_DRV_AMP_OFFSET 28
83
84struct ipq806x_gmac {
85 struct platform_device *pdev;
86 struct regmap *nss_common;
87 struct regmap *qsgmii_csr;
88 uint32_t id;
89 struct clk *core_clk;
90 phy_interface_t phy_mode;
91};
92
93static int get_clk_div_sgmii(struct ipq806x_gmac *gmac, unsigned int speed)
94{
95 struct device *dev = &gmac->pdev->dev;
96 int div;
97
98 switch (speed) {
99 case SPEED_1000:
100 div = NSS_COMMON_CLK_DIV_SGMII_1000;
101 break;
102
103 case SPEED_100:
104 div = NSS_COMMON_CLK_DIV_SGMII_100;
105 break;
106
107 case SPEED_10:
108 div = NSS_COMMON_CLK_DIV_SGMII_10;
109 break;
110
111 default:
112 dev_err(dev, "Speed %dMbps not supported in SGMII\n", speed);
113 return -EINVAL;
114 }
115
116 return div;
117}
118
119static int get_clk_div_rgmii(struct ipq806x_gmac *gmac, unsigned int speed)
120{
121 struct device *dev = &gmac->pdev->dev;
122 int div;
123
124 switch (speed) {
125 case SPEED_1000:
126 div = NSS_COMMON_CLK_DIV_RGMII_1000;
127 break;
128
129 case SPEED_100:
130 div = NSS_COMMON_CLK_DIV_RGMII_100;
131 break;
132
133 case SPEED_10:
134 div = NSS_COMMON_CLK_DIV_RGMII_10;
135 break;
136
137 default:
138 dev_err(dev, "Speed %dMbps not supported in RGMII\n", speed);
139 return -EINVAL;
140 }
141
142 return div;
143}
144
145static int ipq806x_gmac_set_speed(struct ipq806x_gmac *gmac, unsigned int speed)
146{
147 uint32_t clk_bits, val;
148 int div;
149
150 switch (gmac->phy_mode) {
151 case PHY_INTERFACE_MODE_RGMII:
152 div = get_clk_div_rgmii(gmac, speed);
153 clk_bits = NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
154 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
155 break;
156
157 case PHY_INTERFACE_MODE_SGMII:
158 div = get_clk_div_sgmii(gmac, speed);
159 clk_bits = NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
160 NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
161 break;
162
163 default:
164 dev_err(&gmac->pdev->dev, "Unsupported PHY mode: \"%s\"\n",
165 phy_modes(gmac->phy_mode));
166 return -EINVAL;
167 }
168
169 /* Disable the clocks */
170 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
171 val &= ~clk_bits;
172 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
173
174 /* Set the divider */
175 regmap_read(gmac->nss_common, NSS_COMMON_CLK_DIV0, &val);
176 val &= ~(NSS_COMMON_CLK_DIV_MASK
177 << NSS_COMMON_CLK_DIV_OFFSET(gmac->id));
178 val |= div << NSS_COMMON_CLK_DIV_OFFSET(gmac->id);
179 regmap_write(gmac->nss_common, NSS_COMMON_CLK_DIV0, val);
180
181 /* Enable the clock back */
182 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
183 val |= clk_bits;
184 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
185
186 return 0;
187}
188
189static int ipq806x_gmac_of_parse(struct ipq806x_gmac *gmac)
190{
191 struct device *dev = &gmac->pdev->dev;
192 int ret;
193
194 ret = of_get_phy_mode(dev->of_node, &gmac->phy_mode);
195 if (ret) {
196 dev_err(dev, "missing phy mode property\n");
197 return -EINVAL;
198 }
199
200 if (of_property_read_u32(dev->of_node, "qcom,id", &gmac->id) < 0) {
201 dev_err(dev, "missing qcom id property\n");
202 return -EINVAL;
203 }
204
205 /* The GMACs are called 1 to 4 in the documentation, but to simplify the
206 * code and keep it consistent with the Linux convention, we'll number
207 * them from 0 to 3 here.
208 */
209 if (gmac->id > 3) {
210 dev_err(dev, "invalid gmac id\n");
211 return -EINVAL;
212 }
213
214 gmac->core_clk = devm_clk_get(dev, "stmmaceth");
215 if (IS_ERR(gmac->core_clk)) {
216 dev_err(dev, "missing stmmaceth clk property\n");
217 return PTR_ERR(gmac->core_clk);
218 }
219 clk_set_rate(gmac->core_clk, 266000000);
220
221 /* Setup the register map for the nss common registers */
222 gmac->nss_common = syscon_regmap_lookup_by_phandle(dev->of_node,
223 "qcom,nss-common");
224 if (IS_ERR(gmac->nss_common)) {
225 dev_err(dev, "missing nss-common node\n");
226 return PTR_ERR(gmac->nss_common);
227 }
228
229 /* Setup the register map for the qsgmii csr registers */
230 gmac->qsgmii_csr = syscon_regmap_lookup_by_phandle(dev->of_node,
231 "qcom,qsgmii-csr");
232 if (IS_ERR(gmac->qsgmii_csr))
233 dev_err(dev, "missing qsgmii-csr node\n");
234
235 return PTR_ERR_OR_ZERO(gmac->qsgmii_csr);
236}
237
238static void ipq806x_gmac_fix_mac_speed(void *priv, unsigned int speed)
239{
240 struct ipq806x_gmac *gmac = priv;
241
242 ipq806x_gmac_set_speed(gmac, speed);
243}
244
245static int ipq806x_gmac_probe(struct platform_device *pdev)
246{
247 struct plat_stmmacenet_data *plat_dat;
248 struct stmmac_resources stmmac_res;
249 struct device *dev = &pdev->dev;
250 struct ipq806x_gmac *gmac;
251 int val;
252 int err;
253
254 val = stmmac_get_platform_resources(pdev, &stmmac_res);
255 if (val)
256 return val;
257
258 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
259 if (IS_ERR(plat_dat))
260 return PTR_ERR(plat_dat);
261
262 gmac = devm_kzalloc(dev, sizeof(*gmac), GFP_KERNEL);
263 if (!gmac) {
264 err = -ENOMEM;
265 goto err_remove_config_dt;
266 }
267
268 gmac->pdev = pdev;
269
270 err = ipq806x_gmac_of_parse(gmac);
271 if (err) {
272 dev_err(dev, "device tree parsing error\n");
273 goto err_remove_config_dt;
274 }
275
276 regmap_write(gmac->qsgmii_csr, QSGMII_PCS_CAL_LCKDT_CTL,
277 QSGMII_PCS_CAL_LCKDT_CTL_RST);
278
279 /* Inter frame gap is set to 12 */
280 val = 12 << NSS_COMMON_GMAC_CTL_IFG_OFFSET |
281 12 << NSS_COMMON_GMAC_CTL_IFG_LIMIT_OFFSET;
282 /* We also initiate an AXI low power exit request */
283 val |= NSS_COMMON_GMAC_CTL_CSYS_REQ;
284 switch (gmac->phy_mode) {
285 case PHY_INTERFACE_MODE_RGMII:
286 val |= NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
287 break;
288 case PHY_INTERFACE_MODE_SGMII:
289 val &= ~NSS_COMMON_GMAC_CTL_PHY_IFACE_SEL;
290 break;
291 default:
292 dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
293 phy_modes(gmac->phy_mode));
294 err = -EINVAL;
295 goto err_remove_config_dt;
296 }
297 regmap_write(gmac->nss_common, NSS_COMMON_GMAC_CTL(gmac->id), val);
298
299 /* Configure the clock src according to the mode */
300 regmap_read(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, &val);
301 val &= ~(1 << NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id));
302 switch (gmac->phy_mode) {
303 case PHY_INTERFACE_MODE_RGMII:
304 val |= NSS_COMMON_CLK_SRC_CTRL_RGMII(gmac->id) <<
305 NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
306 break;
307 case PHY_INTERFACE_MODE_SGMII:
308 val |= NSS_COMMON_CLK_SRC_CTRL_SGMII(gmac->id) <<
309 NSS_COMMON_CLK_SRC_CTRL_OFFSET(gmac->id);
310 break;
311 default:
312 dev_err(&pdev->dev, "Unsupported PHY mode: \"%s\"\n",
313 phy_modes(gmac->phy_mode));
314 err = -EINVAL;
315 goto err_remove_config_dt;
316 }
317 regmap_write(gmac->nss_common, NSS_COMMON_CLK_SRC_CTRL, val);
318
319 /* Enable PTP clock */
320 regmap_read(gmac->nss_common, NSS_COMMON_CLK_GATE, &val);
321 val |= NSS_COMMON_CLK_GATE_PTP_EN(gmac->id);
322 switch (gmac->phy_mode) {
323 case PHY_INTERFACE_MODE_RGMII:
324 val |= NSS_COMMON_CLK_GATE_RGMII_RX_EN(gmac->id) |
325 NSS_COMMON_CLK_GATE_RGMII_TX_EN(gmac->id);
326 break;
327 case PHY_INTERFACE_MODE_SGMII:
328 val |= NSS_COMMON_CLK_GATE_GMII_RX_EN(gmac->id) |
329 NSS_COMMON_CLK_GATE_GMII_TX_EN(gmac->id);
330 break;
331 default:
332 /* We don't get here; the switch above will have errored out */
333 unreachable();
334 }
335 regmap_write(gmac->nss_common, NSS_COMMON_CLK_GATE, val);
336
337 if (gmac->phy_mode == PHY_INTERFACE_MODE_SGMII) {
338 regmap_write(gmac->qsgmii_csr, QSGMII_PHY_SGMII_CTL(gmac->id),
339 QSGMII_PHY_CDR_EN |
340 QSGMII_PHY_RX_FRONT_EN |
341 QSGMII_PHY_RX_SIGNAL_DETECT_EN |
342 QSGMII_PHY_TX_DRIVER_EN |
343 QSGMII_PHY_QSGMII_EN |
344 0x4ul << QSGMII_PHY_PHASE_LOOP_GAIN_OFFSET |
345 0x3ul << QSGMII_PHY_RX_DC_BIAS_OFFSET |
346 0x1ul << QSGMII_PHY_RX_INPUT_EQU_OFFSET |
347 0x2ul << QSGMII_PHY_CDR_PI_SLEW_OFFSET |
348 0xCul << QSGMII_PHY_TX_DRV_AMP_OFFSET);
349 }
350
351 plat_dat->has_gmac = true;
352 plat_dat->bsp_priv = gmac;
353 plat_dat->fix_mac_speed = ipq806x_gmac_fix_mac_speed;
354 plat_dat->multicast_filter_bins = 0;
355
356 err = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
357 if (err)
358 goto err_remove_config_dt;
359
360 return 0;
361
362err_remove_config_dt:
363 stmmac_remove_config_dt(pdev, plat_dat);
364
365 return err;
366}
367
368static const struct of_device_id ipq806x_gmac_dwmac_match[] = {
369 { .compatible = "qcom,ipq806x-gmac" },
370 { }
371};
372MODULE_DEVICE_TABLE(of, ipq806x_gmac_dwmac_match);
373
374static struct platform_driver ipq806x_gmac_dwmac_driver = {
375 .probe = ipq806x_gmac_probe,
376 .remove = stmmac_pltfr_remove,
377 .driver = {
378 .name = "ipq806x-gmac-dwmac",
379 .pm = &stmmac_pltfr_pm_ops,
380 .of_match_table = ipq806x_gmac_dwmac_match,
381 },
382};
383module_platform_driver(ipq806x_gmac_dwmac_driver);
384
385MODULE_AUTHOR("Mathieu Olivari <mathieu@codeaurora.org>");
386MODULE_DESCRIPTION("Qualcomm Atheros IPQ806x DWMAC specific glue layer");
387MODULE_LICENSE("Dual BSD/GPL");