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1/*
2 * Marvell 88E6xxx Ethernet switch single-chip definition
3 *
4 * Copyright (c) 2008 Marvell Semiconductor
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef _MV88E6XXX_CHIP_H
13#define _MV88E6XXX_CHIP_H
14
15#include <linux/if_vlan.h>
16#include <linux/irq.h>
17#include <linux/gpio/consumer.h>
18#include <linux/kthread.h>
19#include <linux/phy.h>
20#include <linux/ptp_clock_kernel.h>
21#include <linux/timecounter.h>
22#include <net/dsa.h>
23
24#ifndef UINT64_MAX
25#define UINT64_MAX (u64)(~((u64)0))
26#endif
27
28#define SMI_CMD 0x00
29#define SMI_CMD_BUSY BIT(15)
30#define SMI_CMD_CLAUSE_22 BIT(12)
31#define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
32#define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
33#define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
34#define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
35#define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
36#define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
37#define SMI_DATA 0x01
38
39#define MV88E6XXX_N_FID 4096
40
41/* PVT limits for 4-bit port and 5-bit switch */
42#define MV88E6XXX_MAX_PVT_SWITCHES 32
43#define MV88E6XXX_MAX_PVT_PORTS 16
44
45#define MV88E6XXX_MAX_GPIO 16
46
47enum mv88e6xxx_egress_mode {
48 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
49 MV88E6XXX_EGRESS_MODE_UNTAGGED,
50 MV88E6XXX_EGRESS_MODE_TAGGED,
51 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
52};
53
54enum mv88e6xxx_frame_mode {
55 MV88E6XXX_FRAME_MODE_NORMAL,
56 MV88E6XXX_FRAME_MODE_DSA,
57 MV88E6XXX_FRAME_MODE_PROVIDER,
58 MV88E6XXX_FRAME_MODE_ETHERTYPE,
59};
60
61/* List of supported models */
62enum mv88e6xxx_model {
63 MV88E6085,
64 MV88E6095,
65 MV88E6097,
66 MV88E6123,
67 MV88E6131,
68 MV88E6141,
69 MV88E6161,
70 MV88E6165,
71 MV88E6171,
72 MV88E6172,
73 MV88E6175,
74 MV88E6176,
75 MV88E6185,
76 MV88E6190,
77 MV88E6190X,
78 MV88E6191,
79 MV88E6240,
80 MV88E6290,
81 MV88E6320,
82 MV88E6321,
83 MV88E6341,
84 MV88E6350,
85 MV88E6351,
86 MV88E6352,
87 MV88E6390,
88 MV88E6390X,
89};
90
91enum mv88e6xxx_family {
92 MV88E6XXX_FAMILY_NONE,
93 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
94 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
95 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
96 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
97 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
98 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
99 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
100 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
101 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
102 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
103};
104
105struct mv88e6xxx_ops;
106
107struct mv88e6xxx_info {
108 enum mv88e6xxx_family family;
109 u16 prod_num;
110 const char *name;
111 unsigned int num_databases;
112 unsigned int num_ports;
113 unsigned int num_internal_phys;
114 unsigned int num_gpio;
115 unsigned int max_vid;
116 unsigned int port_base_addr;
117 unsigned int phy_base_addr;
118 unsigned int global1_addr;
119 unsigned int global2_addr;
120 unsigned int age_time_coeff;
121 unsigned int g1_irqs;
122 unsigned int g2_irqs;
123 bool pvt;
124
125 /* Multi-chip Addressing Mode.
126 * Some chips respond to only 2 registers of its own SMI device address
127 * when it is non-zero, and use indirect access to internal registers.
128 */
129 bool multi_chip;
130 enum dsa_tag_protocol tag_protocol;
131
132 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
133 * operation. 0 means that the ATU Move operation is not supported.
134 */
135 u8 atu_move_port_mask;
136 const struct mv88e6xxx_ops *ops;
137
138 /* Supports PTP */
139 bool ptp_support;
140};
141
142struct mv88e6xxx_atu_entry {
143 u8 state;
144 bool trunk;
145 u16 portvec;
146 u8 mac[ETH_ALEN];
147};
148
149struct mv88e6xxx_vtu_entry {
150 u16 vid;
151 u16 fid;
152 u8 sid;
153 bool valid;
154 u8 member[DSA_MAX_PORTS];
155 u8 state[DSA_MAX_PORTS];
156};
157
158struct mv88e6xxx_bus_ops;
159struct mv88e6xxx_irq_ops;
160struct mv88e6xxx_gpio_ops;
161struct mv88e6xxx_avb_ops;
162
163struct mv88e6xxx_irq {
164 u16 masked;
165 struct irq_chip chip;
166 struct irq_domain *domain;
167 unsigned int nirqs;
168};
169
170/* state flags for mv88e6xxx_port_hwtstamp::state */
171enum {
172 MV88E6XXX_HWTSTAMP_ENABLED,
173 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
174};
175
176struct mv88e6xxx_port_hwtstamp {
177 /* Port index */
178 int port_id;
179
180 /* Timestamping state */
181 unsigned long state;
182
183 /* Resources for receive timestamping */
184 struct sk_buff_head rx_queue;
185 struct sk_buff_head rx_queue2;
186
187 /* Resources for transmit timestamping */
188 unsigned long tx_tstamp_start;
189 struct sk_buff *tx_skb;
190 u16 tx_seq_id;
191
192 /* Current timestamp configuration */
193 struct hwtstamp_config tstamp_config;
194};
195
196struct mv88e6xxx_port {
197 u64 serdes_stats[2];
198 u64 atu_member_violation;
199 u64 atu_miss_violation;
200 u64 atu_full_violation;
201 u64 vtu_member_violation;
202 u64 vtu_miss_violation;
203};
204
205struct mv88e6xxx_chip {
206 const struct mv88e6xxx_info *info;
207
208 /* The dsa_switch this private structure is related to */
209 struct dsa_switch *ds;
210
211 /* The device this structure is associated to */
212 struct device *dev;
213
214 /* This mutex protects the access to the switch registers */
215 struct mutex reg_lock;
216
217 /* The MII bus and the address on the bus that is used to
218 * communication with the switch
219 */
220 const struct mv88e6xxx_bus_ops *smi_ops;
221 struct mii_bus *bus;
222 int sw_addr;
223
224 /* Handles automatic disabling and re-enabling of the PHY
225 * polling unit.
226 */
227 const struct mv88e6xxx_bus_ops *phy_ops;
228 struct mutex ppu_mutex;
229 int ppu_disabled;
230 struct work_struct ppu_work;
231 struct timer_list ppu_timer;
232
233 /* This mutex serialises access to the statistics unit.
234 * Hold this mutex over snapshot + dump sequences.
235 */
236 struct mutex stats_mutex;
237
238 /* A switch may have a GPIO line tied to its reset pin. Parse
239 * this from the device tree, and use it before performing
240 * switch soft reset.
241 */
242 struct gpio_desc *reset;
243
244 /* set to size of eeprom if supported by the switch */
245 int eeprom_len;
246
247 /* List of mdio busses */
248 struct list_head mdios;
249
250 /* There can be two interrupt controllers, which are chained
251 * off a GPIO as interrupt source
252 */
253 struct mv88e6xxx_irq g1_irq;
254 struct mv88e6xxx_irq g2_irq;
255 int irq;
256 int device_irq;
257 int watchdog_irq;
258
259 int atu_prob_irq;
260 int vtu_prob_irq;
261 struct kthread_worker *kworker;
262 struct kthread_delayed_work irq_poll_work;
263
264 /* GPIO resources */
265 u8 gpio_data[2];
266
267 /* This cyclecounter abstracts the switch PTP time.
268 * reg_lock must be held for any operation that read()s.
269 */
270 struct cyclecounter tstamp_cc;
271 struct timecounter tstamp_tc;
272 struct delayed_work overflow_work;
273
274 struct ptp_clock *ptp_clock;
275 struct ptp_clock_info ptp_clock_info;
276 struct delayed_work tai_event_work;
277 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
278 u16 trig_config;
279 u16 evcap_config;
280
281 /* Per-port timestamping resources. */
282 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
283
284 /* Array of port structures. */
285 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
286};
287
288struct mv88e6xxx_bus_ops {
289 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
290 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
291};
292
293struct mv88e6xxx_mdio_bus {
294 struct mii_bus *bus;
295 struct mv88e6xxx_chip *chip;
296 struct list_head list;
297 bool external;
298};
299
300struct mv88e6xxx_ops {
301 /* Ingress Rate Limit unit (IRL) operations */
302 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
303
304 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
305 struct ethtool_eeprom *eeprom, u8 *data);
306 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
307 struct ethtool_eeprom *eeprom, u8 *data);
308
309 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
310
311 int (*phy_read)(struct mv88e6xxx_chip *chip,
312 struct mii_bus *bus,
313 int addr, int reg, u16 *val);
314 int (*phy_write)(struct mv88e6xxx_chip *chip,
315 struct mii_bus *bus,
316 int addr, int reg, u16 val);
317
318 /* Priority Override Table operations */
319 int (*pot_clear)(struct mv88e6xxx_chip *chip);
320
321 /* PHY Polling Unit (PPU) operations */
322 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
323 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
324
325 /* Switch Software Reset */
326 int (*reset)(struct mv88e6xxx_chip *chip);
327
328 /* RGMII Receive/Transmit Timing Control
329 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
330 */
331 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
332 phy_interface_t mode);
333
334#define LINK_FORCED_DOWN 0
335#define LINK_FORCED_UP 1
336#define LINK_UNFORCED -2
337
338 /* Port's MAC link state
339 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
340 * or LINK_UNFORCED for normal link detection.
341 */
342 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
343
344#define DUPLEX_UNFORCED -2
345
346 /* Port's MAC duplex mode
347 *
348 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
349 * or DUPLEX_UNFORCED for normal duplex detection.
350 */
351 int (*port_set_duplex)(struct mv88e6xxx_chip *chip, int port, int dup);
352
353#define SPEED_MAX INT_MAX
354#define SPEED_UNFORCED -2
355
356 /* Port's MAC speed (in Mbps)
357 *
358 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
359 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
360 */
361 int (*port_set_speed)(struct mv88e6xxx_chip *chip, int port, int speed);
362
363 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
364
365 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
366 enum mv88e6xxx_frame_mode mode);
367 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
368 bool unicast, bool multicast);
369 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
370 u16 etype);
371 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
372 size_t size);
373
374 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
375 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
376 u8 out);
377 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
378 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
379
380 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
381 * Some chips allow this to be configured on specific ports.
382 */
383 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
384 phy_interface_t mode);
385
386 /* Some devices have a per port register indicating what is
387 * the upstream port this port should forward to.
388 */
389 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
390 int upstream_port);
391
392 /* Snapshot the statistics for a port. The statistics can then
393 * be read back a leisure but still with a consistent view.
394 */
395 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
396
397 /* Set the histogram mode for statistics, when the control registers
398 * are separated out of the STATS_OP register.
399 */
400 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
401
402 /* Return the number of strings describing statistics */
403 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
404 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
405 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
406 uint64_t *data);
407 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
408 int (*set_egress_port)(struct mv88e6xxx_chip *chip, int port);
409 const struct mv88e6xxx_irq_ops *watchdog_ops;
410
411 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
412
413 /* Power on/off a SERDES interface */
414 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, bool on);
415
416 /* Statistics from the SERDES interface */
417 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
418 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
419 uint8_t *data);
420 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
421 uint64_t *data);
422
423 /* VLAN Translation Unit operations */
424 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
425 struct mv88e6xxx_vtu_entry *entry);
426 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
427 struct mv88e6xxx_vtu_entry *entry);
428
429 /* GPIO operations */
430 const struct mv88e6xxx_gpio_ops *gpio_ops;
431
432 /* Interface to the AVB/PTP registers */
433 const struct mv88e6xxx_avb_ops *avb_ops;
434};
435
436struct mv88e6xxx_irq_ops {
437 /* Action to be performed when the interrupt happens */
438 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
439 /* Setup the hardware to generate the interrupt */
440 int (*irq_setup)(struct mv88e6xxx_chip *chip);
441 /* Reset the hardware to stop generating the interrupt */
442 void (*irq_free)(struct mv88e6xxx_chip *chip);
443};
444
445struct mv88e6xxx_gpio_ops {
446 /* Get/set data on GPIO pin */
447 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
448 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
449 int value);
450
451 /* get/set GPIO direction */
452 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
453 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
454 bool input);
455
456 /* get/set GPIO pin control */
457 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
458 int *func);
459 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
460 int func);
461};
462
463struct mv88e6xxx_avb_ops {
464 /* Access port-scoped Precision Time Protocol registers */
465 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
466 u16 *data, int len);
467 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
468 u16 data);
469
470 /* Access global Precision Time Protocol registers */
471 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
472 int len);
473 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
474
475 /* Access global Time Application Interface registers */
476 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
477 int len);
478 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
479};
480
481#define STATS_TYPE_PORT BIT(0)
482#define STATS_TYPE_BANK0 BIT(1)
483#define STATS_TYPE_BANK1 BIT(2)
484
485struct mv88e6xxx_hw_stat {
486 char string[ETH_GSTRING_LEN];
487 size_t size;
488 int reg;
489 int type;
490};
491
492static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
493{
494 return chip->info->pvt;
495}
496
497static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
498{
499 return chip->info->num_databases;
500}
501
502static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
503{
504 return chip->info->num_ports;
505}
506
507static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
508{
509 return GENMASK(mv88e6xxx_num_ports(chip) - 1, 0);
510}
511
512static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
513{
514 return chip->info->num_gpio;
515}
516
517int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
518int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
519int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg,
520 u16 update);
521int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask);
522struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
523
524#endif /* _MV88E6XXX_CHIP_H */
1/* SPDX-License-Identifier: GPL-2.0-or-later */
2/*
3 * Marvell 88E6xxx Ethernet switch single-chip definition
4 *
5 * Copyright (c) 2008 Marvell Semiconductor
6 */
7
8#ifndef _MV88E6XXX_CHIP_H
9#define _MV88E6XXX_CHIP_H
10
11#include <linux/idr.h>
12#include <linux/if_vlan.h>
13#include <linux/irq.h>
14#include <linux/gpio/consumer.h>
15#include <linux/kthread.h>
16#include <linux/phy.h>
17#include <linux/ptp_clock_kernel.h>
18#include <linux/timecounter.h>
19#include <net/dsa.h>
20
21#define MV88E6XXX_N_FID 4096
22
23/* PVT limits for 4-bit port and 5-bit switch */
24#define MV88E6XXX_MAX_PVT_SWITCHES 32
25#define MV88E6XXX_MAX_PVT_PORTS 16
26
27#define MV88E6XXX_MAX_GPIO 16
28
29enum mv88e6xxx_egress_mode {
30 MV88E6XXX_EGRESS_MODE_UNMODIFIED,
31 MV88E6XXX_EGRESS_MODE_UNTAGGED,
32 MV88E6XXX_EGRESS_MODE_TAGGED,
33 MV88E6XXX_EGRESS_MODE_ETHERTYPE,
34};
35
36enum mv88e6xxx_egress_direction {
37 MV88E6XXX_EGRESS_DIR_INGRESS,
38 MV88E6XXX_EGRESS_DIR_EGRESS,
39};
40
41enum mv88e6xxx_frame_mode {
42 MV88E6XXX_FRAME_MODE_NORMAL,
43 MV88E6XXX_FRAME_MODE_DSA,
44 MV88E6XXX_FRAME_MODE_PROVIDER,
45 MV88E6XXX_FRAME_MODE_ETHERTYPE,
46};
47
48/* List of supported models */
49enum mv88e6xxx_model {
50 MV88E6085,
51 MV88E6095,
52 MV88E6097,
53 MV88E6123,
54 MV88E6131,
55 MV88E6141,
56 MV88E6161,
57 MV88E6165,
58 MV88E6171,
59 MV88E6172,
60 MV88E6175,
61 MV88E6176,
62 MV88E6185,
63 MV88E6190,
64 MV88E6190X,
65 MV88E6191,
66 MV88E6220,
67 MV88E6240,
68 MV88E6250,
69 MV88E6290,
70 MV88E6320,
71 MV88E6321,
72 MV88E6341,
73 MV88E6350,
74 MV88E6351,
75 MV88E6352,
76 MV88E6390,
77 MV88E6390X,
78};
79
80enum mv88e6xxx_family {
81 MV88E6XXX_FAMILY_NONE,
82 MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
83 MV88E6XXX_FAMILY_6095, /* 6092 6095 */
84 MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
85 MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
86 MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
87 MV88E6XXX_FAMILY_6250, /* 6220 6250 */
88 MV88E6XXX_FAMILY_6320, /* 6320 6321 */
89 MV88E6XXX_FAMILY_6341, /* 6141 6341 */
90 MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
91 MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
92 MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
93};
94
95struct mv88e6xxx_ops;
96
97struct mv88e6xxx_info {
98 enum mv88e6xxx_family family;
99 u16 prod_num;
100 const char *name;
101 unsigned int num_databases;
102 unsigned int num_macs;
103 unsigned int num_ports;
104 unsigned int num_internal_phys;
105 unsigned int num_gpio;
106 unsigned int max_vid;
107 unsigned int port_base_addr;
108 unsigned int phy_base_addr;
109 unsigned int global1_addr;
110 unsigned int global2_addr;
111 unsigned int age_time_coeff;
112 unsigned int g1_irqs;
113 unsigned int g2_irqs;
114 bool pvt;
115
116 /* Mark certain ports as invalid. This is required for example for the
117 * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
118 * ports 2-4 are not routet to pins.
119 */
120 unsigned int invalid_port_mask;
121 /* Multi-chip Addressing Mode.
122 * Some chips respond to only 2 registers of its own SMI device address
123 * when it is non-zero, and use indirect access to internal registers.
124 */
125 bool multi_chip;
126 /* Dual-chip Addressing Mode
127 * Some chips respond to only half of the 32 SMI addresses,
128 * allowing two to coexist on the same SMI interface.
129 */
130 bool dual_chip;
131
132 enum dsa_tag_protocol tag_protocol;
133
134 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
135 * operation. 0 means that the ATU Move operation is not supported.
136 */
137 u8 atu_move_port_mask;
138 const struct mv88e6xxx_ops *ops;
139
140 /* Supports PTP */
141 bool ptp_support;
142};
143
144struct mv88e6xxx_atu_entry {
145 u8 state;
146 bool trunk;
147 u16 portvec;
148 u8 mac[ETH_ALEN];
149};
150
151struct mv88e6xxx_vtu_entry {
152 u16 vid;
153 u16 fid;
154 u8 sid;
155 bool valid;
156 u8 member[DSA_MAX_PORTS];
157 u8 state[DSA_MAX_PORTS];
158};
159
160struct mv88e6xxx_bus_ops;
161struct mv88e6xxx_irq_ops;
162struct mv88e6xxx_gpio_ops;
163struct mv88e6xxx_avb_ops;
164struct mv88e6xxx_ptp_ops;
165
166struct mv88e6xxx_irq {
167 u16 masked;
168 struct irq_chip chip;
169 struct irq_domain *domain;
170 int nirqs;
171};
172
173/* state flags for mv88e6xxx_port_hwtstamp::state */
174enum {
175 MV88E6XXX_HWTSTAMP_ENABLED,
176 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
177};
178
179struct mv88e6xxx_port_hwtstamp {
180 /* Port index */
181 int port_id;
182
183 /* Timestamping state */
184 unsigned long state;
185
186 /* Resources for receive timestamping */
187 struct sk_buff_head rx_queue;
188 struct sk_buff_head rx_queue2;
189
190 /* Resources for transmit timestamping */
191 unsigned long tx_tstamp_start;
192 struct sk_buff *tx_skb;
193 u16 tx_seq_id;
194
195 /* Current timestamp configuration */
196 struct hwtstamp_config tstamp_config;
197};
198
199enum mv88e6xxx_policy_mapping {
200 MV88E6XXX_POLICY_MAPPING_DA,
201 MV88E6XXX_POLICY_MAPPING_SA,
202 MV88E6XXX_POLICY_MAPPING_VTU,
203 MV88E6XXX_POLICY_MAPPING_ETYPE,
204 MV88E6XXX_POLICY_MAPPING_PPPOE,
205 MV88E6XXX_POLICY_MAPPING_VBAS,
206 MV88E6XXX_POLICY_MAPPING_OPT82,
207 MV88E6XXX_POLICY_MAPPING_UDP,
208};
209
210enum mv88e6xxx_policy_action {
211 MV88E6XXX_POLICY_ACTION_NORMAL,
212 MV88E6XXX_POLICY_ACTION_MIRROR,
213 MV88E6XXX_POLICY_ACTION_TRAP,
214 MV88E6XXX_POLICY_ACTION_DISCARD,
215};
216
217struct mv88e6xxx_policy {
218 enum mv88e6xxx_policy_mapping mapping;
219 enum mv88e6xxx_policy_action action;
220 struct ethtool_rx_flow_spec fs;
221 u8 addr[ETH_ALEN];
222 int port;
223 u16 vid;
224};
225
226struct mv88e6xxx_port {
227 struct mv88e6xxx_chip *chip;
228 int port;
229 u64 serdes_stats[2];
230 u64 atu_member_violation;
231 u64 atu_miss_violation;
232 u64 atu_full_violation;
233 u64 vtu_member_violation;
234 u64 vtu_miss_violation;
235 phy_interface_t interface;
236 u8 cmode;
237 bool mirror_ingress;
238 bool mirror_egress;
239 unsigned int serdes_irq;
240 char serdes_irq_name[64];
241};
242
243struct mv88e6xxx_chip {
244 const struct mv88e6xxx_info *info;
245
246 /* The dsa_switch this private structure is related to */
247 struct dsa_switch *ds;
248
249 /* The device this structure is associated to */
250 struct device *dev;
251
252 /* This mutex protects the access to the switch registers */
253 struct mutex reg_lock;
254
255 /* The MII bus and the address on the bus that is used to
256 * communication with the switch
257 */
258 const struct mv88e6xxx_bus_ops *smi_ops;
259 struct mii_bus *bus;
260 int sw_addr;
261
262 /* Handles automatic disabling and re-enabling of the PHY
263 * polling unit.
264 */
265 const struct mv88e6xxx_bus_ops *phy_ops;
266 struct mutex ppu_mutex;
267 int ppu_disabled;
268 struct work_struct ppu_work;
269 struct timer_list ppu_timer;
270
271 /* This mutex serialises access to the statistics unit.
272 * Hold this mutex over snapshot + dump sequences.
273 */
274 struct mutex stats_mutex;
275
276 /* A switch may have a GPIO line tied to its reset pin. Parse
277 * this from the device tree, and use it before performing
278 * switch soft reset.
279 */
280 struct gpio_desc *reset;
281
282 /* set to size of eeprom if supported by the switch */
283 u32 eeprom_len;
284
285 /* List of mdio busses */
286 struct list_head mdios;
287
288 /* Policy Control List IDs and rules */
289 struct idr policies;
290
291 /* There can be two interrupt controllers, which are chained
292 * off a GPIO as interrupt source
293 */
294 struct mv88e6xxx_irq g1_irq;
295 struct mv88e6xxx_irq g2_irq;
296 int irq;
297 char irq_name[64];
298 int device_irq;
299 char device_irq_name[64];
300 int watchdog_irq;
301 char watchdog_irq_name[64];
302
303 int atu_prob_irq;
304 char atu_prob_irq_name[64];
305 int vtu_prob_irq;
306 char vtu_prob_irq_name[64];
307 struct kthread_worker *kworker;
308 struct kthread_delayed_work irq_poll_work;
309
310 /* GPIO resources */
311 u8 gpio_data[2];
312
313 /* This cyclecounter abstracts the switch PTP time.
314 * reg_lock must be held for any operation that read()s.
315 */
316 struct cyclecounter tstamp_cc;
317 struct timecounter tstamp_tc;
318 struct delayed_work overflow_work;
319
320 struct ptp_clock *ptp_clock;
321 struct ptp_clock_info ptp_clock_info;
322 struct delayed_work tai_event_work;
323 struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
324 u16 trig_config;
325 u16 evcap_config;
326 u16 enable_count;
327
328 /* Current ingress and egress monitor ports */
329 int egress_dest_port;
330 int ingress_dest_port;
331
332 /* Per-port timestamping resources. */
333 struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
334
335 /* Array of port structures. */
336 struct mv88e6xxx_port ports[DSA_MAX_PORTS];
337};
338
339struct mv88e6xxx_bus_ops {
340 int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
341 int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
342};
343
344struct mv88e6xxx_mdio_bus {
345 struct mii_bus *bus;
346 struct mv88e6xxx_chip *chip;
347 struct list_head list;
348 bool external;
349};
350
351struct mv88e6xxx_ops {
352 /* Switch Setup Errata, called early in the switch setup to
353 * allow any errata actions to be performed
354 */
355 int (*setup_errata)(struct mv88e6xxx_chip *chip);
356
357 int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
358 int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
359
360 /* Ingress Rate Limit unit (IRL) operations */
361 int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
362
363 int (*get_eeprom)(struct mv88e6xxx_chip *chip,
364 struct ethtool_eeprom *eeprom, u8 *data);
365 int (*set_eeprom)(struct mv88e6xxx_chip *chip,
366 struct ethtool_eeprom *eeprom, u8 *data);
367
368 int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
369
370 int (*phy_read)(struct mv88e6xxx_chip *chip,
371 struct mii_bus *bus,
372 int addr, int reg, u16 *val);
373 int (*phy_write)(struct mv88e6xxx_chip *chip,
374 struct mii_bus *bus,
375 int addr, int reg, u16 val);
376
377 /* Priority Override Table operations */
378 int (*pot_clear)(struct mv88e6xxx_chip *chip);
379
380 /* PHY Polling Unit (PPU) operations */
381 int (*ppu_enable)(struct mv88e6xxx_chip *chip);
382 int (*ppu_disable)(struct mv88e6xxx_chip *chip);
383
384 /* Switch Software Reset */
385 int (*reset)(struct mv88e6xxx_chip *chip);
386
387 /* RGMII Receive/Transmit Timing Control
388 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
389 */
390 int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
391 phy_interface_t mode);
392
393#define LINK_FORCED_DOWN 0
394#define LINK_FORCED_UP 1
395#define LINK_UNFORCED -2
396
397 /* Port's MAC link state
398 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
399 * or LINK_UNFORCED for normal link detection.
400 */
401 int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
402
403#define PAUSE_ON 1
404#define PAUSE_OFF 0
405
406 /* Enable/disable sending Pause */
407 int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
408 int pause);
409
410#define SPEED_MAX INT_MAX
411#define SPEED_UNFORCED -2
412#define DUPLEX_UNFORCED -2
413
414 /* Port's MAC speed (in Mbps) and MAC duplex mode
415 *
416 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
417 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
418 *
419 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
420 * or DUPLEX_UNFORCED for normal duplex detection.
421 */
422 int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
423 int speed, int duplex);
424
425 /* What interface mode should be used for maximum speed? */
426 phy_interface_t (*port_max_speed_mode)(int port);
427
428 int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
429
430 int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
431 enum mv88e6xxx_policy_mapping mapping,
432 enum mv88e6xxx_policy_action action);
433
434 int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
435 enum mv88e6xxx_frame_mode mode);
436 int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
437 bool unicast, bool multicast);
438 int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
439 u16 etype);
440 int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
441 size_t size);
442
443 int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
444 int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
445 u8 out);
446 int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
447 int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
448 int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
449
450 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
451 * Some chips allow this to be configured on specific ports.
452 */
453 int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
454 phy_interface_t mode);
455 int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
456
457 /* Some devices have a per port register indicating what is
458 * the upstream port this port should forward to.
459 */
460 int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
461 int upstream_port);
462
463 /* Snapshot the statistics for a port. The statistics can then
464 * be read back a leisure but still with a consistent view.
465 */
466 int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
467
468 /* Set the histogram mode for statistics, when the control registers
469 * are separated out of the STATS_OP register.
470 */
471 int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
472
473 /* Return the number of strings describing statistics */
474 int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
475 int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
476 int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
477 uint64_t *data);
478 int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
479 int (*set_egress_port)(struct mv88e6xxx_chip *chip,
480 enum mv88e6xxx_egress_direction direction,
481 int port);
482
483#define MV88E6XXX_CASCADE_PORT_NONE 0xe
484#define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
485
486 int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
487
488 const struct mv88e6xxx_irq_ops *watchdog_ops;
489
490 int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
491
492 /* Power on/off a SERDES interface */
493 int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane,
494 bool up);
495
496 /* SERDES lane mapping */
497 u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
498
499 int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,
500 u8 lane, struct phylink_link_state *state);
501 int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,
502 u8 lane, unsigned int mode,
503 phy_interface_t interface,
504 const unsigned long *advertise);
505 int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,
506 u8 lane);
507 int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,
508 u8 lane, int speed, int duplex);
509
510 /* SERDES interrupt handling */
511 unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
512 int port);
513 int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane,
514 bool enable);
515 irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
516 u8 lane);
517
518 /* Statistics from the SERDES interface */
519 int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
520 int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
521 uint8_t *data);
522 int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
523 uint64_t *data);
524
525 /* SERDES registers for ethtool */
526 int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port);
527 void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
528 void *_p);
529
530 /* Address Translation Unit operations */
531 int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
532 int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
533
534 /* VLAN Translation Unit operations */
535 int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
536 struct mv88e6xxx_vtu_entry *entry);
537 int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
538 struct mv88e6xxx_vtu_entry *entry);
539
540 /* GPIO operations */
541 const struct mv88e6xxx_gpio_ops *gpio_ops;
542
543 /* Interface to the AVB/PTP registers */
544 const struct mv88e6xxx_avb_ops *avb_ops;
545
546 /* Remote Management Unit operations */
547 int (*rmu_disable)(struct mv88e6xxx_chip *chip);
548
549 /* Precision Time Protocol operations */
550 const struct mv88e6xxx_ptp_ops *ptp_ops;
551
552 /* Phylink */
553 void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
554 unsigned long *mask,
555 struct phylink_link_state *state);
556
557 /* Max Frame Size */
558 int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
559};
560
561struct mv88e6xxx_irq_ops {
562 /* Action to be performed when the interrupt happens */
563 int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
564 /* Setup the hardware to generate the interrupt */
565 int (*irq_setup)(struct mv88e6xxx_chip *chip);
566 /* Reset the hardware to stop generating the interrupt */
567 void (*irq_free)(struct mv88e6xxx_chip *chip);
568};
569
570struct mv88e6xxx_gpio_ops {
571 /* Get/set data on GPIO pin */
572 int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
573 int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
574 int value);
575
576 /* get/set GPIO direction */
577 int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
578 int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
579 bool input);
580
581 /* get/set GPIO pin control */
582 int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
583 int *func);
584 int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
585 int func);
586};
587
588struct mv88e6xxx_avb_ops {
589 /* Access port-scoped Precision Time Protocol registers */
590 int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
591 u16 *data, int len);
592 int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
593 u16 data);
594
595 /* Access global Precision Time Protocol registers */
596 int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
597 int len);
598 int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
599
600 /* Access global Time Application Interface registers */
601 int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
602 int len);
603 int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
604};
605
606struct mv88e6xxx_ptp_ops {
607 u64 (*clock_read)(const struct cyclecounter *cc);
608 int (*ptp_enable)(struct ptp_clock_info *ptp,
609 struct ptp_clock_request *rq, int on);
610 int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
611 enum ptp_pin_function func, unsigned int chan);
612 void (*event_work)(struct work_struct *ugly);
613 int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
614 int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
615 int (*global_enable)(struct mv88e6xxx_chip *chip);
616 int (*global_disable)(struct mv88e6xxx_chip *chip);
617 int n_ext_ts;
618 int arr0_sts_reg;
619 int arr1_sts_reg;
620 int dep_sts_reg;
621 u32 rx_filters;
622 u32 cc_shift;
623 u32 cc_mult;
624 u32 cc_mult_num;
625 u32 cc_mult_dem;
626};
627
628#define STATS_TYPE_PORT BIT(0)
629#define STATS_TYPE_BANK0 BIT(1)
630#define STATS_TYPE_BANK1 BIT(2)
631
632struct mv88e6xxx_hw_stat {
633 char string[ETH_GSTRING_LEN];
634 size_t size;
635 int reg;
636 int type;
637};
638
639static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
640{
641 return chip->info->pvt;
642}
643
644static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
645{
646 return chip->info->num_databases;
647}
648
649static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip)
650{
651 return chip->info->num_macs;
652}
653
654static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
655{
656 return chip->info->num_ports;
657}
658
659static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
660{
661 return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
662}
663
664static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
665{
666 return chip->info->num_gpio;
667}
668
669static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
670{
671 return (chip->info->invalid_port_mask & BIT(port)) != 0;
672}
673
674int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
675int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
676int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
677 u16 mask, u16 val);
678int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
679 int bit, int val);
680struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
681
682static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
683{
684 mutex_lock(&chip->reg_lock);
685}
686
687static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
688{
689 mutex_unlock(&chip->reg_lock);
690}
691
692#endif /* _MV88E6XXX_CHIP_H */