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1/*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#include <linux/list.h>
13#include <linux/module.h>
14#include <linux/netdevice.h>
15#include <linux/interrupt.h>
16#include <linux/platform_device.h>
17#include <linux/phy.h>
18#include <linux/phy_fixed.h>
19#include <linux/mii.h>
20#include <linux/of.h>
21#include <linux/of_irq.h>
22#include <linux/of_address.h>
23#include <linux/of_net.h>
24#include <linux/of_mdio.h>
25#include <net/dsa.h>
26#include <linux/ethtool.h>
27#include <linux/if_bridge.h>
28#include <linux/brcmphy.h>
29#include <linux/etherdevice.h>
30#include <linux/platform_data/b53.h>
31
32#include "bcm_sf2.h"
33#include "bcm_sf2_regs.h"
34#include "b53/b53_priv.h"
35#include "b53/b53_regs.h"
36
37static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
38{
39 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
40 unsigned int i;
41 u32 reg, offset;
42
43 if (priv->type == BCM7445_DEVICE_ID)
44 offset = CORE_STS_OVERRIDE_IMP;
45 else
46 offset = CORE_STS_OVERRIDE_IMP2;
47
48 /* Enable the port memories */
49 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
50 reg &= ~P_TXQ_PSM_VDD(port);
51 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
52
53 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
54 reg = core_readl(priv, CORE_IMP_CTL);
55 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
56 reg &= ~(RX_DIS | TX_DIS);
57 core_writel(priv, reg, CORE_IMP_CTL);
58
59 /* Enable forwarding */
60 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
61
62 /* Enable IMP port in dumb mode */
63 reg = core_readl(priv, CORE_SWITCH_CTRL);
64 reg |= MII_DUMB_FWDG_EN;
65 core_writel(priv, reg, CORE_SWITCH_CTRL);
66
67 /* Configure Traffic Class to QoS mapping, allow each priority to map
68 * to a different queue number
69 */
70 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
71 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
72 reg |= i << (PRT_TO_QID_SHIFT * i);
73 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
74
75 b53_brcm_hdr_setup(ds, port);
76
77 /* Force link status for IMP port */
78 reg = core_readl(priv, offset);
79 reg |= (MII_SW_OR | LINK_STS);
80 core_writel(priv, reg, offset);
81}
82
83static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
84{
85 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
86 u32 reg;
87
88 reg = reg_readl(priv, REG_SPHY_CNTRL);
89 if (enable) {
90 reg |= PHY_RESET;
91 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
92 reg_writel(priv, reg, REG_SPHY_CNTRL);
93 udelay(21);
94 reg = reg_readl(priv, REG_SPHY_CNTRL);
95 reg &= ~PHY_RESET;
96 } else {
97 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
98 reg_writel(priv, reg, REG_SPHY_CNTRL);
99 mdelay(1);
100 reg |= CK25_DIS;
101 }
102 reg_writel(priv, reg, REG_SPHY_CNTRL);
103
104 /* Use PHY-driven LED signaling */
105 if (!enable) {
106 reg = reg_readl(priv, REG_LED_CNTRL(0));
107 reg |= SPDLNK_SRC_SEL;
108 reg_writel(priv, reg, REG_LED_CNTRL(0));
109 }
110}
111
112static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
113 int port)
114{
115 unsigned int off;
116
117 switch (port) {
118 case 7:
119 off = P7_IRQ_OFF;
120 break;
121 case 0:
122 /* Port 0 interrupts are located on the first bank */
123 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
124 return;
125 default:
126 off = P_IRQ_OFF(port);
127 break;
128 }
129
130 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
131}
132
133static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
134 int port)
135{
136 unsigned int off;
137
138 switch (port) {
139 case 7:
140 off = P7_IRQ_OFF;
141 break;
142 case 0:
143 /* Port 0 interrupts are located on the first bank */
144 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
145 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
146 return;
147 default:
148 off = P_IRQ_OFF(port);
149 break;
150 }
151
152 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
153 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
154}
155
156static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
157 struct phy_device *phy)
158{
159 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
160 unsigned int i;
161 u32 reg;
162
163 /* Clear the memory power down */
164 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
165 reg &= ~P_TXQ_PSM_VDD(port);
166 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
167
168 /* Enable Broadcom tags for that port if requested */
169 if (priv->brcm_tag_mask & BIT(port))
170 b53_brcm_hdr_setup(ds, port);
171
172 /* Configure Traffic Class to QoS mapping, allow each priority to map
173 * to a different queue number
174 */
175 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
176 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
177 reg |= i << (PRT_TO_QID_SHIFT * i);
178 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
179
180 /* Re-enable the GPHY and re-apply workarounds */
181 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
182 bcm_sf2_gphy_enable_set(ds, true);
183 if (phy) {
184 /* if phy_stop() has been called before, phy
185 * will be in halted state, and phy_start()
186 * will call resume.
187 *
188 * the resume path does not configure back
189 * autoneg settings, and since we hard reset
190 * the phy manually here, we need to reset the
191 * state machine also.
192 */
193 phy->state = PHY_READY;
194 phy_init_hw(phy);
195 }
196 }
197
198 /* Enable MoCA port interrupts to get notified */
199 if (port == priv->moca_port)
200 bcm_sf2_port_intr_enable(priv, port);
201
202 /* Set per-queue pause threshold to 32 */
203 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
204
205 /* Set ACB threshold to 24 */
206 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
207 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
208 SF2_NUM_EGRESS_QUEUES + i));
209 reg &= ~XOFF_THRESHOLD_MASK;
210 reg |= 24;
211 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
212 SF2_NUM_EGRESS_QUEUES + i));
213 }
214
215 return b53_enable_port(ds, port, phy);
216}
217
218static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
219 struct phy_device *phy)
220{
221 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
222 u32 off, reg;
223
224 if (priv->wol_ports_mask & (1 << port))
225 return;
226
227 if (port == priv->moca_port)
228 bcm_sf2_port_intr_disable(priv, port);
229
230 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
231 bcm_sf2_gphy_enable_set(ds, false);
232
233 if (dsa_is_cpu_port(ds, port))
234 off = CORE_IMP_CTL;
235 else
236 off = CORE_G_PCTL_PORT(port);
237
238 b53_disable_port(ds, port, phy);
239
240 /* Power down the port memory */
241 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
242 reg |= P_TXQ_PSM_VDD(port);
243 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
244}
245
246
247static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
248 int regnum, u16 val)
249{
250 int ret = 0;
251 u32 reg;
252
253 reg = reg_readl(priv, REG_SWITCH_CNTRL);
254 reg |= MDIO_MASTER_SEL;
255 reg_writel(priv, reg, REG_SWITCH_CNTRL);
256
257 /* Page << 8 | offset */
258 reg = 0x70;
259 reg <<= 2;
260 core_writel(priv, addr, reg);
261
262 /* Page << 8 | offset */
263 reg = 0x80 << 8 | regnum << 1;
264 reg <<= 2;
265
266 if (op)
267 ret = core_readl(priv, reg);
268 else
269 core_writel(priv, val, reg);
270
271 reg = reg_readl(priv, REG_SWITCH_CNTRL);
272 reg &= ~MDIO_MASTER_SEL;
273 reg_writel(priv, reg, REG_SWITCH_CNTRL);
274
275 return ret & 0xffff;
276}
277
278static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
279{
280 struct bcm_sf2_priv *priv = bus->priv;
281
282 /* Intercept reads from Broadcom pseudo-PHY address, else, send
283 * them to our master MDIO bus controller
284 */
285 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
286 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
287 else
288 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
289}
290
291static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
292 u16 val)
293{
294 struct bcm_sf2_priv *priv = bus->priv;
295
296 /* Intercept writes to the Broadcom pseudo-PHY address, else,
297 * send them to our master MDIO bus controller
298 */
299 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
300 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
301 else
302 mdiobus_write_nested(priv->master_mii_bus, addr, regnum, val);
303
304 return 0;
305}
306
307static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
308{
309 struct bcm_sf2_priv *priv = dev_id;
310
311 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
312 ~priv->irq0_mask;
313 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
314
315 return IRQ_HANDLED;
316}
317
318static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
319{
320 struct bcm_sf2_priv *priv = dev_id;
321
322 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
323 ~priv->irq1_mask;
324 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
325
326 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
327 priv->port_sts[7].link = 1;
328 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
329 priv->port_sts[7].link = 0;
330
331 return IRQ_HANDLED;
332}
333
334static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
335{
336 unsigned int timeout = 1000;
337 u32 reg;
338
339 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
340 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
341 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
342
343 do {
344 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
345 if (!(reg & SOFTWARE_RESET))
346 break;
347
348 usleep_range(1000, 2000);
349 } while (timeout-- > 0);
350
351 if (timeout == 0)
352 return -ETIMEDOUT;
353
354 return 0;
355}
356
357static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
358{
359 intrl2_0_mask_set(priv, 0xffffffff);
360 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
361 intrl2_1_mask_set(priv, 0xffffffff);
362 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
363}
364
365static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
366 struct device_node *dn)
367{
368 struct device_node *port;
369 int mode;
370 unsigned int port_num;
371
372 priv->moca_port = -1;
373
374 for_each_available_child_of_node(dn, port) {
375 if (of_property_read_u32(port, "reg", &port_num))
376 continue;
377
378 /* Internal PHYs get assigned a specific 'phy-mode' property
379 * value: "internal" to help flag them before MDIO probing
380 * has completed, since they might be turned off at that
381 * time
382 */
383 mode = of_get_phy_mode(port);
384 if (mode < 0)
385 continue;
386
387 if (mode == PHY_INTERFACE_MODE_INTERNAL)
388 priv->int_phy_mask |= 1 << port_num;
389
390 if (mode == PHY_INTERFACE_MODE_MOCA)
391 priv->moca_port = port_num;
392
393 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
394 priv->brcm_tag_mask |= 1 << port_num;
395 }
396}
397
398static int bcm_sf2_mdio_register(struct dsa_switch *ds)
399{
400 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
401 struct device_node *dn;
402 static int index;
403 int err;
404
405 /* Find our integrated MDIO bus node */
406 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
407 priv->master_mii_bus = of_mdio_find_bus(dn);
408 if (!priv->master_mii_bus)
409 return -EPROBE_DEFER;
410
411 get_device(&priv->master_mii_bus->dev);
412 priv->master_mii_dn = dn;
413
414 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
415 if (!priv->slave_mii_bus)
416 return -ENOMEM;
417
418 priv->slave_mii_bus->priv = priv;
419 priv->slave_mii_bus->name = "sf2 slave mii";
420 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
421 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
422 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
423 index++);
424 priv->slave_mii_bus->dev.of_node = dn;
425
426 /* Include the pseudo-PHY address to divert reads towards our
427 * workaround. This is only required for 7445D0, since 7445E0
428 * disconnects the internal switch pseudo-PHY such that we can use the
429 * regular SWITCH_MDIO master controller instead.
430 *
431 * Here we flag the pseudo PHY as needing special treatment and would
432 * otherwise make all other PHY read/writes go to the master MDIO bus
433 * controller that comes with this switch backed by the "mdio-unimac"
434 * driver.
435 */
436 if (of_machine_is_compatible("brcm,bcm7445d0"))
437 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
438 else
439 priv->indir_phy_mask = 0;
440
441 ds->phys_mii_mask = priv->indir_phy_mask;
442 ds->slave_mii_bus = priv->slave_mii_bus;
443 priv->slave_mii_bus->parent = ds->dev->parent;
444 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
445
446 if (dn)
447 err = of_mdiobus_register(priv->slave_mii_bus, dn);
448 else
449 err = mdiobus_register(priv->slave_mii_bus);
450
451 if (err)
452 of_node_put(dn);
453
454 return err;
455}
456
457static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
458{
459 mdiobus_unregister(priv->slave_mii_bus);
460 if (priv->master_mii_dn)
461 of_node_put(priv->master_mii_dn);
462}
463
464static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
465{
466 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
467
468 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
469 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
470 * the REG_PHY_REVISION register layout is.
471 */
472
473 return priv->hw_params.gphy_rev;
474}
475
476static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
477 struct phy_device *phydev)
478{
479 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
480 struct ethtool_eee *p = &priv->dev->ports[port].eee;
481 u32 id_mode_dis = 0, port_mode;
482 const char *str = NULL;
483 u32 reg, offset;
484
485 if (priv->type == BCM7445_DEVICE_ID)
486 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
487 else
488 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
489
490 switch (phydev->interface) {
491 case PHY_INTERFACE_MODE_RGMII:
492 str = "RGMII (no delay)";
493 id_mode_dis = 1;
494 case PHY_INTERFACE_MODE_RGMII_TXID:
495 if (!str)
496 str = "RGMII (TX delay)";
497 port_mode = EXT_GPHY;
498 break;
499 case PHY_INTERFACE_MODE_MII:
500 str = "MII";
501 port_mode = EXT_EPHY;
502 break;
503 case PHY_INTERFACE_MODE_REVMII:
504 str = "Reverse MII";
505 port_mode = EXT_REVMII;
506 break;
507 default:
508 /* All other PHYs: internal and MoCA */
509 goto force_link;
510 }
511
512 /* If the link is down, just disable the interface to conserve power */
513 if (!phydev->link) {
514 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
515 reg &= ~RGMII_MODE_EN;
516 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
517 goto force_link;
518 }
519
520 /* Clear id_mode_dis bit, and the existing port mode, but
521 * make sure we enable the RGMII block for data to pass
522 */
523 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
524 reg &= ~ID_MODE_DIS;
525 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
526 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
527
528 reg |= port_mode | RGMII_MODE_EN;
529 if (id_mode_dis)
530 reg |= ID_MODE_DIS;
531
532 if (phydev->pause) {
533 if (phydev->asym_pause)
534 reg |= TX_PAUSE_EN;
535 reg |= RX_PAUSE_EN;
536 }
537
538 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
539
540 pr_info("Port %d configured for %s\n", port, str);
541
542force_link:
543 /* Force link settings detected from the PHY */
544 reg = SW_OVERRIDE;
545 switch (phydev->speed) {
546 case SPEED_1000:
547 reg |= SPDSTS_1000 << SPEED_SHIFT;
548 break;
549 case SPEED_100:
550 reg |= SPDSTS_100 << SPEED_SHIFT;
551 break;
552 }
553
554 if (phydev->link)
555 reg |= LINK_STS;
556 if (phydev->duplex == DUPLEX_FULL)
557 reg |= DUPLX_MODE;
558
559 core_writel(priv, reg, offset);
560
561 if (!phydev->is_pseudo_fixed_link)
562 p->eee_enabled = b53_eee_init(ds, port, phydev);
563}
564
565static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
566 struct fixed_phy_status *status)
567{
568 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
569 u32 duplex, pause, offset;
570 u32 reg;
571
572 if (priv->type == BCM7445_DEVICE_ID)
573 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
574 else
575 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
576
577 duplex = core_readl(priv, CORE_DUPSTS);
578 pause = core_readl(priv, CORE_PAUSESTS);
579
580 status->link = 0;
581
582 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
583 * which means that we need to force the link at the port override
584 * level to get the data to flow. We do use what the interrupt handler
585 * did determine before.
586 *
587 * For the other ports, we just force the link status, since this is
588 * a fixed PHY device.
589 */
590 if (port == priv->moca_port) {
591 status->link = priv->port_sts[port].link;
592 /* For MoCA interfaces, also force a link down notification
593 * since some version of the user-space daemon (mocad) use
594 * cmd->autoneg to force the link, which messes up the PHY
595 * state machine and make it go in PHY_FORCING state instead.
596 */
597 if (!status->link)
598 netif_carrier_off(ds->ports[port].slave);
599 status->duplex = 1;
600 } else {
601 status->link = 1;
602 status->duplex = !!(duplex & (1 << port));
603 }
604
605 reg = core_readl(priv, offset);
606 reg |= SW_OVERRIDE;
607 if (status->link)
608 reg |= LINK_STS;
609 else
610 reg &= ~LINK_STS;
611 core_writel(priv, reg, offset);
612
613 if ((pause & (1 << port)) &&
614 (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
615 status->asym_pause = 1;
616 status->pause = 1;
617 }
618
619 if (pause & (1 << port))
620 status->pause = 1;
621}
622
623static void bcm_sf2_enable_acb(struct dsa_switch *ds)
624{
625 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
626 u32 reg;
627
628 /* Enable ACB globally */
629 reg = acb_readl(priv, ACB_CONTROL);
630 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
631 acb_writel(priv, reg, ACB_CONTROL);
632 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
633 reg |= ACB_EN | ACB_ALGORITHM;
634 acb_writel(priv, reg, ACB_CONTROL);
635}
636
637static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
638{
639 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
640 unsigned int port;
641
642 bcm_sf2_intr_disable(priv);
643
644 /* Disable all ports physically present including the IMP
645 * port, the other ones have already been disabled during
646 * bcm_sf2_sw_setup
647 */
648 for (port = 0; port < DSA_MAX_PORTS; port++) {
649 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
650 bcm_sf2_port_disable(ds, port, NULL);
651 }
652
653 return 0;
654}
655
656static int bcm_sf2_sw_resume(struct dsa_switch *ds)
657{
658 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
659 unsigned int port;
660 int ret;
661
662 ret = bcm_sf2_sw_rst(priv);
663 if (ret) {
664 pr_err("%s: failed to software reset switch\n", __func__);
665 return ret;
666 }
667
668 if (priv->hw_params.num_gphy == 1)
669 bcm_sf2_gphy_enable_set(ds, true);
670
671 for (port = 0; port < DSA_MAX_PORTS; port++) {
672 if (dsa_is_user_port(ds, port))
673 bcm_sf2_port_setup(ds, port, NULL);
674 else if (dsa_is_cpu_port(ds, port))
675 bcm_sf2_imp_setup(ds, port);
676 }
677
678 bcm_sf2_enable_acb(ds);
679
680 return 0;
681}
682
683static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
684 struct ethtool_wolinfo *wol)
685{
686 struct net_device *p = ds->ports[port].cpu_dp->master;
687 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
688 struct ethtool_wolinfo pwol;
689
690 /* Get the parent device WoL settings */
691 p->ethtool_ops->get_wol(p, &pwol);
692
693 /* Advertise the parent device supported settings */
694 wol->supported = pwol.supported;
695 memset(&wol->sopass, 0, sizeof(wol->sopass));
696
697 if (pwol.wolopts & WAKE_MAGICSECURE)
698 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
699
700 if (priv->wol_ports_mask & (1 << port))
701 wol->wolopts = pwol.wolopts;
702 else
703 wol->wolopts = 0;
704}
705
706static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
707 struct ethtool_wolinfo *wol)
708{
709 struct net_device *p = ds->ports[port].cpu_dp->master;
710 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
711 s8 cpu_port = ds->ports[port].cpu_dp->index;
712 struct ethtool_wolinfo pwol;
713
714 p->ethtool_ops->get_wol(p, &pwol);
715 if (wol->wolopts & ~pwol.supported)
716 return -EINVAL;
717
718 if (wol->wolopts)
719 priv->wol_ports_mask |= (1 << port);
720 else
721 priv->wol_ports_mask &= ~(1 << port);
722
723 /* If we have at least one port enabled, make sure the CPU port
724 * is also enabled. If the CPU port is the last one enabled, we disable
725 * it since this configuration does not make sense.
726 */
727 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
728 priv->wol_ports_mask |= (1 << cpu_port);
729 else
730 priv->wol_ports_mask &= ~(1 << cpu_port);
731
732 return p->ethtool_ops->set_wol(p, wol);
733}
734
735static int bcm_sf2_sw_setup(struct dsa_switch *ds)
736{
737 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
738 unsigned int port;
739
740 /* Enable all valid ports and disable those unused */
741 for (port = 0; port < priv->hw_params.num_ports; port++) {
742 /* IMP port receives special treatment */
743 if (dsa_is_user_port(ds, port))
744 bcm_sf2_port_setup(ds, port, NULL);
745 else if (dsa_is_cpu_port(ds, port))
746 bcm_sf2_imp_setup(ds, port);
747 else
748 bcm_sf2_port_disable(ds, port, NULL);
749 }
750
751 b53_configure_vlan(ds);
752 bcm_sf2_enable_acb(ds);
753
754 return 0;
755}
756
757/* The SWITCH_CORE register space is managed by b53 but operates on a page +
758 * register basis so we need to translate that into an address that the
759 * bus-glue understands.
760 */
761#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
762
763static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
764 u8 *val)
765{
766 struct bcm_sf2_priv *priv = dev->priv;
767
768 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
769
770 return 0;
771}
772
773static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
774 u16 *val)
775{
776 struct bcm_sf2_priv *priv = dev->priv;
777
778 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
779
780 return 0;
781}
782
783static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
784 u32 *val)
785{
786 struct bcm_sf2_priv *priv = dev->priv;
787
788 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
789
790 return 0;
791}
792
793static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
794 u64 *val)
795{
796 struct bcm_sf2_priv *priv = dev->priv;
797
798 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
799
800 return 0;
801}
802
803static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
804 u8 value)
805{
806 struct bcm_sf2_priv *priv = dev->priv;
807
808 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
809
810 return 0;
811}
812
813static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
814 u16 value)
815{
816 struct bcm_sf2_priv *priv = dev->priv;
817
818 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
819
820 return 0;
821}
822
823static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
824 u32 value)
825{
826 struct bcm_sf2_priv *priv = dev->priv;
827
828 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
829
830 return 0;
831}
832
833static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
834 u64 value)
835{
836 struct bcm_sf2_priv *priv = dev->priv;
837
838 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
839
840 return 0;
841}
842
843static const struct b53_io_ops bcm_sf2_io_ops = {
844 .read8 = bcm_sf2_core_read8,
845 .read16 = bcm_sf2_core_read16,
846 .read32 = bcm_sf2_core_read32,
847 .read48 = bcm_sf2_core_read64,
848 .read64 = bcm_sf2_core_read64,
849 .write8 = bcm_sf2_core_write8,
850 .write16 = bcm_sf2_core_write16,
851 .write32 = bcm_sf2_core_write32,
852 .write48 = bcm_sf2_core_write64,
853 .write64 = bcm_sf2_core_write64,
854};
855
856static const struct dsa_switch_ops bcm_sf2_ops = {
857 .get_tag_protocol = b53_get_tag_protocol,
858 .setup = bcm_sf2_sw_setup,
859 .get_strings = b53_get_strings,
860 .get_ethtool_stats = b53_get_ethtool_stats,
861 .get_sset_count = b53_get_sset_count,
862 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
863 .adjust_link = bcm_sf2_sw_adjust_link,
864 .fixed_link_update = bcm_sf2_sw_fixed_link_update,
865 .suspend = bcm_sf2_sw_suspend,
866 .resume = bcm_sf2_sw_resume,
867 .get_wol = bcm_sf2_sw_get_wol,
868 .set_wol = bcm_sf2_sw_set_wol,
869 .port_enable = bcm_sf2_port_setup,
870 .port_disable = bcm_sf2_port_disable,
871 .get_mac_eee = b53_get_mac_eee,
872 .set_mac_eee = b53_set_mac_eee,
873 .port_bridge_join = b53_br_join,
874 .port_bridge_leave = b53_br_leave,
875 .port_stp_state_set = b53_br_set_stp_state,
876 .port_fast_age = b53_br_fast_age,
877 .port_vlan_filtering = b53_vlan_filtering,
878 .port_vlan_prepare = b53_vlan_prepare,
879 .port_vlan_add = b53_vlan_add,
880 .port_vlan_del = b53_vlan_del,
881 .port_fdb_dump = b53_fdb_dump,
882 .port_fdb_add = b53_fdb_add,
883 .port_fdb_del = b53_fdb_del,
884 .get_rxnfc = bcm_sf2_get_rxnfc,
885 .set_rxnfc = bcm_sf2_set_rxnfc,
886 .port_mirror_add = b53_mirror_add,
887 .port_mirror_del = b53_mirror_del,
888};
889
890struct bcm_sf2_of_data {
891 u32 type;
892 const u16 *reg_offsets;
893 unsigned int core_reg_align;
894 unsigned int num_cfp_rules;
895};
896
897/* Register offsets for the SWITCH_REG_* block */
898static const u16 bcm_sf2_7445_reg_offsets[] = {
899 [REG_SWITCH_CNTRL] = 0x00,
900 [REG_SWITCH_STATUS] = 0x04,
901 [REG_DIR_DATA_WRITE] = 0x08,
902 [REG_DIR_DATA_READ] = 0x0C,
903 [REG_SWITCH_REVISION] = 0x18,
904 [REG_PHY_REVISION] = 0x1C,
905 [REG_SPHY_CNTRL] = 0x2C,
906 [REG_RGMII_0_CNTRL] = 0x34,
907 [REG_RGMII_1_CNTRL] = 0x40,
908 [REG_RGMII_2_CNTRL] = 0x4c,
909 [REG_LED_0_CNTRL] = 0x90,
910 [REG_LED_1_CNTRL] = 0x94,
911 [REG_LED_2_CNTRL] = 0x98,
912};
913
914static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
915 .type = BCM7445_DEVICE_ID,
916 .core_reg_align = 0,
917 .reg_offsets = bcm_sf2_7445_reg_offsets,
918 .num_cfp_rules = 256,
919};
920
921static const u16 bcm_sf2_7278_reg_offsets[] = {
922 [REG_SWITCH_CNTRL] = 0x00,
923 [REG_SWITCH_STATUS] = 0x04,
924 [REG_DIR_DATA_WRITE] = 0x08,
925 [REG_DIR_DATA_READ] = 0x0c,
926 [REG_SWITCH_REVISION] = 0x10,
927 [REG_PHY_REVISION] = 0x14,
928 [REG_SPHY_CNTRL] = 0x24,
929 [REG_RGMII_0_CNTRL] = 0xe0,
930 [REG_RGMII_1_CNTRL] = 0xec,
931 [REG_RGMII_2_CNTRL] = 0xf8,
932 [REG_LED_0_CNTRL] = 0x40,
933 [REG_LED_1_CNTRL] = 0x4c,
934 [REG_LED_2_CNTRL] = 0x58,
935};
936
937static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
938 .type = BCM7278_DEVICE_ID,
939 .core_reg_align = 1,
940 .reg_offsets = bcm_sf2_7278_reg_offsets,
941 .num_cfp_rules = 128,
942};
943
944static const struct of_device_id bcm_sf2_of_match[] = {
945 { .compatible = "brcm,bcm7445-switch-v4.0",
946 .data = &bcm_sf2_7445_data
947 },
948 { .compatible = "brcm,bcm7278-switch-v4.0",
949 .data = &bcm_sf2_7278_data
950 },
951 { .compatible = "brcm,bcm7278-switch-v4.8",
952 .data = &bcm_sf2_7278_data
953 },
954 { /* sentinel */ },
955};
956MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
957
958static int bcm_sf2_sw_probe(struct platform_device *pdev)
959{
960 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
961 struct device_node *dn = pdev->dev.of_node;
962 const struct of_device_id *of_id = NULL;
963 const struct bcm_sf2_of_data *data;
964 struct b53_platform_data *pdata;
965 struct dsa_switch_ops *ops;
966 struct bcm_sf2_priv *priv;
967 struct b53_device *dev;
968 struct dsa_switch *ds;
969 void __iomem **base;
970 struct resource *r;
971 unsigned int i;
972 u32 reg, rev;
973 int ret;
974
975 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
976 if (!priv)
977 return -ENOMEM;
978
979 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
980 if (!ops)
981 return -ENOMEM;
982
983 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
984 if (!dev)
985 return -ENOMEM;
986
987 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
988 if (!pdata)
989 return -ENOMEM;
990
991 of_id = of_match_node(bcm_sf2_of_match, dn);
992 if (!of_id || !of_id->data)
993 return -EINVAL;
994
995 data = of_id->data;
996
997 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
998 priv->type = data->type;
999 priv->reg_offsets = data->reg_offsets;
1000 priv->core_reg_align = data->core_reg_align;
1001 priv->num_cfp_rules = data->num_cfp_rules;
1002
1003 /* Auto-detection using standard registers will not work, so
1004 * provide an indication of what kind of device we are for
1005 * b53_common to work with
1006 */
1007 pdata->chip_id = priv->type;
1008 dev->pdata = pdata;
1009
1010 priv->dev = dev;
1011 ds = dev->ds;
1012 ds->ops = &bcm_sf2_ops;
1013
1014 /* Advertise the 8 egress queues */
1015 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1016
1017 dev_set_drvdata(&pdev->dev, priv);
1018
1019 spin_lock_init(&priv->indir_lock);
1020 mutex_init(&priv->stats_mutex);
1021 mutex_init(&priv->cfp.lock);
1022
1023 /* CFP rule #0 cannot be used for specific classifications, flag it as
1024 * permanently used
1025 */
1026 set_bit(0, priv->cfp.used);
1027 set_bit(0, priv->cfp.unique);
1028
1029 bcm_sf2_identify_ports(priv, dn->child);
1030
1031 priv->irq0 = irq_of_parse_and_map(dn, 0);
1032 priv->irq1 = irq_of_parse_and_map(dn, 1);
1033
1034 base = &priv->core;
1035 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1036 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1037 *base = devm_ioremap_resource(&pdev->dev, r);
1038 if (IS_ERR(*base)) {
1039 pr_err("unable to find register: %s\n", reg_names[i]);
1040 return PTR_ERR(*base);
1041 }
1042 base++;
1043 }
1044
1045 ret = bcm_sf2_sw_rst(priv);
1046 if (ret) {
1047 pr_err("unable to software reset switch: %d\n", ret);
1048 return ret;
1049 }
1050
1051 ret = bcm_sf2_mdio_register(ds);
1052 if (ret) {
1053 pr_err("failed to register MDIO bus\n");
1054 return ret;
1055 }
1056
1057 ret = bcm_sf2_cfp_rst(priv);
1058 if (ret) {
1059 pr_err("failed to reset CFP\n");
1060 goto out_mdio;
1061 }
1062
1063 /* Disable all interrupts and request them */
1064 bcm_sf2_intr_disable(priv);
1065
1066 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1067 "switch_0", priv);
1068 if (ret < 0) {
1069 pr_err("failed to request switch_0 IRQ\n");
1070 goto out_mdio;
1071 }
1072
1073 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1074 "switch_1", priv);
1075 if (ret < 0) {
1076 pr_err("failed to request switch_1 IRQ\n");
1077 goto out_mdio;
1078 }
1079
1080 /* Reset the MIB counters */
1081 reg = core_readl(priv, CORE_GMNCFGCFG);
1082 reg |= RST_MIB_CNT;
1083 core_writel(priv, reg, CORE_GMNCFGCFG);
1084 reg &= ~RST_MIB_CNT;
1085 core_writel(priv, reg, CORE_GMNCFGCFG);
1086
1087 /* Get the maximum number of ports for this switch */
1088 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1089 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1090 priv->hw_params.num_ports = DSA_MAX_PORTS;
1091
1092 /* Assume a single GPHY setup if we can't read that property */
1093 if (of_property_read_u32(dn, "brcm,num-gphy",
1094 &priv->hw_params.num_gphy))
1095 priv->hw_params.num_gphy = 1;
1096
1097 rev = reg_readl(priv, REG_SWITCH_REVISION);
1098 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1099 SWITCH_TOP_REV_MASK;
1100 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1101
1102 rev = reg_readl(priv, REG_PHY_REVISION);
1103 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1104
1105 ret = b53_switch_register(dev);
1106 if (ret)
1107 goto out_mdio;
1108
1109 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1110 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1111 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1112 priv->core, priv->irq0, priv->irq1);
1113
1114 return 0;
1115
1116out_mdio:
1117 bcm_sf2_mdio_unregister(priv);
1118 return ret;
1119}
1120
1121static int bcm_sf2_sw_remove(struct platform_device *pdev)
1122{
1123 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1124
1125 /* Disable all ports and interrupts */
1126 priv->wol_ports_mask = 0;
1127 bcm_sf2_sw_suspend(priv->dev->ds);
1128 dsa_unregister_switch(priv->dev->ds);
1129 bcm_sf2_mdio_unregister(priv);
1130
1131 return 0;
1132}
1133
1134static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1135{
1136 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1137
1138 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1139 * successful MDIO bus scan to occur. If we did turn off the GPHY
1140 * before (e.g: port_disable), this will also power it back on.
1141 *
1142 * Do not rely on kexec_in_progress, just power the PHY on.
1143 */
1144 if (priv->hw_params.num_gphy == 1)
1145 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1146}
1147
1148#ifdef CONFIG_PM_SLEEP
1149static int bcm_sf2_suspend(struct device *dev)
1150{
1151 struct platform_device *pdev = to_platform_device(dev);
1152 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1153
1154 return dsa_switch_suspend(priv->dev->ds);
1155}
1156
1157static int bcm_sf2_resume(struct device *dev)
1158{
1159 struct platform_device *pdev = to_platform_device(dev);
1160 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1161
1162 return dsa_switch_resume(priv->dev->ds);
1163}
1164#endif /* CONFIG_PM_SLEEP */
1165
1166static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1167 bcm_sf2_suspend, bcm_sf2_resume);
1168
1169
1170static struct platform_driver bcm_sf2_driver = {
1171 .probe = bcm_sf2_sw_probe,
1172 .remove = bcm_sf2_sw_remove,
1173 .shutdown = bcm_sf2_sw_shutdown,
1174 .driver = {
1175 .name = "brcm-sf2",
1176 .of_match_table = bcm_sf2_of_match,
1177 .pm = &bcm_sf2_pm_ops,
1178 },
1179};
1180module_platform_driver(bcm_sf2_driver);
1181
1182MODULE_AUTHOR("Broadcom Corporation");
1183MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1184MODULE_LICENSE("GPL");
1185MODULE_ALIAS("platform:brcm-sf2");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Broadcom Starfighter 2 DSA switch driver
4 *
5 * Copyright (C) 2014, Broadcom Corporation
6 */
7
8#include <linux/list.h>
9#include <linux/module.h>
10#include <linux/netdevice.h>
11#include <linux/interrupt.h>
12#include <linux/platform_device.h>
13#include <linux/phy.h>
14#include <linux/phy_fixed.h>
15#include <linux/phylink.h>
16#include <linux/mii.h>
17#include <linux/of.h>
18#include <linux/of_irq.h>
19#include <linux/of_address.h>
20#include <linux/of_net.h>
21#include <linux/of_mdio.h>
22#include <net/dsa.h>
23#include <linux/ethtool.h>
24#include <linux/if_bridge.h>
25#include <linux/brcmphy.h>
26#include <linux/etherdevice.h>
27#include <linux/platform_data/b53.h>
28
29#include "bcm_sf2.h"
30#include "bcm_sf2_regs.h"
31#include "b53/b53_priv.h"
32#include "b53/b53_regs.h"
33
34static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
35{
36 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
37 unsigned int i;
38 u32 reg, offset;
39
40 /* Enable the port memories */
41 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
42 reg &= ~P_TXQ_PSM_VDD(port);
43 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
44
45 /* Enable forwarding */
46 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
47
48 /* Enable IMP port in dumb mode */
49 reg = core_readl(priv, CORE_SWITCH_CTRL);
50 reg |= MII_DUMB_FWDG_EN;
51 core_writel(priv, reg, CORE_SWITCH_CTRL);
52
53 /* Configure Traffic Class to QoS mapping, allow each priority to map
54 * to a different queue number
55 */
56 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
57 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
58 reg |= i << (PRT_TO_QID_SHIFT * i);
59 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
60
61 b53_brcm_hdr_setup(ds, port);
62
63 if (port == 8) {
64 if (priv->type == BCM7445_DEVICE_ID)
65 offset = CORE_STS_OVERRIDE_IMP;
66 else
67 offset = CORE_STS_OVERRIDE_IMP2;
68
69 /* Force link status for IMP port */
70 reg = core_readl(priv, offset);
71 reg |= (MII_SW_OR | LINK_STS);
72 reg &= ~GMII_SPEED_UP_2G;
73 core_writel(priv, reg, offset);
74
75 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
76 reg = core_readl(priv, CORE_IMP_CTL);
77 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
78 reg &= ~(RX_DIS | TX_DIS);
79 core_writel(priv, reg, CORE_IMP_CTL);
80 } else {
81 reg = core_readl(priv, CORE_G_PCTL_PORT(port));
82 reg &= ~(RX_DIS | TX_DIS);
83 core_writel(priv, reg, CORE_G_PCTL_PORT(port));
84 }
85}
86
87static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
88{
89 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
90 u32 reg;
91
92 reg = reg_readl(priv, REG_SPHY_CNTRL);
93 if (enable) {
94 reg |= PHY_RESET;
95 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
96 reg_writel(priv, reg, REG_SPHY_CNTRL);
97 udelay(21);
98 reg = reg_readl(priv, REG_SPHY_CNTRL);
99 reg &= ~PHY_RESET;
100 } else {
101 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
102 reg_writel(priv, reg, REG_SPHY_CNTRL);
103 mdelay(1);
104 reg |= CK25_DIS;
105 }
106 reg_writel(priv, reg, REG_SPHY_CNTRL);
107
108 /* Use PHY-driven LED signaling */
109 if (!enable) {
110 reg = reg_readl(priv, REG_LED_CNTRL(0));
111 reg |= SPDLNK_SRC_SEL;
112 reg_writel(priv, reg, REG_LED_CNTRL(0));
113 }
114}
115
116static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
117 int port)
118{
119 unsigned int off;
120
121 switch (port) {
122 case 7:
123 off = P7_IRQ_OFF;
124 break;
125 case 0:
126 /* Port 0 interrupts are located on the first bank */
127 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
128 return;
129 default:
130 off = P_IRQ_OFF(port);
131 break;
132 }
133
134 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
135}
136
137static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
138 int port)
139{
140 unsigned int off;
141
142 switch (port) {
143 case 7:
144 off = P7_IRQ_OFF;
145 break;
146 case 0:
147 /* Port 0 interrupts are located on the first bank */
148 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
149 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
150 return;
151 default:
152 off = P_IRQ_OFF(port);
153 break;
154 }
155
156 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
157 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
158}
159
160static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
161 struct phy_device *phy)
162{
163 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
164 unsigned int i;
165 u32 reg;
166
167 if (!dsa_is_user_port(ds, port))
168 return 0;
169
170 /* Clear the memory power down */
171 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
172 reg &= ~P_TXQ_PSM_VDD(port);
173 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
174
175 /* Enable learning */
176 reg = core_readl(priv, CORE_DIS_LEARN);
177 reg &= ~BIT(port);
178 core_writel(priv, reg, CORE_DIS_LEARN);
179
180 /* Enable Broadcom tags for that port if requested */
181 if (priv->brcm_tag_mask & BIT(port)) {
182 b53_brcm_hdr_setup(ds, port);
183
184 /* Disable learning on ASP port */
185 if (port == 7) {
186 reg = core_readl(priv, CORE_DIS_LEARN);
187 reg |= BIT(port);
188 core_writel(priv, reg, CORE_DIS_LEARN);
189 }
190 }
191
192 /* Configure Traffic Class to QoS mapping, allow each priority to map
193 * to a different queue number
194 */
195 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
196 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
197 reg |= i << (PRT_TO_QID_SHIFT * i);
198 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
199
200 /* Re-enable the GPHY and re-apply workarounds */
201 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
202 bcm_sf2_gphy_enable_set(ds, true);
203 if (phy) {
204 /* if phy_stop() has been called before, phy
205 * will be in halted state, and phy_start()
206 * will call resume.
207 *
208 * the resume path does not configure back
209 * autoneg settings, and since we hard reset
210 * the phy manually here, we need to reset the
211 * state machine also.
212 */
213 phy->state = PHY_READY;
214 phy_init_hw(phy);
215 }
216 }
217
218 /* Enable MoCA port interrupts to get notified */
219 if (port == priv->moca_port)
220 bcm_sf2_port_intr_enable(priv, port);
221
222 /* Set per-queue pause threshold to 32 */
223 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
224
225 /* Set ACB threshold to 24 */
226 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
227 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
228 SF2_NUM_EGRESS_QUEUES + i));
229 reg &= ~XOFF_THRESHOLD_MASK;
230 reg |= 24;
231 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
232 SF2_NUM_EGRESS_QUEUES + i));
233 }
234
235 return b53_enable_port(ds, port, phy);
236}
237
238static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
239{
240 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
241 u32 reg;
242
243 /* Disable learning while in WoL mode */
244 if (priv->wol_ports_mask & (1 << port)) {
245 reg = core_readl(priv, CORE_DIS_LEARN);
246 reg |= BIT(port);
247 core_writel(priv, reg, CORE_DIS_LEARN);
248 return;
249 }
250
251 if (port == priv->moca_port)
252 bcm_sf2_port_intr_disable(priv, port);
253
254 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
255 bcm_sf2_gphy_enable_set(ds, false);
256
257 b53_disable_port(ds, port);
258
259 /* Power down the port memory */
260 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
261 reg |= P_TXQ_PSM_VDD(port);
262 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
263}
264
265
266static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
267 int regnum, u16 val)
268{
269 int ret = 0;
270 u32 reg;
271
272 reg = reg_readl(priv, REG_SWITCH_CNTRL);
273 reg |= MDIO_MASTER_SEL;
274 reg_writel(priv, reg, REG_SWITCH_CNTRL);
275
276 /* Page << 8 | offset */
277 reg = 0x70;
278 reg <<= 2;
279 core_writel(priv, addr, reg);
280
281 /* Page << 8 | offset */
282 reg = 0x80 << 8 | regnum << 1;
283 reg <<= 2;
284
285 if (op)
286 ret = core_readl(priv, reg);
287 else
288 core_writel(priv, val, reg);
289
290 reg = reg_readl(priv, REG_SWITCH_CNTRL);
291 reg &= ~MDIO_MASTER_SEL;
292 reg_writel(priv, reg, REG_SWITCH_CNTRL);
293
294 return ret & 0xffff;
295}
296
297static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
298{
299 struct bcm_sf2_priv *priv = bus->priv;
300
301 /* Intercept reads from Broadcom pseudo-PHY address, else, send
302 * them to our master MDIO bus controller
303 */
304 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
305 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
306 else
307 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
308}
309
310static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
311 u16 val)
312{
313 struct bcm_sf2_priv *priv = bus->priv;
314
315 /* Intercept writes to the Broadcom pseudo-PHY address, else,
316 * send them to our master MDIO bus controller
317 */
318 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
319 return bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
320 else
321 return mdiobus_write_nested(priv->master_mii_bus, addr,
322 regnum, val);
323}
324
325static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
326{
327 struct dsa_switch *ds = dev_id;
328 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
329
330 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
331 ~priv->irq0_mask;
332 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
333
334 return IRQ_HANDLED;
335}
336
337static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
338{
339 struct dsa_switch *ds = dev_id;
340 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
341
342 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
343 ~priv->irq1_mask;
344 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
345
346 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
347 priv->port_sts[7].link = true;
348 dsa_port_phylink_mac_change(ds, 7, true);
349 }
350 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
351 priv->port_sts[7].link = false;
352 dsa_port_phylink_mac_change(ds, 7, false);
353 }
354
355 return IRQ_HANDLED;
356}
357
358static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
359{
360 unsigned int timeout = 1000;
361 u32 reg;
362 int ret;
363
364 /* The watchdog reset does not work on 7278, we need to hit the
365 * "external" reset line through the reset controller.
366 */
367 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev)) {
368 ret = reset_control_assert(priv->rcdev);
369 if (ret)
370 return ret;
371
372 return reset_control_deassert(priv->rcdev);
373 }
374
375 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
376 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
377 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
378
379 do {
380 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
381 if (!(reg & SOFTWARE_RESET))
382 break;
383
384 usleep_range(1000, 2000);
385 } while (timeout-- > 0);
386
387 if (timeout == 0)
388 return -ETIMEDOUT;
389
390 return 0;
391}
392
393static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
394{
395 intrl2_0_mask_set(priv, 0xffffffff);
396 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
397 intrl2_1_mask_set(priv, 0xffffffff);
398 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
399}
400
401static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
402 struct device_node *dn)
403{
404 struct device_node *port;
405 unsigned int port_num;
406 phy_interface_t mode;
407 int err;
408
409 priv->moca_port = -1;
410
411 for_each_available_child_of_node(dn, port) {
412 if (of_property_read_u32(port, "reg", &port_num))
413 continue;
414
415 /* Internal PHYs get assigned a specific 'phy-mode' property
416 * value: "internal" to help flag them before MDIO probing
417 * has completed, since they might be turned off at that
418 * time
419 */
420 err = of_get_phy_mode(port, &mode);
421 if (err)
422 continue;
423
424 if (mode == PHY_INTERFACE_MODE_INTERNAL)
425 priv->int_phy_mask |= 1 << port_num;
426
427 if (mode == PHY_INTERFACE_MODE_MOCA)
428 priv->moca_port = port_num;
429
430 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
431 priv->brcm_tag_mask |= 1 << port_num;
432 }
433}
434
435static int bcm_sf2_mdio_register(struct dsa_switch *ds)
436{
437 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
438 struct device_node *dn;
439 static int index;
440 int err;
441
442 /* Find our integrated MDIO bus node */
443 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
444 priv->master_mii_bus = of_mdio_find_bus(dn);
445 if (!priv->master_mii_bus)
446 return -EPROBE_DEFER;
447
448 get_device(&priv->master_mii_bus->dev);
449 priv->master_mii_dn = dn;
450
451 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
452 if (!priv->slave_mii_bus)
453 return -ENOMEM;
454
455 priv->slave_mii_bus->priv = priv;
456 priv->slave_mii_bus->name = "sf2 slave mii";
457 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
458 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
459 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
460 index++);
461 priv->slave_mii_bus->dev.of_node = dn;
462
463 /* Include the pseudo-PHY address to divert reads towards our
464 * workaround. This is only required for 7445D0, since 7445E0
465 * disconnects the internal switch pseudo-PHY such that we can use the
466 * regular SWITCH_MDIO master controller instead.
467 *
468 * Here we flag the pseudo PHY as needing special treatment and would
469 * otherwise make all other PHY read/writes go to the master MDIO bus
470 * controller that comes with this switch backed by the "mdio-unimac"
471 * driver.
472 */
473 if (of_machine_is_compatible("brcm,bcm7445d0"))
474 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
475 else
476 priv->indir_phy_mask = 0;
477
478 ds->phys_mii_mask = priv->indir_phy_mask;
479 ds->slave_mii_bus = priv->slave_mii_bus;
480 priv->slave_mii_bus->parent = ds->dev->parent;
481 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
482
483 err = mdiobus_register(priv->slave_mii_bus);
484 if (err && dn)
485 of_node_put(dn);
486
487 return err;
488}
489
490static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
491{
492 mdiobus_unregister(priv->slave_mii_bus);
493 of_node_put(priv->master_mii_dn);
494}
495
496static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
497{
498 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
499
500 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
501 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
502 * the REG_PHY_REVISION register layout is.
503 */
504
505 return priv->hw_params.gphy_rev;
506}
507
508static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
509 unsigned long *supported,
510 struct phylink_link_state *state)
511{
512 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
513 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
514
515 if (!phy_interface_mode_is_rgmii(state->interface) &&
516 state->interface != PHY_INTERFACE_MODE_MII &&
517 state->interface != PHY_INTERFACE_MODE_REVMII &&
518 state->interface != PHY_INTERFACE_MODE_GMII &&
519 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
520 state->interface != PHY_INTERFACE_MODE_MOCA) {
521 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
522 if (port != core_readl(priv, CORE_IMP0_PRT_ID))
523 dev_err(ds->dev,
524 "Unsupported interface: %d for port %d\n",
525 state->interface, port);
526 return;
527 }
528
529 /* Allow all the expected bits */
530 phylink_set(mask, Autoneg);
531 phylink_set_port_modes(mask);
532 phylink_set(mask, Pause);
533 phylink_set(mask, Asym_Pause);
534
535 /* With the exclusion of MII and Reverse MII, we support Gigabit,
536 * including Half duplex
537 */
538 if (state->interface != PHY_INTERFACE_MODE_MII &&
539 state->interface != PHY_INTERFACE_MODE_REVMII) {
540 phylink_set(mask, 1000baseT_Full);
541 phylink_set(mask, 1000baseT_Half);
542 }
543
544 phylink_set(mask, 10baseT_Half);
545 phylink_set(mask, 10baseT_Full);
546 phylink_set(mask, 100baseT_Half);
547 phylink_set(mask, 100baseT_Full);
548
549 bitmap_and(supported, supported, mask,
550 __ETHTOOL_LINK_MODE_MASK_NBITS);
551 bitmap_and(state->advertising, state->advertising, mask,
552 __ETHTOOL_LINK_MODE_MASK_NBITS);
553}
554
555static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
556 unsigned int mode,
557 const struct phylink_link_state *state)
558{
559 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
560 u32 id_mode_dis = 0, port_mode;
561 u32 reg;
562
563 if (port == core_readl(priv, CORE_IMP0_PRT_ID))
564 return;
565
566 switch (state->interface) {
567 case PHY_INTERFACE_MODE_RGMII:
568 id_mode_dis = 1;
569 fallthrough;
570 case PHY_INTERFACE_MODE_RGMII_TXID:
571 port_mode = EXT_GPHY;
572 break;
573 case PHY_INTERFACE_MODE_MII:
574 port_mode = EXT_EPHY;
575 break;
576 case PHY_INTERFACE_MODE_REVMII:
577 port_mode = EXT_REVMII;
578 break;
579 default:
580 /* Nothing required for all other PHYs: internal and MoCA */
581 return;
582 }
583
584 /* Clear id_mode_dis bit, and the existing port mode, let
585 * RGMII_MODE_EN bet set by mac_link_{up,down}
586 */
587 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
588 reg &= ~ID_MODE_DIS;
589 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
590
591 reg |= port_mode;
592 if (id_mode_dis)
593 reg |= ID_MODE_DIS;
594
595 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
596}
597
598static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
599 phy_interface_t interface, bool link)
600{
601 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
602 u32 reg;
603
604 if (!phy_interface_mode_is_rgmii(interface) &&
605 interface != PHY_INTERFACE_MODE_MII &&
606 interface != PHY_INTERFACE_MODE_REVMII)
607 return;
608
609 /* If the link is down, just disable the interface to conserve power */
610 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
611 if (link)
612 reg |= RGMII_MODE_EN;
613 else
614 reg &= ~RGMII_MODE_EN;
615 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
616}
617
618static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
619 unsigned int mode,
620 phy_interface_t interface)
621{
622 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
623 u32 reg, offset;
624
625 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
626 if (priv->type == BCM7445_DEVICE_ID)
627 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
628 else
629 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
630
631 reg = core_readl(priv, offset);
632 reg &= ~LINK_STS;
633 core_writel(priv, reg, offset);
634 }
635
636 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
637}
638
639static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
640 unsigned int mode,
641 phy_interface_t interface,
642 struct phy_device *phydev,
643 int speed, int duplex,
644 bool tx_pause, bool rx_pause)
645{
646 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
647 struct ethtool_eee *p = &priv->dev->ports[port].eee;
648 u32 reg, offset;
649
650 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
651
652 if (port != core_readl(priv, CORE_IMP0_PRT_ID)) {
653 if (priv->type == BCM7445_DEVICE_ID)
654 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
655 else
656 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
657
658 if (interface == PHY_INTERFACE_MODE_RGMII ||
659 interface == PHY_INTERFACE_MODE_RGMII_TXID ||
660 interface == PHY_INTERFACE_MODE_MII ||
661 interface == PHY_INTERFACE_MODE_REVMII) {
662 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
663 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
664
665 if (tx_pause)
666 reg |= TX_PAUSE_EN;
667 if (rx_pause)
668 reg |= RX_PAUSE_EN;
669
670 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
671 }
672
673 reg = SW_OVERRIDE | LINK_STS;
674 switch (speed) {
675 case SPEED_1000:
676 reg |= SPDSTS_1000 << SPEED_SHIFT;
677 break;
678 case SPEED_100:
679 reg |= SPDSTS_100 << SPEED_SHIFT;
680 break;
681 }
682
683 if (duplex == DUPLEX_FULL)
684 reg |= DUPLX_MODE;
685
686 core_writel(priv, reg, offset);
687 }
688
689 if (mode == MLO_AN_PHY && phydev)
690 p->eee_enabled = b53_eee_init(ds, port, phydev);
691}
692
693static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
694 struct phylink_link_state *status)
695{
696 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
697
698 status->link = false;
699
700 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
701 * which means that we need to force the link at the port override
702 * level to get the data to flow. We do use what the interrupt handler
703 * did determine before.
704 *
705 * For the other ports, we just force the link status, since this is
706 * a fixed PHY device.
707 */
708 if (port == priv->moca_port) {
709 status->link = priv->port_sts[port].link;
710 /* For MoCA interfaces, also force a link down notification
711 * since some version of the user-space daemon (mocad) use
712 * cmd->autoneg to force the link, which messes up the PHY
713 * state machine and make it go in PHY_FORCING state instead.
714 */
715 if (!status->link)
716 netif_carrier_off(dsa_to_port(ds, port)->slave);
717 status->duplex = DUPLEX_FULL;
718 } else {
719 status->link = true;
720 }
721}
722
723static void bcm_sf2_enable_acb(struct dsa_switch *ds)
724{
725 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
726 u32 reg;
727
728 /* Enable ACB globally */
729 reg = acb_readl(priv, ACB_CONTROL);
730 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
731 acb_writel(priv, reg, ACB_CONTROL);
732 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
733 reg |= ACB_EN | ACB_ALGORITHM;
734 acb_writel(priv, reg, ACB_CONTROL);
735}
736
737static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
738{
739 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
740 unsigned int port;
741
742 bcm_sf2_intr_disable(priv);
743
744 /* Disable all ports physically present including the IMP
745 * port, the other ones have already been disabled during
746 * bcm_sf2_sw_setup
747 */
748 for (port = 0; port < ds->num_ports; port++) {
749 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
750 bcm_sf2_port_disable(ds, port);
751 }
752
753 return 0;
754}
755
756static int bcm_sf2_sw_resume(struct dsa_switch *ds)
757{
758 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
759 int ret;
760
761 ret = bcm_sf2_sw_rst(priv);
762 if (ret) {
763 pr_err("%s: failed to software reset switch\n", __func__);
764 return ret;
765 }
766
767 ret = bcm_sf2_cfp_resume(ds);
768 if (ret)
769 return ret;
770
771 if (priv->hw_params.num_gphy == 1)
772 bcm_sf2_gphy_enable_set(ds, true);
773
774 ds->ops->setup(ds);
775
776 return 0;
777}
778
779static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
780 struct ethtool_wolinfo *wol)
781{
782 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
783 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
784 struct ethtool_wolinfo pwol = { };
785
786 /* Get the parent device WoL settings */
787 if (p->ethtool_ops->get_wol)
788 p->ethtool_ops->get_wol(p, &pwol);
789
790 /* Advertise the parent device supported settings */
791 wol->supported = pwol.supported;
792 memset(&wol->sopass, 0, sizeof(wol->sopass));
793
794 if (pwol.wolopts & WAKE_MAGICSECURE)
795 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
796
797 if (priv->wol_ports_mask & (1 << port))
798 wol->wolopts = pwol.wolopts;
799 else
800 wol->wolopts = 0;
801}
802
803static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
804 struct ethtool_wolinfo *wol)
805{
806 struct net_device *p = dsa_to_port(ds, port)->cpu_dp->master;
807 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
808 s8 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
809 struct ethtool_wolinfo pwol = { };
810
811 if (p->ethtool_ops->get_wol)
812 p->ethtool_ops->get_wol(p, &pwol);
813 if (wol->wolopts & ~pwol.supported)
814 return -EINVAL;
815
816 if (wol->wolopts)
817 priv->wol_ports_mask |= (1 << port);
818 else
819 priv->wol_ports_mask &= ~(1 << port);
820
821 /* If we have at least one port enabled, make sure the CPU port
822 * is also enabled. If the CPU port is the last one enabled, we disable
823 * it since this configuration does not make sense.
824 */
825 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
826 priv->wol_ports_mask |= (1 << cpu_port);
827 else
828 priv->wol_ports_mask &= ~(1 << cpu_port);
829
830 return p->ethtool_ops->set_wol(p, wol);
831}
832
833static int bcm_sf2_sw_setup(struct dsa_switch *ds)
834{
835 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
836 unsigned int port;
837
838 /* Enable all valid ports and disable those unused */
839 for (port = 0; port < priv->hw_params.num_ports; port++) {
840 /* IMP port receives special treatment */
841 if (dsa_is_user_port(ds, port))
842 bcm_sf2_port_setup(ds, port, NULL);
843 else if (dsa_is_cpu_port(ds, port))
844 bcm_sf2_imp_setup(ds, port);
845 else
846 bcm_sf2_port_disable(ds, port);
847 }
848
849 b53_configure_vlan(ds);
850 bcm_sf2_enable_acb(ds);
851
852 return 0;
853}
854
855/* The SWITCH_CORE register space is managed by b53 but operates on a page +
856 * register basis so we need to translate that into an address that the
857 * bus-glue understands.
858 */
859#define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
860
861static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
862 u8 *val)
863{
864 struct bcm_sf2_priv *priv = dev->priv;
865
866 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
867
868 return 0;
869}
870
871static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
872 u16 *val)
873{
874 struct bcm_sf2_priv *priv = dev->priv;
875
876 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
877
878 return 0;
879}
880
881static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
882 u32 *val)
883{
884 struct bcm_sf2_priv *priv = dev->priv;
885
886 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
887
888 return 0;
889}
890
891static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
892 u64 *val)
893{
894 struct bcm_sf2_priv *priv = dev->priv;
895
896 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
897
898 return 0;
899}
900
901static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
902 u8 value)
903{
904 struct bcm_sf2_priv *priv = dev->priv;
905
906 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
907
908 return 0;
909}
910
911static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
912 u16 value)
913{
914 struct bcm_sf2_priv *priv = dev->priv;
915
916 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
917
918 return 0;
919}
920
921static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
922 u32 value)
923{
924 struct bcm_sf2_priv *priv = dev->priv;
925
926 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
927
928 return 0;
929}
930
931static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
932 u64 value)
933{
934 struct bcm_sf2_priv *priv = dev->priv;
935
936 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
937
938 return 0;
939}
940
941static const struct b53_io_ops bcm_sf2_io_ops = {
942 .read8 = bcm_sf2_core_read8,
943 .read16 = bcm_sf2_core_read16,
944 .read32 = bcm_sf2_core_read32,
945 .read48 = bcm_sf2_core_read64,
946 .read64 = bcm_sf2_core_read64,
947 .write8 = bcm_sf2_core_write8,
948 .write16 = bcm_sf2_core_write16,
949 .write32 = bcm_sf2_core_write32,
950 .write48 = bcm_sf2_core_write64,
951 .write64 = bcm_sf2_core_write64,
952};
953
954static void bcm_sf2_sw_get_strings(struct dsa_switch *ds, int port,
955 u32 stringset, uint8_t *data)
956{
957 int cnt = b53_get_sset_count(ds, port, stringset);
958
959 b53_get_strings(ds, port, stringset, data);
960 bcm_sf2_cfp_get_strings(ds, port, stringset,
961 data + cnt * ETH_GSTRING_LEN);
962}
963
964static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds, int port,
965 uint64_t *data)
966{
967 int cnt = b53_get_sset_count(ds, port, ETH_SS_STATS);
968
969 b53_get_ethtool_stats(ds, port, data);
970 bcm_sf2_cfp_get_ethtool_stats(ds, port, data + cnt);
971}
972
973static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds, int port,
974 int sset)
975{
976 int cnt = b53_get_sset_count(ds, port, sset);
977
978 if (cnt < 0)
979 return cnt;
980
981 cnt += bcm_sf2_cfp_get_sset_count(ds, port, sset);
982
983 return cnt;
984}
985
986static const struct dsa_switch_ops bcm_sf2_ops = {
987 .get_tag_protocol = b53_get_tag_protocol,
988 .setup = bcm_sf2_sw_setup,
989 .get_strings = bcm_sf2_sw_get_strings,
990 .get_ethtool_stats = bcm_sf2_sw_get_ethtool_stats,
991 .get_sset_count = bcm_sf2_sw_get_sset_count,
992 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
993 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
994 .phylink_validate = bcm_sf2_sw_validate,
995 .phylink_mac_config = bcm_sf2_sw_mac_config,
996 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
997 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
998 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
999 .suspend = bcm_sf2_sw_suspend,
1000 .resume = bcm_sf2_sw_resume,
1001 .get_wol = bcm_sf2_sw_get_wol,
1002 .set_wol = bcm_sf2_sw_set_wol,
1003 .port_enable = bcm_sf2_port_setup,
1004 .port_disable = bcm_sf2_port_disable,
1005 .get_mac_eee = b53_get_mac_eee,
1006 .set_mac_eee = b53_set_mac_eee,
1007 .port_bridge_join = b53_br_join,
1008 .port_bridge_leave = b53_br_leave,
1009 .port_stp_state_set = b53_br_set_stp_state,
1010 .port_fast_age = b53_br_fast_age,
1011 .port_vlan_filtering = b53_vlan_filtering,
1012 .port_vlan_prepare = b53_vlan_prepare,
1013 .port_vlan_add = b53_vlan_add,
1014 .port_vlan_del = b53_vlan_del,
1015 .port_fdb_dump = b53_fdb_dump,
1016 .port_fdb_add = b53_fdb_add,
1017 .port_fdb_del = b53_fdb_del,
1018 .get_rxnfc = bcm_sf2_get_rxnfc,
1019 .set_rxnfc = bcm_sf2_set_rxnfc,
1020 .port_mirror_add = b53_mirror_add,
1021 .port_mirror_del = b53_mirror_del,
1022 .port_mdb_prepare = b53_mdb_prepare,
1023 .port_mdb_add = b53_mdb_add,
1024 .port_mdb_del = b53_mdb_del,
1025};
1026
1027struct bcm_sf2_of_data {
1028 u32 type;
1029 const u16 *reg_offsets;
1030 unsigned int core_reg_align;
1031 unsigned int num_cfp_rules;
1032};
1033
1034/* Register offsets for the SWITCH_REG_* block */
1035static const u16 bcm_sf2_7445_reg_offsets[] = {
1036 [REG_SWITCH_CNTRL] = 0x00,
1037 [REG_SWITCH_STATUS] = 0x04,
1038 [REG_DIR_DATA_WRITE] = 0x08,
1039 [REG_DIR_DATA_READ] = 0x0C,
1040 [REG_SWITCH_REVISION] = 0x18,
1041 [REG_PHY_REVISION] = 0x1C,
1042 [REG_SPHY_CNTRL] = 0x2C,
1043 [REG_RGMII_0_CNTRL] = 0x34,
1044 [REG_RGMII_1_CNTRL] = 0x40,
1045 [REG_RGMII_2_CNTRL] = 0x4c,
1046 [REG_LED_0_CNTRL] = 0x90,
1047 [REG_LED_1_CNTRL] = 0x94,
1048 [REG_LED_2_CNTRL] = 0x98,
1049};
1050
1051static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
1052 .type = BCM7445_DEVICE_ID,
1053 .core_reg_align = 0,
1054 .reg_offsets = bcm_sf2_7445_reg_offsets,
1055 .num_cfp_rules = 256,
1056};
1057
1058static const u16 bcm_sf2_7278_reg_offsets[] = {
1059 [REG_SWITCH_CNTRL] = 0x00,
1060 [REG_SWITCH_STATUS] = 0x04,
1061 [REG_DIR_DATA_WRITE] = 0x08,
1062 [REG_DIR_DATA_READ] = 0x0c,
1063 [REG_SWITCH_REVISION] = 0x10,
1064 [REG_PHY_REVISION] = 0x14,
1065 [REG_SPHY_CNTRL] = 0x24,
1066 [REG_RGMII_0_CNTRL] = 0xe0,
1067 [REG_RGMII_1_CNTRL] = 0xec,
1068 [REG_RGMII_2_CNTRL] = 0xf8,
1069 [REG_LED_0_CNTRL] = 0x40,
1070 [REG_LED_1_CNTRL] = 0x4c,
1071 [REG_LED_2_CNTRL] = 0x58,
1072};
1073
1074static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
1075 .type = BCM7278_DEVICE_ID,
1076 .core_reg_align = 1,
1077 .reg_offsets = bcm_sf2_7278_reg_offsets,
1078 .num_cfp_rules = 128,
1079};
1080
1081static const struct of_device_id bcm_sf2_of_match[] = {
1082 { .compatible = "brcm,bcm7445-switch-v4.0",
1083 .data = &bcm_sf2_7445_data
1084 },
1085 { .compatible = "brcm,bcm7278-switch-v4.0",
1086 .data = &bcm_sf2_7278_data
1087 },
1088 { .compatible = "brcm,bcm7278-switch-v4.8",
1089 .data = &bcm_sf2_7278_data
1090 },
1091 { /* sentinel */ },
1092};
1093MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1094
1095static int bcm_sf2_sw_probe(struct platform_device *pdev)
1096{
1097 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1098 struct device_node *dn = pdev->dev.of_node;
1099 const struct of_device_id *of_id = NULL;
1100 const struct bcm_sf2_of_data *data;
1101 struct b53_platform_data *pdata;
1102 struct dsa_switch_ops *ops;
1103 struct device_node *ports;
1104 struct bcm_sf2_priv *priv;
1105 struct b53_device *dev;
1106 struct dsa_switch *ds;
1107 void __iomem **base;
1108 unsigned int i;
1109 u32 reg, rev;
1110 int ret;
1111
1112 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1113 if (!priv)
1114 return -ENOMEM;
1115
1116 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1117 if (!ops)
1118 return -ENOMEM;
1119
1120 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1121 if (!dev)
1122 return -ENOMEM;
1123
1124 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1125 if (!pdata)
1126 return -ENOMEM;
1127
1128 of_id = of_match_node(bcm_sf2_of_match, dn);
1129 if (!of_id || !of_id->data)
1130 return -EINVAL;
1131
1132 data = of_id->data;
1133
1134 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1135 priv->type = data->type;
1136 priv->reg_offsets = data->reg_offsets;
1137 priv->core_reg_align = data->core_reg_align;
1138 priv->num_cfp_rules = data->num_cfp_rules;
1139
1140 priv->rcdev = devm_reset_control_get_optional_exclusive(&pdev->dev,
1141 "switch");
1142 if (PTR_ERR(priv->rcdev) == -EPROBE_DEFER)
1143 return PTR_ERR(priv->rcdev);
1144
1145 /* Auto-detection using standard registers will not work, so
1146 * provide an indication of what kind of device we are for
1147 * b53_common to work with
1148 */
1149 pdata->chip_id = priv->type;
1150 dev->pdata = pdata;
1151
1152 priv->dev = dev;
1153 ds = dev->ds;
1154 ds->ops = &bcm_sf2_ops;
1155
1156 /* Advertise the 8 egress queues */
1157 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1158
1159 dev_set_drvdata(&pdev->dev, priv);
1160
1161 spin_lock_init(&priv->indir_lock);
1162 mutex_init(&priv->cfp.lock);
1163 INIT_LIST_HEAD(&priv->cfp.rules_list);
1164
1165 /* CFP rule #0 cannot be used for specific classifications, flag it as
1166 * permanently used
1167 */
1168 set_bit(0, priv->cfp.used);
1169 set_bit(0, priv->cfp.unique);
1170
1171 /* Balance of_node_put() done by of_find_node_by_name() */
1172 of_node_get(dn);
1173 ports = of_find_node_by_name(dn, "ports");
1174 if (ports) {
1175 bcm_sf2_identify_ports(priv, ports);
1176 of_node_put(ports);
1177 }
1178
1179 priv->irq0 = irq_of_parse_and_map(dn, 0);
1180 priv->irq1 = irq_of_parse_and_map(dn, 1);
1181
1182 base = &priv->core;
1183 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1184 *base = devm_platform_ioremap_resource(pdev, i);
1185 if (IS_ERR(*base)) {
1186 pr_err("unable to find register: %s\n", reg_names[i]);
1187 return PTR_ERR(*base);
1188 }
1189 base++;
1190 }
1191
1192 ret = bcm_sf2_sw_rst(priv);
1193 if (ret) {
1194 pr_err("unable to software reset switch: %d\n", ret);
1195 return ret;
1196 }
1197
1198 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1199
1200 ret = bcm_sf2_mdio_register(ds);
1201 if (ret) {
1202 pr_err("failed to register MDIO bus\n");
1203 return ret;
1204 }
1205
1206 bcm_sf2_gphy_enable_set(priv->dev->ds, false);
1207
1208 ret = bcm_sf2_cfp_rst(priv);
1209 if (ret) {
1210 pr_err("failed to reset CFP\n");
1211 goto out_mdio;
1212 }
1213
1214 /* Disable all interrupts and request them */
1215 bcm_sf2_intr_disable(priv);
1216
1217 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1218 "switch_0", ds);
1219 if (ret < 0) {
1220 pr_err("failed to request switch_0 IRQ\n");
1221 goto out_mdio;
1222 }
1223
1224 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1225 "switch_1", ds);
1226 if (ret < 0) {
1227 pr_err("failed to request switch_1 IRQ\n");
1228 goto out_mdio;
1229 }
1230
1231 /* Reset the MIB counters */
1232 reg = core_readl(priv, CORE_GMNCFGCFG);
1233 reg |= RST_MIB_CNT;
1234 core_writel(priv, reg, CORE_GMNCFGCFG);
1235 reg &= ~RST_MIB_CNT;
1236 core_writel(priv, reg, CORE_GMNCFGCFG);
1237
1238 /* Get the maximum number of ports for this switch */
1239 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1240 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1241 priv->hw_params.num_ports = DSA_MAX_PORTS;
1242
1243 /* Assume a single GPHY setup if we can't read that property */
1244 if (of_property_read_u32(dn, "brcm,num-gphy",
1245 &priv->hw_params.num_gphy))
1246 priv->hw_params.num_gphy = 1;
1247
1248 rev = reg_readl(priv, REG_SWITCH_REVISION);
1249 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1250 SWITCH_TOP_REV_MASK;
1251 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1252
1253 rev = reg_readl(priv, REG_PHY_REVISION);
1254 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1255
1256 ret = b53_switch_register(dev);
1257 if (ret)
1258 goto out_mdio;
1259
1260 dev_info(&pdev->dev,
1261 "Starfighter 2 top: %x.%02x, core: %x.%02x, IRQs: %d, %d\n",
1262 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1263 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1264 priv->irq0, priv->irq1);
1265
1266 return 0;
1267
1268out_mdio:
1269 bcm_sf2_mdio_unregister(priv);
1270 return ret;
1271}
1272
1273static int bcm_sf2_sw_remove(struct platform_device *pdev)
1274{
1275 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1276
1277 priv->wol_ports_mask = 0;
1278 /* Disable interrupts */
1279 bcm_sf2_intr_disable(priv);
1280 dsa_unregister_switch(priv->dev->ds);
1281 bcm_sf2_cfp_exit(priv->dev->ds);
1282 bcm_sf2_mdio_unregister(priv);
1283 if (priv->type == BCM7278_DEVICE_ID && !IS_ERR(priv->rcdev))
1284 reset_control_assert(priv->rcdev);
1285
1286 return 0;
1287}
1288
1289static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1290{
1291 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1292
1293 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1294 * successful MDIO bus scan to occur. If we did turn off the GPHY
1295 * before (e.g: port_disable), this will also power it back on.
1296 *
1297 * Do not rely on kexec_in_progress, just power the PHY on.
1298 */
1299 if (priv->hw_params.num_gphy == 1)
1300 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1301}
1302
1303#ifdef CONFIG_PM_SLEEP
1304static int bcm_sf2_suspend(struct device *dev)
1305{
1306 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1307
1308 return dsa_switch_suspend(priv->dev->ds);
1309}
1310
1311static int bcm_sf2_resume(struct device *dev)
1312{
1313 struct bcm_sf2_priv *priv = dev_get_drvdata(dev);
1314
1315 return dsa_switch_resume(priv->dev->ds);
1316}
1317#endif /* CONFIG_PM_SLEEP */
1318
1319static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1320 bcm_sf2_suspend, bcm_sf2_resume);
1321
1322
1323static struct platform_driver bcm_sf2_driver = {
1324 .probe = bcm_sf2_sw_probe,
1325 .remove = bcm_sf2_sw_remove,
1326 .shutdown = bcm_sf2_sw_shutdown,
1327 .driver = {
1328 .name = "brcm-sf2",
1329 .of_match_table = bcm_sf2_of_match,
1330 .pm = &bcm_sf2_pm_ops,
1331 },
1332};
1333module_platform_driver(bcm_sf2_driver);
1334
1335MODULE_AUTHOR("Broadcom Corporation");
1336MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1337MODULE_LICENSE("GPL");
1338MODULE_ALIAS("platform:brcm-sf2");