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1/*
2 * Copyright (C) 2010 Google, Inc.
3 * Author: Erik Gilling <konkers@android.com>
4 *
5 * Copyright (C) 2011-2017 NVIDIA Corporation
6 *
7 * This software is licensed under the terms of the GNU General Public
8 * License version 2, as published by the Free Software Foundation, and
9 * may be copied, distributed, and modified under those terms.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 */
17
18#include "../dev.h"
19#include "../debug.h"
20#include "../cdma.h"
21#include "../channel.h"
22
23static void host1x_debug_show_channel_cdma(struct host1x *host,
24 struct host1x_channel *ch,
25 struct output *o)
26{
27 struct host1x_cdma *cdma = &ch->cdma;
28 u32 dmaput, dmaget, dmactrl;
29 u32 offset, class;
30 u32 ch_stat;
31
32 dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);
33 dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);
34 dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);
35 offset = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_OFFSET);
36 class = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_CLASS);
37 ch_stat = host1x_ch_readl(ch, HOST1X_CHANNEL_CHANNELSTAT);
38
39 host1x_debug_output(o, "%u-%s: ", ch->id, dev_name(ch->dev));
40
41 if (dmactrl & HOST1X_CHANNEL_DMACTRL_DMASTOP ||
42 !ch->cdma.push_buffer.mapped) {
43 host1x_debug_output(o, "inactive\n\n");
44 return;
45 }
46
47 if (class == HOST1X_CLASS_HOST1X && offset == HOST1X_UCLASS_WAIT_SYNCPT)
48 host1x_debug_output(o, "waiting on syncpt\n");
49 else
50 host1x_debug_output(o, "active class %02x, offset %04x\n",
51 class, offset);
52
53 host1x_debug_output(o, "DMAPUT %08x, DMAGET %08x, DMACTL %08x\n",
54 dmaput, dmaget, dmactrl);
55 host1x_debug_output(o, "CHANNELSTAT %02x\n", ch_stat);
56
57 show_channel_gathers(o, cdma);
58 host1x_debug_output(o, "\n");
59}
60
61static void host1x_debug_show_channel_fifo(struct host1x *host,
62 struct host1x_channel *ch,
63 struct output *o)
64{
65 u32 val, rd_ptr, wr_ptr, start, end;
66 u32 payload = INVALID_PAYLOAD;
67 unsigned int data_count = 0;
68
69 host1x_debug_output(o, "%u: fifo:\n", ch->id);
70
71 val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_STAT);
72 host1x_debug_output(o, "CMDFIFO_STAT %08x\n", val);
73 if (val & HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY) {
74 host1x_debug_output(o, "[empty]\n");
75 return;
76 }
77
78 val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_RDATA);
79 host1x_debug_output(o, "CMDFIFO_RDATA %08x\n", val);
80
81 /* Peek pointer values are invalid during SLCG, so disable it */
82 host1x_hypervisor_writel(host, 0x1, HOST1X_HV_ICG_EN_OVERRIDE);
83
84 val = 0;
85 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE;
86 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);
87 host1x_hypervisor_writel(host, val, HOST1X_HV_CMDFIFO_PEEK_CTRL);
88
89 val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_PEEK_PTRS);
90 rd_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(val);
91 wr_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(val);
92
93 val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_SETUP(ch->id));
94 start = HOST1X_HV_CMDFIFO_SETUP_BASE_V(val);
95 end = HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(val);
96
97 do {
98 val = 0;
99 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE;
100 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);
101 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR(rd_ptr);
102 host1x_hypervisor_writel(host, val,
103 HOST1X_HV_CMDFIFO_PEEK_CTRL);
104
105 val = host1x_hypervisor_readl(host,
106 HOST1X_HV_CMDFIFO_PEEK_READ);
107
108 if (!data_count) {
109 host1x_debug_output(o, "%03x 0x%08x: ",
110 rd_ptr - start, val);
111 data_count = show_channel_command(o, val, &payload);
112 } else {
113 host1x_debug_cont(o, "%08x%s", val,
114 data_count > 1 ? ", " : "])\n");
115 data_count--;
116 }
117
118 if (rd_ptr == end)
119 rd_ptr = start;
120 else
121 rd_ptr++;
122 } while (rd_ptr != wr_ptr);
123
124 if (data_count)
125 host1x_debug_cont(o, ", ...])\n");
126 host1x_debug_output(o, "\n");
127
128 host1x_hypervisor_writel(host, 0x0, HOST1X_HV_CMDFIFO_PEEK_CTRL);
129 host1x_hypervisor_writel(host, 0x0, HOST1X_HV_ICG_EN_OVERRIDE);
130}
131
132static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)
133{
134 /* TODO */
135}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2010 Google, Inc.
4 * Author: Erik Gilling <konkers@android.com>
5 *
6 * Copyright (C) 2011-2017 NVIDIA Corporation
7 */
8
9#include "../dev.h"
10#include "../debug.h"
11#include "../cdma.h"
12#include "../channel.h"
13
14static void host1x_debug_show_channel_cdma(struct host1x *host,
15 struct host1x_channel *ch,
16 struct output *o)
17{
18 struct host1x_cdma *cdma = &ch->cdma;
19 u32 dmaput, dmaget, dmactrl;
20 u32 offset, class;
21 u32 ch_stat;
22
23 dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);
24 dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);
25 dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);
26 offset = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_OFFSET);
27 class = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_CLASS);
28 ch_stat = host1x_ch_readl(ch, HOST1X_CHANNEL_CHANNELSTAT);
29
30 host1x_debug_output(o, "%u-%s: ", ch->id, dev_name(ch->dev));
31
32 if (dmactrl & HOST1X_CHANNEL_DMACTRL_DMASTOP ||
33 !ch->cdma.push_buffer.mapped) {
34 host1x_debug_output(o, "inactive\n\n");
35 return;
36 }
37
38 if (class == HOST1X_CLASS_HOST1X && offset == HOST1X_UCLASS_WAIT_SYNCPT)
39 host1x_debug_output(o, "waiting on syncpt\n");
40 else
41 host1x_debug_output(o, "active class %02x, offset %04x\n",
42 class, offset);
43
44 host1x_debug_output(o, "DMAPUT %08x, DMAGET %08x, DMACTL %08x\n",
45 dmaput, dmaget, dmactrl);
46 host1x_debug_output(o, "CHANNELSTAT %02x\n", ch_stat);
47
48 show_channel_gathers(o, cdma);
49 host1x_debug_output(o, "\n");
50}
51
52static void host1x_debug_show_channel_fifo(struct host1x *host,
53 struct host1x_channel *ch,
54 struct output *o)
55{
56#if HOST1X_HW <= 6
57 u32 rd_ptr, wr_ptr, start, end;
58 u32 payload = INVALID_PAYLOAD;
59 unsigned int data_count = 0;
60#endif
61 u32 val;
62
63 host1x_debug_output(o, "%u: fifo:\n", ch->id);
64
65 val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_STAT);
66 host1x_debug_output(o, "CMDFIFO_STAT %08x\n", val);
67 if (val & HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY) {
68 host1x_debug_output(o, "[empty]\n");
69 return;
70 }
71
72 val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_RDATA);
73 host1x_debug_output(o, "CMDFIFO_RDATA %08x\n", val);
74
75#if HOST1X_HW <= 6
76 /* Peek pointer values are invalid during SLCG, so disable it */
77 host1x_hypervisor_writel(host, 0x1, HOST1X_HV_ICG_EN_OVERRIDE);
78
79 val = 0;
80 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE;
81 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);
82 host1x_hypervisor_writel(host, val, HOST1X_HV_CMDFIFO_PEEK_CTRL);
83
84 val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_PEEK_PTRS);
85 rd_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(val);
86 wr_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(val);
87
88 val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_SETUP(ch->id));
89 start = HOST1X_HV_CMDFIFO_SETUP_BASE_V(val);
90 end = HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(val);
91
92 do {
93 val = 0;
94 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE;
95 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);
96 val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR(rd_ptr);
97 host1x_hypervisor_writel(host, val,
98 HOST1X_HV_CMDFIFO_PEEK_CTRL);
99
100 val = host1x_hypervisor_readl(host,
101 HOST1X_HV_CMDFIFO_PEEK_READ);
102
103 if (!data_count) {
104 host1x_debug_output(o, "%03x 0x%08x: ",
105 rd_ptr - start, val);
106 data_count = show_channel_command(o, val, &payload);
107 } else {
108 host1x_debug_cont(o, "%08x%s", val,
109 data_count > 1 ? ", " : "])\n");
110 data_count--;
111 }
112
113 if (rd_ptr == end)
114 rd_ptr = start;
115 else
116 rd_ptr++;
117 } while (rd_ptr != wr_ptr);
118
119 if (data_count)
120 host1x_debug_cont(o, ", ...])\n");
121 host1x_debug_output(o, "\n");
122
123 host1x_hypervisor_writel(host, 0x0, HOST1X_HV_CMDFIFO_PEEK_CTRL);
124 host1x_hypervisor_writel(host, 0x0, HOST1X_HV_ICG_EN_OVERRIDE);
125#endif
126}
127
128static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)
129{
130 /* TODO */
131}