1/*
  2 * Copyright 2012-15 Advanced Micro Devices, Inc.
  3 *
  4 * Permission is hereby granted, free of charge, to any person obtaining a
  5 * copy of this software and associated documentation files (the "Software"),
  6 * to deal in the Software without restriction, including without limitation
  7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8 * and/or sell copies of the Software, and to permit persons to whom the
  9 * Software is furnished to do so, subject to the following conditions:
 10 *
 11 * The above copyright notice and this permission notice shall be included in
 12 * all copies or substantial portions of the Software.
 13 *
 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 20 * OTHER DEALINGS IN THE SOFTWARE.
 21 *
 22 * Authors: AMD
 23 *
 24 */
 25
 26#ifndef __DAL_AUX_ENGINE_H__
 27#define __DAL_AUX_ENGINE_H__
 28
 29#include "dc_ddc_types.h"
 30#include "include/i2caux_interface.h"
 31
 32enum i2caux_transaction_operation {
 33	I2CAUX_TRANSACTION_READ,
 34	I2CAUX_TRANSACTION_WRITE
 35};
 36
 37enum i2caux_transaction_address_space {
 38	I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C = 1,
 39	I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD
 40};
 41
 42struct i2caux_transaction_payload {
 43	enum i2caux_transaction_address_space address_space;
 44	uint32_t address;
 45	uint32_t length;
 46	uint8_t *data;
 47};
 48
 49enum i2caux_transaction_status {
 50	I2CAUX_TRANSACTION_STATUS_UNKNOWN = (-1L),
 51	I2CAUX_TRANSACTION_STATUS_SUCCEEDED,
 52	I2CAUX_TRANSACTION_STATUS_FAILED_CHANNEL_BUSY,
 53	I2CAUX_TRANSACTION_STATUS_FAILED_TIMEOUT,
 54	I2CAUX_TRANSACTION_STATUS_FAILED_PROTOCOL_ERROR,
 55	I2CAUX_TRANSACTION_STATUS_FAILED_NACK,
 56	I2CAUX_TRANSACTION_STATUS_FAILED_INCOMPLETE,
 57	I2CAUX_TRANSACTION_STATUS_FAILED_OPERATION,
 58	I2CAUX_TRANSACTION_STATUS_FAILED_INVALID_OPERATION,
 59	I2CAUX_TRANSACTION_STATUS_FAILED_BUFFER_OVERFLOW,
 60	I2CAUX_TRANSACTION_STATUS_FAILED_HPD_DISCON
 61};
 62
 63struct i2caux_transaction_request {
 64	enum i2caux_transaction_operation operation;
 65	struct i2caux_transaction_payload payload;
 66	enum i2caux_transaction_status status;
 67};
 68
 69enum i2caux_engine_type {
 70	I2CAUX_ENGINE_TYPE_UNKNOWN = (-1L),
 71	I2CAUX_ENGINE_TYPE_AUX,
 72	I2CAUX_ENGINE_TYPE_I2C_DDC_HW,
 73	I2CAUX_ENGINE_TYPE_I2C_GENERIC_HW,
 74	I2CAUX_ENGINE_TYPE_I2C_SW
 75};
 76
 77enum i2c_default_speed {
 78	I2CAUX_DEFAULT_I2C_HW_SPEED = 50,
 79	I2CAUX_DEFAULT_I2C_SW_SPEED = 50
 80};
 81
 82union aux_config;
 83
 84struct aux_engine {
 85	uint32_t inst;
 86	struct ddc *ddc;
 87	struct dc_context *ctx;
 88	const struct aux_engine_funcs *funcs;
 89	/* following values are expressed in milliseconds */
 90	uint32_t delay;
 91	uint32_t max_defer_write_retry;
 92	bool acquire_reset;
 93};
 94
 95struct read_command_context {
 96	uint8_t *buffer;
 97	uint32_t current_read_length;
 98	uint32_t offset;
 99	enum i2caux_transaction_status status;
100
101	struct aux_request_transaction_data request;
102	struct aux_reply_transaction_data reply;
103
104	uint8_t returned_byte;
105
106	uint32_t timed_out_retry_aux;
107	uint32_t invalid_reply_retry_aux;
108	uint32_t defer_retry_aux;
109	uint32_t defer_retry_i2c;
110	uint32_t invalid_reply_retry_aux_on_ack;
111
112	bool transaction_complete;
113	bool operation_succeeded;
114};
115
116struct write_command_context {
117	bool mot;
118
119	uint8_t *buffer;
120	uint32_t current_write_length;
121	enum i2caux_transaction_status status;
122
123	struct aux_request_transaction_data request;
124	struct aux_reply_transaction_data reply;
125
126	uint8_t returned_byte;
127
128	uint32_t timed_out_retry_aux;
129	uint32_t invalid_reply_retry_aux;
130	uint32_t defer_retry_aux;
131	uint32_t defer_retry_i2c;
132	uint32_t max_defer_retry;
133	uint32_t ack_m_retry;
134
135	uint8_t reply_data[DEFAULT_AUX_MAX_DATA_SIZE];
136
137	bool transaction_complete;
138	bool operation_succeeded;
139};
140
141
142struct aux_engine_funcs {
143	bool (*configure_timeout)(
144		struct ddc_service *ddc,
145		uint32_t timeout);
146	void (*destroy)(
147		struct aux_engine **ptr);
148	bool (*acquire_engine)(
149		struct aux_engine *engine);
150	void (*configure)(
151		struct aux_engine *engine,
152		union aux_config cfg);
153	void (*submit_channel_request)(
154		struct aux_engine *engine,
155		struct aux_request_transaction_data *request);
156	void (*process_channel_reply)(
157		struct aux_engine *engine,
158		struct aux_reply_transaction_data *reply);
159	int (*read_channel_reply)(
160		struct aux_engine *engine,
161		uint32_t size,
162		uint8_t *buffer,
163		uint8_t *reply_result,
164		uint32_t *sw_status);
165	enum aux_channel_operation_result (*get_channel_status)(
166		struct aux_engine *engine,
167		uint8_t *returned_bytes);
168	bool (*is_engine_available)(struct aux_engine *engine);
169	enum i2caux_engine_type (*get_engine_type)(
170		const struct aux_engine *engine);
171	bool (*acquire)(
172		struct aux_engine *engine,
173		struct ddc *ddc);
174	bool (*submit_request)(
175		struct aux_engine *engine,
176		struct i2caux_transaction_request *request,
177		bool middle_of_transaction);
178	void (*release_engine)(
179		struct aux_engine *engine);
180	void (*destroy_engine)(
181		struct aux_engine **engine);
182};
183#endif