Loading...
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _PSP_TEE_GFX_IF_H_
25#define _PSP_TEE_GFX_IF_H_
26
27#define PSP_GFX_CMD_BUF_VERSION 0x00000001
28
29#define GFX_CMD_STATUS_MASK 0x0000FFFF
30#define GFX_CMD_ID_MASK 0x000F0000
31#define GFX_CMD_RESERVED_MASK 0x7FF00000
32#define GFX_CMD_RESPONSE_MASK 0x80000000
33
34/* TEE Gfx Command IDs for the register interface.
35* Command ID must be between 0x00010000 and 0x000F0000.
36*/
37enum psp_gfx_crtl_cmd_id
38{
39 GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */
40 GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */
41 GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */
42 GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */
43
44 GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
45};
46
47
48/* Control registers of the TEE Gfx interface. These are located in
49* SRBM-to-PSP mailbox registers (total 8 registers).
50*/
51struct psp_gfx_ctrl
52{
53 volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */
54 volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */
55 volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */
56 volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */
57 volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */
58 volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of physical address of ring buffer */
59 volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of physical address of ring buffer */
60 volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */
61
62};
63
64
65/* Response flag is set in the command when command is completed by PSP.
66* Used in the GFX_CTRL.CmdResp.
67* When PSP GFX I/F is initialized, the flag is set.
68*/
69#define GFX_FLAG_RESPONSE 0x80000000
70
71
72/* TEE Gfx Command IDs for the ring buffer interface. */
73enum psp_gfx_cmd_id
74{
75 GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */
76 GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */
77 GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */
78 GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */
79 GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */
80 GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */
81
82};
83
84
85/* Command to load Trusted Application binary into PSP OS. */
86struct psp_gfx_cmd_load_ta
87{
88 uint32_t app_phy_addr_lo; /* bits [31:0] of the physical address of the TA binary (must be 4 KB aligned) */
89 uint32_t app_phy_addr_hi; /* bits [63:32] of the physical address of the TA binary */
90 uint32_t app_len; /* length of the TA binary in bytes */
91 uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the physical address of CMD buffer (must be 4 KB aligned) */
92 uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the physical address of CMD buffer */
93 uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */
94
95 /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
96 * for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead
97 * of using global persistent buffer.
98 */
99};
100
101
102/* Command to Unload Trusted Application binary from PSP OS. */
103struct psp_gfx_cmd_unload_ta
104{
105 uint32_t session_id; /* Session ID of the loaded TA to be unloaded */
106
107};
108
109
110/* Shared buffers for InvokeCommand.
111*/
112struct psp_gfx_buf_desc
113{
114 uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of the buffer (must be 4 KB aligned) */
115 uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of the buffer */
116 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
117
118};
119
120/* Max number of descriptors for one shared buffer (in how many different
121* physical locations one shared buffer can be stored). If buffer is too much
122* fragmented, error will be returned.
123*/
124#define GFX_BUF_MAX_DESC 64
125
126struct psp_gfx_buf_list
127{
128 uint32_t num_desc; /* number of buffer descriptors in the list */
129 uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
130 struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */
131
132 /* total 776 bytes */
133};
134
135/* Command to execute InvokeCommand entry point of the TA. */
136struct psp_gfx_cmd_invoke_cmd
137{
138 uint32_t session_id; /* Session ID of the TA to be executed */
139 uint32_t ta_cmd_id; /* Command ID to be sent to TA */
140 struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */
141
142};
143
144
145/* Command to setup TMR region. */
146struct psp_gfx_cmd_setup_tmr
147{
148 uint32_t buf_phy_addr_lo; /* bits [31:0] of physical address of TMR buffer (must be 4 KB aligned) */
149 uint32_t buf_phy_addr_hi; /* bits [63:32] of physical address of TMR buffer */
150 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */
151
152};
153
154
155/* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
156enum psp_gfx_fw_type
157{
158 GFX_FW_TYPE_NONE = 0,
159 GFX_FW_TYPE_CP_ME = 1,
160 GFX_FW_TYPE_CP_PFP = 2,
161 GFX_FW_TYPE_CP_CE = 3,
162 GFX_FW_TYPE_CP_MEC = 4,
163 GFX_FW_TYPE_CP_MEC_ME1 = 5,
164 GFX_FW_TYPE_CP_MEC_ME2 = 6,
165 GFX_FW_TYPE_RLC_V = 7,
166 GFX_FW_TYPE_RLC_G = 8,
167 GFX_FW_TYPE_SDMA0 = 9,
168 GFX_FW_TYPE_SDMA1 = 10,
169 GFX_FW_TYPE_DMCU_ERAM = 11,
170 GFX_FW_TYPE_DMCU_ISR = 12,
171 GFX_FW_TYPE_VCN = 13,
172 GFX_FW_TYPE_UVD = 14,
173 GFX_FW_TYPE_VCE = 15,
174 GFX_FW_TYPE_ISP = 16,
175 GFX_FW_TYPE_ACP = 17,
176 GFX_FW_TYPE_SMU = 18,
177};
178
179/* Command to load HW IP FW. */
180struct psp_gfx_cmd_load_ip_fw
181{
182 uint32_t fw_phy_addr_lo; /* bits [31:0] of physical address of FW location (must be 4 KB aligned) */
183 uint32_t fw_phy_addr_hi; /* bits [63:32] of physical address of FW location */
184 uint32_t fw_size; /* FW buffer size in bytes */
185 enum psp_gfx_fw_type fw_type; /* FW type */
186
187};
188
189
190/* All GFX ring buffer commands. */
191union psp_gfx_commands
192{
193 struct psp_gfx_cmd_load_ta cmd_load_ta;
194 struct psp_gfx_cmd_unload_ta cmd_unload_ta;
195 struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd;
196 struct psp_gfx_cmd_setup_tmr cmd_setup_tmr;
197 struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw;
198
199};
200
201
202/* Structure of GFX Response buffer.
203* For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
204* it is separate buffer.
205*/
206struct psp_gfx_resp
207{
208 uint32_t status; /* +0 status of command execution */
209 uint32_t session_id; /* +4 session ID in response to LoadTa command */
210 uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
211 uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
212
213 uint32_t reserved[4];
214
215 /* total 32 bytes */
216};
217
218/* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi
219* and psp_gfx_rb_frame.cmd_buf_addr_lo.
220*/
221struct psp_gfx_cmd_resp
222{
223 uint32_t buf_size; /* +0 total size of the buffer in bytes */
224 uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */
225 uint32_t cmd_id; /* +8 command ID */
226
227 /* These fields are used for RBI only. They are all 0 in GPCOM commands
228 */
229 uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of physical address of response buffer (must be 4 KB aligned) */
230 uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of physical address of response buffer */
231 uint32_t resp_offset; /* +20 offset within response buffer */
232 uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */
233
234 union psp_gfx_commands cmd; /* +28 command specific structures */
235
236 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
237
238 /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response
239 * is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo.
240 */
241 struct psp_gfx_resp resp; /* +864 response */
242
243 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
244
245 /* total size 1024 bytes */
246};
247
248
249#define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/
250
251/* Structure of the Ring Buffer Frame */
252struct psp_gfx_rb_frame
253{
254 uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of physical address of command buffer (must be 4 KB aligned) */
255 uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of physical address of command buffer */
256 uint32_t cmd_buf_size; /* +8 command buffer size in bytes */
257 uint32_t fence_addr_lo; /* +12 bits [31:0] of physical address of Fence for this frame */
258 uint32_t fence_addr_hi; /* +16 bits [63:32] of physical address of Fence for this frame */
259 uint32_t fence_value; /* +20 Fence value */
260 uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */
261 uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */
262 uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */
263 uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
264 uint8_t reserved1[2]; /* +34 reserved, must be 0 */
265 uint32_t reserved2[7]; /* +40 reserved, must be 0 */
266 /* total 64 bytes */
267};
268
269#endif /* _PSP_TEE_GFX_IF_H_ */
1/*
2 * Copyright 2017 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#ifndef _PSP_TEE_GFX_IF_H_
25#define _PSP_TEE_GFX_IF_H_
26
27#define PSP_GFX_CMD_BUF_VERSION 0x00000001
28
29#define GFX_CMD_STATUS_MASK 0x0000FFFF
30#define GFX_CMD_ID_MASK 0x000F0000
31#define GFX_CMD_RESERVED_MASK 0x7FF00000
32#define GFX_CMD_RESPONSE_MASK 0x80000000
33
34/* USBC PD FW version retrieval command */
35#define C2PMSG_CMD_GFX_USB_PD_FW_VER 0x2000000
36
37/* TEE Gfx Command IDs for the register interface.
38* Command ID must be between 0x00010000 and 0x000F0000.
39*/
40enum psp_gfx_crtl_cmd_id
41{
42 GFX_CTRL_CMD_ID_INIT_RBI_RING = 0x00010000, /* initialize RBI ring */
43 GFX_CTRL_CMD_ID_INIT_GPCOM_RING = 0x00020000, /* initialize GPCOM ring */
44 GFX_CTRL_CMD_ID_DESTROY_RINGS = 0x00030000, /* destroy rings */
45 GFX_CTRL_CMD_ID_CAN_INIT_RINGS = 0x00040000, /* is it allowed to initialized the rings */
46 GFX_CTRL_CMD_ID_ENABLE_INT = 0x00050000, /* enable PSP-to-Gfx interrupt */
47 GFX_CTRL_CMD_ID_DISABLE_INT = 0x00060000, /* disable PSP-to-Gfx interrupt */
48 GFX_CTRL_CMD_ID_MODE1_RST = 0x00070000, /* trigger the Mode 1 reset */
49 GFX_CTRL_CMD_ID_GBR_IH_SET = 0x00080000, /* set Gbr IH_RB_CNTL registers */
50 GFX_CTRL_CMD_ID_CONSUME_CMD = 0x000A0000, /* send interrupt to psp for updating write pointer of vf */
51 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING = 0x000C0000, /* destroy GPCOM ring */
52
53 GFX_CTRL_CMD_ID_MAX = 0x000F0000, /* max command ID */
54};
55
56
57/*-----------------------------------------------------------------------------
58 NOTE: All physical addresses used in this interface are actually
59 GPU Virtual Addresses.
60*/
61
62
63/* Control registers of the TEE Gfx interface. These are located in
64* SRBM-to-PSP mailbox registers (total 8 registers).
65*/
66struct psp_gfx_ctrl
67{
68 volatile uint32_t cmd_resp; /* +0 Command/Response register for Gfx commands */
69 volatile uint32_t rbi_wptr; /* +4 Write pointer (index) of RBI ring */
70 volatile uint32_t rbi_rptr; /* +8 Read pointer (index) of RBI ring */
71 volatile uint32_t gpcom_wptr; /* +12 Write pointer (index) of GPCOM ring */
72 volatile uint32_t gpcom_rptr; /* +16 Read pointer (index) of GPCOM ring */
73 volatile uint32_t ring_addr_lo; /* +20 bits [31:0] of GPU Virtual of ring buffer (VMID=0)*/
74 volatile uint32_t ring_addr_hi; /* +24 bits [63:32] of GPU Virtual of ring buffer (VMID=0) */
75 volatile uint32_t ring_buf_size; /* +28 Ring buffer size (in bytes) */
76
77};
78
79
80/* Response flag is set in the command when command is completed by PSP.
81* Used in the GFX_CTRL.CmdResp.
82* When PSP GFX I/F is initialized, the flag is set.
83*/
84#define GFX_FLAG_RESPONSE 0x80000000
85
86/* Gbr IH registers ID */
87enum ih_reg_id {
88 IH_RB = 0, // IH_RB_CNTL
89 IH_RB_RNG1 = 1, // IH_RB_CNTL_RING1
90 IH_RB_RNG2 = 2, // IH_RB_CNTL_RING2
91};
92
93/* Command to setup Gibraltar IH register */
94struct psp_gfx_cmd_gbr_ih_reg {
95 uint32_t reg_value; /* Value to be set to the IH_RB_CNTL... register*/
96 enum ih_reg_id reg_id; /* ID of the register */
97};
98
99/* TEE Gfx Command IDs for the ring buffer interface. */
100enum psp_gfx_cmd_id
101{
102 GFX_CMD_ID_LOAD_TA = 0x00000001, /* load TA */
103 GFX_CMD_ID_UNLOAD_TA = 0x00000002, /* unload TA */
104 GFX_CMD_ID_INVOKE_CMD = 0x00000003, /* send command to TA */
105 GFX_CMD_ID_LOAD_ASD = 0x00000004, /* load ASD Driver */
106 GFX_CMD_ID_SETUP_TMR = 0x00000005, /* setup TMR region */
107 GFX_CMD_ID_LOAD_IP_FW = 0x00000006, /* load HW IP FW */
108 GFX_CMD_ID_DESTROY_TMR = 0x00000007, /* destroy TMR region */
109 GFX_CMD_ID_SAVE_RESTORE = 0x00000008, /* save/restore HW IP FW */
110 GFX_CMD_ID_SETUP_VMR = 0x00000009, /* setup VMR region */
111 GFX_CMD_ID_DESTROY_VMR = 0x0000000A, /* destroy VMR region */
112 GFX_CMD_ID_PROG_REG = 0x0000000B, /* program regs */
113 GFX_CMD_ID_CLEAR_VF_FW = 0x0000000D, /* Clear VF FW, to be used on VF shutdown. */
114 /* IDs upto 0x1F are reserved for older programs (Raven, Vega 10/12/20) */
115 GFX_CMD_ID_LOAD_TOC = 0x00000020, /* Load TOC and obtain TMR size */
116 GFX_CMD_ID_AUTOLOAD_RLC = 0x00000021, /* Indicates all graphics fw loaded, start RLC autoload */
117};
118
119/* Command to load Trusted Application binary into PSP OS. */
120struct psp_gfx_cmd_load_ta
121{
122 uint32_t app_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of the TA binary (must be 4 KB aligned) */
123 uint32_t app_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of the TA binary */
124 uint32_t app_len; /* length of the TA binary in bytes */
125 uint32_t cmd_buf_phy_addr_lo; /* bits [31:0] of the GPU Virtual address of CMD buffer (must be 4 KB aligned) */
126 uint32_t cmd_buf_phy_addr_hi; /* bits [63:32] of the GPU Virtual address of CMD buffer */
127 uint32_t cmd_buf_len; /* length of the CMD buffer in bytes; must be multiple of 4 KB */
128
129 /* Note: CmdBufLen can be set to 0. In this case no persistent CMD buffer is provided
130 * for the TA. Each InvokeCommand can have dinamically mapped CMD buffer instead
131 * of using global persistent buffer.
132 */
133};
134
135
136/* Command to Unload Trusted Application binary from PSP OS. */
137struct psp_gfx_cmd_unload_ta
138{
139 uint32_t session_id; /* Session ID of the loaded TA to be unloaded */
140
141};
142
143
144/* Shared buffers for InvokeCommand.
145*/
146struct psp_gfx_buf_desc
147{
148 uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of the buffer (must be 4 KB aligned) */
149 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of the buffer */
150 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB and no bigger than 64 MB) */
151
152};
153
154/* Max number of descriptors for one shared buffer (in how many different
155* physical locations one shared buffer can be stored). If buffer is too much
156* fragmented, error will be returned.
157*/
158#define GFX_BUF_MAX_DESC 64
159
160struct psp_gfx_buf_list
161{
162 uint32_t num_desc; /* number of buffer descriptors in the list */
163 uint32_t total_size; /* total size of all buffers in the list in bytes (must be multiple of 4 KB) */
164 struct psp_gfx_buf_desc buf_desc[GFX_BUF_MAX_DESC]; /* list of buffer descriptors */
165
166 /* total 776 bytes */
167};
168
169/* Command to execute InvokeCommand entry point of the TA. */
170struct psp_gfx_cmd_invoke_cmd
171{
172 uint32_t session_id; /* Session ID of the TA to be executed */
173 uint32_t ta_cmd_id; /* Command ID to be sent to TA */
174 struct psp_gfx_buf_list buf; /* one indirect buffer (scatter/gather list) */
175
176};
177
178
179/* Command to setup TMR region. */
180struct psp_gfx_cmd_setup_tmr
181{
182 uint32_t buf_phy_addr_lo; /* bits [31:0] of GPU Virtual address of TMR buffer (must be 4 KB aligned) */
183 uint32_t buf_phy_addr_hi; /* bits [63:32] of GPU Virtual address of TMR buffer */
184 uint32_t buf_size; /* buffer size in bytes (must be multiple of 4 KB) */
185
186};
187
188
189/* FW types for GFX_CMD_ID_LOAD_IP_FW command. Limit 31. */
190enum psp_gfx_fw_type {
191 GFX_FW_TYPE_NONE = 0, /* */
192 GFX_FW_TYPE_CP_ME = 1, /* CP-ME VG + RV */
193 GFX_FW_TYPE_CP_PFP = 2, /* CP-PFP VG + RV */
194 GFX_FW_TYPE_CP_CE = 3, /* CP-CE VG + RV */
195 GFX_FW_TYPE_CP_MEC = 4, /* CP-MEC FW VG + RV */
196 GFX_FW_TYPE_CP_MEC_ME1 = 5, /* CP-MEC Jump Table 1 VG + RV */
197 GFX_FW_TYPE_CP_MEC_ME2 = 6, /* CP-MEC Jump Table 2 VG */
198 GFX_FW_TYPE_RLC_V = 7, /* RLC-V VG */
199 GFX_FW_TYPE_RLC_G = 8, /* RLC-G VG + RV */
200 GFX_FW_TYPE_SDMA0 = 9, /* SDMA0 VG + RV */
201 GFX_FW_TYPE_SDMA1 = 10, /* SDMA1 VG */
202 GFX_FW_TYPE_DMCU_ERAM = 11, /* DMCU-ERAM VG + RV */
203 GFX_FW_TYPE_DMCU_ISR = 12, /* DMCU-ISR VG + RV */
204 GFX_FW_TYPE_VCN = 13, /* VCN RV */
205 GFX_FW_TYPE_UVD = 14, /* UVD VG */
206 GFX_FW_TYPE_VCE = 15, /* VCE VG */
207 GFX_FW_TYPE_ISP = 16, /* ISP RV */
208 GFX_FW_TYPE_ACP = 17, /* ACP RV */
209 GFX_FW_TYPE_SMU = 18, /* SMU VG */
210 GFX_FW_TYPE_MMSCH = 19, /* MMSCH VG */
211 GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM = 20, /* RLC GPM VG + RV */
212 GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM = 21, /* RLC SRM VG + RV */
213 GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL = 22, /* RLC CNTL VG + RV */
214 GFX_FW_TYPE_UVD1 = 23, /* UVD1 VG-20 */
215 GFX_FW_TYPE_TOC = 24, /* TOC NV-10 */
216 GFX_FW_TYPE_RLC_P = 25, /* RLC P NV */
217 GFX_FW_TYPE_RLX6 = 26, /* RLX6 NV */
218 GFX_FW_TYPE_GLOBAL_TAP_DELAYS = 27, /* GLOBAL TAP DELAYS NV */
219 GFX_FW_TYPE_SE0_TAP_DELAYS = 28, /* SE0 TAP DELAYS NV */
220 GFX_FW_TYPE_SE1_TAP_DELAYS = 29, /* SE1 TAP DELAYS NV */
221 GFX_FW_TYPE_GLOBAL_SE0_SE1_SKEW_DELAYS = 30, /* GLOBAL SE0/1 SKEW DELAYS NV */
222 GFX_FW_TYPE_SDMA0_JT = 31, /* SDMA0 JT NV */
223 GFX_FW_TYPE_SDMA1_JT = 32, /* SDNA1 JT NV */
224 GFX_FW_TYPE_CP_MES = 33, /* CP MES NV */
225 GFX_FW_TYPE_MES_STACK = 34, /* MES STACK NV */
226 GFX_FW_TYPE_RLC_SRM_DRAM_SR = 35, /* RLC SRM DRAM NV */
227 GFX_FW_TYPE_RLCG_SCRATCH_SR = 36, /* RLCG SCRATCH NV */
228 GFX_FW_TYPE_RLCP_SCRATCH_SR = 37, /* RLCP SCRATCH NV */
229 GFX_FW_TYPE_RLCV_SCRATCH_SR = 38, /* RLCV SCRATCH NV */
230 GFX_FW_TYPE_RLX6_DRAM_SR = 39, /* RLX6 DRAM NV */
231 GFX_FW_TYPE_SDMA0_PG_CONTEXT = 40, /* SDMA0 PG CONTEXT NV */
232 GFX_FW_TYPE_SDMA1_PG_CONTEXT = 41, /* SDMA1 PG CONTEXT NV */
233 GFX_FW_TYPE_GLOBAL_MUX_SELECT_RAM = 42, /* GLOBAL MUX SEL RAM NV */
234 GFX_FW_TYPE_SE0_MUX_SELECT_RAM = 43, /* SE0 MUX SEL RAM NV */
235 GFX_FW_TYPE_SE1_MUX_SELECT_RAM = 44, /* SE1 MUX SEL RAM NV */
236 GFX_FW_TYPE_ACCUM_CTRL_RAM = 45, /* ACCUM CTRL RAM NV */
237 GFX_FW_TYPE_RLCP_CAM = 46, /* RLCP CAM NV */
238 GFX_FW_TYPE_RLC_SPP_CAM_EXT = 47, /* RLC SPP CAM EXT NV */
239 GFX_FW_TYPE_RLX6_DRAM_BOOT = 48, /* RLX6 DRAM BOOT NV */
240 GFX_FW_TYPE_VCN0_RAM = 49, /* VCN_RAM NV + RN */
241 GFX_FW_TYPE_VCN1_RAM = 50, /* VCN_RAM NV + RN */
242 GFX_FW_TYPE_DMUB = 51, /* DMUB RN */
243 GFX_FW_TYPE_SDMA2 = 52, /* SDMA2 MI */
244 GFX_FW_TYPE_SDMA3 = 53, /* SDMA3 MI */
245 GFX_FW_TYPE_SDMA4 = 54, /* SDMA4 MI */
246 GFX_FW_TYPE_SDMA5 = 55, /* SDMA5 MI */
247 GFX_FW_TYPE_SDMA6 = 56, /* SDMA6 MI */
248 GFX_FW_TYPE_SDMA7 = 57, /* SDMA7 MI */
249 GFX_FW_TYPE_VCN1 = 58, /* VCN1 MI */
250 GFX_FW_TYPE_MAX
251};
252
253/* Command to load HW IP FW. */
254struct psp_gfx_cmd_load_ip_fw
255{
256 uint32_t fw_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
257 uint32_t fw_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
258 uint32_t fw_size; /* FW buffer size in bytes */
259 enum psp_gfx_fw_type fw_type; /* FW type */
260
261};
262
263/* Command to save/restore HW IP FW. */
264struct psp_gfx_cmd_save_restore_ip_fw
265{
266 uint32_t save_fw; /* if set, command is used for saving fw otherwise for resetoring*/
267 uint32_t save_restore_addr_lo; /* bits [31:0] of FB address of GART memory used as save/restore buffer (must be 4 KB aligned) */
268 uint32_t save_restore_addr_hi; /* bits [63:32] of FB address of GART memory used as save/restore buffer */
269 uint32_t buf_size; /* Size of the save/restore buffer in bytes */
270 enum psp_gfx_fw_type fw_type; /* FW type */
271};
272
273/* Command to setup register program */
274struct psp_gfx_cmd_reg_prog {
275 uint32_t reg_value;
276 uint32_t reg_id;
277};
278
279/* Command to load TOC */
280struct psp_gfx_cmd_load_toc
281{
282 uint32_t toc_phy_addr_lo; /* bits [31:0] of GPU Virtual address of FW location (must be 4 KB aligned) */
283 uint32_t toc_phy_addr_hi; /* bits [63:32] of GPU Virtual address of FW location */
284 uint32_t toc_size; /* FW buffer size in bytes */
285};
286
287/* All GFX ring buffer commands. */
288union psp_gfx_commands
289{
290 struct psp_gfx_cmd_load_ta cmd_load_ta;
291 struct psp_gfx_cmd_unload_ta cmd_unload_ta;
292 struct psp_gfx_cmd_invoke_cmd cmd_invoke_cmd;
293 struct psp_gfx_cmd_setup_tmr cmd_setup_tmr;
294 struct psp_gfx_cmd_load_ip_fw cmd_load_ip_fw;
295 struct psp_gfx_cmd_save_restore_ip_fw cmd_save_restore_ip_fw;
296 struct psp_gfx_cmd_reg_prog cmd_setup_reg_prog;
297 struct psp_gfx_cmd_setup_tmr cmd_setup_vmr;
298 struct psp_gfx_cmd_load_toc cmd_load_toc;
299};
300
301/* Structure of GFX Response buffer.
302* For GPCOM I/F it is part of GFX_CMD_RESP buffer, for RBI
303* it is separate buffer.
304*/
305struct psp_gfx_resp
306{
307 uint32_t status; /* +0 status of command execution */
308 uint32_t session_id; /* +4 session ID in response to LoadTa command */
309 uint32_t fw_addr_lo; /* +8 bits [31:0] of FW address within TMR (in response to cmd_load_ip_fw command) */
310 uint32_t fw_addr_hi; /* +12 bits [63:32] of FW address within TMR (in response to cmd_load_ip_fw command) */
311 uint32_t tmr_size; /* +16 size of the TMR to be reserved including MM fw and Gfx fw in response to cmd_load_toc command */
312
313 uint32_t reserved[3];
314
315 /* total 32 bytes */
316};
317
318/* Structure of Command buffer pointed by psp_gfx_rb_frame.cmd_buf_addr_hi
319* and psp_gfx_rb_frame.cmd_buf_addr_lo.
320*/
321struct psp_gfx_cmd_resp
322{
323 uint32_t buf_size; /* +0 total size of the buffer in bytes */
324 uint32_t buf_version; /* +4 version of the buffer strusture; must be PSP_GFX_CMD_BUF_VERSION */
325 uint32_t cmd_id; /* +8 command ID */
326
327 /* These fields are used for RBI only. They are all 0 in GPCOM commands
328 */
329 uint32_t resp_buf_addr_lo; /* +12 bits [31:0] of GPU Virtual address of response buffer (must be 4 KB aligned) */
330 uint32_t resp_buf_addr_hi; /* +16 bits [63:32] of GPU Virtual address of response buffer */
331 uint32_t resp_offset; /* +20 offset within response buffer */
332 uint32_t resp_buf_size; /* +24 total size of the response buffer in bytes */
333
334 union psp_gfx_commands cmd; /* +28 command specific structures */
335
336 uint8_t reserved_1[864 - sizeof(union psp_gfx_commands) - 28];
337
338 /* Note: Resp is part of this buffer for GPCOM ring. For RBI ring the response
339 * is separate buffer pointed by resp_buf_addr_hi and resp_buf_addr_lo.
340 */
341 struct psp_gfx_resp resp; /* +864 response */
342
343 uint8_t reserved_2[1024 - 864 - sizeof(struct psp_gfx_resp)];
344
345 /* total size 1024 bytes */
346};
347
348
349#define FRAME_TYPE_DESTROY 1 /* frame sent by KMD driver when UMD Scheduler context is destroyed*/
350
351/* Structure of the Ring Buffer Frame */
352struct psp_gfx_rb_frame
353{
354 uint32_t cmd_buf_addr_lo; /* +0 bits [31:0] of GPU Virtual address of command buffer (must be 4 KB aligned) */
355 uint32_t cmd_buf_addr_hi; /* +4 bits [63:32] of GPU Virtual address of command buffer */
356 uint32_t cmd_buf_size; /* +8 command buffer size in bytes */
357 uint32_t fence_addr_lo; /* +12 bits [31:0] of GPU Virtual address of Fence for this frame */
358 uint32_t fence_addr_hi; /* +16 bits [63:32] of GPU Virtual address of Fence for this frame */
359 uint32_t fence_value; /* +20 Fence value */
360 uint32_t sid_lo; /* +24 bits [31:0] of SID value (used only for RBI frames) */
361 uint32_t sid_hi; /* +28 bits [63:32] of SID value (used only for RBI frames) */
362 uint8_t vmid; /* +32 VMID value used for mapping of all addresses for this frame */
363 uint8_t frame_type; /* +33 1: destory context frame, 0: all other frames; used only for RBI frames */
364 uint8_t reserved1[2]; /* +34 reserved, must be 0 */
365 uint32_t reserved2[7]; /* +36 reserved, must be 0 */
366 /* total 64 bytes */
367};
368
369#define PSP_ERR_UNKNOWN_COMMAND 0x00000100
370
371enum tee_error_code {
372 TEE_SUCCESS = 0x00000000,
373 TEE_ERROR_NOT_SUPPORTED = 0xFFFF000A,
374};
375
376#endif /* _PSP_TEE_GFX_IF_H_ */