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1/*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include "amdgpu.h"
24#include "amdgpu_ras.h"
25#include "mmhub_v9_4.h"
26
27#include "mmhub/mmhub_9_4_1_offset.h"
28#include "mmhub/mmhub_9_4_1_sh_mask.h"
29#include "mmhub/mmhub_9_4_1_default.h"
30#include "athub/athub_1_0_offset.h"
31#include "athub/athub_1_0_sh_mask.h"
32#include "vega10_enum.h"
33#include "soc15.h"
34#include "soc15_common.h"
35
36#define MMHUB_NUM_INSTANCES 2
37#define MMHUB_INSTANCE_REGISTER_OFFSET 0x3000
38
39u64 mmhub_v9_4_get_fb_location(struct amdgpu_device *adev)
40{
41 /* The base should be same b/t 2 mmhubs on Acrturus. Read one here. */
42 u64 base = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_BASE);
43 u64 top = RREG32_SOC15(MMHUB, 0, mmVMSHAREDVC0_MC_VM_FB_LOCATION_TOP);
44
45 base &= VMSHAREDVC0_MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
46 base <<= 24;
47
48 top &= VMSHAREDVC0_MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
49 top <<= 24;
50
51 adev->gmc.fb_start = base;
52 adev->gmc.fb_end = top;
53
54 return base;
55}
56
57static void mmhub_v9_4_setup_hubid_vm_pt_regs(struct amdgpu_device *adev, int hubid,
58 uint32_t vmid, uint64_t value)
59{
60 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
61
62 WREG32_SOC15_OFFSET(MMHUB, 0,
63 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
64 hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
65 lower_32_bits(value));
66
67 WREG32_SOC15_OFFSET(MMHUB, 0,
68 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
69 hub->ctx_addr_distance * vmid + hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
70 upper_32_bits(value));
71
72}
73
74static void mmhub_v9_4_init_gart_aperture_regs(struct amdgpu_device *adev,
75 int hubid)
76{
77 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
78
79 mmhub_v9_4_setup_hubid_vm_pt_regs(adev, hubid, 0, pt_base);
80
81 WREG32_SOC15_OFFSET(MMHUB, 0,
82 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
83 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
84 (u32)(adev->gmc.gart_start >> 12));
85 WREG32_SOC15_OFFSET(MMHUB, 0,
86 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
87 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
88 (u32)(adev->gmc.gart_start >> 44));
89
90 WREG32_SOC15_OFFSET(MMHUB, 0,
91 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
92 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
93 (u32)(adev->gmc.gart_end >> 12));
94 WREG32_SOC15_OFFSET(MMHUB, 0,
95 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
96 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
97 (u32)(adev->gmc.gart_end >> 44));
98}
99
100void mmhub_v9_4_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
101 uint64_t page_table_base)
102{
103 int i;
104
105 for (i = 0; i < MMHUB_NUM_INSTANCES; i++)
106 mmhub_v9_4_setup_hubid_vm_pt_regs(adev, i, vmid,
107 page_table_base);
108}
109
110static void mmhub_v9_4_init_system_aperture_regs(struct amdgpu_device *adev,
111 int hubid)
112{
113 uint64_t value;
114 uint32_t tmp;
115
116 /* Program the AGP BAR */
117 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BASE,
118 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
119 0);
120 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_TOP,
121 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
122 adev->gmc.agp_end >> 24);
123 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_AGP_BOT,
124 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
125 adev->gmc.agp_start >> 24);
126
127 if (!amdgpu_sriov_vf(adev)) {
128 /* Program the system aperture low logical page number. */
129 WREG32_SOC15_OFFSET(
130 MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_LOW_ADDR,
131 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
132 min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
133 WREG32_SOC15_OFFSET(
134 MMHUB, 0, mmVMSHAREDVC0_MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
135 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
136 max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
137
138 /* Set default page address. */
139 value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start +
140 adev->vm_manager.vram_base_offset;
141 WREG32_SOC15_OFFSET(
142 MMHUB, 0,
143 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
144 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
145 (u32)(value >> 12));
146 WREG32_SOC15_OFFSET(
147 MMHUB, 0,
148 mmVMSHAREDPF0_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
149 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
150 (u32)(value >> 44));
151
152 /* Program "protection fault". */
153 WREG32_SOC15_OFFSET(
154 MMHUB, 0,
155 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
156 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
157 (u32)(adev->dummy_page_addr >> 12));
158 WREG32_SOC15_OFFSET(
159 MMHUB, 0,
160 mmVML2PF0_VM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
161 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
162 (u32)((u64)adev->dummy_page_addr >> 44));
163
164 tmp = RREG32_SOC15_OFFSET(
165 MMHUB, 0, mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
166 hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
167 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
168 ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
169 WREG32_SOC15_OFFSET(MMHUB, 0,
170 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL2,
171 hubid * MMHUB_INSTANCE_REGISTER_OFFSET,
172 tmp);
173 }
174}
175
176static void mmhub_v9_4_init_tlb_regs(struct amdgpu_device *adev, int hubid)
177{
178 uint32_t tmp;
179
180 /* Setup TLB control */
181 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
182 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
183 hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
184
185 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
186 ENABLE_L1_TLB, 1);
187 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
188 SYSTEM_ACCESS_MODE, 3);
189 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
190 ENABLE_ADVANCED_DRIVER_MODEL, 1);
191 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
192 SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
193 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
194 ECO_BITS, 0);
195 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
196 MTYPE, MTYPE_UC);/* XXX for emulation. */
197 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
198 ATC_EN, 1);
199
200 WREG32_SOC15_OFFSET(MMHUB, 0, mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
201 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
202}
203
204static void mmhub_v9_4_init_cache_regs(struct amdgpu_device *adev, int hubid)
205{
206 uint32_t tmp;
207
208 /* Setup L2 cache */
209 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
210 hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
211 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
212 ENABLE_L2_CACHE, 1);
213 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
214 ENABLE_L2_FRAGMENT_PROCESSING, 1);
215 /* XXX for emulation, Refer to closed source code.*/
216 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
217 L2_PDE0_CACHE_TAG_GENERATION_MODE, 0);
218 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
219 PDE_FAULT_CLASSIFICATION, 0);
220 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
221 CONTEXT1_IDENTITY_ACCESS_MODE, 1);
222 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
223 IDENTITY_MODE_FRAGMENT_SIZE, 0);
224 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
225 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
226
227 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
228 hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
229 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
230 INVALIDATE_ALL_L1_TLBS, 1);
231 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL2,
232 INVALIDATE_L2_CACHE, 1);
233 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL2,
234 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
235
236 tmp = mmVML2PF0_VM_L2_CNTL3_DEFAULT;
237 if (adev->gmc.translate_further) {
238 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 12);
239 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
240 L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
241 } else {
242 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3, BANK_SELECT, 9);
243 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL3,
244 L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
245 }
246 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
247 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
248
249 tmp = mmVML2PF0_VM_L2_CNTL4_DEFAULT;
250 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
251 VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
252 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL4,
253 VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
254 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL4,
255 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
256}
257
258static void mmhub_v9_4_enable_system_domain(struct amdgpu_device *adev,
259 int hubid)
260{
261 uint32_t tmp;
262
263 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
264 hubid * MMHUB_INSTANCE_REGISTER_OFFSET);
265 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
266 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
267 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT0_CNTL,
268 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
269 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT0_CNTL,
270 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
271}
272
273static void mmhub_v9_4_disable_identity_aperture(struct amdgpu_device *adev,
274 int hubid)
275{
276 WREG32_SOC15_OFFSET(MMHUB, 0,
277 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
278 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0XFFFFFFFF);
279 WREG32_SOC15_OFFSET(MMHUB, 0,
280 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
281 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0x0000000F);
282
283 WREG32_SOC15_OFFSET(MMHUB, 0,
284 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
285 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
286 WREG32_SOC15_OFFSET(MMHUB, 0,
287 mmVML2PF0_VM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
288 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
289
290 WREG32_SOC15_OFFSET(MMHUB, 0,
291 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
292 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
293 WREG32_SOC15_OFFSET(MMHUB, 0,
294 mmVML2PF0_VM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
295 hubid * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
296}
297
298static void mmhub_v9_4_setup_vmid_config(struct amdgpu_device *adev, int hubid)
299{
300 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
301 uint32_t tmp;
302 int i;
303
304 for (i = 0; i <= 14; i++) {
305 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
306 hubid * MMHUB_INSTANCE_REGISTER_OFFSET + i);
307 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
308 ENABLE_CONTEXT, 1);
309 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
310 PAGE_TABLE_DEPTH,
311 adev->vm_manager.num_level);
312 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
313 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
314 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
315 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
316 1);
317 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
318 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
319 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
320 VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
321 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
322 READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
323 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
324 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
325 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
326 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
327 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
328 PAGE_TABLE_BLOCK_SIZE,
329 adev->vm_manager.block_size - 9);
330 /* Send no-retry XNACK on fault to suppress VM fault storm. */
331 tmp = REG_SET_FIELD(tmp, VML2VC0_VM_CONTEXT1_CNTL,
332 RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
333 !amdgpu_noretry);
334 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2VC0_VM_CONTEXT1_CNTL,
335 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
336 i * hub->ctx_distance, tmp);
337 WREG32_SOC15_OFFSET(MMHUB, 0,
338 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
339 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
340 i * hub->ctx_addr_distance, 0);
341 WREG32_SOC15_OFFSET(MMHUB, 0,
342 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
343 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
344 i * hub->ctx_addr_distance, 0);
345 WREG32_SOC15_OFFSET(MMHUB, 0,
346 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
347 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
348 i * hub->ctx_addr_distance,
349 lower_32_bits(adev->vm_manager.max_pfn - 1));
350 WREG32_SOC15_OFFSET(MMHUB, 0,
351 mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
352 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
353 i * hub->ctx_addr_distance,
354 upper_32_bits(adev->vm_manager.max_pfn - 1));
355 }
356}
357
358static void mmhub_v9_4_program_invalidation(struct amdgpu_device *adev,
359 int hubid)
360{
361 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
362 unsigned i;
363
364 for (i = 0; i < 18; ++i) {
365 WREG32_SOC15_OFFSET(MMHUB, 0,
366 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
367 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
368 i * hub->eng_addr_distance,
369 0xffffffff);
370 WREG32_SOC15_OFFSET(MMHUB, 0,
371 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
372 hubid * MMHUB_INSTANCE_REGISTER_OFFSET +
373 i * hub->eng_addr_distance,
374 0x1f);
375 }
376}
377
378int mmhub_v9_4_gart_enable(struct amdgpu_device *adev)
379{
380 int i;
381
382 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
383 /* GART Enable. */
384 mmhub_v9_4_init_gart_aperture_regs(adev, i);
385 mmhub_v9_4_init_system_aperture_regs(adev, i);
386 mmhub_v9_4_init_tlb_regs(adev, i);
387 if (!amdgpu_sriov_vf(adev))
388 mmhub_v9_4_init_cache_regs(adev, i);
389
390 mmhub_v9_4_enable_system_domain(adev, i);
391 if (!amdgpu_sriov_vf(adev))
392 mmhub_v9_4_disable_identity_aperture(adev, i);
393 mmhub_v9_4_setup_vmid_config(adev, i);
394 mmhub_v9_4_program_invalidation(adev, i);
395 }
396
397 return 0;
398}
399
400void mmhub_v9_4_gart_disable(struct amdgpu_device *adev)
401{
402 struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
403 u32 tmp;
404 u32 i, j;
405
406 for (j = 0; j < MMHUB_NUM_INSTANCES; j++) {
407 /* Disable all tables */
408 for (i = 0; i < 16; i++)
409 WREG32_SOC15_OFFSET(MMHUB, 0,
410 mmVML2VC0_VM_CONTEXT0_CNTL,
411 j * MMHUB_INSTANCE_REGISTER_OFFSET +
412 i * hub->ctx_distance, 0);
413
414 /* Setup TLB control */
415 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
416 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
417 j * MMHUB_INSTANCE_REGISTER_OFFSET);
418 tmp = REG_SET_FIELD(tmp, VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
419 ENABLE_L1_TLB, 0);
420 tmp = REG_SET_FIELD(tmp,
421 VMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
422 ENABLE_ADVANCED_DRIVER_MODEL, 0);
423 WREG32_SOC15_OFFSET(MMHUB, 0,
424 mmVMSHAREDVC0_MC_VM_MX_L1_TLB_CNTL,
425 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
426
427 /* Setup L2 cache */
428 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
429 j * MMHUB_INSTANCE_REGISTER_OFFSET);
430 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_CNTL,
431 ENABLE_L2_CACHE, 0);
432 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL,
433 j * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
434 WREG32_SOC15_OFFSET(MMHUB, 0, mmVML2PF0_VM_L2_CNTL3,
435 j * MMHUB_INSTANCE_REGISTER_OFFSET, 0);
436 }
437}
438
439/**
440 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
441 *
442 * @adev: amdgpu_device pointer
443 * @value: true redirects VM faults to the default page
444 */
445void mmhub_v9_4_set_fault_enable_default(struct amdgpu_device *adev, bool value)
446{
447 u32 tmp;
448 int i;
449
450 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
451 tmp = RREG32_SOC15_OFFSET(MMHUB, 0,
452 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
453 i * MMHUB_INSTANCE_REGISTER_OFFSET);
454 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
455 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT,
456 value);
457 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
458 PDE0_PROTECTION_FAULT_ENABLE_DEFAULT,
459 value);
460 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
461 PDE1_PROTECTION_FAULT_ENABLE_DEFAULT,
462 value);
463 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
464 PDE2_PROTECTION_FAULT_ENABLE_DEFAULT,
465 value);
466 tmp = REG_SET_FIELD(tmp,
467 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
468 TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
469 value);
470 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
471 NACK_PROTECTION_FAULT_ENABLE_DEFAULT,
472 value);
473 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
474 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
475 value);
476 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
477 VALID_PROTECTION_FAULT_ENABLE_DEFAULT,
478 value);
479 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
480 READ_PROTECTION_FAULT_ENABLE_DEFAULT,
481 value);
482 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
483 WRITE_PROTECTION_FAULT_ENABLE_DEFAULT,
484 value);
485 tmp = REG_SET_FIELD(tmp, VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
486 EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT,
487 value);
488 if (!value) {
489 tmp = REG_SET_FIELD(tmp,
490 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
491 CRASH_ON_NO_RETRY_FAULT, 1);
492 tmp = REG_SET_FIELD(tmp,
493 VML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
494 CRASH_ON_RETRY_FAULT, 1);
495 }
496
497 WREG32_SOC15_OFFSET(MMHUB, 0,
498 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL,
499 i * MMHUB_INSTANCE_REGISTER_OFFSET, tmp);
500 }
501}
502
503void mmhub_v9_4_init(struct amdgpu_device *adev)
504{
505 struct amdgpu_vmhub *hub[MMHUB_NUM_INSTANCES] =
506 {&adev->vmhub[AMDGPU_MMHUB_0], &adev->vmhub[AMDGPU_MMHUB_1]};
507 int i;
508
509 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
510 hub[i]->ctx0_ptb_addr_lo32 =
511 SOC15_REG_OFFSET(MMHUB, 0,
512 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32) +
513 i * MMHUB_INSTANCE_REGISTER_OFFSET;
514 hub[i]->ctx0_ptb_addr_hi32 =
515 SOC15_REG_OFFSET(MMHUB, 0,
516 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32) +
517 i * MMHUB_INSTANCE_REGISTER_OFFSET;
518 hub[i]->vm_inv_eng0_sem =
519 SOC15_REG_OFFSET(MMHUB, 0,
520 mmVML2VC0_VM_INVALIDATE_ENG0_SEM) +
521 i * MMHUB_INSTANCE_REGISTER_OFFSET;
522 hub[i]->vm_inv_eng0_req =
523 SOC15_REG_OFFSET(MMHUB, 0,
524 mmVML2VC0_VM_INVALIDATE_ENG0_REQ) +
525 i * MMHUB_INSTANCE_REGISTER_OFFSET;
526 hub[i]->vm_inv_eng0_ack =
527 SOC15_REG_OFFSET(MMHUB, 0,
528 mmVML2VC0_VM_INVALIDATE_ENG0_ACK) +
529 i * MMHUB_INSTANCE_REGISTER_OFFSET;
530 hub[i]->vm_context0_cntl =
531 SOC15_REG_OFFSET(MMHUB, 0,
532 mmVML2VC0_VM_CONTEXT0_CNTL) +
533 i * MMHUB_INSTANCE_REGISTER_OFFSET;
534 hub[i]->vm_l2_pro_fault_status =
535 SOC15_REG_OFFSET(MMHUB, 0,
536 mmVML2PF0_VM_L2_PROTECTION_FAULT_STATUS) +
537 i * MMHUB_INSTANCE_REGISTER_OFFSET;
538 hub[i]->vm_l2_pro_fault_cntl =
539 SOC15_REG_OFFSET(MMHUB, 0,
540 mmVML2PF0_VM_L2_PROTECTION_FAULT_CNTL) +
541 i * MMHUB_INSTANCE_REGISTER_OFFSET;
542
543 hub[i]->ctx_distance = mmVML2VC0_VM_CONTEXT1_CNTL -
544 mmVML2VC0_VM_CONTEXT0_CNTL;
545 hub[i]->ctx_addr_distance = mmVML2VC0_VM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
546 mmVML2VC0_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
547 hub[i]->eng_distance = mmVML2VC0_VM_INVALIDATE_ENG1_REQ -
548 mmVML2VC0_VM_INVALIDATE_ENG0_REQ;
549 hub[i]->eng_addr_distance = mmVML2VC0_VM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
550 mmVML2VC0_VM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
551 }
552}
553
554static void mmhub_v9_4_update_medium_grain_clock_gating(struct amdgpu_device *adev,
555 bool enable)
556{
557 uint32_t def, data, def1, data1;
558 int i, j;
559 int dist = mmDAGB1_CNTL_MISC2 - mmDAGB0_CNTL_MISC2;
560
561 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
562 def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
563 mmATCL2_0_ATC_L2_MISC_CG,
564 i * MMHUB_INSTANCE_REGISTER_OFFSET);
565
566 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
567 data |= ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
568 else
569 data &= ~ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK;
570
571 if (def != data)
572 WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
573 i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
574
575 for (j = 0; j < 5; j++) {
576 def1 = data1 = RREG32_SOC15_OFFSET(MMHUB, 0,
577 mmDAGB0_CNTL_MISC2,
578 i * MMHUB_INSTANCE_REGISTER_OFFSET +
579 j * dist);
580 if (enable &&
581 (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)) {
582 data1 &=
583 ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
584 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
585 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
586 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
587 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
588 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
589 } else {
590 data1 |=
591 (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
592 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
593 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
594 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
595 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
596 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
597 }
598
599 if (def1 != data1)
600 WREG32_SOC15_OFFSET(MMHUB, 0,
601 mmDAGB0_CNTL_MISC2,
602 i * MMHUB_INSTANCE_REGISTER_OFFSET +
603 j * dist, data1);
604
605 if (i == 1 && j == 3)
606 break;
607 }
608 }
609}
610
611static void mmhub_v9_4_update_medium_grain_light_sleep(struct amdgpu_device *adev,
612 bool enable)
613{
614 uint32_t def, data;
615 int i;
616
617 for (i = 0; i < MMHUB_NUM_INSTANCES; i++) {
618 def = data = RREG32_SOC15_OFFSET(MMHUB, 0,
619 mmATCL2_0_ATC_L2_MISC_CG,
620 i * MMHUB_INSTANCE_REGISTER_OFFSET);
621
622 if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS))
623 data |= ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
624 else
625 data &= ~ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
626
627 if (def != data)
628 WREG32_SOC15_OFFSET(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG,
629 i * MMHUB_INSTANCE_REGISTER_OFFSET, data);
630 }
631}
632
633int mmhub_v9_4_set_clockgating(struct amdgpu_device *adev,
634 enum amd_clockgating_state state)
635{
636 if (amdgpu_sriov_vf(adev))
637 return 0;
638
639 switch (adev->asic_type) {
640 case CHIP_ARCTURUS:
641 mmhub_v9_4_update_medium_grain_clock_gating(adev,
642 state == AMD_CG_STATE_GATE);
643 mmhub_v9_4_update_medium_grain_light_sleep(adev,
644 state == AMD_CG_STATE_GATE);
645 break;
646 default:
647 break;
648 }
649
650 return 0;
651}
652
653void mmhub_v9_4_get_clockgating(struct amdgpu_device *adev, u32 *flags)
654{
655 int data, data1;
656
657 if (amdgpu_sriov_vf(adev))
658 *flags = 0;
659
660 /* AMD_CG_SUPPORT_MC_MGCG */
661 data = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
662
663 data1 = RREG32_SOC15(MMHUB, 0, mmATCL2_0_ATC_L2_MISC_CG);
664
665 if ((data & ATCL2_0_ATC_L2_MISC_CG__ENABLE_MASK) &&
666 !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
667 DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
668 DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
669 DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
670 DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
671 DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
672 *flags |= AMD_CG_SUPPORT_MC_MGCG;
673
674 /* AMD_CG_SUPPORT_MC_LS */
675 if (data & ATCL2_0_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
676 *flags |= AMD_CG_SUPPORT_MC_LS;
677}
678
679static const struct soc15_ras_field_entry mmhub_v9_4_ras_fields[] = {
680 /* MMHUB Range 0 */
681 { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
682 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
683 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
684 },
685 { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
686 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
687 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
688 },
689 { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
690 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
691 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
692 },
693 { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
694 SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
695 SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
696 },
697 { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
698 SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
699 SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
700 },
701 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
702 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
703 0, 0,
704 },
705 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
706 SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
707 0, 0,
708 },
709 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
710 SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
711 0, 0,
712 },
713 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
714 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
715 0, 0,
716 },
717 { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT),
718 SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
719 0, 0,
720 },
721 { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
722 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
723 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
724 },
725 { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
726 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
727 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
728 },
729 { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
730 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
731 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
732 },
733 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
734 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
735 0, 0,
736 },
737 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
738 SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
739 0, 0,
740 },
741 { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
742 0, 0,
743 SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
744 },
745 { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
746 0, 0,
747 SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
748 },
749 { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
750 0, 0,
751 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
752 },
753 { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
754 0, 0,
755 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
756 },
757 { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
758 0, 0,
759 SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
760 },
761 { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
762 0, 0,
763 SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
764 },
765 { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3),
766 0, 0,
767 SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
768 },
769 { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
770 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
771 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
772 },
773 { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
774 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT),
775 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT),
776 },
777 { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
778 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT),
779 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT),
780 },
781 { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2),
782 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT),
783 SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT),
784 },
785
786 /* MMHUB Range 1 */
787 { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
788 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
789 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
790 },
791 { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
792 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
793 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
794 },
795 { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
796 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
797 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
798 },
799 { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
800 SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
801 SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
802 },
803 { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
804 SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
805 SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
806 },
807 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
808 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
809 0, 0,
810 },
811 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
812 SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
813 0, 0,
814 },
815 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
816 SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
817 0, 0,
818 },
819 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
820 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
821 0, 0,
822 },
823 { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT),
824 SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
825 0, 0,
826 },
827 { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
828 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
829 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
830 },
831 { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
832 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
833 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
834 },
835 { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
836 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
837 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
838 },
839 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
840 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
841 0, 0,
842 },
843 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
844 SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
845 0, 0,
846 },
847 { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
848 0, 0,
849 SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
850 },
851 { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
852 0, 0,
853 SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
854 },
855 { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
856 0, 0,
857 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
858 },
859 { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
860 0, 0,
861 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
862 },
863 { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
864 0, 0,
865 SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
866 },
867 { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
868 0, 0,
869 SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
870 },
871 { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3),
872 0, 0,
873 SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
874 },
875 { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
876 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT),
877 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT),
878 },
879 { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
880 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT),
881 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT),
882 },
883 { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
884 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT),
885 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT),
886 },
887 { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2),
888 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT),
889 SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT),
890 },
891
892 /* MMHAB Range 2*/
893 { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
894 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
895 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
896 },
897 { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
898 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
899 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
900 },
901 { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
902 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
903 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
904 },
905 { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
906 SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
907 SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT),
908 },
909 { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
910 SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
911 SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT),
912 },
913 { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
914 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
915 0, 0,
916 },
917 { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
918 SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
919 0, 0,
920 },
921 { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
922 SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT),
923 0, 0,
924 },
925 { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
926 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
927 0, 0,
928 },
929 { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT),
930 SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
931 0, 0,
932 },
933 { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
934 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
935 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
936 },
937 { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
938 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
939 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
940 },
941 { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
942 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
943 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
944 },
945 { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
946 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
947 0, 0,
948 },
949 { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
950 SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
951 0, 0,
952 },
953 { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
954 0, 0,
955 SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
956 },
957 { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
958 0, 0,
959 SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
960 },
961 { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
962 0, 0,
963 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
964 },
965 { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
966 0, 0,
967 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
968 },
969 { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
970 0, 0,
971 SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
972 },
973 { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
974 0, 0,
975 SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
976 },
977 { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3),
978 0, 0,
979 SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
980 },
981 { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
982 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_SED_COUNT),
983 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D0MEM_DED_COUNT),
984 },
985 { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
986 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT),
987 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT),
988 },
989 { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
990 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT),
991 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT),
992 },
993 { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2),
994 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT),
995 SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT),
996 },
997
998 /* MMHUB Rang 3 */
999 { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1000 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1001 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1002 },
1003 { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1004 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1005 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1006 },
1007 { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1008 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1009 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1010 },
1011 { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1012 SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1013 SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1014 },
1015 { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1016 SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1017 SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1018 },
1019 { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1020 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1021 0, 0,
1022 },
1023 { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1024 SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1025 0, 0,
1026 },
1027 { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1028 SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1029 0, 0,
1030 },
1031 { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1032 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1033 0, 0,
1034 },
1035 { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT),
1036 SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1037 0, 0,
1038 },
1039 { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1040 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1041 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1042 },
1043 { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1044 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1045 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1046 },
1047 { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1048 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1049 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1050 },
1051 { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1052 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1053 0, 0,
1054 },
1055 { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1056 SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1057 0, 0,
1058 },
1059 { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1060 0, 0,
1061 SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1062 },
1063 { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1064 0, 0,
1065 SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1066 },
1067 { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1068 0, 0,
1069 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1070 },
1071 { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1072 0, 0,
1073 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1074 },
1075 { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1076 0, 0,
1077 SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1078 },
1079 { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1080 0, 0,
1081 SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1082 },
1083 { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3),
1084 0, 0,
1085 SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1086 },
1087 { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1088 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1089 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1090 },
1091 { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1092 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1093 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1094 },
1095 { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1096 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1097 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1098 },
1099 { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2),
1100 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1101 SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1102 },
1103
1104 /* MMHUB Range 4 */
1105 { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1106 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1107 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1108 },
1109 { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1110 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1111 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1112 },
1113 { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1114 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1115 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1116 },
1117 { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1118 SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1119 SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1120 },
1121 { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1122 SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1123 SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1124 },
1125 { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1126 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1127 0, 0,
1128 },
1129 { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1130 SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1131 0, 0,
1132 },
1133 { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1134 SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1135 0, 0,
1136 },
1137 { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1138 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1139 0, 0,
1140 },
1141 { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT),
1142 SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1143 0, 0,
1144 },
1145 { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1146 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1147 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1148 },
1149 { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1150 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1151 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1152 },
1153 { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1154 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1155 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1156 },
1157 { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1158 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1159 0, 0,
1160 },
1161 { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1162 SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1163 0, 0,
1164 },
1165 { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1166 0, 0,
1167 SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1168 },
1169 { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1170 0, 0,
1171 SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1172 },
1173 { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1174 0, 0,
1175 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1176 },
1177 { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1178 0, 0,
1179 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1180 },
1181 { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1182 0, 0,
1183 SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1184 },
1185 { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1186 0, 0,
1187 SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1188 },
1189 { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3),
1190 0, 0,
1191 SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1192 },
1193 { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1194 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1195 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1196 },
1197 { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1198 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1199 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1200 },
1201 { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1202 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1203 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1204 },
1205 { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2),
1206 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1207 SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1208 },
1209
1210 /* MMHUAB Range 5 */
1211 { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1212 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1213 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1214 },
1215 { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1216 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1217 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1218 },
1219 { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1220 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1221 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1222 },
1223 { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1224 SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1225 SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1226 },
1227 { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1228 SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1229 SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1230 },
1231 { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1232 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1233 0, 0,
1234 },
1235 { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1236 SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1237 0, 0,
1238 },
1239 { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1240 SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1241 0, 0,
1242 },
1243 { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1244 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1245 0, 0,
1246 },
1247 { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT),
1248 SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1249 0, 0,
1250 },
1251 { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1252 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1253 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1254 },
1255 { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1256 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1257 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1258 },
1259 { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1260 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1261 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1262 },
1263 { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1264 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1265 0, 0,
1266 },
1267 { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1268 SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1269 0, 0,
1270 },
1271 { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1272 0, 0,
1273 SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1274 },
1275 { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1276 0, 0,
1277 SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1278 },
1279 { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1280 0, 0,
1281 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1282 },
1283 { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1284 0, 0,
1285 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1286 },
1287 { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1288 0, 0,
1289 SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1290 },
1291 { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1292 0, 0,
1293 SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1294 },
1295 { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3),
1296 0, 0,
1297 SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1298 },
1299 { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1300 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1301 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1302 },
1303 { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1304 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1305 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1306 },
1307 { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1308 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1309 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1310 },
1311 { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2),
1312 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1313 SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1314 },
1315
1316 /* MMHUB Range 6 */
1317 { "MMEA6_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1318 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1319 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1320 },
1321 { "MMEA6_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1322 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1323 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1324 },
1325 { "MMEA6_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1326 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1327 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1328 },
1329 { "MMEA6_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1330 SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1331 SOC15_REG_FIELD(MMEA6_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1332 },
1333 { "MMEA6_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1334 SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1335 SOC15_REG_FIELD(MMEA6_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1336 },
1337 { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1338 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1339 0, 0,
1340 },
1341 { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1342 SOC15_REG_FIELD(MMEA6_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1343 0, 0,
1344 },
1345 { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1346 SOC15_REG_FIELD(MMEA6_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1347 0, 0,
1348 },
1349 { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1350 SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1351 0, 0,
1352 },
1353 { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT),
1354 SOC15_REG_FIELD(MMEA6_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1355 0, 0,
1356 },
1357 { "MMEA6_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1358 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1359 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1360 },
1361 { "MMEA6_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1362 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1363 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1364 },
1365 { "MMEA6_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1366 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1367 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1368 },
1369 { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1370 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1371 0, 0,
1372 },
1373 { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1374 SOC15_REG_FIELD(MMEA6_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1375 0, 0,
1376 },
1377 { "MMEA6_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1378 0, 0,
1379 SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1380 },
1381 { "MMEA6_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1382 0, 0,
1383 SOC15_REG_FIELD(MMEA6_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1384 },
1385 { "MMEA6_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1386 0, 0,
1387 SOC15_REG_FIELD(MMEA6_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1388 },
1389 { "MMEA6_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1390 0, 0,
1391 SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1392 },
1393 { "MMEA6_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1394 0, 0,
1395 SOC15_REG_FIELD(MMEA6_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1396 },
1397 { "MMEA6_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1398 0, 0,
1399 SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1400 },
1401 { "MMEA6_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3),
1402 0, 0,
1403 SOC15_REG_FIELD(MMEA6_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1404 },
1405 { "MMEA6_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1406 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1407 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1408 },
1409 { "MMEA6_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1410 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1411 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1412 },
1413 { "MMEA6_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1414 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1415 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1416 },
1417 { "MMEA6_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2),
1418 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1419 SOC15_REG_FIELD(MMEA6_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1420 },
1421
1422 /* MMHUB Range 7*/
1423 { "MMEA7_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1424 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1425 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1426 },
1427 { "MMEA7_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1428 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1429 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1430 },
1431 { "MMEA7_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1432 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1433 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1434 },
1435 { "MMEA7_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1436 SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1437 SOC15_REG_FIELD(MMEA7_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1438 },
1439 { "MMEA7_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1440 SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1441 SOC15_REG_FIELD(MMEA7_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1442 },
1443 { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1444 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1445 0, 0,
1446 },
1447 { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1448 SOC15_REG_FIELD(MMEA7_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1449 0, 0,
1450 },
1451 { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1452 SOC15_REG_FIELD(MMEA7_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1453 0, 0,
1454 },
1455 { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1456 SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1457 0, 0,
1458 },
1459 { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT),
1460 SOC15_REG_FIELD(MMEA7_EDC_CNT, IOWR_DATAMEM_SED_COUNT),
1461 0, 0,
1462 },
1463 { "MMEA7_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1464 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1465 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1466 },
1467 { "MMEA7_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1468 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1469 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1470 },
1471 { "MMEA7_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1472 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1473 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1474 },
1475 { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1476 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1477 0, 0,
1478 },
1479 { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1480 SOC15_REG_FIELD(MMEA7_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1481 0, 0,
1482 },
1483 { "MMEA7_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1484 0, 0,
1485 SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1486 },
1487 { "MMEA7_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1488 0, 0,
1489 SOC15_REG_FIELD(MMEA7_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1490 },
1491 { "MMEA7_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1492 0, 0,
1493 SOC15_REG_FIELD(MMEA7_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1494 },
1495 { "MMEA7_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1496 0, 0,
1497 SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1498 },
1499 { "MMEA7_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1500 0, 0,
1501 SOC15_REG_FIELD(MMEA7_EDC_CNT3, IOWR_DATAMEM_DED_COUNT),
1502 },
1503 { "MMEA7_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1504 0, 0,
1505 SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1506 },
1507 { "MMEA7_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3),
1508 0, 0,
1509 SOC15_REG_FIELD(MMEA7_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1510 },
1511 { "MMEA7_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1512 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1513 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1514 },
1515 { "MMEA7_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1516 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1517 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1518 },
1519 { "MMEA7_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1520 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1521 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1522 },
1523 { "MMEA7_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2),
1524 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1525 SOC15_REG_FIELD(MMEA7_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1526 }
1527};
1528
1529static const struct soc15_reg_entry mmhub_v9_4_edc_cnt_regs[] = {
1530 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT), 0, 0, 0 },
1531 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT2), 0, 0, 0 },
1532 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA0_EDC_CNT3), 0, 0, 0 },
1533 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT), 0, 0, 0 },
1534 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT2), 0, 0, 0 },
1535 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA1_EDC_CNT3), 0, 0, 0 },
1536 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT), 0, 0, 0 },
1537 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT2), 0, 0, 0 },
1538 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA2_EDC_CNT3), 0, 0, 0 },
1539 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT), 0, 0, 0 },
1540 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT2), 0, 0, 0 },
1541 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA3_EDC_CNT3), 0, 0, 0 },
1542 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT), 0, 0, 0 },
1543 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT2), 0, 0, 0 },
1544 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA4_EDC_CNT3), 0, 0, 0 },
1545 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT), 0, 0, 0 },
1546 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT2), 0, 0, 0 },
1547 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA5_EDC_CNT3), 0, 0, 0 },
1548 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT), 0, 0, 0 },
1549 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT2), 0, 0, 0 },
1550 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA6_EDC_CNT3), 0, 0, 0 },
1551 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT), 0, 0, 0 },
1552 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT2), 0, 0, 0 },
1553 { SOC15_REG_ENTRY(MMHUB, 0, mmMMEA7_EDC_CNT3), 0, 0, 0 },
1554};
1555
1556static int mmhub_v9_4_get_ras_error_count(struct amdgpu_device *adev,
1557 const struct soc15_reg_entry *reg,
1558 uint32_t value,
1559 uint32_t *sec_count,
1560 uint32_t *ded_count)
1561{
1562 uint32_t i;
1563 uint32_t sec_cnt, ded_cnt;
1564
1565 for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_ras_fields); i++) {
1566 if(mmhub_v9_4_ras_fields[i].reg_offset != reg->reg_offset)
1567 continue;
1568
1569 sec_cnt = (value &
1570 mmhub_v9_4_ras_fields[i].sec_count_mask) >>
1571 mmhub_v9_4_ras_fields[i].sec_count_shift;
1572 if (sec_cnt) {
1573 dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
1574 mmhub_v9_4_ras_fields[i].name,
1575 sec_cnt);
1576 *sec_count += sec_cnt;
1577 }
1578
1579 ded_cnt = (value &
1580 mmhub_v9_4_ras_fields[i].ded_count_mask) >>
1581 mmhub_v9_4_ras_fields[i].ded_count_shift;
1582 if (ded_cnt) {
1583 dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
1584 mmhub_v9_4_ras_fields[i].name,
1585 ded_cnt);
1586 *ded_count += ded_cnt;
1587 }
1588 }
1589
1590 return 0;
1591}
1592
1593static void mmhub_v9_4_query_ras_error_count(struct amdgpu_device *adev,
1594 void *ras_error_status)
1595{
1596 struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1597 uint32_t sec_count = 0, ded_count = 0;
1598 uint32_t i;
1599 uint32_t reg_value;
1600
1601 err_data->ue_count = 0;
1602 err_data->ce_count = 0;
1603
1604 for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++) {
1605 reg_value =
1606 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1607 if (reg_value)
1608 mmhub_v9_4_get_ras_error_count(adev, &mmhub_v9_4_edc_cnt_regs[i],
1609 reg_value, &sec_count, &ded_count);
1610 }
1611
1612 err_data->ce_count += sec_count;
1613 err_data->ue_count += ded_count;
1614}
1615
1616static void mmhub_v9_4_reset_ras_error_count(struct amdgpu_device *adev)
1617{
1618 uint32_t i;
1619
1620 /* read back edc counter registers to reset the counters to 0 */
1621 if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
1622 for (i = 0; i < ARRAY_SIZE(mmhub_v9_4_edc_cnt_regs); i++)
1623 RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v9_4_edc_cnt_regs[i]));
1624 }
1625}
1626
1627const struct amdgpu_mmhub_funcs mmhub_v9_4_funcs = {
1628 .ras_late_init = amdgpu_mmhub_ras_late_init,
1629 .query_ras_error_count = mmhub_v9_4_query_ras_error_count,
1630 .reset_ras_error_count = mmhub_v9_4_reset_ras_error_count,
1631};