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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23#include <drm/drmP.h>
24#include "amdgpu.h"
25#include "amdgpu_pm.h"
26#include "amdgpu_i2c.h"
27#include "vid.h"
28#include "atom.h"
29#include "amdgpu_atombios.h"
30#include "atombios_crtc.h"
31#include "atombios_encoders.h"
32#include "amdgpu_pll.h"
33#include "amdgpu_connectors.h"
34#include "dce_v11_0.h"
35
36#include "dce/dce_11_0_d.h"
37#include "dce/dce_11_0_sh_mask.h"
38#include "dce/dce_11_0_enum.h"
39#include "oss/oss_3_0_d.h"
40#include "oss/oss_3_0_sh_mask.h"
41#include "gmc/gmc_8_1_d.h"
42#include "gmc/gmc_8_1_sh_mask.h"
43
44static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
45static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
46
47static const u32 crtc_offsets[] =
48{
49 CRTC0_REGISTER_OFFSET,
50 CRTC1_REGISTER_OFFSET,
51 CRTC2_REGISTER_OFFSET,
52 CRTC3_REGISTER_OFFSET,
53 CRTC4_REGISTER_OFFSET,
54 CRTC5_REGISTER_OFFSET,
55 CRTC6_REGISTER_OFFSET
56};
57
58static const u32 hpd_offsets[] =
59{
60 HPD0_REGISTER_OFFSET,
61 HPD1_REGISTER_OFFSET,
62 HPD2_REGISTER_OFFSET,
63 HPD3_REGISTER_OFFSET,
64 HPD4_REGISTER_OFFSET,
65 HPD5_REGISTER_OFFSET
66};
67
68static const uint32_t dig_offsets[] = {
69 DIG0_REGISTER_OFFSET,
70 DIG1_REGISTER_OFFSET,
71 DIG2_REGISTER_OFFSET,
72 DIG3_REGISTER_OFFSET,
73 DIG4_REGISTER_OFFSET,
74 DIG5_REGISTER_OFFSET,
75 DIG6_REGISTER_OFFSET,
76 DIG7_REGISTER_OFFSET,
77 DIG8_REGISTER_OFFSET
78};
79
80static const struct {
81 uint32_t reg;
82 uint32_t vblank;
83 uint32_t vline;
84 uint32_t hpd;
85
86} interrupt_status_offsets[] = { {
87 .reg = mmDISP_INTERRUPT_STATUS,
88 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
89 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
90 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
91}, {
92 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
93 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
94 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
95 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
96}, {
97 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
98 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
99 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
100 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
101}, {
102 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
103 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
104 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
105 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
106}, {
107 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
108 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
109 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
110 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
111}, {
112 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
113 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
114 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
115 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
116} };
117
118static const u32 cz_golden_settings_a11[] =
119{
120 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
121 mmFBC_MISC, 0x1f311fff, 0x14300000,
122};
123
124static const u32 cz_mgcg_cgcg_init[] =
125{
126 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
127 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
128};
129
130static const u32 stoney_golden_settings_a11[] =
131{
132 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
133 mmFBC_MISC, 0x1f311fff, 0x14302000,
134};
135
136static const u32 polaris11_golden_settings_a11[] =
137{
138 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
139 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
140 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
141 mmFBC_MISC, 0x9f313fff, 0x14302008,
142 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
143};
144
145static const u32 polaris10_golden_settings_a11[] =
146{
147 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
148 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
149 mmFBC_MISC, 0x9f313fff, 0x14302008,
150 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
151};
152
153static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
154{
155 switch (adev->asic_type) {
156 case CHIP_CARRIZO:
157 amdgpu_device_program_register_sequence(adev,
158 cz_mgcg_cgcg_init,
159 ARRAY_SIZE(cz_mgcg_cgcg_init));
160 amdgpu_device_program_register_sequence(adev,
161 cz_golden_settings_a11,
162 ARRAY_SIZE(cz_golden_settings_a11));
163 break;
164 case CHIP_STONEY:
165 amdgpu_device_program_register_sequence(adev,
166 stoney_golden_settings_a11,
167 ARRAY_SIZE(stoney_golden_settings_a11));
168 break;
169 case CHIP_POLARIS11:
170 case CHIP_POLARIS12:
171 amdgpu_device_program_register_sequence(adev,
172 polaris11_golden_settings_a11,
173 ARRAY_SIZE(polaris11_golden_settings_a11));
174 break;
175 case CHIP_POLARIS10:
176 amdgpu_device_program_register_sequence(adev,
177 polaris10_golden_settings_a11,
178 ARRAY_SIZE(polaris10_golden_settings_a11));
179 break;
180 default:
181 break;
182 }
183}
184
185static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
186 u32 block_offset, u32 reg)
187{
188 unsigned long flags;
189 u32 r;
190
191 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
192 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
193 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
194 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
195
196 return r;
197}
198
199static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
200 u32 block_offset, u32 reg, u32 v)
201{
202 unsigned long flags;
203
204 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
205 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
206 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
207 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
208}
209
210static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
211{
212 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
213 return 0;
214 else
215 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
216}
217
218static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
219{
220 unsigned i;
221
222 /* Enable pflip interrupts */
223 for (i = 0; i < adev->mode_info.num_crtc; i++)
224 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
225}
226
227static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
228{
229 unsigned i;
230
231 /* Disable pflip interrupts */
232 for (i = 0; i < adev->mode_info.num_crtc; i++)
233 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
234}
235
236/**
237 * dce_v11_0_page_flip - pageflip callback.
238 *
239 * @adev: amdgpu_device pointer
240 * @crtc_id: crtc to cleanup pageflip on
241 * @crtc_base: new address of the crtc (GPU MC address)
242 *
243 * Triggers the actual pageflip by updating the primary
244 * surface base address.
245 */
246static void dce_v11_0_page_flip(struct amdgpu_device *adev,
247 int crtc_id, u64 crtc_base, bool async)
248{
249 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
250 u32 tmp;
251
252 /* flip immediate for async, default is vsync */
253 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
254 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
255 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
256 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
257 /* update the scanout addresses */
258 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
259 upper_32_bits(crtc_base));
260 /* writing to the low address triggers the update */
261 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
262 lower_32_bits(crtc_base));
263 /* post the write */
264 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
265}
266
267static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
268 u32 *vbl, u32 *position)
269{
270 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
271 return -EINVAL;
272
273 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
274 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
275
276 return 0;
277}
278
279/**
280 * dce_v11_0_hpd_sense - hpd sense callback.
281 *
282 * @adev: amdgpu_device pointer
283 * @hpd: hpd (hotplug detect) pin
284 *
285 * Checks if a digital monitor is connected (evergreen+).
286 * Returns true if connected, false if not connected.
287 */
288static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
289 enum amdgpu_hpd_id hpd)
290{
291 bool connected = false;
292
293 if (hpd >= adev->mode_info.num_hpd)
294 return connected;
295
296 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
297 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
298 connected = true;
299
300 return connected;
301}
302
303/**
304 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
305 *
306 * @adev: amdgpu_device pointer
307 * @hpd: hpd (hotplug detect) pin
308 *
309 * Set the polarity of the hpd pin (evergreen+).
310 */
311static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
312 enum amdgpu_hpd_id hpd)
313{
314 u32 tmp;
315 bool connected = dce_v11_0_hpd_sense(adev, hpd);
316
317 if (hpd >= adev->mode_info.num_hpd)
318 return;
319
320 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
321 if (connected)
322 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
323 else
324 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
325 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
326}
327
328/**
329 * dce_v11_0_hpd_init - hpd setup callback.
330 *
331 * @adev: amdgpu_device pointer
332 *
333 * Setup the hpd pins used by the card (evergreen+).
334 * Enable the pin, set the polarity, and enable the hpd interrupts.
335 */
336static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
337{
338 struct drm_device *dev = adev->ddev;
339 struct drm_connector *connector;
340 u32 tmp;
341
342 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
343 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
344
345 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
346 continue;
347
348 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
349 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
350 /* don't try to enable hpd on eDP or LVDS avoid breaking the
351 * aux dp channel on imac and help (but not completely fix)
352 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
353 * also avoid interrupt storms during dpms.
354 */
355 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
356 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
357 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
358 continue;
359 }
360
361 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
362 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
363 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
364
365 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
366 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
367 DC_HPD_CONNECT_INT_DELAY,
368 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
369 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
370 DC_HPD_DISCONNECT_INT_DELAY,
371 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
372 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
373
374 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
375 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
376 }
377}
378
379/**
380 * dce_v11_0_hpd_fini - hpd tear down callback.
381 *
382 * @adev: amdgpu_device pointer
383 *
384 * Tear down the hpd pins used by the card (evergreen+).
385 * Disable the hpd interrupts.
386 */
387static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
388{
389 struct drm_device *dev = adev->ddev;
390 struct drm_connector *connector;
391 u32 tmp;
392
393 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
394 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
395
396 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
397 continue;
398
399 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
400 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
401 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
402
403 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
404 }
405}
406
407static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
408{
409 return mmDC_GPIO_HPD_A;
410}
411
412static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
413{
414 u32 crtc_hung = 0;
415 u32 crtc_status[6];
416 u32 i, j, tmp;
417
418 for (i = 0; i < adev->mode_info.num_crtc; i++) {
419 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
420 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
421 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
422 crtc_hung |= (1 << i);
423 }
424 }
425
426 for (j = 0; j < 10; j++) {
427 for (i = 0; i < adev->mode_info.num_crtc; i++) {
428 if (crtc_hung & (1 << i)) {
429 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
430 if (tmp != crtc_status[i])
431 crtc_hung &= ~(1 << i);
432 }
433 }
434 if (crtc_hung == 0)
435 return false;
436 udelay(100);
437 }
438
439 return true;
440}
441
442static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
443 bool render)
444{
445 u32 tmp;
446
447 /* Lockout access through VGA aperture*/
448 tmp = RREG32(mmVGA_HDP_CONTROL);
449 if (render)
450 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
451 else
452 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
453 WREG32(mmVGA_HDP_CONTROL, tmp);
454
455 /* disable VGA render */
456 tmp = RREG32(mmVGA_RENDER_CONTROL);
457 if (render)
458 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
459 else
460 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
461 WREG32(mmVGA_RENDER_CONTROL, tmp);
462}
463
464static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
465{
466 int num_crtc = 0;
467
468 switch (adev->asic_type) {
469 case CHIP_CARRIZO:
470 num_crtc = 3;
471 break;
472 case CHIP_STONEY:
473 num_crtc = 2;
474 break;
475 case CHIP_POLARIS10:
476 num_crtc = 6;
477 break;
478 case CHIP_POLARIS11:
479 case CHIP_POLARIS12:
480 num_crtc = 5;
481 break;
482 default:
483 num_crtc = 0;
484 }
485 return num_crtc;
486}
487
488void dce_v11_0_disable_dce(struct amdgpu_device *adev)
489{
490 /*Disable VGA render and enabled crtc, if has DCE engine*/
491 if (amdgpu_atombios_has_dce_engine_info(adev)) {
492 u32 tmp;
493 int crtc_enabled, i;
494
495 dce_v11_0_set_vga_render_state(adev, false);
496
497 /*Disable crtc*/
498 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
499 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
500 CRTC_CONTROL, CRTC_MASTER_EN);
501 if (crtc_enabled) {
502 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
503 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
504 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
505 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
506 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
507 }
508 }
509 }
510}
511
512static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
513{
514 struct drm_device *dev = encoder->dev;
515 struct amdgpu_device *adev = dev->dev_private;
516 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
517 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
518 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
519 int bpc = 0;
520 u32 tmp = 0;
521 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
522
523 if (connector) {
524 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
525 bpc = amdgpu_connector_get_monitor_bpc(connector);
526 dither = amdgpu_connector->dither;
527 }
528
529 /* LVDS/eDP FMT is set up by atom */
530 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
531 return;
532
533 /* not needed for analog */
534 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
535 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
536 return;
537
538 if (bpc == 0)
539 return;
540
541 switch (bpc) {
542 case 6:
543 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
544 /* XXX sort out optimal dither settings */
545 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
546 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
547 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
548 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
549 } else {
550 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
551 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
552 }
553 break;
554 case 8:
555 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
556 /* XXX sort out optimal dither settings */
557 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
558 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
559 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
560 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
561 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
562 } else {
563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
565 }
566 break;
567 case 10:
568 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
569 /* XXX sort out optimal dither settings */
570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
572 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
573 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
574 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
575 } else {
576 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
577 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
578 }
579 break;
580 default:
581 /* not needed */
582 break;
583 }
584
585 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
586}
587
588
589/* display watermark setup */
590/**
591 * dce_v11_0_line_buffer_adjust - Set up the line buffer
592 *
593 * @adev: amdgpu_device pointer
594 * @amdgpu_crtc: the selected display controller
595 * @mode: the current display mode on the selected display
596 * controller
597 *
598 * Setup up the line buffer allocation for
599 * the selected display controller (CIK).
600 * Returns the line buffer size in pixels.
601 */
602static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
603 struct amdgpu_crtc *amdgpu_crtc,
604 struct drm_display_mode *mode)
605{
606 u32 tmp, buffer_alloc, i, mem_cfg;
607 u32 pipe_offset = amdgpu_crtc->crtc_id;
608 /*
609 * Line Buffer Setup
610 * There are 6 line buffers, one for each display controllers.
611 * There are 3 partitions per LB. Select the number of partitions
612 * to enable based on the display width. For display widths larger
613 * than 4096, you need use to use 2 display controllers and combine
614 * them using the stereo blender.
615 */
616 if (amdgpu_crtc->base.enabled && mode) {
617 if (mode->crtc_hdisplay < 1920) {
618 mem_cfg = 1;
619 buffer_alloc = 2;
620 } else if (mode->crtc_hdisplay < 2560) {
621 mem_cfg = 2;
622 buffer_alloc = 2;
623 } else if (mode->crtc_hdisplay < 4096) {
624 mem_cfg = 0;
625 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
626 } else {
627 DRM_DEBUG_KMS("Mode too big for LB!\n");
628 mem_cfg = 0;
629 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
630 }
631 } else {
632 mem_cfg = 1;
633 buffer_alloc = 0;
634 }
635
636 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
637 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
638 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
639
640 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
641 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
642 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
643
644 for (i = 0; i < adev->usec_timeout; i++) {
645 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
646 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
647 break;
648 udelay(1);
649 }
650
651 if (amdgpu_crtc->base.enabled && mode) {
652 switch (mem_cfg) {
653 case 0:
654 default:
655 return 4096 * 2;
656 case 1:
657 return 1920 * 2;
658 case 2:
659 return 2560 * 2;
660 }
661 }
662
663 /* controller not enabled, so no lb used */
664 return 0;
665}
666
667/**
668 * cik_get_number_of_dram_channels - get the number of dram channels
669 *
670 * @adev: amdgpu_device pointer
671 *
672 * Look up the number of video ram channels (CIK).
673 * Used for display watermark bandwidth calculations
674 * Returns the number of dram channels
675 */
676static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
677{
678 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
679
680 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
681 case 0:
682 default:
683 return 1;
684 case 1:
685 return 2;
686 case 2:
687 return 4;
688 case 3:
689 return 8;
690 case 4:
691 return 3;
692 case 5:
693 return 6;
694 case 6:
695 return 10;
696 case 7:
697 return 12;
698 case 8:
699 return 16;
700 }
701}
702
703struct dce10_wm_params {
704 u32 dram_channels; /* number of dram channels */
705 u32 yclk; /* bandwidth per dram data pin in kHz */
706 u32 sclk; /* engine clock in kHz */
707 u32 disp_clk; /* display clock in kHz */
708 u32 src_width; /* viewport width */
709 u32 active_time; /* active display time in ns */
710 u32 blank_time; /* blank time in ns */
711 bool interlaced; /* mode is interlaced */
712 fixed20_12 vsc; /* vertical scale ratio */
713 u32 num_heads; /* number of active crtcs */
714 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
715 u32 lb_size; /* line buffer allocated to pipe */
716 u32 vtaps; /* vertical scaler taps */
717};
718
719/**
720 * dce_v11_0_dram_bandwidth - get the dram bandwidth
721 *
722 * @wm: watermark calculation data
723 *
724 * Calculate the raw dram bandwidth (CIK).
725 * Used for display watermark bandwidth calculations
726 * Returns the dram bandwidth in MBytes/s
727 */
728static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
729{
730 /* Calculate raw DRAM Bandwidth */
731 fixed20_12 dram_efficiency; /* 0.7 */
732 fixed20_12 yclk, dram_channels, bandwidth;
733 fixed20_12 a;
734
735 a.full = dfixed_const(1000);
736 yclk.full = dfixed_const(wm->yclk);
737 yclk.full = dfixed_div(yclk, a);
738 dram_channels.full = dfixed_const(wm->dram_channels * 4);
739 a.full = dfixed_const(10);
740 dram_efficiency.full = dfixed_const(7);
741 dram_efficiency.full = dfixed_div(dram_efficiency, a);
742 bandwidth.full = dfixed_mul(dram_channels, yclk);
743 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
744
745 return dfixed_trunc(bandwidth);
746}
747
748/**
749 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
750 *
751 * @wm: watermark calculation data
752 *
753 * Calculate the dram bandwidth used for display (CIK).
754 * Used for display watermark bandwidth calculations
755 * Returns the dram bandwidth for display in MBytes/s
756 */
757static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
758{
759 /* Calculate DRAM Bandwidth and the part allocated to display. */
760 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
761 fixed20_12 yclk, dram_channels, bandwidth;
762 fixed20_12 a;
763
764 a.full = dfixed_const(1000);
765 yclk.full = dfixed_const(wm->yclk);
766 yclk.full = dfixed_div(yclk, a);
767 dram_channels.full = dfixed_const(wm->dram_channels * 4);
768 a.full = dfixed_const(10);
769 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
770 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
771 bandwidth.full = dfixed_mul(dram_channels, yclk);
772 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
773
774 return dfixed_trunc(bandwidth);
775}
776
777/**
778 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
779 *
780 * @wm: watermark calculation data
781 *
782 * Calculate the data return bandwidth used for display (CIK).
783 * Used for display watermark bandwidth calculations
784 * Returns the data return bandwidth in MBytes/s
785 */
786static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
787{
788 /* Calculate the display Data return Bandwidth */
789 fixed20_12 return_efficiency; /* 0.8 */
790 fixed20_12 sclk, bandwidth;
791 fixed20_12 a;
792
793 a.full = dfixed_const(1000);
794 sclk.full = dfixed_const(wm->sclk);
795 sclk.full = dfixed_div(sclk, a);
796 a.full = dfixed_const(10);
797 return_efficiency.full = dfixed_const(8);
798 return_efficiency.full = dfixed_div(return_efficiency, a);
799 a.full = dfixed_const(32);
800 bandwidth.full = dfixed_mul(a, sclk);
801 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
802
803 return dfixed_trunc(bandwidth);
804}
805
806/**
807 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
808 *
809 * @wm: watermark calculation data
810 *
811 * Calculate the dmif bandwidth used for display (CIK).
812 * Used for display watermark bandwidth calculations
813 * Returns the dmif bandwidth in MBytes/s
814 */
815static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
816{
817 /* Calculate the DMIF Request Bandwidth */
818 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
819 fixed20_12 disp_clk, bandwidth;
820 fixed20_12 a, b;
821
822 a.full = dfixed_const(1000);
823 disp_clk.full = dfixed_const(wm->disp_clk);
824 disp_clk.full = dfixed_div(disp_clk, a);
825 a.full = dfixed_const(32);
826 b.full = dfixed_mul(a, disp_clk);
827
828 a.full = dfixed_const(10);
829 disp_clk_request_efficiency.full = dfixed_const(8);
830 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
831
832 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
833
834 return dfixed_trunc(bandwidth);
835}
836
837/**
838 * dce_v11_0_available_bandwidth - get the min available bandwidth
839 *
840 * @wm: watermark calculation data
841 *
842 * Calculate the min available bandwidth used for display (CIK).
843 * Used for display watermark bandwidth calculations
844 * Returns the min available bandwidth in MBytes/s
845 */
846static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
847{
848 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
849 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
850 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
851 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
852
853 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
854}
855
856/**
857 * dce_v11_0_average_bandwidth - get the average available bandwidth
858 *
859 * @wm: watermark calculation data
860 *
861 * Calculate the average available bandwidth used for display (CIK).
862 * Used for display watermark bandwidth calculations
863 * Returns the average available bandwidth in MBytes/s
864 */
865static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
866{
867 /* Calculate the display mode Average Bandwidth
868 * DisplayMode should contain the source and destination dimensions,
869 * timing, etc.
870 */
871 fixed20_12 bpp;
872 fixed20_12 line_time;
873 fixed20_12 src_width;
874 fixed20_12 bandwidth;
875 fixed20_12 a;
876
877 a.full = dfixed_const(1000);
878 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
879 line_time.full = dfixed_div(line_time, a);
880 bpp.full = dfixed_const(wm->bytes_per_pixel);
881 src_width.full = dfixed_const(wm->src_width);
882 bandwidth.full = dfixed_mul(src_width, bpp);
883 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
884 bandwidth.full = dfixed_div(bandwidth, line_time);
885
886 return dfixed_trunc(bandwidth);
887}
888
889/**
890 * dce_v11_0_latency_watermark - get the latency watermark
891 *
892 * @wm: watermark calculation data
893 *
894 * Calculate the latency watermark (CIK).
895 * Used for display watermark bandwidth calculations
896 * Returns the latency watermark in ns
897 */
898static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
899{
900 /* First calculate the latency in ns */
901 u32 mc_latency = 2000; /* 2000 ns. */
902 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
903 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
904 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
905 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
906 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
907 (wm->num_heads * cursor_line_pair_return_time);
908 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
909 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
910 u32 tmp, dmif_size = 12288;
911 fixed20_12 a, b, c;
912
913 if (wm->num_heads == 0)
914 return 0;
915
916 a.full = dfixed_const(2);
917 b.full = dfixed_const(1);
918 if ((wm->vsc.full > a.full) ||
919 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
920 (wm->vtaps >= 5) ||
921 ((wm->vsc.full >= a.full) && wm->interlaced))
922 max_src_lines_per_dst_line = 4;
923 else
924 max_src_lines_per_dst_line = 2;
925
926 a.full = dfixed_const(available_bandwidth);
927 b.full = dfixed_const(wm->num_heads);
928 a.full = dfixed_div(a, b);
929 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
930 tmp = min(dfixed_trunc(a), tmp);
931
932 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
933
934 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
935 b.full = dfixed_const(1000);
936 c.full = dfixed_const(lb_fill_bw);
937 b.full = dfixed_div(c, b);
938 a.full = dfixed_div(a, b);
939 line_fill_time = dfixed_trunc(a);
940
941 if (line_fill_time < wm->active_time)
942 return latency;
943 else
944 return latency + (line_fill_time - wm->active_time);
945
946}
947
948/**
949 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
950 * average and available dram bandwidth
951 *
952 * @wm: watermark calculation data
953 *
954 * Check if the display average bandwidth fits in the display
955 * dram bandwidth (CIK).
956 * Used for display watermark bandwidth calculations
957 * Returns true if the display fits, false if not.
958 */
959static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
960{
961 if (dce_v11_0_average_bandwidth(wm) <=
962 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
963 return true;
964 else
965 return false;
966}
967
968/**
969 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
970 * average and available bandwidth
971 *
972 * @wm: watermark calculation data
973 *
974 * Check if the display average bandwidth fits in the display
975 * available bandwidth (CIK).
976 * Used for display watermark bandwidth calculations
977 * Returns true if the display fits, false if not.
978 */
979static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
980{
981 if (dce_v11_0_average_bandwidth(wm) <=
982 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
983 return true;
984 else
985 return false;
986}
987
988/**
989 * dce_v11_0_check_latency_hiding - check latency hiding
990 *
991 * @wm: watermark calculation data
992 *
993 * Check latency hiding (CIK).
994 * Used for display watermark bandwidth calculations
995 * Returns true if the display fits, false if not.
996 */
997static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
998{
999 u32 lb_partitions = wm->lb_size / wm->src_width;
1000 u32 line_time = wm->active_time + wm->blank_time;
1001 u32 latency_tolerant_lines;
1002 u32 latency_hiding;
1003 fixed20_12 a;
1004
1005 a.full = dfixed_const(1);
1006 if (wm->vsc.full > a.full)
1007 latency_tolerant_lines = 1;
1008 else {
1009 if (lb_partitions <= (wm->vtaps + 1))
1010 latency_tolerant_lines = 1;
1011 else
1012 latency_tolerant_lines = 2;
1013 }
1014
1015 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1016
1017 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1018 return true;
1019 else
1020 return false;
1021}
1022
1023/**
1024 * dce_v11_0_program_watermarks - program display watermarks
1025 *
1026 * @adev: amdgpu_device pointer
1027 * @amdgpu_crtc: the selected display controller
1028 * @lb_size: line buffer size
1029 * @num_heads: number of display controllers in use
1030 *
1031 * Calculate and program the display watermarks for the
1032 * selected display controller (CIK).
1033 */
1034static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1035 struct amdgpu_crtc *amdgpu_crtc,
1036 u32 lb_size, u32 num_heads)
1037{
1038 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1039 struct dce10_wm_params wm_low, wm_high;
1040 u32 active_time;
1041 u32 line_time = 0;
1042 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1043 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1044
1045 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1046 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1047 (u32)mode->clock);
1048 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1049 (u32)mode->clock);
1050 line_time = min(line_time, (u32)65535);
1051
1052 /* watermark for high clocks */
1053 if (adev->pm.dpm_enabled) {
1054 wm_high.yclk =
1055 amdgpu_dpm_get_mclk(adev, false) * 10;
1056 wm_high.sclk =
1057 amdgpu_dpm_get_sclk(adev, false) * 10;
1058 } else {
1059 wm_high.yclk = adev->pm.current_mclk * 10;
1060 wm_high.sclk = adev->pm.current_sclk * 10;
1061 }
1062
1063 wm_high.disp_clk = mode->clock;
1064 wm_high.src_width = mode->crtc_hdisplay;
1065 wm_high.active_time = active_time;
1066 wm_high.blank_time = line_time - wm_high.active_time;
1067 wm_high.interlaced = false;
1068 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1069 wm_high.interlaced = true;
1070 wm_high.vsc = amdgpu_crtc->vsc;
1071 wm_high.vtaps = 1;
1072 if (amdgpu_crtc->rmx_type != RMX_OFF)
1073 wm_high.vtaps = 2;
1074 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1075 wm_high.lb_size = lb_size;
1076 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1077 wm_high.num_heads = num_heads;
1078
1079 /* set for high clocks */
1080 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1081
1082 /* possibly force display priority to high */
1083 /* should really do this at mode validation time... */
1084 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1085 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1086 !dce_v11_0_check_latency_hiding(&wm_high) ||
1087 (adev->mode_info.disp_priority == 2)) {
1088 DRM_DEBUG_KMS("force priority to high\n");
1089 }
1090
1091 /* watermark for low clocks */
1092 if (adev->pm.dpm_enabled) {
1093 wm_low.yclk =
1094 amdgpu_dpm_get_mclk(adev, true) * 10;
1095 wm_low.sclk =
1096 amdgpu_dpm_get_sclk(adev, true) * 10;
1097 } else {
1098 wm_low.yclk = adev->pm.current_mclk * 10;
1099 wm_low.sclk = adev->pm.current_sclk * 10;
1100 }
1101
1102 wm_low.disp_clk = mode->clock;
1103 wm_low.src_width = mode->crtc_hdisplay;
1104 wm_low.active_time = active_time;
1105 wm_low.blank_time = line_time - wm_low.active_time;
1106 wm_low.interlaced = false;
1107 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1108 wm_low.interlaced = true;
1109 wm_low.vsc = amdgpu_crtc->vsc;
1110 wm_low.vtaps = 1;
1111 if (amdgpu_crtc->rmx_type != RMX_OFF)
1112 wm_low.vtaps = 2;
1113 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1114 wm_low.lb_size = lb_size;
1115 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1116 wm_low.num_heads = num_heads;
1117
1118 /* set for low clocks */
1119 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1120
1121 /* possibly force display priority to high */
1122 /* should really do this at mode validation time... */
1123 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1124 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1125 !dce_v11_0_check_latency_hiding(&wm_low) ||
1126 (adev->mode_info.disp_priority == 2)) {
1127 DRM_DEBUG_KMS("force priority to high\n");
1128 }
1129 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1130 }
1131
1132 /* select wm A */
1133 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1134 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1135 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1136 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1137 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1138 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1139 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1140 /* select wm B */
1141 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1142 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1143 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1144 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1145 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1146 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1147 /* restore original selection */
1148 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1149
1150 /* save values for DPM */
1151 amdgpu_crtc->line_time = line_time;
1152 amdgpu_crtc->wm_high = latency_watermark_a;
1153 amdgpu_crtc->wm_low = latency_watermark_b;
1154 /* Save number of lines the linebuffer leads before the scanout */
1155 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1156}
1157
1158/**
1159 * dce_v11_0_bandwidth_update - program display watermarks
1160 *
1161 * @adev: amdgpu_device pointer
1162 *
1163 * Calculate and program the display watermarks and line
1164 * buffer allocation (CIK).
1165 */
1166static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1167{
1168 struct drm_display_mode *mode = NULL;
1169 u32 num_heads = 0, lb_size;
1170 int i;
1171
1172 amdgpu_display_update_priority(adev);
1173
1174 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1175 if (adev->mode_info.crtcs[i]->base.enabled)
1176 num_heads++;
1177 }
1178 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1179 mode = &adev->mode_info.crtcs[i]->base.mode;
1180 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1181 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1182 lb_size, num_heads);
1183 }
1184}
1185
1186static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1187{
1188 int i;
1189 u32 offset, tmp;
1190
1191 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1192 offset = adev->mode_info.audio.pin[i].offset;
1193 tmp = RREG32_AUDIO_ENDPT(offset,
1194 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1195 if (((tmp &
1196 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1197 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1198 adev->mode_info.audio.pin[i].connected = false;
1199 else
1200 adev->mode_info.audio.pin[i].connected = true;
1201 }
1202}
1203
1204static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1205{
1206 int i;
1207
1208 dce_v11_0_audio_get_connected_pins(adev);
1209
1210 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1211 if (adev->mode_info.audio.pin[i].connected)
1212 return &adev->mode_info.audio.pin[i];
1213 }
1214 DRM_ERROR("No connected audio pins found!\n");
1215 return NULL;
1216}
1217
1218static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1219{
1220 struct amdgpu_device *adev = encoder->dev->dev_private;
1221 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1222 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1223 u32 tmp;
1224
1225 if (!dig || !dig->afmt || !dig->afmt->pin)
1226 return;
1227
1228 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1229 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1230 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1231}
1232
1233static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1234 struct drm_display_mode *mode)
1235{
1236 struct amdgpu_device *adev = encoder->dev->dev_private;
1237 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1238 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1239 struct drm_connector *connector;
1240 struct amdgpu_connector *amdgpu_connector = NULL;
1241 u32 tmp;
1242 int interlace = 0;
1243
1244 if (!dig || !dig->afmt || !dig->afmt->pin)
1245 return;
1246
1247 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1248 if (connector->encoder == encoder) {
1249 amdgpu_connector = to_amdgpu_connector(connector);
1250 break;
1251 }
1252 }
1253
1254 if (!amdgpu_connector) {
1255 DRM_ERROR("Couldn't find encoder's connector\n");
1256 return;
1257 }
1258
1259 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1260 interlace = 1;
1261 if (connector->latency_present[interlace]) {
1262 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1263 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1264 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1265 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1266 } else {
1267 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1268 VIDEO_LIPSYNC, 0);
1269 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1270 AUDIO_LIPSYNC, 0);
1271 }
1272 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1273 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1274}
1275
1276static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1277{
1278 struct amdgpu_device *adev = encoder->dev->dev_private;
1279 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1280 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1281 struct drm_connector *connector;
1282 struct amdgpu_connector *amdgpu_connector = NULL;
1283 u32 tmp;
1284 u8 *sadb = NULL;
1285 int sad_count;
1286
1287 if (!dig || !dig->afmt || !dig->afmt->pin)
1288 return;
1289
1290 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1291 if (connector->encoder == encoder) {
1292 amdgpu_connector = to_amdgpu_connector(connector);
1293 break;
1294 }
1295 }
1296
1297 if (!amdgpu_connector) {
1298 DRM_ERROR("Couldn't find encoder's connector\n");
1299 return;
1300 }
1301
1302 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1303 if (sad_count < 0) {
1304 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1305 sad_count = 0;
1306 }
1307
1308 /* program the speaker allocation */
1309 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1310 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1311 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1312 DP_CONNECTION, 0);
1313 /* set HDMI mode */
1314 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1315 HDMI_CONNECTION, 1);
1316 if (sad_count)
1317 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1318 SPEAKER_ALLOCATION, sadb[0]);
1319 else
1320 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1321 SPEAKER_ALLOCATION, 5); /* stereo */
1322 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1323 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1324
1325 kfree(sadb);
1326}
1327
1328static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1329{
1330 struct amdgpu_device *adev = encoder->dev->dev_private;
1331 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1332 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1333 struct drm_connector *connector;
1334 struct amdgpu_connector *amdgpu_connector = NULL;
1335 struct cea_sad *sads;
1336 int i, sad_count;
1337
1338 static const u16 eld_reg_to_type[][2] = {
1339 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1340 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1341 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1342 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1343 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1344 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1345 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1346 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1347 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1348 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1349 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1350 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1351 };
1352
1353 if (!dig || !dig->afmt || !dig->afmt->pin)
1354 return;
1355
1356 list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
1357 if (connector->encoder == encoder) {
1358 amdgpu_connector = to_amdgpu_connector(connector);
1359 break;
1360 }
1361 }
1362
1363 if (!amdgpu_connector) {
1364 DRM_ERROR("Couldn't find encoder's connector\n");
1365 return;
1366 }
1367
1368 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1369 if (sad_count <= 0) {
1370 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1371 return;
1372 }
1373 BUG_ON(!sads);
1374
1375 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1376 u32 tmp = 0;
1377 u8 stereo_freqs = 0;
1378 int max_channels = -1;
1379 int j;
1380
1381 for (j = 0; j < sad_count; j++) {
1382 struct cea_sad *sad = &sads[j];
1383
1384 if (sad->format == eld_reg_to_type[i][1]) {
1385 if (sad->channels > max_channels) {
1386 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1387 MAX_CHANNELS, sad->channels);
1388 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1389 DESCRIPTOR_BYTE_2, sad->byte2);
1390 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1391 SUPPORTED_FREQUENCIES, sad->freq);
1392 max_channels = sad->channels;
1393 }
1394
1395 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1396 stereo_freqs |= sad->freq;
1397 else
1398 break;
1399 }
1400 }
1401
1402 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1403 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1404 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1405 }
1406
1407 kfree(sads);
1408}
1409
1410static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1411 struct amdgpu_audio_pin *pin,
1412 bool enable)
1413{
1414 if (!pin)
1415 return;
1416
1417 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1418 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1419}
1420
1421static const u32 pin_offsets[] =
1422{
1423 AUD0_REGISTER_OFFSET,
1424 AUD1_REGISTER_OFFSET,
1425 AUD2_REGISTER_OFFSET,
1426 AUD3_REGISTER_OFFSET,
1427 AUD4_REGISTER_OFFSET,
1428 AUD5_REGISTER_OFFSET,
1429 AUD6_REGISTER_OFFSET,
1430 AUD7_REGISTER_OFFSET,
1431};
1432
1433static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1434{
1435 int i;
1436
1437 if (!amdgpu_audio)
1438 return 0;
1439
1440 adev->mode_info.audio.enabled = true;
1441
1442 switch (adev->asic_type) {
1443 case CHIP_CARRIZO:
1444 case CHIP_STONEY:
1445 adev->mode_info.audio.num_pins = 7;
1446 break;
1447 case CHIP_POLARIS10:
1448 adev->mode_info.audio.num_pins = 8;
1449 break;
1450 case CHIP_POLARIS11:
1451 case CHIP_POLARIS12:
1452 adev->mode_info.audio.num_pins = 6;
1453 break;
1454 default:
1455 return -EINVAL;
1456 }
1457
1458 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1459 adev->mode_info.audio.pin[i].channels = -1;
1460 adev->mode_info.audio.pin[i].rate = -1;
1461 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1462 adev->mode_info.audio.pin[i].status_bits = 0;
1463 adev->mode_info.audio.pin[i].category_code = 0;
1464 adev->mode_info.audio.pin[i].connected = false;
1465 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1466 adev->mode_info.audio.pin[i].id = i;
1467 /* disable audio. it will be set up later */
1468 /* XXX remove once we switch to ip funcs */
1469 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1470 }
1471
1472 return 0;
1473}
1474
1475static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1476{
1477 int i;
1478
1479 if (!amdgpu_audio)
1480 return;
1481
1482 if (!adev->mode_info.audio.enabled)
1483 return;
1484
1485 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1486 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1487
1488 adev->mode_info.audio.enabled = false;
1489}
1490
1491/*
1492 * update the N and CTS parameters for a given pixel clock rate
1493 */
1494static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1495{
1496 struct drm_device *dev = encoder->dev;
1497 struct amdgpu_device *adev = dev->dev_private;
1498 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1499 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1500 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1501 u32 tmp;
1502
1503 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1504 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1505 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1506 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1507 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1508 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1509
1510 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1511 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1512 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1513 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1514 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1515 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1516
1517 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1518 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1519 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1520 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1521 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1522 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1523
1524}
1525
1526/*
1527 * build a HDMI Video Info Frame
1528 */
1529static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1530 void *buffer, size_t size)
1531{
1532 struct drm_device *dev = encoder->dev;
1533 struct amdgpu_device *adev = dev->dev_private;
1534 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1535 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1536 uint8_t *frame = buffer + 3;
1537 uint8_t *header = buffer;
1538
1539 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1540 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1541 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1542 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1543 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1544 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1545 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1546 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1547}
1548
1549static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1550{
1551 struct drm_device *dev = encoder->dev;
1552 struct amdgpu_device *adev = dev->dev_private;
1553 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1554 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1555 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1556 u32 dto_phase = 24 * 1000;
1557 u32 dto_modulo = clock;
1558 u32 tmp;
1559
1560 if (!dig || !dig->afmt)
1561 return;
1562
1563 /* XXX two dtos; generally use dto0 for hdmi */
1564 /* Express [24MHz / target pixel clock] as an exact rational
1565 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1566 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1567 */
1568 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1569 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1570 amdgpu_crtc->crtc_id);
1571 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1572 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1573 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1574}
1575
1576/*
1577 * update the info frames with the data from the current display mode
1578 */
1579static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1580 struct drm_display_mode *mode)
1581{
1582 struct drm_device *dev = encoder->dev;
1583 struct amdgpu_device *adev = dev->dev_private;
1584 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1585 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1586 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1587 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1588 struct hdmi_avi_infoframe frame;
1589 ssize_t err;
1590 u32 tmp;
1591 int bpc = 8;
1592
1593 if (!dig || !dig->afmt)
1594 return;
1595
1596 /* Silent, r600_hdmi_enable will raise WARN for us */
1597 if (!dig->afmt->enabled)
1598 return;
1599
1600 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1601 if (encoder->crtc) {
1602 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1603 bpc = amdgpu_crtc->bpc;
1604 }
1605
1606 /* disable audio prior to setting up hw */
1607 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1608 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1609
1610 dce_v11_0_audio_set_dto(encoder, mode->clock);
1611
1612 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1613 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1614 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1615
1616 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1617
1618 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1619 switch (bpc) {
1620 case 0:
1621 case 6:
1622 case 8:
1623 case 16:
1624 default:
1625 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1626 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1627 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1628 connector->name, bpc);
1629 break;
1630 case 10:
1631 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1632 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1633 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1634 connector->name);
1635 break;
1636 case 12:
1637 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1638 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1639 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1640 connector->name);
1641 break;
1642 }
1643 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1644
1645 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1646 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1647 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1648 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1649 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1650
1651 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1652 /* enable audio info frames (frames won't be set until audio is enabled) */
1653 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1654 /* required for audio info values to be updated */
1655 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1656 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1657
1658 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1659 /* required for audio info values to be updated */
1660 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1661 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1662
1663 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1664 /* anything other than 0 */
1665 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1666 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1667
1668 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1669
1670 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1671 /* set the default audio delay */
1672 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1673 /* should be suffient for all audio modes and small enough for all hblanks */
1674 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1675 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1676
1677 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1678 /* allow 60958 channel status fields to be updated */
1679 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1680 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1681
1682 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1683 if (bpc > 8)
1684 /* clear SW CTS value */
1685 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1686 else
1687 /* select SW CTS value */
1688 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1689 /* allow hw to sent ACR packets when required */
1690 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1691 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1692
1693 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1694
1695 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1696 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1697 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1698
1699 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1700 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1701 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1702
1703 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1704 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1705 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1706 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1707 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1708 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1709 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1710 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1711
1712 dce_v11_0_audio_write_speaker_allocation(encoder);
1713
1714 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1715 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1716
1717 dce_v11_0_afmt_audio_select_pin(encoder);
1718 dce_v11_0_audio_write_sad_regs(encoder);
1719 dce_v11_0_audio_write_latency_fields(encoder, mode);
1720
1721 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode, false);
1722 if (err < 0) {
1723 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1724 return;
1725 }
1726
1727 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1728 if (err < 0) {
1729 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1730 return;
1731 }
1732
1733 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1734
1735 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1736 /* enable AVI info frames */
1737 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1738 /* required for audio info values to be updated */
1739 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1740 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1741
1742 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1743 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1744 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1745
1746 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1747 /* send audio packets */
1748 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1749 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1750
1751 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1752 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1753 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1754 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1755
1756 /* enable audio after to setting up hw */
1757 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1758}
1759
1760static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1761{
1762 struct drm_device *dev = encoder->dev;
1763 struct amdgpu_device *adev = dev->dev_private;
1764 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1765 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1766
1767 if (!dig || !dig->afmt)
1768 return;
1769
1770 /* Silent, r600_hdmi_enable will raise WARN for us */
1771 if (enable && dig->afmt->enabled)
1772 return;
1773 if (!enable && !dig->afmt->enabled)
1774 return;
1775
1776 if (!enable && dig->afmt->pin) {
1777 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1778 dig->afmt->pin = NULL;
1779 }
1780
1781 dig->afmt->enabled = enable;
1782
1783 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1784 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1785}
1786
1787static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1788{
1789 int i;
1790
1791 for (i = 0; i < adev->mode_info.num_dig; i++)
1792 adev->mode_info.afmt[i] = NULL;
1793
1794 /* DCE11 has audio blocks tied to DIG encoders */
1795 for (i = 0; i < adev->mode_info.num_dig; i++) {
1796 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1797 if (adev->mode_info.afmt[i]) {
1798 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1799 adev->mode_info.afmt[i]->id = i;
1800 } else {
1801 int j;
1802 for (j = 0; j < i; j++) {
1803 kfree(adev->mode_info.afmt[j]);
1804 adev->mode_info.afmt[j] = NULL;
1805 }
1806 return -ENOMEM;
1807 }
1808 }
1809 return 0;
1810}
1811
1812static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1813{
1814 int i;
1815
1816 for (i = 0; i < adev->mode_info.num_dig; i++) {
1817 kfree(adev->mode_info.afmt[i]);
1818 adev->mode_info.afmt[i] = NULL;
1819 }
1820}
1821
1822static const u32 vga_control_regs[6] =
1823{
1824 mmD1VGA_CONTROL,
1825 mmD2VGA_CONTROL,
1826 mmD3VGA_CONTROL,
1827 mmD4VGA_CONTROL,
1828 mmD5VGA_CONTROL,
1829 mmD6VGA_CONTROL,
1830};
1831
1832static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1833{
1834 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1835 struct drm_device *dev = crtc->dev;
1836 struct amdgpu_device *adev = dev->dev_private;
1837 u32 vga_control;
1838
1839 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1840 if (enable)
1841 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1842 else
1843 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1844}
1845
1846static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1847{
1848 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1849 struct drm_device *dev = crtc->dev;
1850 struct amdgpu_device *adev = dev->dev_private;
1851
1852 if (enable)
1853 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1854 else
1855 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1856}
1857
1858static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1859 struct drm_framebuffer *fb,
1860 int x, int y, int atomic)
1861{
1862 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1863 struct drm_device *dev = crtc->dev;
1864 struct amdgpu_device *adev = dev->dev_private;
1865 struct amdgpu_framebuffer *amdgpu_fb;
1866 struct drm_framebuffer *target_fb;
1867 struct drm_gem_object *obj;
1868 struct amdgpu_bo *abo;
1869 uint64_t fb_location, tiling_flags;
1870 uint32_t fb_format, fb_pitch_pixels;
1871 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1872 u32 pipe_config;
1873 u32 tmp, viewport_w, viewport_h;
1874 int r;
1875 bool bypass_lut = false;
1876 struct drm_format_name_buf format_name;
1877
1878 /* no fb bound */
1879 if (!atomic && !crtc->primary->fb) {
1880 DRM_DEBUG_KMS("No FB bound\n");
1881 return 0;
1882 }
1883
1884 if (atomic) {
1885 amdgpu_fb = to_amdgpu_framebuffer(fb);
1886 target_fb = fb;
1887 } else {
1888 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
1889 target_fb = crtc->primary->fb;
1890 }
1891
1892 /* If atomic, assume fb object is pinned & idle & fenced and
1893 * just update base pointers
1894 */
1895 obj = amdgpu_fb->obj;
1896 abo = gem_to_amdgpu_bo(obj);
1897 r = amdgpu_bo_reserve(abo, false);
1898 if (unlikely(r != 0))
1899 return r;
1900
1901 if (atomic) {
1902 fb_location = amdgpu_bo_gpu_offset(abo);
1903 } else {
1904 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM, &fb_location);
1905 if (unlikely(r != 0)) {
1906 amdgpu_bo_unreserve(abo);
1907 return -EINVAL;
1908 }
1909 }
1910
1911 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1912 amdgpu_bo_unreserve(abo);
1913
1914 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1915
1916 switch (target_fb->format->format) {
1917 case DRM_FORMAT_C8:
1918 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1919 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1920 break;
1921 case DRM_FORMAT_XRGB4444:
1922 case DRM_FORMAT_ARGB4444:
1923 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1924 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1925#ifdef __BIG_ENDIAN
1926 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1927 ENDIAN_8IN16);
1928#endif
1929 break;
1930 case DRM_FORMAT_XRGB1555:
1931 case DRM_FORMAT_ARGB1555:
1932 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1933 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1934#ifdef __BIG_ENDIAN
1935 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1936 ENDIAN_8IN16);
1937#endif
1938 break;
1939 case DRM_FORMAT_BGRX5551:
1940 case DRM_FORMAT_BGRA5551:
1941 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1942 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1943#ifdef __BIG_ENDIAN
1944 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1945 ENDIAN_8IN16);
1946#endif
1947 break;
1948 case DRM_FORMAT_RGB565:
1949 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1950 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1951#ifdef __BIG_ENDIAN
1952 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1953 ENDIAN_8IN16);
1954#endif
1955 break;
1956 case DRM_FORMAT_XRGB8888:
1957 case DRM_FORMAT_ARGB8888:
1958 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1959 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1960#ifdef __BIG_ENDIAN
1961 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1962 ENDIAN_8IN32);
1963#endif
1964 break;
1965 case DRM_FORMAT_XRGB2101010:
1966 case DRM_FORMAT_ARGB2101010:
1967 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1968 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1969#ifdef __BIG_ENDIAN
1970 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1971 ENDIAN_8IN32);
1972#endif
1973 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1974 bypass_lut = true;
1975 break;
1976 case DRM_FORMAT_BGRX1010102:
1977 case DRM_FORMAT_BGRA1010102:
1978 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1979 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
1980#ifdef __BIG_ENDIAN
1981 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1982 ENDIAN_8IN32);
1983#endif
1984 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
1985 bypass_lut = true;
1986 break;
1987 default:
1988 DRM_ERROR("Unsupported screen format %s\n",
1989 drm_get_format_name(target_fb->format->format, &format_name));
1990 return -EINVAL;
1991 }
1992
1993 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
1994 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
1995
1996 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
1997 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
1998 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
1999 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2000 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2001
2002 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2003 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2004 ARRAY_2D_TILED_THIN1);
2005 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2006 tile_split);
2007 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2008 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2009 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2010 mtaspect);
2011 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2012 ADDR_SURF_MICRO_TILING_DISPLAY);
2013 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2014 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2015 ARRAY_1D_TILED_THIN1);
2016 }
2017
2018 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2019 pipe_config);
2020
2021 dce_v11_0_vga_enable(crtc, false);
2022
2023 /* Make sure surface address is updated at vertical blank rather than
2024 * horizontal blank
2025 */
2026 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2027 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2028 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2029 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2030
2031 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2032 upper_32_bits(fb_location));
2033 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2034 upper_32_bits(fb_location));
2035 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2036 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2037 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2038 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2039 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2040 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2041
2042 /*
2043 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2044 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2045 * retain the full precision throughout the pipeline.
2046 */
2047 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2048 if (bypass_lut)
2049 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2050 else
2051 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2052 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2053
2054 if (bypass_lut)
2055 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2056
2057 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2058 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2059 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2060 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2061 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2062 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2063
2064 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2065 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2066
2067 dce_v11_0_grph_enable(crtc, true);
2068
2069 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2070 target_fb->height);
2071
2072 x &= ~3;
2073 y &= ~1;
2074 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2075 (x << 16) | y);
2076 viewport_w = crtc->mode.hdisplay;
2077 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2078 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2079 (viewport_w << 16) | viewport_h);
2080
2081 /* set pageflip to happen anywhere in vblank interval */
2082 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2083
2084 if (!atomic && fb && fb != crtc->primary->fb) {
2085 amdgpu_fb = to_amdgpu_framebuffer(fb);
2086 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2087 r = amdgpu_bo_reserve(abo, true);
2088 if (unlikely(r != 0))
2089 return r;
2090 amdgpu_bo_unpin(abo);
2091 amdgpu_bo_unreserve(abo);
2092 }
2093
2094 /* Bytes per pixel may have changed */
2095 dce_v11_0_bandwidth_update(adev);
2096
2097 return 0;
2098}
2099
2100static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2101 struct drm_display_mode *mode)
2102{
2103 struct drm_device *dev = crtc->dev;
2104 struct amdgpu_device *adev = dev->dev_private;
2105 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2106 u32 tmp;
2107
2108 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2109 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2110 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2111 else
2112 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2113 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2114}
2115
2116static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2117{
2118 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2119 struct drm_device *dev = crtc->dev;
2120 struct amdgpu_device *adev = dev->dev_private;
2121 u16 *r, *g, *b;
2122 int i;
2123 u32 tmp;
2124
2125 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2126
2127 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2128 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2129 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2130
2131 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2132 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2133 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2134
2135 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2136 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2137 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2138
2139 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2140
2141 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2142 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2143 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2144
2145 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2146 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2147 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2148
2149 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2150 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2151
2152 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2153 r = crtc->gamma_store;
2154 g = r + crtc->gamma_size;
2155 b = g + crtc->gamma_size;
2156 for (i = 0; i < 256; i++) {
2157 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2158 ((*r++ & 0xffc0) << 14) |
2159 ((*g++ & 0xffc0) << 4) |
2160 (*b++ >> 6));
2161 }
2162
2163 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2164 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2165 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2166 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2167 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2168
2169 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2170 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2171 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2172
2173 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2174 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2175 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2176
2177 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2178 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2179 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2180
2181 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2182 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2183 /* XXX this only needs to be programmed once per crtc at startup,
2184 * not sure where the best place for it is
2185 */
2186 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2187 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2188 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2189}
2190
2191static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2192{
2193 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2194 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2195
2196 switch (amdgpu_encoder->encoder_id) {
2197 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2198 if (dig->linkb)
2199 return 1;
2200 else
2201 return 0;
2202 break;
2203 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2204 if (dig->linkb)
2205 return 3;
2206 else
2207 return 2;
2208 break;
2209 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2210 if (dig->linkb)
2211 return 5;
2212 else
2213 return 4;
2214 break;
2215 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2216 return 6;
2217 break;
2218 default:
2219 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2220 return 0;
2221 }
2222}
2223
2224/**
2225 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2226 *
2227 * @crtc: drm crtc
2228 *
2229 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2230 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2231 * monitors a dedicated PPLL must be used. If a particular board has
2232 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2233 * as there is no need to program the PLL itself. If we are not able to
2234 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2235 * avoid messing up an existing monitor.
2236 *
2237 * Asic specific PLL information
2238 *
2239 * DCE 10.x
2240 * Tonga
2241 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2242 * CI
2243 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2244 *
2245 */
2246static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2247{
2248 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2249 struct drm_device *dev = crtc->dev;
2250 struct amdgpu_device *adev = dev->dev_private;
2251 u32 pll_in_use;
2252 int pll;
2253
2254 if ((adev->asic_type == CHIP_POLARIS10) ||
2255 (adev->asic_type == CHIP_POLARIS11) ||
2256 (adev->asic_type == CHIP_POLARIS12)) {
2257 struct amdgpu_encoder *amdgpu_encoder =
2258 to_amdgpu_encoder(amdgpu_crtc->encoder);
2259 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2260
2261 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2262 return ATOM_DP_DTO;
2263
2264 switch (amdgpu_encoder->encoder_id) {
2265 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2266 if (dig->linkb)
2267 return ATOM_COMBOPHY_PLL1;
2268 else
2269 return ATOM_COMBOPHY_PLL0;
2270 break;
2271 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2272 if (dig->linkb)
2273 return ATOM_COMBOPHY_PLL3;
2274 else
2275 return ATOM_COMBOPHY_PLL2;
2276 break;
2277 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2278 if (dig->linkb)
2279 return ATOM_COMBOPHY_PLL5;
2280 else
2281 return ATOM_COMBOPHY_PLL4;
2282 break;
2283 default:
2284 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2285 return ATOM_PPLL_INVALID;
2286 }
2287 }
2288
2289 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2290 if (adev->clock.dp_extclk)
2291 /* skip PPLL programming if using ext clock */
2292 return ATOM_PPLL_INVALID;
2293 else {
2294 /* use the same PPLL for all DP monitors */
2295 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2296 if (pll != ATOM_PPLL_INVALID)
2297 return pll;
2298 }
2299 } else {
2300 /* use the same PPLL for all monitors with the same clock */
2301 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2302 if (pll != ATOM_PPLL_INVALID)
2303 return pll;
2304 }
2305
2306 /* XXX need to determine what plls are available on each DCE11 part */
2307 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2308 if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) {
2309 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2310 return ATOM_PPLL1;
2311 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2312 return ATOM_PPLL0;
2313 DRM_ERROR("unable to allocate a PPLL\n");
2314 return ATOM_PPLL_INVALID;
2315 } else {
2316 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2317 return ATOM_PPLL2;
2318 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2319 return ATOM_PPLL1;
2320 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2321 return ATOM_PPLL0;
2322 DRM_ERROR("unable to allocate a PPLL\n");
2323 return ATOM_PPLL_INVALID;
2324 }
2325 return ATOM_PPLL_INVALID;
2326}
2327
2328static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2329{
2330 struct amdgpu_device *adev = crtc->dev->dev_private;
2331 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2332 uint32_t cur_lock;
2333
2334 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2335 if (lock)
2336 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2337 else
2338 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2339 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2340}
2341
2342static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2343{
2344 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2345 struct amdgpu_device *adev = crtc->dev->dev_private;
2346 u32 tmp;
2347
2348 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2349 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2350 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2351}
2352
2353static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2354{
2355 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2356 struct amdgpu_device *adev = crtc->dev->dev_private;
2357 u32 tmp;
2358
2359 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2360 upper_32_bits(amdgpu_crtc->cursor_addr));
2361 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2362 lower_32_bits(amdgpu_crtc->cursor_addr));
2363
2364 tmp = RREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2365 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2366 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2367 WREG32_IDX(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2368}
2369
2370static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2371 int x, int y)
2372{
2373 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2374 struct amdgpu_device *adev = crtc->dev->dev_private;
2375 int xorigin = 0, yorigin = 0;
2376
2377 amdgpu_crtc->cursor_x = x;
2378 amdgpu_crtc->cursor_y = y;
2379
2380 /* avivo cursor are offset into the total surface */
2381 x += crtc->x;
2382 y += crtc->y;
2383 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2384
2385 if (x < 0) {
2386 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2387 x = 0;
2388 }
2389 if (y < 0) {
2390 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2391 y = 0;
2392 }
2393
2394 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2395 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2396 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2397 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2398
2399 return 0;
2400}
2401
2402static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2403 int x, int y)
2404{
2405 int ret;
2406
2407 dce_v11_0_lock_cursor(crtc, true);
2408 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2409 dce_v11_0_lock_cursor(crtc, false);
2410
2411 return ret;
2412}
2413
2414static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2415 struct drm_file *file_priv,
2416 uint32_t handle,
2417 uint32_t width,
2418 uint32_t height,
2419 int32_t hot_x,
2420 int32_t hot_y)
2421{
2422 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2423 struct drm_gem_object *obj;
2424 struct amdgpu_bo *aobj;
2425 int ret;
2426
2427 if (!handle) {
2428 /* turn off cursor */
2429 dce_v11_0_hide_cursor(crtc);
2430 obj = NULL;
2431 goto unpin;
2432 }
2433
2434 if ((width > amdgpu_crtc->max_cursor_width) ||
2435 (height > amdgpu_crtc->max_cursor_height)) {
2436 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2437 return -EINVAL;
2438 }
2439
2440 obj = drm_gem_object_lookup(file_priv, handle);
2441 if (!obj) {
2442 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2443 return -ENOENT;
2444 }
2445
2446 aobj = gem_to_amdgpu_bo(obj);
2447 ret = amdgpu_bo_reserve(aobj, false);
2448 if (ret != 0) {
2449 drm_gem_object_put_unlocked(obj);
2450 return ret;
2451 }
2452
2453 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
2454 amdgpu_bo_unreserve(aobj);
2455 if (ret) {
2456 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2457 drm_gem_object_put_unlocked(obj);
2458 return ret;
2459 }
2460
2461 dce_v11_0_lock_cursor(crtc, true);
2462
2463 if (width != amdgpu_crtc->cursor_width ||
2464 height != amdgpu_crtc->cursor_height ||
2465 hot_x != amdgpu_crtc->cursor_hot_x ||
2466 hot_y != amdgpu_crtc->cursor_hot_y) {
2467 int x, y;
2468
2469 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2470 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2471
2472 dce_v11_0_cursor_move_locked(crtc, x, y);
2473
2474 amdgpu_crtc->cursor_width = width;
2475 amdgpu_crtc->cursor_height = height;
2476 amdgpu_crtc->cursor_hot_x = hot_x;
2477 amdgpu_crtc->cursor_hot_y = hot_y;
2478 }
2479
2480 dce_v11_0_show_cursor(crtc);
2481 dce_v11_0_lock_cursor(crtc, false);
2482
2483unpin:
2484 if (amdgpu_crtc->cursor_bo) {
2485 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2486 ret = amdgpu_bo_reserve(aobj, true);
2487 if (likely(ret == 0)) {
2488 amdgpu_bo_unpin(aobj);
2489 amdgpu_bo_unreserve(aobj);
2490 }
2491 drm_gem_object_put_unlocked(amdgpu_crtc->cursor_bo);
2492 }
2493
2494 amdgpu_crtc->cursor_bo = obj;
2495 return 0;
2496}
2497
2498static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2499{
2500 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2501
2502 if (amdgpu_crtc->cursor_bo) {
2503 dce_v11_0_lock_cursor(crtc, true);
2504
2505 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2506 amdgpu_crtc->cursor_y);
2507
2508 dce_v11_0_show_cursor(crtc);
2509
2510 dce_v11_0_lock_cursor(crtc, false);
2511 }
2512}
2513
2514static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2515 u16 *blue, uint32_t size,
2516 struct drm_modeset_acquire_ctx *ctx)
2517{
2518 dce_v11_0_crtc_load_lut(crtc);
2519
2520 return 0;
2521}
2522
2523static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2524{
2525 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2526
2527 drm_crtc_cleanup(crtc);
2528 kfree(amdgpu_crtc);
2529}
2530
2531static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2532 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2533 .cursor_move = dce_v11_0_crtc_cursor_move,
2534 .gamma_set = dce_v11_0_crtc_gamma_set,
2535 .set_config = amdgpu_display_crtc_set_config,
2536 .destroy = dce_v11_0_crtc_destroy,
2537 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2538};
2539
2540static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2541{
2542 struct drm_device *dev = crtc->dev;
2543 struct amdgpu_device *adev = dev->dev_private;
2544 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2545 unsigned type;
2546
2547 switch (mode) {
2548 case DRM_MODE_DPMS_ON:
2549 amdgpu_crtc->enabled = true;
2550 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2551 dce_v11_0_vga_enable(crtc, true);
2552 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2553 dce_v11_0_vga_enable(crtc, false);
2554 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2555 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2556 amdgpu_crtc->crtc_id);
2557 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2558 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2559 drm_crtc_vblank_on(crtc);
2560 dce_v11_0_crtc_load_lut(crtc);
2561 break;
2562 case DRM_MODE_DPMS_STANDBY:
2563 case DRM_MODE_DPMS_SUSPEND:
2564 case DRM_MODE_DPMS_OFF:
2565 drm_crtc_vblank_off(crtc);
2566 if (amdgpu_crtc->enabled) {
2567 dce_v11_0_vga_enable(crtc, true);
2568 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2569 dce_v11_0_vga_enable(crtc, false);
2570 }
2571 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2572 amdgpu_crtc->enabled = false;
2573 break;
2574 }
2575 /* adjust pm to dpms */
2576 amdgpu_pm_compute_clocks(adev);
2577}
2578
2579static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2580{
2581 /* disable crtc pair power gating before programming */
2582 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2583 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2584 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2585}
2586
2587static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2588{
2589 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2590 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2591}
2592
2593static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2594{
2595 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2596 struct drm_device *dev = crtc->dev;
2597 struct amdgpu_device *adev = dev->dev_private;
2598 struct amdgpu_atom_ss ss;
2599 int i;
2600
2601 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2602 if (crtc->primary->fb) {
2603 int r;
2604 struct amdgpu_framebuffer *amdgpu_fb;
2605 struct amdgpu_bo *abo;
2606
2607 amdgpu_fb = to_amdgpu_framebuffer(crtc->primary->fb);
2608 abo = gem_to_amdgpu_bo(amdgpu_fb->obj);
2609 r = amdgpu_bo_reserve(abo, true);
2610 if (unlikely(r))
2611 DRM_ERROR("failed to reserve abo before unpin\n");
2612 else {
2613 amdgpu_bo_unpin(abo);
2614 amdgpu_bo_unreserve(abo);
2615 }
2616 }
2617 /* disable the GRPH */
2618 dce_v11_0_grph_enable(crtc, false);
2619
2620 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2621
2622 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2623 if (adev->mode_info.crtcs[i] &&
2624 adev->mode_info.crtcs[i]->enabled &&
2625 i != amdgpu_crtc->crtc_id &&
2626 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2627 /* one other crtc is using this pll don't turn
2628 * off the pll
2629 */
2630 goto done;
2631 }
2632 }
2633
2634 switch (amdgpu_crtc->pll_id) {
2635 case ATOM_PPLL0:
2636 case ATOM_PPLL1:
2637 case ATOM_PPLL2:
2638 /* disable the ppll */
2639 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2640 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2641 break;
2642 case ATOM_COMBOPHY_PLL0:
2643 case ATOM_COMBOPHY_PLL1:
2644 case ATOM_COMBOPHY_PLL2:
2645 case ATOM_COMBOPHY_PLL3:
2646 case ATOM_COMBOPHY_PLL4:
2647 case ATOM_COMBOPHY_PLL5:
2648 /* disable the ppll */
2649 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2650 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2651 break;
2652 default:
2653 break;
2654 }
2655done:
2656 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2657 amdgpu_crtc->adjusted_clock = 0;
2658 amdgpu_crtc->encoder = NULL;
2659 amdgpu_crtc->connector = NULL;
2660}
2661
2662static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2663 struct drm_display_mode *mode,
2664 struct drm_display_mode *adjusted_mode,
2665 int x, int y, struct drm_framebuffer *old_fb)
2666{
2667 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2668 struct drm_device *dev = crtc->dev;
2669 struct amdgpu_device *adev = dev->dev_private;
2670
2671 if (!amdgpu_crtc->adjusted_clock)
2672 return -EINVAL;
2673
2674 if ((adev->asic_type == CHIP_POLARIS10) ||
2675 (adev->asic_type == CHIP_POLARIS11) ||
2676 (adev->asic_type == CHIP_POLARIS12)) {
2677 struct amdgpu_encoder *amdgpu_encoder =
2678 to_amdgpu_encoder(amdgpu_crtc->encoder);
2679 int encoder_mode =
2680 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2681
2682 /* SetPixelClock calculates the plls and ss values now */
2683 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2684 amdgpu_crtc->pll_id,
2685 encoder_mode, amdgpu_encoder->encoder_id,
2686 adjusted_mode->clock, 0, 0, 0, 0,
2687 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2688 } else {
2689 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2690 }
2691 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2692 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2693 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2694 amdgpu_atombios_crtc_scaler_setup(crtc);
2695 dce_v11_0_cursor_reset(crtc);
2696 /* update the hw version fpr dpm */
2697 amdgpu_crtc->hw_mode = *adjusted_mode;
2698
2699 return 0;
2700}
2701
2702static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2703 const struct drm_display_mode *mode,
2704 struct drm_display_mode *adjusted_mode)
2705{
2706 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2707 struct drm_device *dev = crtc->dev;
2708 struct drm_encoder *encoder;
2709
2710 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2711 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2712 if (encoder->crtc == crtc) {
2713 amdgpu_crtc->encoder = encoder;
2714 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2715 break;
2716 }
2717 }
2718 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2719 amdgpu_crtc->encoder = NULL;
2720 amdgpu_crtc->connector = NULL;
2721 return false;
2722 }
2723 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2724 return false;
2725 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2726 return false;
2727 /* pick pll */
2728 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2729 /* if we can't get a PPLL for a non-DP encoder, fail */
2730 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2731 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2732 return false;
2733
2734 return true;
2735}
2736
2737static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2738 struct drm_framebuffer *old_fb)
2739{
2740 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2741}
2742
2743static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2744 struct drm_framebuffer *fb,
2745 int x, int y, enum mode_set_atomic state)
2746{
2747 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2748}
2749
2750static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2751 .dpms = dce_v11_0_crtc_dpms,
2752 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2753 .mode_set = dce_v11_0_crtc_mode_set,
2754 .mode_set_base = dce_v11_0_crtc_set_base,
2755 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2756 .prepare = dce_v11_0_crtc_prepare,
2757 .commit = dce_v11_0_crtc_commit,
2758 .disable = dce_v11_0_crtc_disable,
2759};
2760
2761static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2762{
2763 struct amdgpu_crtc *amdgpu_crtc;
2764
2765 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2766 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2767 if (amdgpu_crtc == NULL)
2768 return -ENOMEM;
2769
2770 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2771
2772 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2773 amdgpu_crtc->crtc_id = index;
2774 adev->mode_info.crtcs[index] = amdgpu_crtc;
2775
2776 amdgpu_crtc->max_cursor_width = 128;
2777 amdgpu_crtc->max_cursor_height = 128;
2778 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2779 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2780
2781 switch (amdgpu_crtc->crtc_id) {
2782 case 0:
2783 default:
2784 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2785 break;
2786 case 1:
2787 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2788 break;
2789 case 2:
2790 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2791 break;
2792 case 3:
2793 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2794 break;
2795 case 4:
2796 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2797 break;
2798 case 5:
2799 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2800 break;
2801 }
2802
2803 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2804 amdgpu_crtc->adjusted_clock = 0;
2805 amdgpu_crtc->encoder = NULL;
2806 amdgpu_crtc->connector = NULL;
2807 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2808
2809 return 0;
2810}
2811
2812static int dce_v11_0_early_init(void *handle)
2813{
2814 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2815
2816 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2817 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2818
2819 dce_v11_0_set_display_funcs(adev);
2820
2821 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2822
2823 switch (adev->asic_type) {
2824 case CHIP_CARRIZO:
2825 adev->mode_info.num_hpd = 6;
2826 adev->mode_info.num_dig = 9;
2827 break;
2828 case CHIP_STONEY:
2829 adev->mode_info.num_hpd = 6;
2830 adev->mode_info.num_dig = 9;
2831 break;
2832 case CHIP_POLARIS10:
2833 adev->mode_info.num_hpd = 6;
2834 adev->mode_info.num_dig = 6;
2835 break;
2836 case CHIP_POLARIS11:
2837 case CHIP_POLARIS12:
2838 adev->mode_info.num_hpd = 5;
2839 adev->mode_info.num_dig = 5;
2840 break;
2841 default:
2842 /* FIXME: not supported yet */
2843 return -EINVAL;
2844 }
2845
2846 dce_v11_0_set_irq_funcs(adev);
2847
2848 return 0;
2849}
2850
2851static int dce_v11_0_sw_init(void *handle)
2852{
2853 int r, i;
2854 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2855
2856 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2857 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2858 if (r)
2859 return r;
2860 }
2861
2862 for (i = 8; i < 20; i += 2) {
2863 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2864 if (r)
2865 return r;
2866 }
2867
2868 /* HPD hotplug */
2869 r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
2870 if (r)
2871 return r;
2872
2873 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2874
2875 adev->ddev->mode_config.async_page_flip = true;
2876
2877 adev->ddev->mode_config.max_width = 16384;
2878 adev->ddev->mode_config.max_height = 16384;
2879
2880 adev->ddev->mode_config.preferred_depth = 24;
2881 adev->ddev->mode_config.prefer_shadow = 1;
2882
2883 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2884
2885 r = amdgpu_display_modeset_create_props(adev);
2886 if (r)
2887 return r;
2888
2889 adev->ddev->mode_config.max_width = 16384;
2890 adev->ddev->mode_config.max_height = 16384;
2891
2892
2893 /* allocate crtcs */
2894 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2895 r = dce_v11_0_crtc_init(adev, i);
2896 if (r)
2897 return r;
2898 }
2899
2900 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2901 amdgpu_display_print_display_setup(adev->ddev);
2902 else
2903 return -EINVAL;
2904
2905 /* setup afmt */
2906 r = dce_v11_0_afmt_init(adev);
2907 if (r)
2908 return r;
2909
2910 r = dce_v11_0_audio_init(adev);
2911 if (r)
2912 return r;
2913
2914 drm_kms_helper_poll_init(adev->ddev);
2915
2916 adev->mode_info.mode_config_initialized = true;
2917 return 0;
2918}
2919
2920static int dce_v11_0_sw_fini(void *handle)
2921{
2922 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2923
2924 kfree(adev->mode_info.bios_hardcoded_edid);
2925
2926 drm_kms_helper_poll_fini(adev->ddev);
2927
2928 dce_v11_0_audio_fini(adev);
2929
2930 dce_v11_0_afmt_fini(adev);
2931
2932 drm_mode_config_cleanup(adev->ddev);
2933 adev->mode_info.mode_config_initialized = false;
2934
2935 return 0;
2936}
2937
2938static int dce_v11_0_hw_init(void *handle)
2939{
2940 int i;
2941 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2942
2943 dce_v11_0_init_golden_registers(adev);
2944
2945 /* disable vga render */
2946 dce_v11_0_set_vga_render_state(adev, false);
2947 /* init dig PHYs, disp eng pll */
2948 amdgpu_atombios_crtc_powergate_init(adev);
2949 amdgpu_atombios_encoder_init_dig(adev);
2950 if ((adev->asic_type == CHIP_POLARIS10) ||
2951 (adev->asic_type == CHIP_POLARIS11) ||
2952 (adev->asic_type == CHIP_POLARIS12)) {
2953 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
2954 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
2955 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
2956 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
2957 } else {
2958 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
2959 }
2960
2961 /* initialize hpd */
2962 dce_v11_0_hpd_init(adev);
2963
2964 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2965 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2966 }
2967
2968 dce_v11_0_pageflip_interrupt_init(adev);
2969
2970 return 0;
2971}
2972
2973static int dce_v11_0_hw_fini(void *handle)
2974{
2975 int i;
2976 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2977
2978 dce_v11_0_hpd_fini(adev);
2979
2980 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
2981 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
2982 }
2983
2984 dce_v11_0_pageflip_interrupt_fini(adev);
2985
2986 return 0;
2987}
2988
2989static int dce_v11_0_suspend(void *handle)
2990{
2991 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2992
2993 adev->mode_info.bl_level =
2994 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
2995
2996 return dce_v11_0_hw_fini(handle);
2997}
2998
2999static int dce_v11_0_resume(void *handle)
3000{
3001 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3002 int ret;
3003
3004 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3005 adev->mode_info.bl_level);
3006
3007 ret = dce_v11_0_hw_init(handle);
3008
3009 /* turn on the BL */
3010 if (adev->mode_info.bl_encoder) {
3011 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3012 adev->mode_info.bl_encoder);
3013 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3014 bl_level);
3015 }
3016
3017 return ret;
3018}
3019
3020static bool dce_v11_0_is_idle(void *handle)
3021{
3022 return true;
3023}
3024
3025static int dce_v11_0_wait_for_idle(void *handle)
3026{
3027 return 0;
3028}
3029
3030static int dce_v11_0_soft_reset(void *handle)
3031{
3032 u32 srbm_soft_reset = 0, tmp;
3033 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3034
3035 if (dce_v11_0_is_display_hung(adev))
3036 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3037
3038 if (srbm_soft_reset) {
3039 tmp = RREG32(mmSRBM_SOFT_RESET);
3040 tmp |= srbm_soft_reset;
3041 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3042 WREG32(mmSRBM_SOFT_RESET, tmp);
3043 tmp = RREG32(mmSRBM_SOFT_RESET);
3044
3045 udelay(50);
3046
3047 tmp &= ~srbm_soft_reset;
3048 WREG32(mmSRBM_SOFT_RESET, tmp);
3049 tmp = RREG32(mmSRBM_SOFT_RESET);
3050
3051 /* Wait a little for things to settle down */
3052 udelay(50);
3053 }
3054 return 0;
3055}
3056
3057static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3058 int crtc,
3059 enum amdgpu_interrupt_state state)
3060{
3061 u32 lb_interrupt_mask;
3062
3063 if (crtc >= adev->mode_info.num_crtc) {
3064 DRM_DEBUG("invalid crtc %d\n", crtc);
3065 return;
3066 }
3067
3068 switch (state) {
3069 case AMDGPU_IRQ_STATE_DISABLE:
3070 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3071 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3072 VBLANK_INTERRUPT_MASK, 0);
3073 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3074 break;
3075 case AMDGPU_IRQ_STATE_ENABLE:
3076 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3077 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3078 VBLANK_INTERRUPT_MASK, 1);
3079 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3080 break;
3081 default:
3082 break;
3083 }
3084}
3085
3086static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3087 int crtc,
3088 enum amdgpu_interrupt_state state)
3089{
3090 u32 lb_interrupt_mask;
3091
3092 if (crtc >= adev->mode_info.num_crtc) {
3093 DRM_DEBUG("invalid crtc %d\n", crtc);
3094 return;
3095 }
3096
3097 switch (state) {
3098 case AMDGPU_IRQ_STATE_DISABLE:
3099 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3100 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3101 VLINE_INTERRUPT_MASK, 0);
3102 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3103 break;
3104 case AMDGPU_IRQ_STATE_ENABLE:
3105 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3106 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3107 VLINE_INTERRUPT_MASK, 1);
3108 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3109 break;
3110 default:
3111 break;
3112 }
3113}
3114
3115static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3116 struct amdgpu_irq_src *source,
3117 unsigned hpd,
3118 enum amdgpu_interrupt_state state)
3119{
3120 u32 tmp;
3121
3122 if (hpd >= adev->mode_info.num_hpd) {
3123 DRM_DEBUG("invalid hdp %d\n", hpd);
3124 return 0;
3125 }
3126
3127 switch (state) {
3128 case AMDGPU_IRQ_STATE_DISABLE:
3129 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3130 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3131 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3132 break;
3133 case AMDGPU_IRQ_STATE_ENABLE:
3134 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3135 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3136 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3137 break;
3138 default:
3139 break;
3140 }
3141
3142 return 0;
3143}
3144
3145static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3146 struct amdgpu_irq_src *source,
3147 unsigned type,
3148 enum amdgpu_interrupt_state state)
3149{
3150 switch (type) {
3151 case AMDGPU_CRTC_IRQ_VBLANK1:
3152 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3153 break;
3154 case AMDGPU_CRTC_IRQ_VBLANK2:
3155 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3156 break;
3157 case AMDGPU_CRTC_IRQ_VBLANK3:
3158 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3159 break;
3160 case AMDGPU_CRTC_IRQ_VBLANK4:
3161 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3162 break;
3163 case AMDGPU_CRTC_IRQ_VBLANK5:
3164 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3165 break;
3166 case AMDGPU_CRTC_IRQ_VBLANK6:
3167 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3168 break;
3169 case AMDGPU_CRTC_IRQ_VLINE1:
3170 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3171 break;
3172 case AMDGPU_CRTC_IRQ_VLINE2:
3173 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3174 break;
3175 case AMDGPU_CRTC_IRQ_VLINE3:
3176 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3177 break;
3178 case AMDGPU_CRTC_IRQ_VLINE4:
3179 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3180 break;
3181 case AMDGPU_CRTC_IRQ_VLINE5:
3182 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3183 break;
3184 case AMDGPU_CRTC_IRQ_VLINE6:
3185 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3186 break;
3187 default:
3188 break;
3189 }
3190 return 0;
3191}
3192
3193static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3194 struct amdgpu_irq_src *src,
3195 unsigned type,
3196 enum amdgpu_interrupt_state state)
3197{
3198 u32 reg;
3199
3200 if (type >= adev->mode_info.num_crtc) {
3201 DRM_ERROR("invalid pageflip crtc %d\n", type);
3202 return -EINVAL;
3203 }
3204
3205 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3206 if (state == AMDGPU_IRQ_STATE_DISABLE)
3207 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3208 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3209 else
3210 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3211 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3212
3213 return 0;
3214}
3215
3216static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3217 struct amdgpu_irq_src *source,
3218 struct amdgpu_iv_entry *entry)
3219{
3220 unsigned long flags;
3221 unsigned crtc_id;
3222 struct amdgpu_crtc *amdgpu_crtc;
3223 struct amdgpu_flip_work *works;
3224
3225 crtc_id = (entry->src_id - 8) >> 1;
3226 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3227
3228 if (crtc_id >= adev->mode_info.num_crtc) {
3229 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3230 return -EINVAL;
3231 }
3232
3233 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3234 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3235 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3236 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3237
3238 /* IRQ could occur when in initial stage */
3239 if(amdgpu_crtc == NULL)
3240 return 0;
3241
3242 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3243 works = amdgpu_crtc->pflip_works;
3244 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3245 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3246 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3247 amdgpu_crtc->pflip_status,
3248 AMDGPU_FLIP_SUBMITTED);
3249 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3250 return 0;
3251 }
3252
3253 /* page flip completed. clean up */
3254 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3255 amdgpu_crtc->pflip_works = NULL;
3256
3257 /* wakeup usersapce */
3258 if(works->event)
3259 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3260
3261 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3262
3263 drm_crtc_vblank_put(&amdgpu_crtc->base);
3264 schedule_work(&works->unpin_work);
3265
3266 return 0;
3267}
3268
3269static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3270 int hpd)
3271{
3272 u32 tmp;
3273
3274 if (hpd >= adev->mode_info.num_hpd) {
3275 DRM_DEBUG("invalid hdp %d\n", hpd);
3276 return;
3277 }
3278
3279 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3280 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3281 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3282}
3283
3284static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3285 int crtc)
3286{
3287 u32 tmp;
3288
3289 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3290 DRM_DEBUG("invalid crtc %d\n", crtc);
3291 return;
3292 }
3293
3294 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3295 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3296 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3297}
3298
3299static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3300 int crtc)
3301{
3302 u32 tmp;
3303
3304 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3305 DRM_DEBUG("invalid crtc %d\n", crtc);
3306 return;
3307 }
3308
3309 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3310 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3311 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3312}
3313
3314static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3315 struct amdgpu_irq_src *source,
3316 struct amdgpu_iv_entry *entry)
3317{
3318 unsigned crtc = entry->src_id - 1;
3319 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3320 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3321 crtc);
3322
3323 switch (entry->src_data[0]) {
3324 case 0: /* vblank */
3325 if (disp_int & interrupt_status_offsets[crtc].vblank)
3326 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3327 else
3328 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3329
3330 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3331 drm_handle_vblank(adev->ddev, crtc);
3332 }
3333 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3334
3335 break;
3336 case 1: /* vline */
3337 if (disp_int & interrupt_status_offsets[crtc].vline)
3338 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3339 else
3340 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3341
3342 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3343
3344 break;
3345 default:
3346 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3347 break;
3348 }
3349
3350 return 0;
3351}
3352
3353static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3354 struct amdgpu_irq_src *source,
3355 struct amdgpu_iv_entry *entry)
3356{
3357 uint32_t disp_int, mask;
3358 unsigned hpd;
3359
3360 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3361 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3362 return 0;
3363 }
3364
3365 hpd = entry->src_data[0];
3366 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3367 mask = interrupt_status_offsets[hpd].hpd;
3368
3369 if (disp_int & mask) {
3370 dce_v11_0_hpd_int_ack(adev, hpd);
3371 schedule_work(&adev->hotplug_work);
3372 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3373 }
3374
3375 return 0;
3376}
3377
3378static int dce_v11_0_set_clockgating_state(void *handle,
3379 enum amd_clockgating_state state)
3380{
3381 return 0;
3382}
3383
3384static int dce_v11_0_set_powergating_state(void *handle,
3385 enum amd_powergating_state state)
3386{
3387 return 0;
3388}
3389
3390static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3391 .name = "dce_v11_0",
3392 .early_init = dce_v11_0_early_init,
3393 .late_init = NULL,
3394 .sw_init = dce_v11_0_sw_init,
3395 .sw_fini = dce_v11_0_sw_fini,
3396 .hw_init = dce_v11_0_hw_init,
3397 .hw_fini = dce_v11_0_hw_fini,
3398 .suspend = dce_v11_0_suspend,
3399 .resume = dce_v11_0_resume,
3400 .is_idle = dce_v11_0_is_idle,
3401 .wait_for_idle = dce_v11_0_wait_for_idle,
3402 .soft_reset = dce_v11_0_soft_reset,
3403 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3404 .set_powergating_state = dce_v11_0_set_powergating_state,
3405};
3406
3407static void
3408dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3409 struct drm_display_mode *mode,
3410 struct drm_display_mode *adjusted_mode)
3411{
3412 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3413
3414 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3415
3416 /* need to call this here rather than in prepare() since we need some crtc info */
3417 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3418
3419 /* set scaler clears this on some chips */
3420 dce_v11_0_set_interleave(encoder->crtc, mode);
3421
3422 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3423 dce_v11_0_afmt_enable(encoder, true);
3424 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3425 }
3426}
3427
3428static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3429{
3430 struct amdgpu_device *adev = encoder->dev->dev_private;
3431 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3432 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3433
3434 if ((amdgpu_encoder->active_device &
3435 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3436 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3437 ENCODER_OBJECT_ID_NONE)) {
3438 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3439 if (dig) {
3440 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3441 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3442 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3443 }
3444 }
3445
3446 amdgpu_atombios_scratch_regs_lock(adev, true);
3447
3448 if (connector) {
3449 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3450
3451 /* select the clock/data port if it uses a router */
3452 if (amdgpu_connector->router.cd_valid)
3453 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3454
3455 /* turn eDP panel on for mode set */
3456 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3457 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3458 ATOM_TRANSMITTER_ACTION_POWER_ON);
3459 }
3460
3461 /* this is needed for the pll/ss setup to work correctly in some cases */
3462 amdgpu_atombios_encoder_set_crtc_source(encoder);
3463 /* set up the FMT blocks */
3464 dce_v11_0_program_fmt(encoder);
3465}
3466
3467static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3468{
3469 struct drm_device *dev = encoder->dev;
3470 struct amdgpu_device *adev = dev->dev_private;
3471
3472 /* need to call this here as we need the crtc set up */
3473 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3474 amdgpu_atombios_scratch_regs_lock(adev, false);
3475}
3476
3477static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3478{
3479 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3480 struct amdgpu_encoder_atom_dig *dig;
3481
3482 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3483
3484 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3485 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3486 dce_v11_0_afmt_enable(encoder, false);
3487 dig = amdgpu_encoder->enc_priv;
3488 dig->dig_encoder = -1;
3489 }
3490 amdgpu_encoder->active_device = 0;
3491}
3492
3493/* these are handled by the primary encoders */
3494static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3495{
3496
3497}
3498
3499static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3500{
3501
3502}
3503
3504static void
3505dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3506 struct drm_display_mode *mode,
3507 struct drm_display_mode *adjusted_mode)
3508{
3509
3510}
3511
3512static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3513{
3514
3515}
3516
3517static void
3518dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3519{
3520
3521}
3522
3523static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3524 .dpms = dce_v11_0_ext_dpms,
3525 .prepare = dce_v11_0_ext_prepare,
3526 .mode_set = dce_v11_0_ext_mode_set,
3527 .commit = dce_v11_0_ext_commit,
3528 .disable = dce_v11_0_ext_disable,
3529 /* no detect for TMDS/LVDS yet */
3530};
3531
3532static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3533 .dpms = amdgpu_atombios_encoder_dpms,
3534 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3535 .prepare = dce_v11_0_encoder_prepare,
3536 .mode_set = dce_v11_0_encoder_mode_set,
3537 .commit = dce_v11_0_encoder_commit,
3538 .disable = dce_v11_0_encoder_disable,
3539 .detect = amdgpu_atombios_encoder_dig_detect,
3540};
3541
3542static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3543 .dpms = amdgpu_atombios_encoder_dpms,
3544 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3545 .prepare = dce_v11_0_encoder_prepare,
3546 .mode_set = dce_v11_0_encoder_mode_set,
3547 .commit = dce_v11_0_encoder_commit,
3548 .detect = amdgpu_atombios_encoder_dac_detect,
3549};
3550
3551static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3552{
3553 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3554 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3555 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3556 kfree(amdgpu_encoder->enc_priv);
3557 drm_encoder_cleanup(encoder);
3558 kfree(amdgpu_encoder);
3559}
3560
3561static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3562 .destroy = dce_v11_0_encoder_destroy,
3563};
3564
3565static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3566 uint32_t encoder_enum,
3567 uint32_t supported_device,
3568 u16 caps)
3569{
3570 struct drm_device *dev = adev->ddev;
3571 struct drm_encoder *encoder;
3572 struct amdgpu_encoder *amdgpu_encoder;
3573
3574 /* see if we already added it */
3575 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3576 amdgpu_encoder = to_amdgpu_encoder(encoder);
3577 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3578 amdgpu_encoder->devices |= supported_device;
3579 return;
3580 }
3581
3582 }
3583
3584 /* add a new one */
3585 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3586 if (!amdgpu_encoder)
3587 return;
3588
3589 encoder = &amdgpu_encoder->base;
3590 switch (adev->mode_info.num_crtc) {
3591 case 1:
3592 encoder->possible_crtcs = 0x1;
3593 break;
3594 case 2:
3595 default:
3596 encoder->possible_crtcs = 0x3;
3597 break;
3598 case 3:
3599 encoder->possible_crtcs = 0x7;
3600 break;
3601 case 4:
3602 encoder->possible_crtcs = 0xf;
3603 break;
3604 case 5:
3605 encoder->possible_crtcs = 0x1f;
3606 break;
3607 case 6:
3608 encoder->possible_crtcs = 0x3f;
3609 break;
3610 }
3611
3612 amdgpu_encoder->enc_priv = NULL;
3613
3614 amdgpu_encoder->encoder_enum = encoder_enum;
3615 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3616 amdgpu_encoder->devices = supported_device;
3617 amdgpu_encoder->rmx_type = RMX_OFF;
3618 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3619 amdgpu_encoder->is_ext_encoder = false;
3620 amdgpu_encoder->caps = caps;
3621
3622 switch (amdgpu_encoder->encoder_id) {
3623 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3624 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3625 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3626 DRM_MODE_ENCODER_DAC, NULL);
3627 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3628 break;
3629 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3630 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3631 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3632 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3633 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3634 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3635 amdgpu_encoder->rmx_type = RMX_FULL;
3636 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3637 DRM_MODE_ENCODER_LVDS, NULL);
3638 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3639 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3640 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3641 DRM_MODE_ENCODER_DAC, NULL);
3642 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3643 } else {
3644 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3645 DRM_MODE_ENCODER_TMDS, NULL);
3646 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3647 }
3648 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3649 break;
3650 case ENCODER_OBJECT_ID_SI170B:
3651 case ENCODER_OBJECT_ID_CH7303:
3652 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3653 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3654 case ENCODER_OBJECT_ID_TITFP513:
3655 case ENCODER_OBJECT_ID_VT1623:
3656 case ENCODER_OBJECT_ID_HDMI_SI1930:
3657 case ENCODER_OBJECT_ID_TRAVIS:
3658 case ENCODER_OBJECT_ID_NUTMEG:
3659 /* these are handled by the primary encoders */
3660 amdgpu_encoder->is_ext_encoder = true;
3661 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3662 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3663 DRM_MODE_ENCODER_LVDS, NULL);
3664 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3665 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3666 DRM_MODE_ENCODER_DAC, NULL);
3667 else
3668 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3669 DRM_MODE_ENCODER_TMDS, NULL);
3670 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3671 break;
3672 }
3673}
3674
3675static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3676 .bandwidth_update = &dce_v11_0_bandwidth_update,
3677 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3678 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3679 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3680 .hpd_sense = &dce_v11_0_hpd_sense,
3681 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3682 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3683 .page_flip = &dce_v11_0_page_flip,
3684 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3685 .add_encoder = &dce_v11_0_encoder_add,
3686 .add_connector = &amdgpu_connector_add,
3687};
3688
3689static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3690{
3691 if (adev->mode_info.funcs == NULL)
3692 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3693}
3694
3695static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3696 .set = dce_v11_0_set_crtc_irq_state,
3697 .process = dce_v11_0_crtc_irq,
3698};
3699
3700static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3701 .set = dce_v11_0_set_pageflip_irq_state,
3702 .process = dce_v11_0_pageflip_irq,
3703};
3704
3705static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3706 .set = dce_v11_0_set_hpd_irq_state,
3707 .process = dce_v11_0_hpd_irq,
3708};
3709
3710static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3711{
3712 if (adev->mode_info.num_crtc > 0)
3713 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3714 else
3715 adev->crtc_irq.num_types = 0;
3716 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3717
3718 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3719 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3720
3721 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3722 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3723}
3724
3725const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3726{
3727 .type = AMD_IP_BLOCK_TYPE_DCE,
3728 .major = 11,
3729 .minor = 0,
3730 .rev = 0,
3731 .funcs = &dce_v11_0_ip_funcs,
3732};
3733
3734const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3735{
3736 .type = AMD_IP_BLOCK_TYPE_DCE,
3737 .major = 11,
3738 .minor = 2,
3739 .rev = 0,
3740 .funcs = &dce_v11_0_ip_funcs,
3741};
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24#include <drm/drm_fourcc.h>
25#include <drm/drm_vblank.h>
26
27#include "amdgpu.h"
28#include "amdgpu_pm.h"
29#include "amdgpu_i2c.h"
30#include "vid.h"
31#include "atom.h"
32#include "amdgpu_atombios.h"
33#include "atombios_crtc.h"
34#include "atombios_encoders.h"
35#include "amdgpu_pll.h"
36#include "amdgpu_connectors.h"
37#include "amdgpu_display.h"
38#include "dce_v11_0.h"
39
40#include "dce/dce_11_0_d.h"
41#include "dce/dce_11_0_sh_mask.h"
42#include "dce/dce_11_0_enum.h"
43#include "oss/oss_3_0_d.h"
44#include "oss/oss_3_0_sh_mask.h"
45#include "gmc/gmc_8_1_d.h"
46#include "gmc/gmc_8_1_sh_mask.h"
47
48#include "ivsrcid/ivsrcid_vislands30.h"
49
50static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev);
51static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev);
52
53static const u32 crtc_offsets[] =
54{
55 CRTC0_REGISTER_OFFSET,
56 CRTC1_REGISTER_OFFSET,
57 CRTC2_REGISTER_OFFSET,
58 CRTC3_REGISTER_OFFSET,
59 CRTC4_REGISTER_OFFSET,
60 CRTC5_REGISTER_OFFSET,
61 CRTC6_REGISTER_OFFSET
62};
63
64static const u32 hpd_offsets[] =
65{
66 HPD0_REGISTER_OFFSET,
67 HPD1_REGISTER_OFFSET,
68 HPD2_REGISTER_OFFSET,
69 HPD3_REGISTER_OFFSET,
70 HPD4_REGISTER_OFFSET,
71 HPD5_REGISTER_OFFSET
72};
73
74static const uint32_t dig_offsets[] = {
75 DIG0_REGISTER_OFFSET,
76 DIG1_REGISTER_OFFSET,
77 DIG2_REGISTER_OFFSET,
78 DIG3_REGISTER_OFFSET,
79 DIG4_REGISTER_OFFSET,
80 DIG5_REGISTER_OFFSET,
81 DIG6_REGISTER_OFFSET,
82 DIG7_REGISTER_OFFSET,
83 DIG8_REGISTER_OFFSET
84};
85
86static const struct {
87 uint32_t reg;
88 uint32_t vblank;
89 uint32_t vline;
90 uint32_t hpd;
91
92} interrupt_status_offsets[] = { {
93 .reg = mmDISP_INTERRUPT_STATUS,
94 .vblank = DISP_INTERRUPT_STATUS__LB_D1_VBLANK_INTERRUPT_MASK,
95 .vline = DISP_INTERRUPT_STATUS__LB_D1_VLINE_INTERRUPT_MASK,
96 .hpd = DISP_INTERRUPT_STATUS__DC_HPD1_INTERRUPT_MASK
97}, {
98 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE,
99 .vblank = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VBLANK_INTERRUPT_MASK,
100 .vline = DISP_INTERRUPT_STATUS_CONTINUE__LB_D2_VLINE_INTERRUPT_MASK,
101 .hpd = DISP_INTERRUPT_STATUS_CONTINUE__DC_HPD2_INTERRUPT_MASK
102}, {
103 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE2,
104 .vblank = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VBLANK_INTERRUPT_MASK,
105 .vline = DISP_INTERRUPT_STATUS_CONTINUE2__LB_D3_VLINE_INTERRUPT_MASK,
106 .hpd = DISP_INTERRUPT_STATUS_CONTINUE2__DC_HPD3_INTERRUPT_MASK
107}, {
108 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE3,
109 .vblank = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VBLANK_INTERRUPT_MASK,
110 .vline = DISP_INTERRUPT_STATUS_CONTINUE3__LB_D4_VLINE_INTERRUPT_MASK,
111 .hpd = DISP_INTERRUPT_STATUS_CONTINUE3__DC_HPD4_INTERRUPT_MASK
112}, {
113 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE4,
114 .vblank = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VBLANK_INTERRUPT_MASK,
115 .vline = DISP_INTERRUPT_STATUS_CONTINUE4__LB_D5_VLINE_INTERRUPT_MASK,
116 .hpd = DISP_INTERRUPT_STATUS_CONTINUE4__DC_HPD5_INTERRUPT_MASK
117}, {
118 .reg = mmDISP_INTERRUPT_STATUS_CONTINUE5,
119 .vblank = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VBLANK_INTERRUPT_MASK,
120 .vline = DISP_INTERRUPT_STATUS_CONTINUE5__LB_D6_VLINE_INTERRUPT_MASK,
121 .hpd = DISP_INTERRUPT_STATUS_CONTINUE5__DC_HPD6_INTERRUPT_MASK
122} };
123
124static const u32 cz_golden_settings_a11[] =
125{
126 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
127 mmFBC_MISC, 0x1f311fff, 0x14300000,
128};
129
130static const u32 cz_mgcg_cgcg_init[] =
131{
132 mmXDMA_CLOCK_GATING_CNTL, 0xffffffff, 0x00000100,
133 mmXDMA_MEM_POWER_CNTL, 0x00000101, 0x00000000,
134};
135
136static const u32 stoney_golden_settings_a11[] =
137{
138 mmCRTC_DOUBLE_BUFFER_CONTROL, 0x00010101, 0x00010000,
139 mmFBC_MISC, 0x1f311fff, 0x14302000,
140};
141
142static const u32 polaris11_golden_settings_a11[] =
143{
144 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
145 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
146 mmFBC_DEBUG1, 0xffffffff, 0x00000008,
147 mmFBC_MISC, 0x9f313fff, 0x14302008,
148 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
149};
150
151static const u32 polaris10_golden_settings_a11[] =
152{
153 mmDCI_CLK_CNTL, 0x00000080, 0x00000000,
154 mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070,
155 mmFBC_MISC, 0x9f313fff, 0x14302008,
156 mmHDMI_CONTROL, 0x313f031f, 0x00000011,
157};
158
159static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
160{
161 switch (adev->asic_type) {
162 case CHIP_CARRIZO:
163 amdgpu_device_program_register_sequence(adev,
164 cz_mgcg_cgcg_init,
165 ARRAY_SIZE(cz_mgcg_cgcg_init));
166 amdgpu_device_program_register_sequence(adev,
167 cz_golden_settings_a11,
168 ARRAY_SIZE(cz_golden_settings_a11));
169 break;
170 case CHIP_STONEY:
171 amdgpu_device_program_register_sequence(adev,
172 stoney_golden_settings_a11,
173 ARRAY_SIZE(stoney_golden_settings_a11));
174 break;
175 case CHIP_POLARIS11:
176 case CHIP_POLARIS12:
177 amdgpu_device_program_register_sequence(adev,
178 polaris11_golden_settings_a11,
179 ARRAY_SIZE(polaris11_golden_settings_a11));
180 break;
181 case CHIP_POLARIS10:
182 case CHIP_VEGAM:
183 amdgpu_device_program_register_sequence(adev,
184 polaris10_golden_settings_a11,
185 ARRAY_SIZE(polaris10_golden_settings_a11));
186 break;
187 default:
188 break;
189 }
190}
191
192static u32 dce_v11_0_audio_endpt_rreg(struct amdgpu_device *adev,
193 u32 block_offset, u32 reg)
194{
195 unsigned long flags;
196 u32 r;
197
198 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
199 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
200 r = RREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset);
201 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
202
203 return r;
204}
205
206static void dce_v11_0_audio_endpt_wreg(struct amdgpu_device *adev,
207 u32 block_offset, u32 reg, u32 v)
208{
209 unsigned long flags;
210
211 spin_lock_irqsave(&adev->audio_endpt_idx_lock, flags);
212 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
213 WREG32(mmAZALIA_F0_CODEC_ENDPOINT_DATA + block_offset, v);
214 spin_unlock_irqrestore(&adev->audio_endpt_idx_lock, flags);
215}
216
217static u32 dce_v11_0_vblank_get_counter(struct amdgpu_device *adev, int crtc)
218{
219 if (crtc < 0 || crtc >= adev->mode_info.num_crtc)
220 return 0;
221 else
222 return RREG32(mmCRTC_STATUS_FRAME_COUNT + crtc_offsets[crtc]);
223}
224
225static void dce_v11_0_pageflip_interrupt_init(struct amdgpu_device *adev)
226{
227 unsigned i;
228
229 /* Enable pflip interrupts */
230 for (i = 0; i < adev->mode_info.num_crtc; i++)
231 amdgpu_irq_get(adev, &adev->pageflip_irq, i);
232}
233
234static void dce_v11_0_pageflip_interrupt_fini(struct amdgpu_device *adev)
235{
236 unsigned i;
237
238 /* Disable pflip interrupts */
239 for (i = 0; i < adev->mode_info.num_crtc; i++)
240 amdgpu_irq_put(adev, &adev->pageflip_irq, i);
241}
242
243/**
244 * dce_v11_0_page_flip - pageflip callback.
245 *
246 * @adev: amdgpu_device pointer
247 * @crtc_id: crtc to cleanup pageflip on
248 * @crtc_base: new address of the crtc (GPU MC address)
249 *
250 * Triggers the actual pageflip by updating the primary
251 * surface base address.
252 */
253static void dce_v11_0_page_flip(struct amdgpu_device *adev,
254 int crtc_id, u64 crtc_base, bool async)
255{
256 struct amdgpu_crtc *amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
257 struct drm_framebuffer *fb = amdgpu_crtc->base.primary->fb;
258 u32 tmp;
259
260 /* flip immediate for async, default is vsync */
261 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
262 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
263 GRPH_SURFACE_UPDATE_IMMEDIATE_EN, async ? 1 : 0);
264 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
265 /* update pitch */
266 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset,
267 fb->pitches[0] / fb->format->cpp[0]);
268 /* update the scanout addresses */
269 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
270 upper_32_bits(crtc_base));
271 /* writing to the low address triggers the update */
272 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
273 lower_32_bits(crtc_base));
274 /* post the write */
275 RREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset);
276}
277
278static int dce_v11_0_crtc_get_scanoutpos(struct amdgpu_device *adev, int crtc,
279 u32 *vbl, u32 *position)
280{
281 if ((crtc < 0) || (crtc >= adev->mode_info.num_crtc))
282 return -EINVAL;
283
284 *vbl = RREG32(mmCRTC_V_BLANK_START_END + crtc_offsets[crtc]);
285 *position = RREG32(mmCRTC_STATUS_POSITION + crtc_offsets[crtc]);
286
287 return 0;
288}
289
290/**
291 * dce_v11_0_hpd_sense - hpd sense callback.
292 *
293 * @adev: amdgpu_device pointer
294 * @hpd: hpd (hotplug detect) pin
295 *
296 * Checks if a digital monitor is connected (evergreen+).
297 * Returns true if connected, false if not connected.
298 */
299static bool dce_v11_0_hpd_sense(struct amdgpu_device *adev,
300 enum amdgpu_hpd_id hpd)
301{
302 bool connected = false;
303
304 if (hpd >= adev->mode_info.num_hpd)
305 return connected;
306
307 if (RREG32(mmDC_HPD_INT_STATUS + hpd_offsets[hpd]) &
308 DC_HPD_INT_STATUS__DC_HPD_SENSE_MASK)
309 connected = true;
310
311 return connected;
312}
313
314/**
315 * dce_v11_0_hpd_set_polarity - hpd set polarity callback.
316 *
317 * @adev: amdgpu_device pointer
318 * @hpd: hpd (hotplug detect) pin
319 *
320 * Set the polarity of the hpd pin (evergreen+).
321 */
322static void dce_v11_0_hpd_set_polarity(struct amdgpu_device *adev,
323 enum amdgpu_hpd_id hpd)
324{
325 u32 tmp;
326 bool connected = dce_v11_0_hpd_sense(adev, hpd);
327
328 if (hpd >= adev->mode_info.num_hpd)
329 return;
330
331 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
332 if (connected)
333 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 0);
334 else
335 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_POLARITY, 1);
336 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
337}
338
339/**
340 * dce_v11_0_hpd_init - hpd setup callback.
341 *
342 * @adev: amdgpu_device pointer
343 *
344 * Setup the hpd pins used by the card (evergreen+).
345 * Enable the pin, set the polarity, and enable the hpd interrupts.
346 */
347static void dce_v11_0_hpd_init(struct amdgpu_device *adev)
348{
349 struct drm_device *dev = adev->ddev;
350 struct drm_connector *connector;
351 struct drm_connector_list_iter iter;
352 u32 tmp;
353
354 drm_connector_list_iter_begin(dev, &iter);
355 drm_for_each_connector_iter(connector, &iter) {
356 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
357
358 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
359 continue;
360
361 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP ||
362 connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
363 /* don't try to enable hpd on eDP or LVDS avoid breaking the
364 * aux dp channel on imac and help (but not completely fix)
365 * https://bugzilla.redhat.com/show_bug.cgi?id=726143
366 * also avoid interrupt storms during dpms.
367 */
368 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
369 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
370 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
371 continue;
372 }
373
374 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
375 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 1);
376 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
377
378 tmp = RREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd]);
379 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
380 DC_HPD_CONNECT_INT_DELAY,
381 AMDGPU_HPD_CONNECT_INT_DELAY_IN_MS);
382 tmp = REG_SET_FIELD(tmp, DC_HPD_TOGGLE_FILT_CNTL,
383 DC_HPD_DISCONNECT_INT_DELAY,
384 AMDGPU_HPD_DISCONNECT_INT_DELAY_IN_MS);
385 WREG32(mmDC_HPD_TOGGLE_FILT_CNTL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
386
387 dce_v11_0_hpd_set_polarity(adev, amdgpu_connector->hpd.hpd);
388 amdgpu_irq_get(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
389 }
390 drm_connector_list_iter_end(&iter);
391}
392
393/**
394 * dce_v11_0_hpd_fini - hpd tear down callback.
395 *
396 * @adev: amdgpu_device pointer
397 *
398 * Tear down the hpd pins used by the card (evergreen+).
399 * Disable the hpd interrupts.
400 */
401static void dce_v11_0_hpd_fini(struct amdgpu_device *adev)
402{
403 struct drm_device *dev = adev->ddev;
404 struct drm_connector *connector;
405 struct drm_connector_list_iter iter;
406 u32 tmp;
407
408 drm_connector_list_iter_begin(dev, &iter);
409 drm_for_each_connector_iter(connector, &iter) {
410 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
411
412 if (amdgpu_connector->hpd.hpd >= adev->mode_info.num_hpd)
413 continue;
414
415 tmp = RREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd]);
416 tmp = REG_SET_FIELD(tmp, DC_HPD_CONTROL, DC_HPD_EN, 0);
417 WREG32(mmDC_HPD_CONTROL + hpd_offsets[amdgpu_connector->hpd.hpd], tmp);
418
419 amdgpu_irq_put(adev, &adev->hpd_irq, amdgpu_connector->hpd.hpd);
420 }
421 drm_connector_list_iter_end(&iter);
422}
423
424static u32 dce_v11_0_hpd_get_gpio_reg(struct amdgpu_device *adev)
425{
426 return mmDC_GPIO_HPD_A;
427}
428
429static bool dce_v11_0_is_display_hung(struct amdgpu_device *adev)
430{
431 u32 crtc_hung = 0;
432 u32 crtc_status[6];
433 u32 i, j, tmp;
434
435 for (i = 0; i < adev->mode_info.num_crtc; i++) {
436 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
437 if (REG_GET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN)) {
438 crtc_status[i] = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
439 crtc_hung |= (1 << i);
440 }
441 }
442
443 for (j = 0; j < 10; j++) {
444 for (i = 0; i < adev->mode_info.num_crtc; i++) {
445 if (crtc_hung & (1 << i)) {
446 tmp = RREG32(mmCRTC_STATUS_HV_COUNT + crtc_offsets[i]);
447 if (tmp != crtc_status[i])
448 crtc_hung &= ~(1 << i);
449 }
450 }
451 if (crtc_hung == 0)
452 return false;
453 udelay(100);
454 }
455
456 return true;
457}
458
459static void dce_v11_0_set_vga_render_state(struct amdgpu_device *adev,
460 bool render)
461{
462 u32 tmp;
463
464 /* Lockout access through VGA aperture*/
465 tmp = RREG32(mmVGA_HDP_CONTROL);
466 if (render)
467 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 0);
468 else
469 tmp = REG_SET_FIELD(tmp, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
470 WREG32(mmVGA_HDP_CONTROL, tmp);
471
472 /* disable VGA render */
473 tmp = RREG32(mmVGA_RENDER_CONTROL);
474 if (render)
475 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 1);
476 else
477 tmp = REG_SET_FIELD(tmp, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
478 WREG32(mmVGA_RENDER_CONTROL, tmp);
479}
480
481static int dce_v11_0_get_num_crtc (struct amdgpu_device *adev)
482{
483 int num_crtc = 0;
484
485 switch (adev->asic_type) {
486 case CHIP_CARRIZO:
487 num_crtc = 3;
488 break;
489 case CHIP_STONEY:
490 num_crtc = 2;
491 break;
492 case CHIP_POLARIS10:
493 case CHIP_VEGAM:
494 num_crtc = 6;
495 break;
496 case CHIP_POLARIS11:
497 case CHIP_POLARIS12:
498 num_crtc = 5;
499 break;
500 default:
501 num_crtc = 0;
502 }
503 return num_crtc;
504}
505
506void dce_v11_0_disable_dce(struct amdgpu_device *adev)
507{
508 /*Disable VGA render and enabled crtc, if has DCE engine*/
509 if (amdgpu_atombios_has_dce_engine_info(adev)) {
510 u32 tmp;
511 int crtc_enabled, i;
512
513 dce_v11_0_set_vga_render_state(adev, false);
514
515 /*Disable crtc*/
516 for (i = 0; i < dce_v11_0_get_num_crtc(adev); i++) {
517 crtc_enabled = REG_GET_FIELD(RREG32(mmCRTC_CONTROL + crtc_offsets[i]),
518 CRTC_CONTROL, CRTC_MASTER_EN);
519 if (crtc_enabled) {
520 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 1);
521 tmp = RREG32(mmCRTC_CONTROL + crtc_offsets[i]);
522 tmp = REG_SET_FIELD(tmp, CRTC_CONTROL, CRTC_MASTER_EN, 0);
523 WREG32(mmCRTC_CONTROL + crtc_offsets[i], tmp);
524 WREG32(mmCRTC_UPDATE_LOCK + crtc_offsets[i], 0);
525 }
526 }
527 }
528}
529
530static void dce_v11_0_program_fmt(struct drm_encoder *encoder)
531{
532 struct drm_device *dev = encoder->dev;
533 struct amdgpu_device *adev = dev->dev_private;
534 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
535 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
536 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
537 int bpc = 0;
538 u32 tmp = 0;
539 enum amdgpu_connector_dither dither = AMDGPU_FMT_DITHER_DISABLE;
540
541 if (connector) {
542 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
543 bpc = amdgpu_connector_get_monitor_bpc(connector);
544 dither = amdgpu_connector->dither;
545 }
546
547 /* LVDS/eDP FMT is set up by atom */
548 if (amdgpu_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
549 return;
550
551 /* not needed for analog */
552 if ((amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1) ||
553 (amdgpu_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2))
554 return;
555
556 if (bpc == 0)
557 return;
558
559 switch (bpc) {
560 case 6:
561 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
562 /* XXX sort out optimal dither settings */
563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
564 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
565 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
566 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0);
567 } else {
568 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0);
570 }
571 break;
572 case 8:
573 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
574 /* XXX sort out optimal dither settings */
575 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
576 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
577 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
578 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
579 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 1);
580 } else {
581 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
582 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 1);
583 }
584 break;
585 case 10:
586 if (dither == AMDGPU_FMT_DITHER_ENABLE) {
587 /* XXX sort out optimal dither settings */
588 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1);
589 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1);
590 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1);
591 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1);
592 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 2);
593 } else {
594 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1);
595 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 2);
596 }
597 break;
598 default:
599 /* not needed */
600 break;
601 }
602
603 WREG32(mmFMT_BIT_DEPTH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
604}
605
606
607/* display watermark setup */
608/**
609 * dce_v11_0_line_buffer_adjust - Set up the line buffer
610 *
611 * @adev: amdgpu_device pointer
612 * @amdgpu_crtc: the selected display controller
613 * @mode: the current display mode on the selected display
614 * controller
615 *
616 * Setup up the line buffer allocation for
617 * the selected display controller (CIK).
618 * Returns the line buffer size in pixels.
619 */
620static u32 dce_v11_0_line_buffer_adjust(struct amdgpu_device *adev,
621 struct amdgpu_crtc *amdgpu_crtc,
622 struct drm_display_mode *mode)
623{
624 u32 tmp, buffer_alloc, i, mem_cfg;
625 u32 pipe_offset = amdgpu_crtc->crtc_id;
626 /*
627 * Line Buffer Setup
628 * There are 6 line buffers, one for each display controllers.
629 * There are 3 partitions per LB. Select the number of partitions
630 * to enable based on the display width. For display widths larger
631 * than 4096, you need use to use 2 display controllers and combine
632 * them using the stereo blender.
633 */
634 if (amdgpu_crtc->base.enabled && mode) {
635 if (mode->crtc_hdisplay < 1920) {
636 mem_cfg = 1;
637 buffer_alloc = 2;
638 } else if (mode->crtc_hdisplay < 2560) {
639 mem_cfg = 2;
640 buffer_alloc = 2;
641 } else if (mode->crtc_hdisplay < 4096) {
642 mem_cfg = 0;
643 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
644 } else {
645 DRM_DEBUG_KMS("Mode too big for LB!\n");
646 mem_cfg = 0;
647 buffer_alloc = (adev->flags & AMD_IS_APU) ? 2 : 4;
648 }
649 } else {
650 mem_cfg = 1;
651 buffer_alloc = 0;
652 }
653
654 tmp = RREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset);
655 tmp = REG_SET_FIELD(tmp, LB_MEMORY_CTRL, LB_MEMORY_CONFIG, mem_cfg);
656 WREG32(mmLB_MEMORY_CTRL + amdgpu_crtc->crtc_offset, tmp);
657
658 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
659 tmp = REG_SET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATED, buffer_alloc);
660 WREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset, tmp);
661
662 for (i = 0; i < adev->usec_timeout; i++) {
663 tmp = RREG32(mmPIPE0_DMIF_BUFFER_CONTROL + pipe_offset);
664 if (REG_GET_FIELD(tmp, PIPE0_DMIF_BUFFER_CONTROL, DMIF_BUFFERS_ALLOCATION_COMPLETED))
665 break;
666 udelay(1);
667 }
668
669 if (amdgpu_crtc->base.enabled && mode) {
670 switch (mem_cfg) {
671 case 0:
672 default:
673 return 4096 * 2;
674 case 1:
675 return 1920 * 2;
676 case 2:
677 return 2560 * 2;
678 }
679 }
680
681 /* controller not enabled, so no lb used */
682 return 0;
683}
684
685/**
686 * cik_get_number_of_dram_channels - get the number of dram channels
687 *
688 * @adev: amdgpu_device pointer
689 *
690 * Look up the number of video ram channels (CIK).
691 * Used for display watermark bandwidth calculations
692 * Returns the number of dram channels
693 */
694static u32 cik_get_number_of_dram_channels(struct amdgpu_device *adev)
695{
696 u32 tmp = RREG32(mmMC_SHARED_CHMAP);
697
698 switch (REG_GET_FIELD(tmp, MC_SHARED_CHMAP, NOOFCHAN)) {
699 case 0:
700 default:
701 return 1;
702 case 1:
703 return 2;
704 case 2:
705 return 4;
706 case 3:
707 return 8;
708 case 4:
709 return 3;
710 case 5:
711 return 6;
712 case 6:
713 return 10;
714 case 7:
715 return 12;
716 case 8:
717 return 16;
718 }
719}
720
721struct dce10_wm_params {
722 u32 dram_channels; /* number of dram channels */
723 u32 yclk; /* bandwidth per dram data pin in kHz */
724 u32 sclk; /* engine clock in kHz */
725 u32 disp_clk; /* display clock in kHz */
726 u32 src_width; /* viewport width */
727 u32 active_time; /* active display time in ns */
728 u32 blank_time; /* blank time in ns */
729 bool interlaced; /* mode is interlaced */
730 fixed20_12 vsc; /* vertical scale ratio */
731 u32 num_heads; /* number of active crtcs */
732 u32 bytes_per_pixel; /* bytes per pixel display + overlay */
733 u32 lb_size; /* line buffer allocated to pipe */
734 u32 vtaps; /* vertical scaler taps */
735};
736
737/**
738 * dce_v11_0_dram_bandwidth - get the dram bandwidth
739 *
740 * @wm: watermark calculation data
741 *
742 * Calculate the raw dram bandwidth (CIK).
743 * Used for display watermark bandwidth calculations
744 * Returns the dram bandwidth in MBytes/s
745 */
746static u32 dce_v11_0_dram_bandwidth(struct dce10_wm_params *wm)
747{
748 /* Calculate raw DRAM Bandwidth */
749 fixed20_12 dram_efficiency; /* 0.7 */
750 fixed20_12 yclk, dram_channels, bandwidth;
751 fixed20_12 a;
752
753 a.full = dfixed_const(1000);
754 yclk.full = dfixed_const(wm->yclk);
755 yclk.full = dfixed_div(yclk, a);
756 dram_channels.full = dfixed_const(wm->dram_channels * 4);
757 a.full = dfixed_const(10);
758 dram_efficiency.full = dfixed_const(7);
759 dram_efficiency.full = dfixed_div(dram_efficiency, a);
760 bandwidth.full = dfixed_mul(dram_channels, yclk);
761 bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
762
763 return dfixed_trunc(bandwidth);
764}
765
766/**
767 * dce_v11_0_dram_bandwidth_for_display - get the dram bandwidth for display
768 *
769 * @wm: watermark calculation data
770 *
771 * Calculate the dram bandwidth used for display (CIK).
772 * Used for display watermark bandwidth calculations
773 * Returns the dram bandwidth for display in MBytes/s
774 */
775static u32 dce_v11_0_dram_bandwidth_for_display(struct dce10_wm_params *wm)
776{
777 /* Calculate DRAM Bandwidth and the part allocated to display. */
778 fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
779 fixed20_12 yclk, dram_channels, bandwidth;
780 fixed20_12 a;
781
782 a.full = dfixed_const(1000);
783 yclk.full = dfixed_const(wm->yclk);
784 yclk.full = dfixed_div(yclk, a);
785 dram_channels.full = dfixed_const(wm->dram_channels * 4);
786 a.full = dfixed_const(10);
787 disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
788 disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
789 bandwidth.full = dfixed_mul(dram_channels, yclk);
790 bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
791
792 return dfixed_trunc(bandwidth);
793}
794
795/**
796 * dce_v11_0_data_return_bandwidth - get the data return bandwidth
797 *
798 * @wm: watermark calculation data
799 *
800 * Calculate the data return bandwidth used for display (CIK).
801 * Used for display watermark bandwidth calculations
802 * Returns the data return bandwidth in MBytes/s
803 */
804static u32 dce_v11_0_data_return_bandwidth(struct dce10_wm_params *wm)
805{
806 /* Calculate the display Data return Bandwidth */
807 fixed20_12 return_efficiency; /* 0.8 */
808 fixed20_12 sclk, bandwidth;
809 fixed20_12 a;
810
811 a.full = dfixed_const(1000);
812 sclk.full = dfixed_const(wm->sclk);
813 sclk.full = dfixed_div(sclk, a);
814 a.full = dfixed_const(10);
815 return_efficiency.full = dfixed_const(8);
816 return_efficiency.full = dfixed_div(return_efficiency, a);
817 a.full = dfixed_const(32);
818 bandwidth.full = dfixed_mul(a, sclk);
819 bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
820
821 return dfixed_trunc(bandwidth);
822}
823
824/**
825 * dce_v11_0_dmif_request_bandwidth - get the dmif bandwidth
826 *
827 * @wm: watermark calculation data
828 *
829 * Calculate the dmif bandwidth used for display (CIK).
830 * Used for display watermark bandwidth calculations
831 * Returns the dmif bandwidth in MBytes/s
832 */
833static u32 dce_v11_0_dmif_request_bandwidth(struct dce10_wm_params *wm)
834{
835 /* Calculate the DMIF Request Bandwidth */
836 fixed20_12 disp_clk_request_efficiency; /* 0.8 */
837 fixed20_12 disp_clk, bandwidth;
838 fixed20_12 a, b;
839
840 a.full = dfixed_const(1000);
841 disp_clk.full = dfixed_const(wm->disp_clk);
842 disp_clk.full = dfixed_div(disp_clk, a);
843 a.full = dfixed_const(32);
844 b.full = dfixed_mul(a, disp_clk);
845
846 a.full = dfixed_const(10);
847 disp_clk_request_efficiency.full = dfixed_const(8);
848 disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
849
850 bandwidth.full = dfixed_mul(b, disp_clk_request_efficiency);
851
852 return dfixed_trunc(bandwidth);
853}
854
855/**
856 * dce_v11_0_available_bandwidth - get the min available bandwidth
857 *
858 * @wm: watermark calculation data
859 *
860 * Calculate the min available bandwidth used for display (CIK).
861 * Used for display watermark bandwidth calculations
862 * Returns the min available bandwidth in MBytes/s
863 */
864static u32 dce_v11_0_available_bandwidth(struct dce10_wm_params *wm)
865{
866 /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
867 u32 dram_bandwidth = dce_v11_0_dram_bandwidth(wm);
868 u32 data_return_bandwidth = dce_v11_0_data_return_bandwidth(wm);
869 u32 dmif_req_bandwidth = dce_v11_0_dmif_request_bandwidth(wm);
870
871 return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
872}
873
874/**
875 * dce_v11_0_average_bandwidth - get the average available bandwidth
876 *
877 * @wm: watermark calculation data
878 *
879 * Calculate the average available bandwidth used for display (CIK).
880 * Used for display watermark bandwidth calculations
881 * Returns the average available bandwidth in MBytes/s
882 */
883static u32 dce_v11_0_average_bandwidth(struct dce10_wm_params *wm)
884{
885 /* Calculate the display mode Average Bandwidth
886 * DisplayMode should contain the source and destination dimensions,
887 * timing, etc.
888 */
889 fixed20_12 bpp;
890 fixed20_12 line_time;
891 fixed20_12 src_width;
892 fixed20_12 bandwidth;
893 fixed20_12 a;
894
895 a.full = dfixed_const(1000);
896 line_time.full = dfixed_const(wm->active_time + wm->blank_time);
897 line_time.full = dfixed_div(line_time, a);
898 bpp.full = dfixed_const(wm->bytes_per_pixel);
899 src_width.full = dfixed_const(wm->src_width);
900 bandwidth.full = dfixed_mul(src_width, bpp);
901 bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
902 bandwidth.full = dfixed_div(bandwidth, line_time);
903
904 return dfixed_trunc(bandwidth);
905}
906
907/**
908 * dce_v11_0_latency_watermark - get the latency watermark
909 *
910 * @wm: watermark calculation data
911 *
912 * Calculate the latency watermark (CIK).
913 * Used for display watermark bandwidth calculations
914 * Returns the latency watermark in ns
915 */
916static u32 dce_v11_0_latency_watermark(struct dce10_wm_params *wm)
917{
918 /* First calculate the latency in ns */
919 u32 mc_latency = 2000; /* 2000 ns. */
920 u32 available_bandwidth = dce_v11_0_available_bandwidth(wm);
921 u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
922 u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
923 u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
924 u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
925 (wm->num_heads * cursor_line_pair_return_time);
926 u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
927 u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
928 u32 tmp, dmif_size = 12288;
929 fixed20_12 a, b, c;
930
931 if (wm->num_heads == 0)
932 return 0;
933
934 a.full = dfixed_const(2);
935 b.full = dfixed_const(1);
936 if ((wm->vsc.full > a.full) ||
937 ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
938 (wm->vtaps >= 5) ||
939 ((wm->vsc.full >= a.full) && wm->interlaced))
940 max_src_lines_per_dst_line = 4;
941 else
942 max_src_lines_per_dst_line = 2;
943
944 a.full = dfixed_const(available_bandwidth);
945 b.full = dfixed_const(wm->num_heads);
946 a.full = dfixed_div(a, b);
947 tmp = div_u64((u64) dmif_size * (u64) wm->disp_clk, mc_latency + 512);
948 tmp = min(dfixed_trunc(a), tmp);
949
950 lb_fill_bw = min(tmp, wm->disp_clk * wm->bytes_per_pixel / 1000);
951
952 a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
953 b.full = dfixed_const(1000);
954 c.full = dfixed_const(lb_fill_bw);
955 b.full = dfixed_div(c, b);
956 a.full = dfixed_div(a, b);
957 line_fill_time = dfixed_trunc(a);
958
959 if (line_fill_time < wm->active_time)
960 return latency;
961 else
962 return latency + (line_fill_time - wm->active_time);
963
964}
965
966/**
967 * dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display - check
968 * average and available dram bandwidth
969 *
970 * @wm: watermark calculation data
971 *
972 * Check if the display average bandwidth fits in the display
973 * dram bandwidth (CIK).
974 * Used for display watermark bandwidth calculations
975 * Returns true if the display fits, false if not.
976 */
977static bool dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(struct dce10_wm_params *wm)
978{
979 if (dce_v11_0_average_bandwidth(wm) <=
980 (dce_v11_0_dram_bandwidth_for_display(wm) / wm->num_heads))
981 return true;
982 else
983 return false;
984}
985
986/**
987 * dce_v11_0_average_bandwidth_vs_available_bandwidth - check
988 * average and available bandwidth
989 *
990 * @wm: watermark calculation data
991 *
992 * Check if the display average bandwidth fits in the display
993 * available bandwidth (CIK).
994 * Used for display watermark bandwidth calculations
995 * Returns true if the display fits, false if not.
996 */
997static bool dce_v11_0_average_bandwidth_vs_available_bandwidth(struct dce10_wm_params *wm)
998{
999 if (dce_v11_0_average_bandwidth(wm) <=
1000 (dce_v11_0_available_bandwidth(wm) / wm->num_heads))
1001 return true;
1002 else
1003 return false;
1004}
1005
1006/**
1007 * dce_v11_0_check_latency_hiding - check latency hiding
1008 *
1009 * @wm: watermark calculation data
1010 *
1011 * Check latency hiding (CIK).
1012 * Used for display watermark bandwidth calculations
1013 * Returns true if the display fits, false if not.
1014 */
1015static bool dce_v11_0_check_latency_hiding(struct dce10_wm_params *wm)
1016{
1017 u32 lb_partitions = wm->lb_size / wm->src_width;
1018 u32 line_time = wm->active_time + wm->blank_time;
1019 u32 latency_tolerant_lines;
1020 u32 latency_hiding;
1021 fixed20_12 a;
1022
1023 a.full = dfixed_const(1);
1024 if (wm->vsc.full > a.full)
1025 latency_tolerant_lines = 1;
1026 else {
1027 if (lb_partitions <= (wm->vtaps + 1))
1028 latency_tolerant_lines = 1;
1029 else
1030 latency_tolerant_lines = 2;
1031 }
1032
1033 latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
1034
1035 if (dce_v11_0_latency_watermark(wm) <= latency_hiding)
1036 return true;
1037 else
1038 return false;
1039}
1040
1041/**
1042 * dce_v11_0_program_watermarks - program display watermarks
1043 *
1044 * @adev: amdgpu_device pointer
1045 * @amdgpu_crtc: the selected display controller
1046 * @lb_size: line buffer size
1047 * @num_heads: number of display controllers in use
1048 *
1049 * Calculate and program the display watermarks for the
1050 * selected display controller (CIK).
1051 */
1052static void dce_v11_0_program_watermarks(struct amdgpu_device *adev,
1053 struct amdgpu_crtc *amdgpu_crtc,
1054 u32 lb_size, u32 num_heads)
1055{
1056 struct drm_display_mode *mode = &amdgpu_crtc->base.mode;
1057 struct dce10_wm_params wm_low, wm_high;
1058 u32 active_time;
1059 u32 line_time = 0;
1060 u32 latency_watermark_a = 0, latency_watermark_b = 0;
1061 u32 tmp, wm_mask, lb_vblank_lead_lines = 0;
1062
1063 if (amdgpu_crtc->base.enabled && num_heads && mode) {
1064 active_time = (u32) div_u64((u64)mode->crtc_hdisplay * 1000000,
1065 (u32)mode->clock);
1066 line_time = (u32) div_u64((u64)mode->crtc_htotal * 1000000,
1067 (u32)mode->clock);
1068 line_time = min(line_time, (u32)65535);
1069
1070 /* watermark for high clocks */
1071 if (adev->pm.dpm_enabled) {
1072 wm_high.yclk =
1073 amdgpu_dpm_get_mclk(adev, false) * 10;
1074 wm_high.sclk =
1075 amdgpu_dpm_get_sclk(adev, false) * 10;
1076 } else {
1077 wm_high.yclk = adev->pm.current_mclk * 10;
1078 wm_high.sclk = adev->pm.current_sclk * 10;
1079 }
1080
1081 wm_high.disp_clk = mode->clock;
1082 wm_high.src_width = mode->crtc_hdisplay;
1083 wm_high.active_time = active_time;
1084 wm_high.blank_time = line_time - wm_high.active_time;
1085 wm_high.interlaced = false;
1086 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1087 wm_high.interlaced = true;
1088 wm_high.vsc = amdgpu_crtc->vsc;
1089 wm_high.vtaps = 1;
1090 if (amdgpu_crtc->rmx_type != RMX_OFF)
1091 wm_high.vtaps = 2;
1092 wm_high.bytes_per_pixel = 4; /* XXX: get this from fb config */
1093 wm_high.lb_size = lb_size;
1094 wm_high.dram_channels = cik_get_number_of_dram_channels(adev);
1095 wm_high.num_heads = num_heads;
1096
1097 /* set for high clocks */
1098 latency_watermark_a = min(dce_v11_0_latency_watermark(&wm_high), (u32)65535);
1099
1100 /* possibly force display priority to high */
1101 /* should really do this at mode validation time... */
1102 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_high) ||
1103 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_high) ||
1104 !dce_v11_0_check_latency_hiding(&wm_high) ||
1105 (adev->mode_info.disp_priority == 2)) {
1106 DRM_DEBUG_KMS("force priority to high\n");
1107 }
1108
1109 /* watermark for low clocks */
1110 if (adev->pm.dpm_enabled) {
1111 wm_low.yclk =
1112 amdgpu_dpm_get_mclk(adev, true) * 10;
1113 wm_low.sclk =
1114 amdgpu_dpm_get_sclk(adev, true) * 10;
1115 } else {
1116 wm_low.yclk = adev->pm.current_mclk * 10;
1117 wm_low.sclk = adev->pm.current_sclk * 10;
1118 }
1119
1120 wm_low.disp_clk = mode->clock;
1121 wm_low.src_width = mode->crtc_hdisplay;
1122 wm_low.active_time = active_time;
1123 wm_low.blank_time = line_time - wm_low.active_time;
1124 wm_low.interlaced = false;
1125 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1126 wm_low.interlaced = true;
1127 wm_low.vsc = amdgpu_crtc->vsc;
1128 wm_low.vtaps = 1;
1129 if (amdgpu_crtc->rmx_type != RMX_OFF)
1130 wm_low.vtaps = 2;
1131 wm_low.bytes_per_pixel = 4; /* XXX: get this from fb config */
1132 wm_low.lb_size = lb_size;
1133 wm_low.dram_channels = cik_get_number_of_dram_channels(adev);
1134 wm_low.num_heads = num_heads;
1135
1136 /* set for low clocks */
1137 latency_watermark_b = min(dce_v11_0_latency_watermark(&wm_low), (u32)65535);
1138
1139 /* possibly force display priority to high */
1140 /* should really do this at mode validation time... */
1141 if (!dce_v11_0_average_bandwidth_vs_dram_bandwidth_for_display(&wm_low) ||
1142 !dce_v11_0_average_bandwidth_vs_available_bandwidth(&wm_low) ||
1143 !dce_v11_0_check_latency_hiding(&wm_low) ||
1144 (adev->mode_info.disp_priority == 2)) {
1145 DRM_DEBUG_KMS("force priority to high\n");
1146 }
1147 lb_vblank_lead_lines = DIV_ROUND_UP(lb_size, mode->crtc_hdisplay);
1148 }
1149
1150 /* select wm A */
1151 wm_mask = RREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset);
1152 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 1);
1153 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1154 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1155 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_a);
1156 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1157 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1158 /* select wm B */
1159 tmp = REG_SET_FIELD(wm_mask, DPG_WATERMARK_MASK_CONTROL, URGENCY_WATERMARK_MASK, 2);
1160 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1161 tmp = RREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset);
1162 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_LOW_WATERMARK, latency_watermark_b);
1163 tmp = REG_SET_FIELD(tmp, DPG_PIPE_URGENCY_CONTROL, URGENCY_HIGH_WATERMARK, line_time);
1164 WREG32(mmDPG_PIPE_URGENCY_CONTROL + amdgpu_crtc->crtc_offset, tmp);
1165 /* restore original selection */
1166 WREG32(mmDPG_WATERMARK_MASK_CONTROL + amdgpu_crtc->crtc_offset, wm_mask);
1167
1168 /* save values for DPM */
1169 amdgpu_crtc->line_time = line_time;
1170 amdgpu_crtc->wm_high = latency_watermark_a;
1171 amdgpu_crtc->wm_low = latency_watermark_b;
1172 /* Save number of lines the linebuffer leads before the scanout */
1173 amdgpu_crtc->lb_vblank_lead_lines = lb_vblank_lead_lines;
1174}
1175
1176/**
1177 * dce_v11_0_bandwidth_update - program display watermarks
1178 *
1179 * @adev: amdgpu_device pointer
1180 *
1181 * Calculate and program the display watermarks and line
1182 * buffer allocation (CIK).
1183 */
1184static void dce_v11_0_bandwidth_update(struct amdgpu_device *adev)
1185{
1186 struct drm_display_mode *mode = NULL;
1187 u32 num_heads = 0, lb_size;
1188 int i;
1189
1190 amdgpu_display_update_priority(adev);
1191
1192 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1193 if (adev->mode_info.crtcs[i]->base.enabled)
1194 num_heads++;
1195 }
1196 for (i = 0; i < adev->mode_info.num_crtc; i++) {
1197 mode = &adev->mode_info.crtcs[i]->base.mode;
1198 lb_size = dce_v11_0_line_buffer_adjust(adev, adev->mode_info.crtcs[i], mode);
1199 dce_v11_0_program_watermarks(adev, adev->mode_info.crtcs[i],
1200 lb_size, num_heads);
1201 }
1202}
1203
1204static void dce_v11_0_audio_get_connected_pins(struct amdgpu_device *adev)
1205{
1206 int i;
1207 u32 offset, tmp;
1208
1209 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1210 offset = adev->mode_info.audio.pin[i].offset;
1211 tmp = RREG32_AUDIO_ENDPT(offset,
1212 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
1213 if (((tmp &
1214 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY_MASK) >>
1215 AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT__PORT_CONNECTIVITY__SHIFT) == 1)
1216 adev->mode_info.audio.pin[i].connected = false;
1217 else
1218 adev->mode_info.audio.pin[i].connected = true;
1219 }
1220}
1221
1222static struct amdgpu_audio_pin *dce_v11_0_audio_get_pin(struct amdgpu_device *adev)
1223{
1224 int i;
1225
1226 dce_v11_0_audio_get_connected_pins(adev);
1227
1228 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1229 if (adev->mode_info.audio.pin[i].connected)
1230 return &adev->mode_info.audio.pin[i];
1231 }
1232 DRM_ERROR("No connected audio pins found!\n");
1233 return NULL;
1234}
1235
1236static void dce_v11_0_afmt_audio_select_pin(struct drm_encoder *encoder)
1237{
1238 struct amdgpu_device *adev = encoder->dev->dev_private;
1239 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1240 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1241 u32 tmp;
1242
1243 if (!dig || !dig->afmt || !dig->afmt->pin)
1244 return;
1245
1246 tmp = RREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset);
1247 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_SRC_CONTROL, AFMT_AUDIO_SRC_SELECT, dig->afmt->pin->id);
1248 WREG32(mmAFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, tmp);
1249}
1250
1251static void dce_v11_0_audio_write_latency_fields(struct drm_encoder *encoder,
1252 struct drm_display_mode *mode)
1253{
1254 struct drm_device *dev = encoder->dev;
1255 struct amdgpu_device *adev = dev->dev_private;
1256 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1257 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1258 struct drm_connector *connector;
1259 struct drm_connector_list_iter iter;
1260 struct amdgpu_connector *amdgpu_connector = NULL;
1261 u32 tmp;
1262 int interlace = 0;
1263
1264 if (!dig || !dig->afmt || !dig->afmt->pin)
1265 return;
1266
1267 drm_connector_list_iter_begin(dev, &iter);
1268 drm_for_each_connector_iter(connector, &iter) {
1269 if (connector->encoder == encoder) {
1270 amdgpu_connector = to_amdgpu_connector(connector);
1271 break;
1272 }
1273 }
1274 drm_connector_list_iter_end(&iter);
1275
1276 if (!amdgpu_connector) {
1277 DRM_ERROR("Couldn't find encoder's connector\n");
1278 return;
1279 }
1280
1281 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1282 interlace = 1;
1283 if (connector->latency_present[interlace]) {
1284 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1285 VIDEO_LIPSYNC, connector->video_latency[interlace]);
1286 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1287 AUDIO_LIPSYNC, connector->audio_latency[interlace]);
1288 } else {
1289 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1290 VIDEO_LIPSYNC, 0);
1291 tmp = REG_SET_FIELD(0, AZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC,
1292 AUDIO_LIPSYNC, 0);
1293 }
1294 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1295 ixAZALIA_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
1296}
1297
1298static void dce_v11_0_audio_write_speaker_allocation(struct drm_encoder *encoder)
1299{
1300 struct drm_device *dev = encoder->dev;
1301 struct amdgpu_device *adev = dev->dev_private;
1302 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1303 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1304 struct drm_connector *connector;
1305 struct drm_connector_list_iter iter;
1306 struct amdgpu_connector *amdgpu_connector = NULL;
1307 u32 tmp;
1308 u8 *sadb = NULL;
1309 int sad_count;
1310
1311 if (!dig || !dig->afmt || !dig->afmt->pin)
1312 return;
1313
1314 drm_connector_list_iter_begin(dev, &iter);
1315 drm_for_each_connector_iter(connector, &iter) {
1316 if (connector->encoder == encoder) {
1317 amdgpu_connector = to_amdgpu_connector(connector);
1318 break;
1319 }
1320 }
1321 drm_connector_list_iter_end(&iter);
1322
1323 if (!amdgpu_connector) {
1324 DRM_ERROR("Couldn't find encoder's connector\n");
1325 return;
1326 }
1327
1328 sad_count = drm_edid_to_speaker_allocation(amdgpu_connector_edid(connector), &sadb);
1329 if (sad_count < 0) {
1330 DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
1331 sad_count = 0;
1332 }
1333
1334 /* program the speaker allocation */
1335 tmp = RREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1336 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
1337 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1338 DP_CONNECTION, 0);
1339 /* set HDMI mode */
1340 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1341 HDMI_CONNECTION, 1);
1342 if (sad_count)
1343 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1344 SPEAKER_ALLOCATION, sadb[0]);
1345 else
1346 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER,
1347 SPEAKER_ALLOCATION, 5); /* stereo */
1348 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset,
1349 ixAZALIA_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
1350
1351 kfree(sadb);
1352}
1353
1354static void dce_v11_0_audio_write_sad_regs(struct drm_encoder *encoder)
1355{
1356 struct drm_device *dev = encoder->dev;
1357 struct amdgpu_device *adev = dev->dev_private;
1358 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1359 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1360 struct drm_connector *connector;
1361 struct drm_connector_list_iter iter;
1362 struct amdgpu_connector *amdgpu_connector = NULL;
1363 struct cea_sad *sads;
1364 int i, sad_count;
1365
1366 static const u16 eld_reg_to_type[][2] = {
1367 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
1368 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
1369 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
1370 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
1371 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
1372 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
1373 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
1374 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
1375 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
1376 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
1377 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
1378 { ixAZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
1379 };
1380
1381 if (!dig || !dig->afmt || !dig->afmt->pin)
1382 return;
1383
1384 drm_connector_list_iter_begin(dev, &iter);
1385 drm_for_each_connector_iter(connector, &iter) {
1386 if (connector->encoder == encoder) {
1387 amdgpu_connector = to_amdgpu_connector(connector);
1388 break;
1389 }
1390 }
1391 drm_connector_list_iter_end(&iter);
1392
1393 if (!amdgpu_connector) {
1394 DRM_ERROR("Couldn't find encoder's connector\n");
1395 return;
1396 }
1397
1398 sad_count = drm_edid_to_sad(amdgpu_connector_edid(connector), &sads);
1399 if (sad_count < 0)
1400 DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
1401 if (sad_count <= 0)
1402 return;
1403 BUG_ON(!sads);
1404
1405 for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
1406 u32 tmp = 0;
1407 u8 stereo_freqs = 0;
1408 int max_channels = -1;
1409 int j;
1410
1411 for (j = 0; j < sad_count; j++) {
1412 struct cea_sad *sad = &sads[j];
1413
1414 if (sad->format == eld_reg_to_type[i][1]) {
1415 if (sad->channels > max_channels) {
1416 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1417 MAX_CHANNELS, sad->channels);
1418 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1419 DESCRIPTOR_BYTE_2, sad->byte2);
1420 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1421 SUPPORTED_FREQUENCIES, sad->freq);
1422 max_channels = sad->channels;
1423 }
1424
1425 if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
1426 stereo_freqs |= sad->freq;
1427 else
1428 break;
1429 }
1430 }
1431
1432 tmp = REG_SET_FIELD(tmp, AZALIA_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0,
1433 SUPPORTED_FREQUENCIES_STEREO, stereo_freqs);
1434 WREG32_AUDIO_ENDPT(dig->afmt->pin->offset, eld_reg_to_type[i][0], tmp);
1435 }
1436
1437 kfree(sads);
1438}
1439
1440static void dce_v11_0_audio_enable(struct amdgpu_device *adev,
1441 struct amdgpu_audio_pin *pin,
1442 bool enable)
1443{
1444 if (!pin)
1445 return;
1446
1447 WREG32_AUDIO_ENDPT(pin->offset, ixAZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL,
1448 enable ? AZALIA_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL__AUDIO_ENABLED_MASK : 0);
1449}
1450
1451static const u32 pin_offsets[] =
1452{
1453 AUD0_REGISTER_OFFSET,
1454 AUD1_REGISTER_OFFSET,
1455 AUD2_REGISTER_OFFSET,
1456 AUD3_REGISTER_OFFSET,
1457 AUD4_REGISTER_OFFSET,
1458 AUD5_REGISTER_OFFSET,
1459 AUD6_REGISTER_OFFSET,
1460 AUD7_REGISTER_OFFSET,
1461};
1462
1463static int dce_v11_0_audio_init(struct amdgpu_device *adev)
1464{
1465 int i;
1466
1467 if (!amdgpu_audio)
1468 return 0;
1469
1470 adev->mode_info.audio.enabled = true;
1471
1472 switch (adev->asic_type) {
1473 case CHIP_CARRIZO:
1474 case CHIP_STONEY:
1475 adev->mode_info.audio.num_pins = 7;
1476 break;
1477 case CHIP_POLARIS10:
1478 case CHIP_VEGAM:
1479 adev->mode_info.audio.num_pins = 8;
1480 break;
1481 case CHIP_POLARIS11:
1482 case CHIP_POLARIS12:
1483 adev->mode_info.audio.num_pins = 6;
1484 break;
1485 default:
1486 return -EINVAL;
1487 }
1488
1489 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
1490 adev->mode_info.audio.pin[i].channels = -1;
1491 adev->mode_info.audio.pin[i].rate = -1;
1492 adev->mode_info.audio.pin[i].bits_per_sample = -1;
1493 adev->mode_info.audio.pin[i].status_bits = 0;
1494 adev->mode_info.audio.pin[i].category_code = 0;
1495 adev->mode_info.audio.pin[i].connected = false;
1496 adev->mode_info.audio.pin[i].offset = pin_offsets[i];
1497 adev->mode_info.audio.pin[i].id = i;
1498 /* disable audio. it will be set up later */
1499 /* XXX remove once we switch to ip funcs */
1500 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1501 }
1502
1503 return 0;
1504}
1505
1506static void dce_v11_0_audio_fini(struct amdgpu_device *adev)
1507{
1508 int i;
1509
1510 if (!amdgpu_audio)
1511 return;
1512
1513 if (!adev->mode_info.audio.enabled)
1514 return;
1515
1516 for (i = 0; i < adev->mode_info.audio.num_pins; i++)
1517 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
1518
1519 adev->mode_info.audio.enabled = false;
1520}
1521
1522/*
1523 * update the N and CTS parameters for a given pixel clock rate
1524 */
1525static void dce_v11_0_afmt_update_ACR(struct drm_encoder *encoder, uint32_t clock)
1526{
1527 struct drm_device *dev = encoder->dev;
1528 struct amdgpu_device *adev = dev->dev_private;
1529 struct amdgpu_afmt_acr acr = amdgpu_afmt_acr(clock);
1530 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1531 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1532 u32 tmp;
1533
1534 tmp = RREG32(mmHDMI_ACR_32_0 + dig->afmt->offset);
1535 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_0, HDMI_ACR_CTS_32, acr.cts_32khz);
1536 WREG32(mmHDMI_ACR_32_0 + dig->afmt->offset, tmp);
1537 tmp = RREG32(mmHDMI_ACR_32_1 + dig->afmt->offset);
1538 tmp = REG_SET_FIELD(tmp, HDMI_ACR_32_1, HDMI_ACR_N_32, acr.n_32khz);
1539 WREG32(mmHDMI_ACR_32_1 + dig->afmt->offset, tmp);
1540
1541 tmp = RREG32(mmHDMI_ACR_44_0 + dig->afmt->offset);
1542 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_0, HDMI_ACR_CTS_44, acr.cts_44_1khz);
1543 WREG32(mmHDMI_ACR_44_0 + dig->afmt->offset, tmp);
1544 tmp = RREG32(mmHDMI_ACR_44_1 + dig->afmt->offset);
1545 tmp = REG_SET_FIELD(tmp, HDMI_ACR_44_1, HDMI_ACR_N_44, acr.n_44_1khz);
1546 WREG32(mmHDMI_ACR_44_1 + dig->afmt->offset, tmp);
1547
1548 tmp = RREG32(mmHDMI_ACR_48_0 + dig->afmt->offset);
1549 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_0, HDMI_ACR_CTS_48, acr.cts_48khz);
1550 WREG32(mmHDMI_ACR_48_0 + dig->afmt->offset, tmp);
1551 tmp = RREG32(mmHDMI_ACR_48_1 + dig->afmt->offset);
1552 tmp = REG_SET_FIELD(tmp, HDMI_ACR_48_1, HDMI_ACR_N_48, acr.n_48khz);
1553 WREG32(mmHDMI_ACR_48_1 + dig->afmt->offset, tmp);
1554
1555}
1556
1557/*
1558 * build a HDMI Video Info Frame
1559 */
1560static void dce_v11_0_afmt_update_avi_infoframe(struct drm_encoder *encoder,
1561 void *buffer, size_t size)
1562{
1563 struct drm_device *dev = encoder->dev;
1564 struct amdgpu_device *adev = dev->dev_private;
1565 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1566 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1567 uint8_t *frame = buffer + 3;
1568 uint8_t *header = buffer;
1569
1570 WREG32(mmAFMT_AVI_INFO0 + dig->afmt->offset,
1571 frame[0x0] | (frame[0x1] << 8) | (frame[0x2] << 16) | (frame[0x3] << 24));
1572 WREG32(mmAFMT_AVI_INFO1 + dig->afmt->offset,
1573 frame[0x4] | (frame[0x5] << 8) | (frame[0x6] << 16) | (frame[0x7] << 24));
1574 WREG32(mmAFMT_AVI_INFO2 + dig->afmt->offset,
1575 frame[0x8] | (frame[0x9] << 8) | (frame[0xA] << 16) | (frame[0xB] << 24));
1576 WREG32(mmAFMT_AVI_INFO3 + dig->afmt->offset,
1577 frame[0xC] | (frame[0xD] << 8) | (header[1] << 24));
1578}
1579
1580static void dce_v11_0_audio_set_dto(struct drm_encoder *encoder, u32 clock)
1581{
1582 struct drm_device *dev = encoder->dev;
1583 struct amdgpu_device *adev = dev->dev_private;
1584 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1585 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1586 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1587 u32 dto_phase = 24 * 1000;
1588 u32 dto_modulo = clock;
1589 u32 tmp;
1590
1591 if (!dig || !dig->afmt)
1592 return;
1593
1594 /* XXX two dtos; generally use dto0 for hdmi */
1595 /* Express [24MHz / target pixel clock] as an exact rational
1596 * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE
1597 * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator
1598 */
1599 tmp = RREG32(mmDCCG_AUDIO_DTO_SOURCE);
1600 tmp = REG_SET_FIELD(tmp, DCCG_AUDIO_DTO_SOURCE, DCCG_AUDIO_DTO0_SOURCE_SEL,
1601 amdgpu_crtc->crtc_id);
1602 WREG32(mmDCCG_AUDIO_DTO_SOURCE, tmp);
1603 WREG32(mmDCCG_AUDIO_DTO0_PHASE, dto_phase);
1604 WREG32(mmDCCG_AUDIO_DTO0_MODULE, dto_modulo);
1605}
1606
1607/*
1608 * update the info frames with the data from the current display mode
1609 */
1610static void dce_v11_0_afmt_setmode(struct drm_encoder *encoder,
1611 struct drm_display_mode *mode)
1612{
1613 struct drm_device *dev = encoder->dev;
1614 struct amdgpu_device *adev = dev->dev_private;
1615 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1616 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1617 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
1618 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
1619 struct hdmi_avi_infoframe frame;
1620 ssize_t err;
1621 u32 tmp;
1622 int bpc = 8;
1623
1624 if (!dig || !dig->afmt)
1625 return;
1626
1627 /* Silent, r600_hdmi_enable will raise WARN for us */
1628 if (!dig->afmt->enabled)
1629 return;
1630
1631 /* hdmi deep color mode general control packets setup, if bpc > 8 */
1632 if (encoder->crtc) {
1633 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(encoder->crtc);
1634 bpc = amdgpu_crtc->bpc;
1635 }
1636
1637 /* disable audio prior to setting up hw */
1638 dig->afmt->pin = dce_v11_0_audio_get_pin(adev);
1639 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1640
1641 dce_v11_0_audio_set_dto(encoder, mode->clock);
1642
1643 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1644 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1);
1645 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp); /* send null packets when required */
1646
1647 WREG32(mmAFMT_AUDIO_CRC_CONTROL + dig->afmt->offset, 0x1000);
1648
1649 tmp = RREG32(mmHDMI_CONTROL + dig->afmt->offset);
1650 switch (bpc) {
1651 case 0:
1652 case 6:
1653 case 8:
1654 case 16:
1655 default:
1656 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 0);
1657 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 0);
1658 DRM_DEBUG("%s: Disabling hdmi deep color for %d bpc.\n",
1659 connector->name, bpc);
1660 break;
1661 case 10:
1662 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1663 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 1);
1664 DRM_DEBUG("%s: Enabling hdmi deep color 30 for 10 bpc.\n",
1665 connector->name);
1666 break;
1667 case 12:
1668 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_ENABLE, 1);
1669 tmp = REG_SET_FIELD(tmp, HDMI_CONTROL, HDMI_DEEP_COLOR_DEPTH, 2);
1670 DRM_DEBUG("%s: Enabling hdmi deep color 36 for 12 bpc.\n",
1671 connector->name);
1672 break;
1673 }
1674 WREG32(mmHDMI_CONTROL + dig->afmt->offset, tmp);
1675
1676 tmp = RREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset);
1677 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_NULL_SEND, 1); /* send null packets when required */
1678 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_SEND, 1); /* send general control packets */
1679 tmp = REG_SET_FIELD(tmp, HDMI_VBI_PACKET_CONTROL, HDMI_GC_CONT, 1); /* send general control packets every frame */
1680 WREG32(mmHDMI_VBI_PACKET_CONTROL + dig->afmt->offset, tmp);
1681
1682 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1683 /* enable audio info frames (frames won't be set until audio is enabled) */
1684 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_SEND, 1);
1685 /* required for audio info values to be updated */
1686 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AUDIO_INFO_CONT, 1);
1687 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1688
1689 tmp = RREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset);
1690 /* required for audio info values to be updated */
1691 tmp = REG_SET_FIELD(tmp, AFMT_INFOFRAME_CONTROL0, AFMT_AUDIO_INFO_UPDATE, 1);
1692 WREG32(mmAFMT_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1693
1694 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1695 /* anything other than 0 */
1696 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AUDIO_INFO_LINE, 2);
1697 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1698
1699 WREG32(mmHDMI_GC + dig->afmt->offset, 0); /* unset HDMI_GC_AVMUTE */
1700
1701 tmp = RREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1702 /* set the default audio delay */
1703 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_DELAY_EN, 1);
1704 /* should be suffient for all audio modes and small enough for all hblanks */
1705 tmp = REG_SET_FIELD(tmp, HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, 3);
1706 WREG32(mmHDMI_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1707
1708 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1709 /* allow 60958 channel status fields to be updated */
1710 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
1711 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1712
1713 tmp = RREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset);
1714 if (bpc > 8)
1715 /* clear SW CTS value */
1716 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 0);
1717 else
1718 /* select SW CTS value */
1719 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_SOURCE, 1);
1720 /* allow hw to sent ACR packets when required */
1721 tmp = REG_SET_FIELD(tmp, HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1);
1722 WREG32(mmHDMI_ACR_PACKET_CONTROL + dig->afmt->offset, tmp);
1723
1724 dce_v11_0_afmt_update_ACR(encoder, mode->clock);
1725
1726 tmp = RREG32(mmAFMT_60958_0 + dig->afmt->offset);
1727 tmp = REG_SET_FIELD(tmp, AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1);
1728 WREG32(mmAFMT_60958_0 + dig->afmt->offset, tmp);
1729
1730 tmp = RREG32(mmAFMT_60958_1 + dig->afmt->offset);
1731 tmp = REG_SET_FIELD(tmp, AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
1732 WREG32(mmAFMT_60958_1 + dig->afmt->offset, tmp);
1733
1734 tmp = RREG32(mmAFMT_60958_2 + dig->afmt->offset);
1735 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3);
1736 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_3, 4);
1737 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_4, 5);
1738 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_5, 6);
1739 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_6, 7);
1740 tmp = REG_SET_FIELD(tmp, AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
1741 WREG32(mmAFMT_60958_2 + dig->afmt->offset, tmp);
1742
1743 dce_v11_0_audio_write_speaker_allocation(encoder);
1744
1745 WREG32(mmAFMT_AUDIO_PACKET_CONTROL2 + dig->afmt->offset,
1746 (0xff << AFMT_AUDIO_PACKET_CONTROL2__AFMT_AUDIO_CHANNEL_ENABLE__SHIFT));
1747
1748 dce_v11_0_afmt_audio_select_pin(encoder);
1749 dce_v11_0_audio_write_sad_regs(encoder);
1750 dce_v11_0_audio_write_latency_fields(encoder, mode);
1751
1752 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode);
1753 if (err < 0) {
1754 DRM_ERROR("failed to setup AVI infoframe: %zd\n", err);
1755 return;
1756 }
1757
1758 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
1759 if (err < 0) {
1760 DRM_ERROR("failed to pack AVI infoframe: %zd\n", err);
1761 return;
1762 }
1763
1764 dce_v11_0_afmt_update_avi_infoframe(encoder, buffer, sizeof(buffer));
1765
1766 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset);
1767 /* enable AVI info frames */
1768 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_SEND, 1);
1769 /* required for audio info values to be updated */
1770 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL0, HDMI_AVI_INFO_CONT, 1);
1771 WREG32(mmHDMI_INFOFRAME_CONTROL0 + dig->afmt->offset, tmp);
1772
1773 tmp = RREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset);
1774 tmp = REG_SET_FIELD(tmp, HDMI_INFOFRAME_CONTROL1, HDMI_AVI_INFO_LINE, 2);
1775 WREG32(mmHDMI_INFOFRAME_CONTROL1 + dig->afmt->offset, tmp);
1776
1777 tmp = RREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset);
1778 /* send audio packets */
1779 tmp = REG_SET_FIELD(tmp, AFMT_AUDIO_PACKET_CONTROL, AFMT_AUDIO_SAMPLE_SEND, 1);
1780 WREG32(mmAFMT_AUDIO_PACKET_CONTROL + dig->afmt->offset, tmp);
1781
1782 WREG32(mmAFMT_RAMP_CONTROL0 + dig->afmt->offset, 0x00FFFFFF);
1783 WREG32(mmAFMT_RAMP_CONTROL1 + dig->afmt->offset, 0x007FFFFF);
1784 WREG32(mmAFMT_RAMP_CONTROL2 + dig->afmt->offset, 0x00000001);
1785 WREG32(mmAFMT_RAMP_CONTROL3 + dig->afmt->offset, 0x00000001);
1786
1787 /* enable audio after to setting up hw */
1788 dce_v11_0_audio_enable(adev, dig->afmt->pin, true);
1789}
1790
1791static void dce_v11_0_afmt_enable(struct drm_encoder *encoder, bool enable)
1792{
1793 struct drm_device *dev = encoder->dev;
1794 struct amdgpu_device *adev = dev->dev_private;
1795 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
1796 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
1797
1798 if (!dig || !dig->afmt)
1799 return;
1800
1801 /* Silent, r600_hdmi_enable will raise WARN for us */
1802 if (enable && dig->afmt->enabled)
1803 return;
1804 if (!enable && !dig->afmt->enabled)
1805 return;
1806
1807 if (!enable && dig->afmt->pin) {
1808 dce_v11_0_audio_enable(adev, dig->afmt->pin, false);
1809 dig->afmt->pin = NULL;
1810 }
1811
1812 dig->afmt->enabled = enable;
1813
1814 DRM_DEBUG("%sabling AFMT interface @ 0x%04X for encoder 0x%x\n",
1815 enable ? "En" : "Dis", dig->afmt->offset, amdgpu_encoder->encoder_id);
1816}
1817
1818static int dce_v11_0_afmt_init(struct amdgpu_device *adev)
1819{
1820 int i;
1821
1822 for (i = 0; i < adev->mode_info.num_dig; i++)
1823 adev->mode_info.afmt[i] = NULL;
1824
1825 /* DCE11 has audio blocks tied to DIG encoders */
1826 for (i = 0; i < adev->mode_info.num_dig; i++) {
1827 adev->mode_info.afmt[i] = kzalloc(sizeof(struct amdgpu_afmt), GFP_KERNEL);
1828 if (adev->mode_info.afmt[i]) {
1829 adev->mode_info.afmt[i]->offset = dig_offsets[i];
1830 adev->mode_info.afmt[i]->id = i;
1831 } else {
1832 int j;
1833 for (j = 0; j < i; j++) {
1834 kfree(adev->mode_info.afmt[j]);
1835 adev->mode_info.afmt[j] = NULL;
1836 }
1837 return -ENOMEM;
1838 }
1839 }
1840 return 0;
1841}
1842
1843static void dce_v11_0_afmt_fini(struct amdgpu_device *adev)
1844{
1845 int i;
1846
1847 for (i = 0; i < adev->mode_info.num_dig; i++) {
1848 kfree(adev->mode_info.afmt[i]);
1849 adev->mode_info.afmt[i] = NULL;
1850 }
1851}
1852
1853static const u32 vga_control_regs[6] =
1854{
1855 mmD1VGA_CONTROL,
1856 mmD2VGA_CONTROL,
1857 mmD3VGA_CONTROL,
1858 mmD4VGA_CONTROL,
1859 mmD5VGA_CONTROL,
1860 mmD6VGA_CONTROL,
1861};
1862
1863static void dce_v11_0_vga_enable(struct drm_crtc *crtc, bool enable)
1864{
1865 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1866 struct drm_device *dev = crtc->dev;
1867 struct amdgpu_device *adev = dev->dev_private;
1868 u32 vga_control;
1869
1870 vga_control = RREG32(vga_control_regs[amdgpu_crtc->crtc_id]) & ~1;
1871 if (enable)
1872 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control | 1);
1873 else
1874 WREG32(vga_control_regs[amdgpu_crtc->crtc_id], vga_control);
1875}
1876
1877static void dce_v11_0_grph_enable(struct drm_crtc *crtc, bool enable)
1878{
1879 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1880 struct drm_device *dev = crtc->dev;
1881 struct amdgpu_device *adev = dev->dev_private;
1882
1883 if (enable)
1884 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 1);
1885 else
1886 WREG32(mmGRPH_ENABLE + amdgpu_crtc->crtc_offset, 0);
1887}
1888
1889static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
1890 struct drm_framebuffer *fb,
1891 int x, int y, int atomic)
1892{
1893 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
1894 struct drm_device *dev = crtc->dev;
1895 struct amdgpu_device *adev = dev->dev_private;
1896 struct drm_framebuffer *target_fb;
1897 struct drm_gem_object *obj;
1898 struct amdgpu_bo *abo;
1899 uint64_t fb_location, tiling_flags;
1900 uint32_t fb_format, fb_pitch_pixels;
1901 u32 fb_swap = REG_SET_FIELD(0, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, ENDIAN_NONE);
1902 u32 pipe_config;
1903 u32 tmp, viewport_w, viewport_h;
1904 int r;
1905 bool bypass_lut = false;
1906 struct drm_format_name_buf format_name;
1907
1908 /* no fb bound */
1909 if (!atomic && !crtc->primary->fb) {
1910 DRM_DEBUG_KMS("No FB bound\n");
1911 return 0;
1912 }
1913
1914 if (atomic)
1915 target_fb = fb;
1916 else
1917 target_fb = crtc->primary->fb;
1918
1919 /* If atomic, assume fb object is pinned & idle & fenced and
1920 * just update base pointers
1921 */
1922 obj = target_fb->obj[0];
1923 abo = gem_to_amdgpu_bo(obj);
1924 r = amdgpu_bo_reserve(abo, false);
1925 if (unlikely(r != 0))
1926 return r;
1927
1928 if (!atomic) {
1929 r = amdgpu_bo_pin(abo, AMDGPU_GEM_DOMAIN_VRAM);
1930 if (unlikely(r != 0)) {
1931 amdgpu_bo_unreserve(abo);
1932 return -EINVAL;
1933 }
1934 }
1935 fb_location = amdgpu_bo_gpu_offset(abo);
1936
1937 amdgpu_bo_get_tiling_flags(abo, &tiling_flags);
1938 amdgpu_bo_unreserve(abo);
1939
1940 pipe_config = AMDGPU_TILING_GET(tiling_flags, PIPE_CONFIG);
1941
1942 switch (target_fb->format->format) {
1943 case DRM_FORMAT_C8:
1944 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 0);
1945 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1946 break;
1947 case DRM_FORMAT_XRGB4444:
1948 case DRM_FORMAT_ARGB4444:
1949 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1950 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 2);
1951#ifdef __BIG_ENDIAN
1952 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1953 ENDIAN_8IN16);
1954#endif
1955 break;
1956 case DRM_FORMAT_XRGB1555:
1957 case DRM_FORMAT_ARGB1555:
1958 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1959 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1960#ifdef __BIG_ENDIAN
1961 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1962 ENDIAN_8IN16);
1963#endif
1964 break;
1965 case DRM_FORMAT_BGRX5551:
1966 case DRM_FORMAT_BGRA5551:
1967 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1968 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 5);
1969#ifdef __BIG_ENDIAN
1970 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1971 ENDIAN_8IN16);
1972#endif
1973 break;
1974 case DRM_FORMAT_RGB565:
1975 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 1);
1976 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1977#ifdef __BIG_ENDIAN
1978 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1979 ENDIAN_8IN16);
1980#endif
1981 break;
1982 case DRM_FORMAT_XRGB8888:
1983 case DRM_FORMAT_ARGB8888:
1984 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1985 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
1986#ifdef __BIG_ENDIAN
1987 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1988 ENDIAN_8IN32);
1989#endif
1990 break;
1991 case DRM_FORMAT_XRGB2101010:
1992 case DRM_FORMAT_ARGB2101010:
1993 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
1994 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 1);
1995#ifdef __BIG_ENDIAN
1996 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
1997 ENDIAN_8IN32);
1998#endif
1999 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2000 bypass_lut = true;
2001 break;
2002 case DRM_FORMAT_BGRX1010102:
2003 case DRM_FORMAT_BGRA1010102:
2004 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2005 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 4);
2006#ifdef __BIG_ENDIAN
2007 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2008 ENDIAN_8IN32);
2009#endif
2010 /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
2011 bypass_lut = true;
2012 break;
2013 case DRM_FORMAT_XBGR8888:
2014 case DRM_FORMAT_ABGR8888:
2015 fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
2016 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
2017 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_RED_CROSSBAR, 2);
2018 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_BLUE_CROSSBAR, 2);
2019#ifdef __BIG_ENDIAN
2020 fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
2021 ENDIAN_8IN32);
2022#endif
2023 break;
2024 default:
2025 DRM_ERROR("Unsupported screen format %s\n",
2026 drm_get_format_name(target_fb->format->format, &format_name));
2027 return -EINVAL;
2028 }
2029
2030 if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_2D_TILED_THIN1) {
2031 unsigned bankw, bankh, mtaspect, tile_split, num_banks;
2032
2033 bankw = AMDGPU_TILING_GET(tiling_flags, BANK_WIDTH);
2034 bankh = AMDGPU_TILING_GET(tiling_flags, BANK_HEIGHT);
2035 mtaspect = AMDGPU_TILING_GET(tiling_flags, MACRO_TILE_ASPECT);
2036 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT);
2037 num_banks = AMDGPU_TILING_GET(tiling_flags, NUM_BANKS);
2038
2039 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_NUM_BANKS, num_banks);
2040 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2041 ARRAY_2D_TILED_THIN1);
2042 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_TILE_SPLIT,
2043 tile_split);
2044 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_WIDTH, bankw);
2045 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_BANK_HEIGHT, bankh);
2046 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MACRO_TILE_ASPECT,
2047 mtaspect);
2048 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_MICRO_TILE_MODE,
2049 ADDR_SURF_MICRO_TILING_DISPLAY);
2050 } else if (AMDGPU_TILING_GET(tiling_flags, ARRAY_MODE) == ARRAY_1D_TILED_THIN1) {
2051 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_ARRAY_MODE,
2052 ARRAY_1D_TILED_THIN1);
2053 }
2054
2055 fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_PIPE_CONFIG,
2056 pipe_config);
2057
2058 dce_v11_0_vga_enable(crtc, false);
2059
2060 /* Make sure surface address is updated at vertical blank rather than
2061 * horizontal blank
2062 */
2063 tmp = RREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset);
2064 tmp = REG_SET_FIELD(tmp, GRPH_FLIP_CONTROL,
2065 GRPH_SURFACE_UPDATE_H_RETRACE_EN, 0);
2066 WREG32(mmGRPH_FLIP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2067
2068 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2069 upper_32_bits(fb_location));
2070 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2071 upper_32_bits(fb_location));
2072 WREG32(mmGRPH_PRIMARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2073 (u32)fb_location & GRPH_PRIMARY_SURFACE_ADDRESS__GRPH_PRIMARY_SURFACE_ADDRESS_MASK);
2074 WREG32(mmGRPH_SECONDARY_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2075 (u32) fb_location & GRPH_SECONDARY_SURFACE_ADDRESS__GRPH_SECONDARY_SURFACE_ADDRESS_MASK);
2076 WREG32(mmGRPH_CONTROL + amdgpu_crtc->crtc_offset, fb_format);
2077 WREG32(mmGRPH_SWAP_CNTL + amdgpu_crtc->crtc_offset, fb_swap);
2078
2079 /*
2080 * The LUT only has 256 slots for indexing by a 8 bpc fb. Bypass the LUT
2081 * for > 8 bpc scanout to avoid truncation of fb indices to 8 msb's, to
2082 * retain the full precision throughout the pipeline.
2083 */
2084 tmp = RREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset);
2085 if (bypass_lut)
2086 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 1);
2087 else
2088 tmp = REG_SET_FIELD(tmp, GRPH_LUT_10BIT_BYPASS, GRPH_LUT_10BIT_BYPASS_EN, 0);
2089 WREG32(mmGRPH_LUT_10BIT_BYPASS + amdgpu_crtc->crtc_offset, tmp);
2090
2091 if (bypass_lut)
2092 DRM_DEBUG_KMS("Bypassing hardware LUT due to 10 bit fb scanout.\n");
2093
2094 WREG32(mmGRPH_SURFACE_OFFSET_X + amdgpu_crtc->crtc_offset, 0);
2095 WREG32(mmGRPH_SURFACE_OFFSET_Y + amdgpu_crtc->crtc_offset, 0);
2096 WREG32(mmGRPH_X_START + amdgpu_crtc->crtc_offset, 0);
2097 WREG32(mmGRPH_Y_START + amdgpu_crtc->crtc_offset, 0);
2098 WREG32(mmGRPH_X_END + amdgpu_crtc->crtc_offset, target_fb->width);
2099 WREG32(mmGRPH_Y_END + amdgpu_crtc->crtc_offset, target_fb->height);
2100
2101 fb_pitch_pixels = target_fb->pitches[0] / target_fb->format->cpp[0];
2102 WREG32(mmGRPH_PITCH + amdgpu_crtc->crtc_offset, fb_pitch_pixels);
2103
2104 dce_v11_0_grph_enable(crtc, true);
2105
2106 WREG32(mmLB_DESKTOP_HEIGHT + amdgpu_crtc->crtc_offset,
2107 target_fb->height);
2108
2109 x &= ~3;
2110 y &= ~1;
2111 WREG32(mmVIEWPORT_START + amdgpu_crtc->crtc_offset,
2112 (x << 16) | y);
2113 viewport_w = crtc->mode.hdisplay;
2114 viewport_h = (crtc->mode.vdisplay + 1) & ~1;
2115 WREG32(mmVIEWPORT_SIZE + amdgpu_crtc->crtc_offset,
2116 (viewport_w << 16) | viewport_h);
2117
2118 /* set pageflip to happen anywhere in vblank interval */
2119 WREG32(mmCRTC_MASTER_UPDATE_MODE + amdgpu_crtc->crtc_offset, 0);
2120
2121 if (!atomic && fb && fb != crtc->primary->fb) {
2122 abo = gem_to_amdgpu_bo(fb->obj[0]);
2123 r = amdgpu_bo_reserve(abo, true);
2124 if (unlikely(r != 0))
2125 return r;
2126 amdgpu_bo_unpin(abo);
2127 amdgpu_bo_unreserve(abo);
2128 }
2129
2130 /* Bytes per pixel may have changed */
2131 dce_v11_0_bandwidth_update(adev);
2132
2133 return 0;
2134}
2135
2136static void dce_v11_0_set_interleave(struct drm_crtc *crtc,
2137 struct drm_display_mode *mode)
2138{
2139 struct drm_device *dev = crtc->dev;
2140 struct amdgpu_device *adev = dev->dev_private;
2141 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2142 u32 tmp;
2143
2144 tmp = RREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset);
2145 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2146 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 1);
2147 else
2148 tmp = REG_SET_FIELD(tmp, LB_DATA_FORMAT, INTERLEAVE_EN, 0);
2149 WREG32(mmLB_DATA_FORMAT + amdgpu_crtc->crtc_offset, tmp);
2150}
2151
2152static void dce_v11_0_crtc_load_lut(struct drm_crtc *crtc)
2153{
2154 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2155 struct drm_device *dev = crtc->dev;
2156 struct amdgpu_device *adev = dev->dev_private;
2157 u16 *r, *g, *b;
2158 int i;
2159 u32 tmp;
2160
2161 DRM_DEBUG_KMS("%d\n", amdgpu_crtc->crtc_id);
2162
2163 tmp = RREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2164 tmp = REG_SET_FIELD(tmp, INPUT_CSC_CONTROL, INPUT_CSC_GRPH_MODE, 0);
2165 WREG32(mmINPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2166
2167 tmp = RREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset);
2168 tmp = REG_SET_FIELD(tmp, PRESCALE_GRPH_CONTROL, GRPH_PRESCALE_BYPASS, 1);
2169 WREG32(mmPRESCALE_GRPH_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2170
2171 tmp = RREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2172 tmp = REG_SET_FIELD(tmp, INPUT_GAMMA_CONTROL, GRPH_INPUT_GAMMA_MODE, 0);
2173 WREG32(mmINPUT_GAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2174
2175 WREG32(mmDC_LUT_CONTROL + amdgpu_crtc->crtc_offset, 0);
2176
2177 WREG32(mmDC_LUT_BLACK_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0);
2178 WREG32(mmDC_LUT_BLACK_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0);
2179 WREG32(mmDC_LUT_BLACK_OFFSET_RED + amdgpu_crtc->crtc_offset, 0);
2180
2181 WREG32(mmDC_LUT_WHITE_OFFSET_BLUE + amdgpu_crtc->crtc_offset, 0xffff);
2182 WREG32(mmDC_LUT_WHITE_OFFSET_GREEN + amdgpu_crtc->crtc_offset, 0xffff);
2183 WREG32(mmDC_LUT_WHITE_OFFSET_RED + amdgpu_crtc->crtc_offset, 0xffff);
2184
2185 WREG32(mmDC_LUT_RW_MODE + amdgpu_crtc->crtc_offset, 0);
2186 WREG32(mmDC_LUT_WRITE_EN_MASK + amdgpu_crtc->crtc_offset, 0x00000007);
2187
2188 WREG32(mmDC_LUT_RW_INDEX + amdgpu_crtc->crtc_offset, 0);
2189 r = crtc->gamma_store;
2190 g = r + crtc->gamma_size;
2191 b = g + crtc->gamma_size;
2192 for (i = 0; i < 256; i++) {
2193 WREG32(mmDC_LUT_30_COLOR + amdgpu_crtc->crtc_offset,
2194 ((*r++ & 0xffc0) << 14) |
2195 ((*g++ & 0xffc0) << 4) |
2196 (*b++ >> 6));
2197 }
2198
2199 tmp = RREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2200 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, GRPH_DEGAMMA_MODE, 0);
2201 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR_DEGAMMA_MODE, 0);
2202 tmp = REG_SET_FIELD(tmp, DEGAMMA_CONTROL, CURSOR2_DEGAMMA_MODE, 0);
2203 WREG32(mmDEGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2204
2205 tmp = RREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset);
2206 tmp = REG_SET_FIELD(tmp, GAMUT_REMAP_CONTROL, GRPH_GAMUT_REMAP_MODE, 0);
2207 WREG32(mmGAMUT_REMAP_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2208
2209 tmp = RREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset);
2210 tmp = REG_SET_FIELD(tmp, REGAMMA_CONTROL, GRPH_REGAMMA_MODE, 0);
2211 WREG32(mmREGAMMA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2212
2213 tmp = RREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset);
2214 tmp = REG_SET_FIELD(tmp, OUTPUT_CSC_CONTROL, OUTPUT_CSC_GRPH_MODE, 0);
2215 WREG32(mmOUTPUT_CSC_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2216
2217 /* XXX match this to the depth of the crtc fmt block, move to modeset? */
2218 WREG32(mmDENORM_CONTROL + amdgpu_crtc->crtc_offset, 0);
2219 /* XXX this only needs to be programmed once per crtc at startup,
2220 * not sure where the best place for it is
2221 */
2222 tmp = RREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset);
2223 tmp = REG_SET_FIELD(tmp, ALPHA_CONTROL, CURSOR_ALPHA_BLND_ENA, 1);
2224 WREG32(mmALPHA_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2225}
2226
2227static int dce_v11_0_pick_dig_encoder(struct drm_encoder *encoder)
2228{
2229 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
2230 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2231
2232 switch (amdgpu_encoder->encoder_id) {
2233 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2234 if (dig->linkb)
2235 return 1;
2236 else
2237 return 0;
2238 break;
2239 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2240 if (dig->linkb)
2241 return 3;
2242 else
2243 return 2;
2244 break;
2245 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2246 if (dig->linkb)
2247 return 5;
2248 else
2249 return 4;
2250 break;
2251 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2252 return 6;
2253 break;
2254 default:
2255 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2256 return 0;
2257 }
2258}
2259
2260/**
2261 * dce_v11_0_pick_pll - Allocate a PPLL for use by the crtc.
2262 *
2263 * @crtc: drm crtc
2264 *
2265 * Returns the PPLL (Pixel PLL) to be used by the crtc. For DP monitors
2266 * a single PPLL can be used for all DP crtcs/encoders. For non-DP
2267 * monitors a dedicated PPLL must be used. If a particular board has
2268 * an external DP PLL, return ATOM_PPLL_INVALID to skip PLL programming
2269 * as there is no need to program the PLL itself. If we are not able to
2270 * allocate a PLL, return ATOM_PPLL_INVALID to skip PLL programming to
2271 * avoid messing up an existing monitor.
2272 *
2273 * Asic specific PLL information
2274 *
2275 * DCE 10.x
2276 * Tonga
2277 * - PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP)
2278 * CI
2279 * - PPLL0, PPLL1, PPLL2 are available for all UNIPHY (both DP and non-DP) and DAC
2280 *
2281 */
2282static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc)
2283{
2284 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2285 struct drm_device *dev = crtc->dev;
2286 struct amdgpu_device *adev = dev->dev_private;
2287 u32 pll_in_use;
2288 int pll;
2289
2290 if ((adev->asic_type == CHIP_POLARIS10) ||
2291 (adev->asic_type == CHIP_POLARIS11) ||
2292 (adev->asic_type == CHIP_POLARIS12) ||
2293 (adev->asic_type == CHIP_VEGAM)) {
2294 struct amdgpu_encoder *amdgpu_encoder =
2295 to_amdgpu_encoder(amdgpu_crtc->encoder);
2296 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
2297
2298 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2299 return ATOM_DP_DTO;
2300
2301 switch (amdgpu_encoder->encoder_id) {
2302 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2303 if (dig->linkb)
2304 return ATOM_COMBOPHY_PLL1;
2305 else
2306 return ATOM_COMBOPHY_PLL0;
2307 break;
2308 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2309 if (dig->linkb)
2310 return ATOM_COMBOPHY_PLL3;
2311 else
2312 return ATOM_COMBOPHY_PLL2;
2313 break;
2314 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2315 if (dig->linkb)
2316 return ATOM_COMBOPHY_PLL5;
2317 else
2318 return ATOM_COMBOPHY_PLL4;
2319 break;
2320 default:
2321 DRM_ERROR("invalid encoder_id: 0x%x\n", amdgpu_encoder->encoder_id);
2322 return ATOM_PPLL_INVALID;
2323 }
2324 }
2325
2326 if (ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder))) {
2327 if (adev->clock.dp_extclk)
2328 /* skip PPLL programming if using ext clock */
2329 return ATOM_PPLL_INVALID;
2330 else {
2331 /* use the same PPLL for all DP monitors */
2332 pll = amdgpu_pll_get_shared_dp_ppll(crtc);
2333 if (pll != ATOM_PPLL_INVALID)
2334 return pll;
2335 }
2336 } else {
2337 /* use the same PPLL for all monitors with the same clock */
2338 pll = amdgpu_pll_get_shared_nondp_ppll(crtc);
2339 if (pll != ATOM_PPLL_INVALID)
2340 return pll;
2341 }
2342
2343 /* XXX need to determine what plls are available on each DCE11 part */
2344 pll_in_use = amdgpu_pll_get_use_mask(crtc);
2345 if (adev->flags & AMD_IS_APU) {
2346 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2347 return ATOM_PPLL1;
2348 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2349 return ATOM_PPLL0;
2350 DRM_ERROR("unable to allocate a PPLL\n");
2351 return ATOM_PPLL_INVALID;
2352 } else {
2353 if (!(pll_in_use & (1 << ATOM_PPLL2)))
2354 return ATOM_PPLL2;
2355 if (!(pll_in_use & (1 << ATOM_PPLL1)))
2356 return ATOM_PPLL1;
2357 if (!(pll_in_use & (1 << ATOM_PPLL0)))
2358 return ATOM_PPLL0;
2359 DRM_ERROR("unable to allocate a PPLL\n");
2360 return ATOM_PPLL_INVALID;
2361 }
2362 return ATOM_PPLL_INVALID;
2363}
2364
2365static void dce_v11_0_lock_cursor(struct drm_crtc *crtc, bool lock)
2366{
2367 struct amdgpu_device *adev = crtc->dev->dev_private;
2368 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2369 uint32_t cur_lock;
2370
2371 cur_lock = RREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset);
2372 if (lock)
2373 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 1);
2374 else
2375 cur_lock = REG_SET_FIELD(cur_lock, CUR_UPDATE, CURSOR_UPDATE_LOCK, 0);
2376 WREG32(mmCUR_UPDATE + amdgpu_crtc->crtc_offset, cur_lock);
2377}
2378
2379static void dce_v11_0_hide_cursor(struct drm_crtc *crtc)
2380{
2381 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2382 struct amdgpu_device *adev = crtc->dev->dev_private;
2383 u32 tmp;
2384
2385 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2386 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 0);
2387 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2388}
2389
2390static void dce_v11_0_show_cursor(struct drm_crtc *crtc)
2391{
2392 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2393 struct amdgpu_device *adev = crtc->dev->dev_private;
2394 u32 tmp;
2395
2396 WREG32(mmCUR_SURFACE_ADDRESS_HIGH + amdgpu_crtc->crtc_offset,
2397 upper_32_bits(amdgpu_crtc->cursor_addr));
2398 WREG32(mmCUR_SURFACE_ADDRESS + amdgpu_crtc->crtc_offset,
2399 lower_32_bits(amdgpu_crtc->cursor_addr));
2400
2401 tmp = RREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset);
2402 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_EN, 1);
2403 tmp = REG_SET_FIELD(tmp, CUR_CONTROL, CURSOR_MODE, 2);
2404 WREG32(mmCUR_CONTROL + amdgpu_crtc->crtc_offset, tmp);
2405}
2406
2407static int dce_v11_0_cursor_move_locked(struct drm_crtc *crtc,
2408 int x, int y)
2409{
2410 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2411 struct amdgpu_device *adev = crtc->dev->dev_private;
2412 int xorigin = 0, yorigin = 0;
2413
2414 amdgpu_crtc->cursor_x = x;
2415 amdgpu_crtc->cursor_y = y;
2416
2417 /* avivo cursor are offset into the total surface */
2418 x += crtc->x;
2419 y += crtc->y;
2420 DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
2421
2422 if (x < 0) {
2423 xorigin = min(-x, amdgpu_crtc->max_cursor_width - 1);
2424 x = 0;
2425 }
2426 if (y < 0) {
2427 yorigin = min(-y, amdgpu_crtc->max_cursor_height - 1);
2428 y = 0;
2429 }
2430
2431 WREG32(mmCUR_POSITION + amdgpu_crtc->crtc_offset, (x << 16) | y);
2432 WREG32(mmCUR_HOT_SPOT + amdgpu_crtc->crtc_offset, (xorigin << 16) | yorigin);
2433 WREG32(mmCUR_SIZE + amdgpu_crtc->crtc_offset,
2434 ((amdgpu_crtc->cursor_width - 1) << 16) | (amdgpu_crtc->cursor_height - 1));
2435
2436 return 0;
2437}
2438
2439static int dce_v11_0_crtc_cursor_move(struct drm_crtc *crtc,
2440 int x, int y)
2441{
2442 int ret;
2443
2444 dce_v11_0_lock_cursor(crtc, true);
2445 ret = dce_v11_0_cursor_move_locked(crtc, x, y);
2446 dce_v11_0_lock_cursor(crtc, false);
2447
2448 return ret;
2449}
2450
2451static int dce_v11_0_crtc_cursor_set2(struct drm_crtc *crtc,
2452 struct drm_file *file_priv,
2453 uint32_t handle,
2454 uint32_t width,
2455 uint32_t height,
2456 int32_t hot_x,
2457 int32_t hot_y)
2458{
2459 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2460 struct drm_gem_object *obj;
2461 struct amdgpu_bo *aobj;
2462 int ret;
2463
2464 if (!handle) {
2465 /* turn off cursor */
2466 dce_v11_0_hide_cursor(crtc);
2467 obj = NULL;
2468 goto unpin;
2469 }
2470
2471 if ((width > amdgpu_crtc->max_cursor_width) ||
2472 (height > amdgpu_crtc->max_cursor_height)) {
2473 DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
2474 return -EINVAL;
2475 }
2476
2477 obj = drm_gem_object_lookup(file_priv, handle);
2478 if (!obj) {
2479 DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, amdgpu_crtc->crtc_id);
2480 return -ENOENT;
2481 }
2482
2483 aobj = gem_to_amdgpu_bo(obj);
2484 ret = amdgpu_bo_reserve(aobj, false);
2485 if (ret != 0) {
2486 drm_gem_object_put(obj);
2487 return ret;
2488 }
2489
2490 ret = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
2491 amdgpu_bo_unreserve(aobj);
2492 if (ret) {
2493 DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
2494 drm_gem_object_put(obj);
2495 return ret;
2496 }
2497 amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
2498
2499 dce_v11_0_lock_cursor(crtc, true);
2500
2501 if (width != amdgpu_crtc->cursor_width ||
2502 height != amdgpu_crtc->cursor_height ||
2503 hot_x != amdgpu_crtc->cursor_hot_x ||
2504 hot_y != amdgpu_crtc->cursor_hot_y) {
2505 int x, y;
2506
2507 x = amdgpu_crtc->cursor_x + amdgpu_crtc->cursor_hot_x - hot_x;
2508 y = amdgpu_crtc->cursor_y + amdgpu_crtc->cursor_hot_y - hot_y;
2509
2510 dce_v11_0_cursor_move_locked(crtc, x, y);
2511
2512 amdgpu_crtc->cursor_width = width;
2513 amdgpu_crtc->cursor_height = height;
2514 amdgpu_crtc->cursor_hot_x = hot_x;
2515 amdgpu_crtc->cursor_hot_y = hot_y;
2516 }
2517
2518 dce_v11_0_show_cursor(crtc);
2519 dce_v11_0_lock_cursor(crtc, false);
2520
2521unpin:
2522 if (amdgpu_crtc->cursor_bo) {
2523 struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
2524 ret = amdgpu_bo_reserve(aobj, true);
2525 if (likely(ret == 0)) {
2526 amdgpu_bo_unpin(aobj);
2527 amdgpu_bo_unreserve(aobj);
2528 }
2529 drm_gem_object_put(amdgpu_crtc->cursor_bo);
2530 }
2531
2532 amdgpu_crtc->cursor_bo = obj;
2533 return 0;
2534}
2535
2536static void dce_v11_0_cursor_reset(struct drm_crtc *crtc)
2537{
2538 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2539
2540 if (amdgpu_crtc->cursor_bo) {
2541 dce_v11_0_lock_cursor(crtc, true);
2542
2543 dce_v11_0_cursor_move_locked(crtc, amdgpu_crtc->cursor_x,
2544 amdgpu_crtc->cursor_y);
2545
2546 dce_v11_0_show_cursor(crtc);
2547
2548 dce_v11_0_lock_cursor(crtc, false);
2549 }
2550}
2551
2552static int dce_v11_0_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
2553 u16 *blue, uint32_t size,
2554 struct drm_modeset_acquire_ctx *ctx)
2555{
2556 dce_v11_0_crtc_load_lut(crtc);
2557
2558 return 0;
2559}
2560
2561static void dce_v11_0_crtc_destroy(struct drm_crtc *crtc)
2562{
2563 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2564
2565 drm_crtc_cleanup(crtc);
2566 kfree(amdgpu_crtc);
2567}
2568
2569static const struct drm_crtc_funcs dce_v11_0_crtc_funcs = {
2570 .cursor_set2 = dce_v11_0_crtc_cursor_set2,
2571 .cursor_move = dce_v11_0_crtc_cursor_move,
2572 .gamma_set = dce_v11_0_crtc_gamma_set,
2573 .set_config = amdgpu_display_crtc_set_config,
2574 .destroy = dce_v11_0_crtc_destroy,
2575 .page_flip_target = amdgpu_display_crtc_page_flip_target,
2576 .get_vblank_counter = amdgpu_get_vblank_counter_kms,
2577 .enable_vblank = amdgpu_enable_vblank_kms,
2578 .disable_vblank = amdgpu_disable_vblank_kms,
2579 .get_vblank_timestamp = drm_crtc_vblank_helper_get_vblank_timestamp,
2580};
2581
2582static void dce_v11_0_crtc_dpms(struct drm_crtc *crtc, int mode)
2583{
2584 struct drm_device *dev = crtc->dev;
2585 struct amdgpu_device *adev = dev->dev_private;
2586 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2587 unsigned type;
2588
2589 switch (mode) {
2590 case DRM_MODE_DPMS_ON:
2591 amdgpu_crtc->enabled = true;
2592 amdgpu_atombios_crtc_enable(crtc, ATOM_ENABLE);
2593 dce_v11_0_vga_enable(crtc, true);
2594 amdgpu_atombios_crtc_blank(crtc, ATOM_DISABLE);
2595 dce_v11_0_vga_enable(crtc, false);
2596 /* Make sure VBLANK and PFLIP interrupts are still enabled */
2597 type = amdgpu_display_crtc_idx_to_irq_type(adev,
2598 amdgpu_crtc->crtc_id);
2599 amdgpu_irq_update(adev, &adev->crtc_irq, type);
2600 amdgpu_irq_update(adev, &adev->pageflip_irq, type);
2601 drm_crtc_vblank_on(crtc);
2602 dce_v11_0_crtc_load_lut(crtc);
2603 break;
2604 case DRM_MODE_DPMS_STANDBY:
2605 case DRM_MODE_DPMS_SUSPEND:
2606 case DRM_MODE_DPMS_OFF:
2607 drm_crtc_vblank_off(crtc);
2608 if (amdgpu_crtc->enabled) {
2609 dce_v11_0_vga_enable(crtc, true);
2610 amdgpu_atombios_crtc_blank(crtc, ATOM_ENABLE);
2611 dce_v11_0_vga_enable(crtc, false);
2612 }
2613 amdgpu_atombios_crtc_enable(crtc, ATOM_DISABLE);
2614 amdgpu_crtc->enabled = false;
2615 break;
2616 }
2617 /* adjust pm to dpms */
2618 amdgpu_pm_compute_clocks(adev);
2619}
2620
2621static void dce_v11_0_crtc_prepare(struct drm_crtc *crtc)
2622{
2623 /* disable crtc pair power gating before programming */
2624 amdgpu_atombios_crtc_powergate(crtc, ATOM_DISABLE);
2625 amdgpu_atombios_crtc_lock(crtc, ATOM_ENABLE);
2626 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2627}
2628
2629static void dce_v11_0_crtc_commit(struct drm_crtc *crtc)
2630{
2631 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
2632 amdgpu_atombios_crtc_lock(crtc, ATOM_DISABLE);
2633}
2634
2635static void dce_v11_0_crtc_disable(struct drm_crtc *crtc)
2636{
2637 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2638 struct drm_device *dev = crtc->dev;
2639 struct amdgpu_device *adev = dev->dev_private;
2640 struct amdgpu_atom_ss ss;
2641 int i;
2642
2643 dce_v11_0_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
2644 if (crtc->primary->fb) {
2645 int r;
2646 struct amdgpu_bo *abo;
2647
2648 abo = gem_to_amdgpu_bo(crtc->primary->fb->obj[0]);
2649 r = amdgpu_bo_reserve(abo, true);
2650 if (unlikely(r))
2651 DRM_ERROR("failed to reserve abo before unpin\n");
2652 else {
2653 amdgpu_bo_unpin(abo);
2654 amdgpu_bo_unreserve(abo);
2655 }
2656 }
2657 /* disable the GRPH */
2658 dce_v11_0_grph_enable(crtc, false);
2659
2660 amdgpu_atombios_crtc_powergate(crtc, ATOM_ENABLE);
2661
2662 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2663 if (adev->mode_info.crtcs[i] &&
2664 adev->mode_info.crtcs[i]->enabled &&
2665 i != amdgpu_crtc->crtc_id &&
2666 amdgpu_crtc->pll_id == adev->mode_info.crtcs[i]->pll_id) {
2667 /* one other crtc is using this pll don't turn
2668 * off the pll
2669 */
2670 goto done;
2671 }
2672 }
2673
2674 switch (amdgpu_crtc->pll_id) {
2675 case ATOM_PPLL0:
2676 case ATOM_PPLL1:
2677 case ATOM_PPLL2:
2678 /* disable the ppll */
2679 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id, amdgpu_crtc->pll_id,
2680 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2681 break;
2682 case ATOM_COMBOPHY_PLL0:
2683 case ATOM_COMBOPHY_PLL1:
2684 case ATOM_COMBOPHY_PLL2:
2685 case ATOM_COMBOPHY_PLL3:
2686 case ATOM_COMBOPHY_PLL4:
2687 case ATOM_COMBOPHY_PLL5:
2688 /* disable the ppll */
2689 amdgpu_atombios_crtc_program_pll(crtc, ATOM_CRTC_INVALID, amdgpu_crtc->pll_id,
2690 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
2691 break;
2692 default:
2693 break;
2694 }
2695done:
2696 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2697 amdgpu_crtc->adjusted_clock = 0;
2698 amdgpu_crtc->encoder = NULL;
2699 amdgpu_crtc->connector = NULL;
2700}
2701
2702static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc,
2703 struct drm_display_mode *mode,
2704 struct drm_display_mode *adjusted_mode,
2705 int x, int y, struct drm_framebuffer *old_fb)
2706{
2707 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2708 struct drm_device *dev = crtc->dev;
2709 struct amdgpu_device *adev = dev->dev_private;
2710
2711 if (!amdgpu_crtc->adjusted_clock)
2712 return -EINVAL;
2713
2714 if ((adev->asic_type == CHIP_POLARIS10) ||
2715 (adev->asic_type == CHIP_POLARIS11) ||
2716 (adev->asic_type == CHIP_POLARIS12) ||
2717 (adev->asic_type == CHIP_VEGAM)) {
2718 struct amdgpu_encoder *amdgpu_encoder =
2719 to_amdgpu_encoder(amdgpu_crtc->encoder);
2720 int encoder_mode =
2721 amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder);
2722
2723 /* SetPixelClock calculates the plls and ss values now */
2724 amdgpu_atombios_crtc_program_pll(crtc, amdgpu_crtc->crtc_id,
2725 amdgpu_crtc->pll_id,
2726 encoder_mode, amdgpu_encoder->encoder_id,
2727 adjusted_mode->clock, 0, 0, 0, 0,
2728 amdgpu_crtc->bpc, amdgpu_crtc->ss_enabled, &amdgpu_crtc->ss);
2729 } else {
2730 amdgpu_atombios_crtc_set_pll(crtc, adjusted_mode);
2731 }
2732 amdgpu_atombios_crtc_set_dtd_timing(crtc, adjusted_mode);
2733 dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2734 amdgpu_atombios_crtc_overscan_setup(crtc, mode, adjusted_mode);
2735 amdgpu_atombios_crtc_scaler_setup(crtc);
2736 dce_v11_0_cursor_reset(crtc);
2737 /* update the hw version fpr dpm */
2738 amdgpu_crtc->hw_mode = *adjusted_mode;
2739
2740 return 0;
2741}
2742
2743static bool dce_v11_0_crtc_mode_fixup(struct drm_crtc *crtc,
2744 const struct drm_display_mode *mode,
2745 struct drm_display_mode *adjusted_mode)
2746{
2747 struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
2748 struct drm_device *dev = crtc->dev;
2749 struct drm_encoder *encoder;
2750
2751 /* assign the encoder to the amdgpu crtc to avoid repeated lookups later */
2752 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2753 if (encoder->crtc == crtc) {
2754 amdgpu_crtc->encoder = encoder;
2755 amdgpu_crtc->connector = amdgpu_get_connector_for_encoder(encoder);
2756 break;
2757 }
2758 }
2759 if ((amdgpu_crtc->encoder == NULL) || (amdgpu_crtc->connector == NULL)) {
2760 amdgpu_crtc->encoder = NULL;
2761 amdgpu_crtc->connector = NULL;
2762 return false;
2763 }
2764 if (!amdgpu_display_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
2765 return false;
2766 if (amdgpu_atombios_crtc_prepare_pll(crtc, adjusted_mode))
2767 return false;
2768 /* pick pll */
2769 amdgpu_crtc->pll_id = dce_v11_0_pick_pll(crtc);
2770 /* if we can't get a PPLL for a non-DP encoder, fail */
2771 if ((amdgpu_crtc->pll_id == ATOM_PPLL_INVALID) &&
2772 !ENCODER_MODE_IS_DP(amdgpu_atombios_encoder_get_encoder_mode(amdgpu_crtc->encoder)))
2773 return false;
2774
2775 return true;
2776}
2777
2778static int dce_v11_0_crtc_set_base(struct drm_crtc *crtc, int x, int y,
2779 struct drm_framebuffer *old_fb)
2780{
2781 return dce_v11_0_crtc_do_set_base(crtc, old_fb, x, y, 0);
2782}
2783
2784static int dce_v11_0_crtc_set_base_atomic(struct drm_crtc *crtc,
2785 struct drm_framebuffer *fb,
2786 int x, int y, enum mode_set_atomic state)
2787{
2788 return dce_v11_0_crtc_do_set_base(crtc, fb, x, y, 1);
2789}
2790
2791static const struct drm_crtc_helper_funcs dce_v11_0_crtc_helper_funcs = {
2792 .dpms = dce_v11_0_crtc_dpms,
2793 .mode_fixup = dce_v11_0_crtc_mode_fixup,
2794 .mode_set = dce_v11_0_crtc_mode_set,
2795 .mode_set_base = dce_v11_0_crtc_set_base,
2796 .mode_set_base_atomic = dce_v11_0_crtc_set_base_atomic,
2797 .prepare = dce_v11_0_crtc_prepare,
2798 .commit = dce_v11_0_crtc_commit,
2799 .disable = dce_v11_0_crtc_disable,
2800 .get_scanout_position = amdgpu_crtc_get_scanout_position,
2801};
2802
2803static int dce_v11_0_crtc_init(struct amdgpu_device *adev, int index)
2804{
2805 struct amdgpu_crtc *amdgpu_crtc;
2806
2807 amdgpu_crtc = kzalloc(sizeof(struct amdgpu_crtc) +
2808 (AMDGPUFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
2809 if (amdgpu_crtc == NULL)
2810 return -ENOMEM;
2811
2812 drm_crtc_init(adev->ddev, &amdgpu_crtc->base, &dce_v11_0_crtc_funcs);
2813
2814 drm_mode_crtc_set_gamma_size(&amdgpu_crtc->base, 256);
2815 amdgpu_crtc->crtc_id = index;
2816 adev->mode_info.crtcs[index] = amdgpu_crtc;
2817
2818 amdgpu_crtc->max_cursor_width = 128;
2819 amdgpu_crtc->max_cursor_height = 128;
2820 adev->ddev->mode_config.cursor_width = amdgpu_crtc->max_cursor_width;
2821 adev->ddev->mode_config.cursor_height = amdgpu_crtc->max_cursor_height;
2822
2823 switch (amdgpu_crtc->crtc_id) {
2824 case 0:
2825 default:
2826 amdgpu_crtc->crtc_offset = CRTC0_REGISTER_OFFSET;
2827 break;
2828 case 1:
2829 amdgpu_crtc->crtc_offset = CRTC1_REGISTER_OFFSET;
2830 break;
2831 case 2:
2832 amdgpu_crtc->crtc_offset = CRTC2_REGISTER_OFFSET;
2833 break;
2834 case 3:
2835 amdgpu_crtc->crtc_offset = CRTC3_REGISTER_OFFSET;
2836 break;
2837 case 4:
2838 amdgpu_crtc->crtc_offset = CRTC4_REGISTER_OFFSET;
2839 break;
2840 case 5:
2841 amdgpu_crtc->crtc_offset = CRTC5_REGISTER_OFFSET;
2842 break;
2843 }
2844
2845 amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
2846 amdgpu_crtc->adjusted_clock = 0;
2847 amdgpu_crtc->encoder = NULL;
2848 amdgpu_crtc->connector = NULL;
2849 drm_crtc_helper_add(&amdgpu_crtc->base, &dce_v11_0_crtc_helper_funcs);
2850
2851 return 0;
2852}
2853
2854static int dce_v11_0_early_init(void *handle)
2855{
2856 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2857
2858 adev->audio_endpt_rreg = &dce_v11_0_audio_endpt_rreg;
2859 adev->audio_endpt_wreg = &dce_v11_0_audio_endpt_wreg;
2860
2861 dce_v11_0_set_display_funcs(adev);
2862
2863 adev->mode_info.num_crtc = dce_v11_0_get_num_crtc(adev);
2864
2865 switch (adev->asic_type) {
2866 case CHIP_CARRIZO:
2867 adev->mode_info.num_hpd = 6;
2868 adev->mode_info.num_dig = 9;
2869 break;
2870 case CHIP_STONEY:
2871 adev->mode_info.num_hpd = 6;
2872 adev->mode_info.num_dig = 9;
2873 break;
2874 case CHIP_POLARIS10:
2875 case CHIP_VEGAM:
2876 adev->mode_info.num_hpd = 6;
2877 adev->mode_info.num_dig = 6;
2878 break;
2879 case CHIP_POLARIS11:
2880 case CHIP_POLARIS12:
2881 adev->mode_info.num_hpd = 5;
2882 adev->mode_info.num_dig = 5;
2883 break;
2884 default:
2885 /* FIXME: not supported yet */
2886 return -EINVAL;
2887 }
2888
2889 dce_v11_0_set_irq_funcs(adev);
2890
2891 return 0;
2892}
2893
2894static int dce_v11_0_sw_init(void *handle)
2895{
2896 int r, i;
2897 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2898
2899 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2900 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
2901 if (r)
2902 return r;
2903 }
2904
2905 for (i = VISLANDS30_IV_SRCID_D1_GRPH_PFLIP; i < 20; i += 2) {
2906 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i, &adev->pageflip_irq);
2907 if (r)
2908 return r;
2909 }
2910
2911 /* HPD hotplug */
2912 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
2913 if (r)
2914 return r;
2915
2916 adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
2917
2918 adev->ddev->mode_config.async_page_flip = true;
2919
2920 adev->ddev->mode_config.max_width = 16384;
2921 adev->ddev->mode_config.max_height = 16384;
2922
2923 adev->ddev->mode_config.preferred_depth = 24;
2924 adev->ddev->mode_config.prefer_shadow = 1;
2925
2926 adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
2927
2928 r = amdgpu_display_modeset_create_props(adev);
2929 if (r)
2930 return r;
2931
2932 adev->ddev->mode_config.max_width = 16384;
2933 adev->ddev->mode_config.max_height = 16384;
2934
2935
2936 /* allocate crtcs */
2937 for (i = 0; i < adev->mode_info.num_crtc; i++) {
2938 r = dce_v11_0_crtc_init(adev, i);
2939 if (r)
2940 return r;
2941 }
2942
2943 if (amdgpu_atombios_get_connector_info_from_object_table(adev))
2944 amdgpu_display_print_display_setup(adev->ddev);
2945 else
2946 return -EINVAL;
2947
2948 /* setup afmt */
2949 r = dce_v11_0_afmt_init(adev);
2950 if (r)
2951 return r;
2952
2953 r = dce_v11_0_audio_init(adev);
2954 if (r)
2955 return r;
2956
2957 drm_kms_helper_poll_init(adev->ddev);
2958
2959 adev->mode_info.mode_config_initialized = true;
2960 return 0;
2961}
2962
2963static int dce_v11_0_sw_fini(void *handle)
2964{
2965 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2966
2967 kfree(adev->mode_info.bios_hardcoded_edid);
2968
2969 drm_kms_helper_poll_fini(adev->ddev);
2970
2971 dce_v11_0_audio_fini(adev);
2972
2973 dce_v11_0_afmt_fini(adev);
2974
2975 drm_mode_config_cleanup(adev->ddev);
2976 adev->mode_info.mode_config_initialized = false;
2977
2978 return 0;
2979}
2980
2981static int dce_v11_0_hw_init(void *handle)
2982{
2983 int i;
2984 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2985
2986 dce_v11_0_init_golden_registers(adev);
2987
2988 /* disable vga render */
2989 dce_v11_0_set_vga_render_state(adev, false);
2990 /* init dig PHYs, disp eng pll */
2991 amdgpu_atombios_crtc_powergate_init(adev);
2992 amdgpu_atombios_encoder_init_dig(adev);
2993 if ((adev->asic_type == CHIP_POLARIS10) ||
2994 (adev->asic_type == CHIP_POLARIS11) ||
2995 (adev->asic_type == CHIP_POLARIS12) ||
2996 (adev->asic_type == CHIP_VEGAM)) {
2997 amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk,
2998 DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS);
2999 amdgpu_atombios_crtc_set_dce_clock(adev, 0,
3000 DCE_CLOCK_TYPE_DPREFCLK, ATOM_GCK_DFS);
3001 } else {
3002 amdgpu_atombios_crtc_set_disp_eng_pll(adev, adev->clock.default_dispclk);
3003 }
3004
3005 /* initialize hpd */
3006 dce_v11_0_hpd_init(adev);
3007
3008 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3009 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3010 }
3011
3012 dce_v11_0_pageflip_interrupt_init(adev);
3013
3014 return 0;
3015}
3016
3017static int dce_v11_0_hw_fini(void *handle)
3018{
3019 int i;
3020 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3021
3022 dce_v11_0_hpd_fini(adev);
3023
3024 for (i = 0; i < adev->mode_info.audio.num_pins; i++) {
3025 dce_v11_0_audio_enable(adev, &adev->mode_info.audio.pin[i], false);
3026 }
3027
3028 dce_v11_0_pageflip_interrupt_fini(adev);
3029
3030 return 0;
3031}
3032
3033static int dce_v11_0_suspend(void *handle)
3034{
3035 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3036
3037 adev->mode_info.bl_level =
3038 amdgpu_atombios_encoder_get_backlight_level_from_reg(adev);
3039
3040 return dce_v11_0_hw_fini(handle);
3041}
3042
3043static int dce_v11_0_resume(void *handle)
3044{
3045 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3046 int ret;
3047
3048 amdgpu_atombios_encoder_set_backlight_level_to_reg(adev,
3049 adev->mode_info.bl_level);
3050
3051 ret = dce_v11_0_hw_init(handle);
3052
3053 /* turn on the BL */
3054 if (adev->mode_info.bl_encoder) {
3055 u8 bl_level = amdgpu_display_backlight_get_level(adev,
3056 adev->mode_info.bl_encoder);
3057 amdgpu_display_backlight_set_level(adev, adev->mode_info.bl_encoder,
3058 bl_level);
3059 }
3060
3061 return ret;
3062}
3063
3064static bool dce_v11_0_is_idle(void *handle)
3065{
3066 return true;
3067}
3068
3069static int dce_v11_0_wait_for_idle(void *handle)
3070{
3071 return 0;
3072}
3073
3074static int dce_v11_0_soft_reset(void *handle)
3075{
3076 u32 srbm_soft_reset = 0, tmp;
3077 struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3078
3079 if (dce_v11_0_is_display_hung(adev))
3080 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_DC_MASK;
3081
3082 if (srbm_soft_reset) {
3083 tmp = RREG32(mmSRBM_SOFT_RESET);
3084 tmp |= srbm_soft_reset;
3085 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
3086 WREG32(mmSRBM_SOFT_RESET, tmp);
3087 tmp = RREG32(mmSRBM_SOFT_RESET);
3088
3089 udelay(50);
3090
3091 tmp &= ~srbm_soft_reset;
3092 WREG32(mmSRBM_SOFT_RESET, tmp);
3093 tmp = RREG32(mmSRBM_SOFT_RESET);
3094
3095 /* Wait a little for things to settle down */
3096 udelay(50);
3097 }
3098 return 0;
3099}
3100
3101static void dce_v11_0_set_crtc_vblank_interrupt_state(struct amdgpu_device *adev,
3102 int crtc,
3103 enum amdgpu_interrupt_state state)
3104{
3105 u32 lb_interrupt_mask;
3106
3107 if (crtc >= adev->mode_info.num_crtc) {
3108 DRM_DEBUG("invalid crtc %d\n", crtc);
3109 return;
3110 }
3111
3112 switch (state) {
3113 case AMDGPU_IRQ_STATE_DISABLE:
3114 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3115 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3116 VBLANK_INTERRUPT_MASK, 0);
3117 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3118 break;
3119 case AMDGPU_IRQ_STATE_ENABLE:
3120 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3121 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3122 VBLANK_INTERRUPT_MASK, 1);
3123 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3124 break;
3125 default:
3126 break;
3127 }
3128}
3129
3130static void dce_v11_0_set_crtc_vline_interrupt_state(struct amdgpu_device *adev,
3131 int crtc,
3132 enum amdgpu_interrupt_state state)
3133{
3134 u32 lb_interrupt_mask;
3135
3136 if (crtc >= adev->mode_info.num_crtc) {
3137 DRM_DEBUG("invalid crtc %d\n", crtc);
3138 return;
3139 }
3140
3141 switch (state) {
3142 case AMDGPU_IRQ_STATE_DISABLE:
3143 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3144 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3145 VLINE_INTERRUPT_MASK, 0);
3146 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3147 break;
3148 case AMDGPU_IRQ_STATE_ENABLE:
3149 lb_interrupt_mask = RREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc]);
3150 lb_interrupt_mask = REG_SET_FIELD(lb_interrupt_mask, LB_INTERRUPT_MASK,
3151 VLINE_INTERRUPT_MASK, 1);
3152 WREG32(mmLB_INTERRUPT_MASK + crtc_offsets[crtc], lb_interrupt_mask);
3153 break;
3154 default:
3155 break;
3156 }
3157}
3158
3159static int dce_v11_0_set_hpd_irq_state(struct amdgpu_device *adev,
3160 struct amdgpu_irq_src *source,
3161 unsigned hpd,
3162 enum amdgpu_interrupt_state state)
3163{
3164 u32 tmp;
3165
3166 if (hpd >= adev->mode_info.num_hpd) {
3167 DRM_DEBUG("invalid hdp %d\n", hpd);
3168 return 0;
3169 }
3170
3171 switch (state) {
3172 case AMDGPU_IRQ_STATE_DISABLE:
3173 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3174 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 0);
3175 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3176 break;
3177 case AMDGPU_IRQ_STATE_ENABLE:
3178 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3179 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_EN, 1);
3180 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3181 break;
3182 default:
3183 break;
3184 }
3185
3186 return 0;
3187}
3188
3189static int dce_v11_0_set_crtc_irq_state(struct amdgpu_device *adev,
3190 struct amdgpu_irq_src *source,
3191 unsigned type,
3192 enum amdgpu_interrupt_state state)
3193{
3194 switch (type) {
3195 case AMDGPU_CRTC_IRQ_VBLANK1:
3196 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 0, state);
3197 break;
3198 case AMDGPU_CRTC_IRQ_VBLANK2:
3199 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 1, state);
3200 break;
3201 case AMDGPU_CRTC_IRQ_VBLANK3:
3202 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 2, state);
3203 break;
3204 case AMDGPU_CRTC_IRQ_VBLANK4:
3205 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 3, state);
3206 break;
3207 case AMDGPU_CRTC_IRQ_VBLANK5:
3208 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 4, state);
3209 break;
3210 case AMDGPU_CRTC_IRQ_VBLANK6:
3211 dce_v11_0_set_crtc_vblank_interrupt_state(adev, 5, state);
3212 break;
3213 case AMDGPU_CRTC_IRQ_VLINE1:
3214 dce_v11_0_set_crtc_vline_interrupt_state(adev, 0, state);
3215 break;
3216 case AMDGPU_CRTC_IRQ_VLINE2:
3217 dce_v11_0_set_crtc_vline_interrupt_state(adev, 1, state);
3218 break;
3219 case AMDGPU_CRTC_IRQ_VLINE3:
3220 dce_v11_0_set_crtc_vline_interrupt_state(adev, 2, state);
3221 break;
3222 case AMDGPU_CRTC_IRQ_VLINE4:
3223 dce_v11_0_set_crtc_vline_interrupt_state(adev, 3, state);
3224 break;
3225 case AMDGPU_CRTC_IRQ_VLINE5:
3226 dce_v11_0_set_crtc_vline_interrupt_state(adev, 4, state);
3227 break;
3228 case AMDGPU_CRTC_IRQ_VLINE6:
3229 dce_v11_0_set_crtc_vline_interrupt_state(adev, 5, state);
3230 break;
3231 default:
3232 break;
3233 }
3234 return 0;
3235}
3236
3237static int dce_v11_0_set_pageflip_irq_state(struct amdgpu_device *adev,
3238 struct amdgpu_irq_src *src,
3239 unsigned type,
3240 enum amdgpu_interrupt_state state)
3241{
3242 u32 reg;
3243
3244 if (type >= adev->mode_info.num_crtc) {
3245 DRM_ERROR("invalid pageflip crtc %d\n", type);
3246 return -EINVAL;
3247 }
3248
3249 reg = RREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type]);
3250 if (state == AMDGPU_IRQ_STATE_DISABLE)
3251 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3252 reg & ~GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3253 else
3254 WREG32(mmGRPH_INTERRUPT_CONTROL + crtc_offsets[type],
3255 reg | GRPH_INTERRUPT_CONTROL__GRPH_PFLIP_INT_MASK_MASK);
3256
3257 return 0;
3258}
3259
3260static int dce_v11_0_pageflip_irq(struct amdgpu_device *adev,
3261 struct amdgpu_irq_src *source,
3262 struct amdgpu_iv_entry *entry)
3263{
3264 unsigned long flags;
3265 unsigned crtc_id;
3266 struct amdgpu_crtc *amdgpu_crtc;
3267 struct amdgpu_flip_work *works;
3268
3269 crtc_id = (entry->src_id - 8) >> 1;
3270 amdgpu_crtc = adev->mode_info.crtcs[crtc_id];
3271
3272 if (crtc_id >= adev->mode_info.num_crtc) {
3273 DRM_ERROR("invalid pageflip crtc %d\n", crtc_id);
3274 return -EINVAL;
3275 }
3276
3277 if (RREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id]) &
3278 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_OCCURRED_MASK)
3279 WREG32(mmGRPH_INTERRUPT_STATUS + crtc_offsets[crtc_id],
3280 GRPH_INTERRUPT_STATUS__GRPH_PFLIP_INT_CLEAR_MASK);
3281
3282 /* IRQ could occur when in initial stage */
3283 if(amdgpu_crtc == NULL)
3284 return 0;
3285
3286 spin_lock_irqsave(&adev->ddev->event_lock, flags);
3287 works = amdgpu_crtc->pflip_works;
3288 if (amdgpu_crtc->pflip_status != AMDGPU_FLIP_SUBMITTED){
3289 DRM_DEBUG_DRIVER("amdgpu_crtc->pflip_status = %d != "
3290 "AMDGPU_FLIP_SUBMITTED(%d)\n",
3291 amdgpu_crtc->pflip_status,
3292 AMDGPU_FLIP_SUBMITTED);
3293 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3294 return 0;
3295 }
3296
3297 /* page flip completed. clean up */
3298 amdgpu_crtc->pflip_status = AMDGPU_FLIP_NONE;
3299 amdgpu_crtc->pflip_works = NULL;
3300
3301 /* wakeup usersapce */
3302 if(works->event)
3303 drm_crtc_send_vblank_event(&amdgpu_crtc->base, works->event);
3304
3305 spin_unlock_irqrestore(&adev->ddev->event_lock, flags);
3306
3307 drm_crtc_vblank_put(&amdgpu_crtc->base);
3308 schedule_work(&works->unpin_work);
3309
3310 return 0;
3311}
3312
3313static void dce_v11_0_hpd_int_ack(struct amdgpu_device *adev,
3314 int hpd)
3315{
3316 u32 tmp;
3317
3318 if (hpd >= adev->mode_info.num_hpd) {
3319 DRM_DEBUG("invalid hdp %d\n", hpd);
3320 return;
3321 }
3322
3323 tmp = RREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd]);
3324 tmp = REG_SET_FIELD(tmp, DC_HPD_INT_CONTROL, DC_HPD_INT_ACK, 1);
3325 WREG32(mmDC_HPD_INT_CONTROL + hpd_offsets[hpd], tmp);
3326}
3327
3328static void dce_v11_0_crtc_vblank_int_ack(struct amdgpu_device *adev,
3329 int crtc)
3330{
3331 u32 tmp;
3332
3333 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3334 DRM_DEBUG("invalid crtc %d\n", crtc);
3335 return;
3336 }
3337
3338 tmp = RREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc]);
3339 tmp = REG_SET_FIELD(tmp, LB_VBLANK_STATUS, VBLANK_ACK, 1);
3340 WREG32(mmLB_VBLANK_STATUS + crtc_offsets[crtc], tmp);
3341}
3342
3343static void dce_v11_0_crtc_vline_int_ack(struct amdgpu_device *adev,
3344 int crtc)
3345{
3346 u32 tmp;
3347
3348 if (crtc < 0 || crtc >= adev->mode_info.num_crtc) {
3349 DRM_DEBUG("invalid crtc %d\n", crtc);
3350 return;
3351 }
3352
3353 tmp = RREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc]);
3354 tmp = REG_SET_FIELD(tmp, LB_VLINE_STATUS, VLINE_ACK, 1);
3355 WREG32(mmLB_VLINE_STATUS + crtc_offsets[crtc], tmp);
3356}
3357
3358static int dce_v11_0_crtc_irq(struct amdgpu_device *adev,
3359 struct amdgpu_irq_src *source,
3360 struct amdgpu_iv_entry *entry)
3361{
3362 unsigned crtc = entry->src_id - 1;
3363 uint32_t disp_int = RREG32(interrupt_status_offsets[crtc].reg);
3364 unsigned int irq_type = amdgpu_display_crtc_idx_to_irq_type(adev,
3365 crtc);
3366
3367 switch (entry->src_data[0]) {
3368 case 0: /* vblank */
3369 if (disp_int & interrupt_status_offsets[crtc].vblank)
3370 dce_v11_0_crtc_vblank_int_ack(adev, crtc);
3371 else
3372 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3373
3374 if (amdgpu_irq_enabled(adev, source, irq_type)) {
3375 drm_handle_vblank(adev->ddev, crtc);
3376 }
3377 DRM_DEBUG("IH: D%d vblank\n", crtc + 1);
3378
3379 break;
3380 case 1: /* vline */
3381 if (disp_int & interrupt_status_offsets[crtc].vline)
3382 dce_v11_0_crtc_vline_int_ack(adev, crtc);
3383 else
3384 DRM_DEBUG("IH: IH event w/o asserted irq bit?\n");
3385
3386 DRM_DEBUG("IH: D%d vline\n", crtc + 1);
3387
3388 break;
3389 default:
3390 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3391 break;
3392 }
3393
3394 return 0;
3395}
3396
3397static int dce_v11_0_hpd_irq(struct amdgpu_device *adev,
3398 struct amdgpu_irq_src *source,
3399 struct amdgpu_iv_entry *entry)
3400{
3401 uint32_t disp_int, mask;
3402 unsigned hpd;
3403
3404 if (entry->src_data[0] >= adev->mode_info.num_hpd) {
3405 DRM_DEBUG("Unhandled interrupt: %d %d\n", entry->src_id, entry->src_data[0]);
3406 return 0;
3407 }
3408
3409 hpd = entry->src_data[0];
3410 disp_int = RREG32(interrupt_status_offsets[hpd].reg);
3411 mask = interrupt_status_offsets[hpd].hpd;
3412
3413 if (disp_int & mask) {
3414 dce_v11_0_hpd_int_ack(adev, hpd);
3415 schedule_work(&adev->hotplug_work);
3416 DRM_DEBUG("IH: HPD%d\n", hpd + 1);
3417 }
3418
3419 return 0;
3420}
3421
3422static int dce_v11_0_set_clockgating_state(void *handle,
3423 enum amd_clockgating_state state)
3424{
3425 return 0;
3426}
3427
3428static int dce_v11_0_set_powergating_state(void *handle,
3429 enum amd_powergating_state state)
3430{
3431 return 0;
3432}
3433
3434static const struct amd_ip_funcs dce_v11_0_ip_funcs = {
3435 .name = "dce_v11_0",
3436 .early_init = dce_v11_0_early_init,
3437 .late_init = NULL,
3438 .sw_init = dce_v11_0_sw_init,
3439 .sw_fini = dce_v11_0_sw_fini,
3440 .hw_init = dce_v11_0_hw_init,
3441 .hw_fini = dce_v11_0_hw_fini,
3442 .suspend = dce_v11_0_suspend,
3443 .resume = dce_v11_0_resume,
3444 .is_idle = dce_v11_0_is_idle,
3445 .wait_for_idle = dce_v11_0_wait_for_idle,
3446 .soft_reset = dce_v11_0_soft_reset,
3447 .set_clockgating_state = dce_v11_0_set_clockgating_state,
3448 .set_powergating_state = dce_v11_0_set_powergating_state,
3449};
3450
3451static void
3452dce_v11_0_encoder_mode_set(struct drm_encoder *encoder,
3453 struct drm_display_mode *mode,
3454 struct drm_display_mode *adjusted_mode)
3455{
3456 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3457
3458 amdgpu_encoder->pixel_clock = adjusted_mode->clock;
3459
3460 /* need to call this here rather than in prepare() since we need some crtc info */
3461 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3462
3463 /* set scaler clears this on some chips */
3464 dce_v11_0_set_interleave(encoder->crtc, mode);
3465
3466 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
3467 dce_v11_0_afmt_enable(encoder, true);
3468 dce_v11_0_afmt_setmode(encoder, adjusted_mode);
3469 }
3470}
3471
3472static void dce_v11_0_encoder_prepare(struct drm_encoder *encoder)
3473{
3474 struct amdgpu_device *adev = encoder->dev->dev_private;
3475 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3476 struct drm_connector *connector = amdgpu_get_connector_for_encoder(encoder);
3477
3478 if ((amdgpu_encoder->active_device &
3479 (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
3480 (amdgpu_encoder_get_dp_bridge_encoder_id(encoder) !=
3481 ENCODER_OBJECT_ID_NONE)) {
3482 struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv;
3483 if (dig) {
3484 dig->dig_encoder = dce_v11_0_pick_dig_encoder(encoder);
3485 if (amdgpu_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT)
3486 dig->afmt = adev->mode_info.afmt[dig->dig_encoder];
3487 }
3488 }
3489
3490 amdgpu_atombios_scratch_regs_lock(adev, true);
3491
3492 if (connector) {
3493 struct amdgpu_connector *amdgpu_connector = to_amdgpu_connector(connector);
3494
3495 /* select the clock/data port if it uses a router */
3496 if (amdgpu_connector->router.cd_valid)
3497 amdgpu_i2c_router_select_cd_port(amdgpu_connector);
3498
3499 /* turn eDP panel on for mode set */
3500 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
3501 amdgpu_atombios_encoder_set_edp_panel_power(connector,
3502 ATOM_TRANSMITTER_ACTION_POWER_ON);
3503 }
3504
3505 /* this is needed for the pll/ss setup to work correctly in some cases */
3506 amdgpu_atombios_encoder_set_crtc_source(encoder);
3507 /* set up the FMT blocks */
3508 dce_v11_0_program_fmt(encoder);
3509}
3510
3511static void dce_v11_0_encoder_commit(struct drm_encoder *encoder)
3512{
3513 struct drm_device *dev = encoder->dev;
3514 struct amdgpu_device *adev = dev->dev_private;
3515
3516 /* need to call this here as we need the crtc set up */
3517 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
3518 amdgpu_atombios_scratch_regs_lock(adev, false);
3519}
3520
3521static void dce_v11_0_encoder_disable(struct drm_encoder *encoder)
3522{
3523 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3524 struct amdgpu_encoder_atom_dig *dig;
3525
3526 amdgpu_atombios_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
3527
3528 if (amdgpu_atombios_encoder_is_digital(encoder)) {
3529 if (amdgpu_atombios_encoder_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
3530 dce_v11_0_afmt_enable(encoder, false);
3531 dig = amdgpu_encoder->enc_priv;
3532 dig->dig_encoder = -1;
3533 }
3534 amdgpu_encoder->active_device = 0;
3535}
3536
3537/* these are handled by the primary encoders */
3538static void dce_v11_0_ext_prepare(struct drm_encoder *encoder)
3539{
3540
3541}
3542
3543static void dce_v11_0_ext_commit(struct drm_encoder *encoder)
3544{
3545
3546}
3547
3548static void
3549dce_v11_0_ext_mode_set(struct drm_encoder *encoder,
3550 struct drm_display_mode *mode,
3551 struct drm_display_mode *adjusted_mode)
3552{
3553
3554}
3555
3556static void dce_v11_0_ext_disable(struct drm_encoder *encoder)
3557{
3558
3559}
3560
3561static void
3562dce_v11_0_ext_dpms(struct drm_encoder *encoder, int mode)
3563{
3564
3565}
3566
3567static const struct drm_encoder_helper_funcs dce_v11_0_ext_helper_funcs = {
3568 .dpms = dce_v11_0_ext_dpms,
3569 .prepare = dce_v11_0_ext_prepare,
3570 .mode_set = dce_v11_0_ext_mode_set,
3571 .commit = dce_v11_0_ext_commit,
3572 .disable = dce_v11_0_ext_disable,
3573 /* no detect for TMDS/LVDS yet */
3574};
3575
3576static const struct drm_encoder_helper_funcs dce_v11_0_dig_helper_funcs = {
3577 .dpms = amdgpu_atombios_encoder_dpms,
3578 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3579 .prepare = dce_v11_0_encoder_prepare,
3580 .mode_set = dce_v11_0_encoder_mode_set,
3581 .commit = dce_v11_0_encoder_commit,
3582 .disable = dce_v11_0_encoder_disable,
3583 .detect = amdgpu_atombios_encoder_dig_detect,
3584};
3585
3586static const struct drm_encoder_helper_funcs dce_v11_0_dac_helper_funcs = {
3587 .dpms = amdgpu_atombios_encoder_dpms,
3588 .mode_fixup = amdgpu_atombios_encoder_mode_fixup,
3589 .prepare = dce_v11_0_encoder_prepare,
3590 .mode_set = dce_v11_0_encoder_mode_set,
3591 .commit = dce_v11_0_encoder_commit,
3592 .detect = amdgpu_atombios_encoder_dac_detect,
3593};
3594
3595static void dce_v11_0_encoder_destroy(struct drm_encoder *encoder)
3596{
3597 struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(encoder);
3598 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3599 amdgpu_atombios_encoder_fini_backlight(amdgpu_encoder);
3600 kfree(amdgpu_encoder->enc_priv);
3601 drm_encoder_cleanup(encoder);
3602 kfree(amdgpu_encoder);
3603}
3604
3605static const struct drm_encoder_funcs dce_v11_0_encoder_funcs = {
3606 .destroy = dce_v11_0_encoder_destroy,
3607};
3608
3609static void dce_v11_0_encoder_add(struct amdgpu_device *adev,
3610 uint32_t encoder_enum,
3611 uint32_t supported_device,
3612 u16 caps)
3613{
3614 struct drm_device *dev = adev->ddev;
3615 struct drm_encoder *encoder;
3616 struct amdgpu_encoder *amdgpu_encoder;
3617
3618 /* see if we already added it */
3619 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3620 amdgpu_encoder = to_amdgpu_encoder(encoder);
3621 if (amdgpu_encoder->encoder_enum == encoder_enum) {
3622 amdgpu_encoder->devices |= supported_device;
3623 return;
3624 }
3625
3626 }
3627
3628 /* add a new one */
3629 amdgpu_encoder = kzalloc(sizeof(struct amdgpu_encoder), GFP_KERNEL);
3630 if (!amdgpu_encoder)
3631 return;
3632
3633 encoder = &amdgpu_encoder->base;
3634 switch (adev->mode_info.num_crtc) {
3635 case 1:
3636 encoder->possible_crtcs = 0x1;
3637 break;
3638 case 2:
3639 default:
3640 encoder->possible_crtcs = 0x3;
3641 break;
3642 case 3:
3643 encoder->possible_crtcs = 0x7;
3644 break;
3645 case 4:
3646 encoder->possible_crtcs = 0xf;
3647 break;
3648 case 5:
3649 encoder->possible_crtcs = 0x1f;
3650 break;
3651 case 6:
3652 encoder->possible_crtcs = 0x3f;
3653 break;
3654 }
3655
3656 amdgpu_encoder->enc_priv = NULL;
3657
3658 amdgpu_encoder->encoder_enum = encoder_enum;
3659 amdgpu_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
3660 amdgpu_encoder->devices = supported_device;
3661 amdgpu_encoder->rmx_type = RMX_OFF;
3662 amdgpu_encoder->underscan_type = UNDERSCAN_OFF;
3663 amdgpu_encoder->is_ext_encoder = false;
3664 amdgpu_encoder->caps = caps;
3665
3666 switch (amdgpu_encoder->encoder_id) {
3667 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
3668 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
3669 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3670 DRM_MODE_ENCODER_DAC, NULL);
3671 drm_encoder_helper_add(encoder, &dce_v11_0_dac_helper_funcs);
3672 break;
3673 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
3674 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
3675 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
3676 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
3677 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
3678 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
3679 amdgpu_encoder->rmx_type = RMX_FULL;
3680 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3681 DRM_MODE_ENCODER_LVDS, NULL);
3682 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_lcd_info(amdgpu_encoder);
3683 } else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
3684 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3685 DRM_MODE_ENCODER_DAC, NULL);
3686 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3687 } else {
3688 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3689 DRM_MODE_ENCODER_TMDS, NULL);
3690 amdgpu_encoder->enc_priv = amdgpu_atombios_encoder_get_dig_info(amdgpu_encoder);
3691 }
3692 drm_encoder_helper_add(encoder, &dce_v11_0_dig_helper_funcs);
3693 break;
3694 case ENCODER_OBJECT_ID_SI170B:
3695 case ENCODER_OBJECT_ID_CH7303:
3696 case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
3697 case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
3698 case ENCODER_OBJECT_ID_TITFP513:
3699 case ENCODER_OBJECT_ID_VT1623:
3700 case ENCODER_OBJECT_ID_HDMI_SI1930:
3701 case ENCODER_OBJECT_ID_TRAVIS:
3702 case ENCODER_OBJECT_ID_NUTMEG:
3703 /* these are handled by the primary encoders */
3704 amdgpu_encoder->is_ext_encoder = true;
3705 if (amdgpu_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
3706 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3707 DRM_MODE_ENCODER_LVDS, NULL);
3708 else if (amdgpu_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
3709 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3710 DRM_MODE_ENCODER_DAC, NULL);
3711 else
3712 drm_encoder_init(dev, encoder, &dce_v11_0_encoder_funcs,
3713 DRM_MODE_ENCODER_TMDS, NULL);
3714 drm_encoder_helper_add(encoder, &dce_v11_0_ext_helper_funcs);
3715 break;
3716 }
3717}
3718
3719static const struct amdgpu_display_funcs dce_v11_0_display_funcs = {
3720 .bandwidth_update = &dce_v11_0_bandwidth_update,
3721 .vblank_get_counter = &dce_v11_0_vblank_get_counter,
3722 .backlight_set_level = &amdgpu_atombios_encoder_set_backlight_level,
3723 .backlight_get_level = &amdgpu_atombios_encoder_get_backlight_level,
3724 .hpd_sense = &dce_v11_0_hpd_sense,
3725 .hpd_set_polarity = &dce_v11_0_hpd_set_polarity,
3726 .hpd_get_gpio_reg = &dce_v11_0_hpd_get_gpio_reg,
3727 .page_flip = &dce_v11_0_page_flip,
3728 .page_flip_get_scanoutpos = &dce_v11_0_crtc_get_scanoutpos,
3729 .add_encoder = &dce_v11_0_encoder_add,
3730 .add_connector = &amdgpu_connector_add,
3731};
3732
3733static void dce_v11_0_set_display_funcs(struct amdgpu_device *adev)
3734{
3735 adev->mode_info.funcs = &dce_v11_0_display_funcs;
3736}
3737
3738static const struct amdgpu_irq_src_funcs dce_v11_0_crtc_irq_funcs = {
3739 .set = dce_v11_0_set_crtc_irq_state,
3740 .process = dce_v11_0_crtc_irq,
3741};
3742
3743static const struct amdgpu_irq_src_funcs dce_v11_0_pageflip_irq_funcs = {
3744 .set = dce_v11_0_set_pageflip_irq_state,
3745 .process = dce_v11_0_pageflip_irq,
3746};
3747
3748static const struct amdgpu_irq_src_funcs dce_v11_0_hpd_irq_funcs = {
3749 .set = dce_v11_0_set_hpd_irq_state,
3750 .process = dce_v11_0_hpd_irq,
3751};
3752
3753static void dce_v11_0_set_irq_funcs(struct amdgpu_device *adev)
3754{
3755 if (adev->mode_info.num_crtc > 0)
3756 adev->crtc_irq.num_types = AMDGPU_CRTC_IRQ_VLINE1 + adev->mode_info.num_crtc;
3757 else
3758 adev->crtc_irq.num_types = 0;
3759 adev->crtc_irq.funcs = &dce_v11_0_crtc_irq_funcs;
3760
3761 adev->pageflip_irq.num_types = adev->mode_info.num_crtc;
3762 adev->pageflip_irq.funcs = &dce_v11_0_pageflip_irq_funcs;
3763
3764 adev->hpd_irq.num_types = adev->mode_info.num_hpd;
3765 adev->hpd_irq.funcs = &dce_v11_0_hpd_irq_funcs;
3766}
3767
3768const struct amdgpu_ip_block_version dce_v11_0_ip_block =
3769{
3770 .type = AMD_IP_BLOCK_TYPE_DCE,
3771 .major = 11,
3772 .minor = 0,
3773 .rev = 0,
3774 .funcs = &dce_v11_0_ip_funcs,
3775};
3776
3777const struct amdgpu_ip_block_version dce_v11_2_ip_block =
3778{
3779 .type = AMD_IP_BLOCK_TYPE_DCE,
3780 .major = 11,
3781 .minor = 2,
3782 .rev = 0,
3783 .funcs = &dce_v11_0_ip_funcs,
3784};