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1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
33#include <linux/slab.h>
34#include <drm/drmP.h>
35#include <drm/amdgpu_drm.h>
36#include <drm/drm_cache.h>
37#include "amdgpu.h"
38#include "amdgpu_trace.h"
39#include "amdgpu_amdkfd.h"
40
41static bool amdgpu_need_backup(struct amdgpu_device *adev)
42{
43 if (adev->flags & AMD_IS_APU)
44 return false;
45
46 if (amdgpu_gpu_recovery == 0 ||
47 (amdgpu_gpu_recovery == -1 && !amdgpu_sriov_vf(adev)))
48 return false;
49
50 return true;
51}
52
53static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
54{
55 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
56 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
57
58 if (bo->kfd_bo)
59 amdgpu_amdkfd_unreserve_system_memory_limit(bo);
60
61 amdgpu_bo_kunmap(bo);
62
63 if (bo->gem_base.import_attach)
64 drm_prime_gem_destroy(&bo->gem_base, bo->tbo.sg);
65 drm_gem_object_release(&bo->gem_base);
66 amdgpu_bo_unref(&bo->parent);
67 if (!list_empty(&bo->shadow_list)) {
68 mutex_lock(&adev->shadow_list_lock);
69 list_del_init(&bo->shadow_list);
70 mutex_unlock(&adev->shadow_list_lock);
71 }
72 kfree(bo->metadata);
73 kfree(bo);
74}
75
76bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
77{
78 if (bo->destroy == &amdgpu_ttm_bo_destroy)
79 return true;
80 return false;
81}
82
83void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
84{
85 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
86 struct ttm_placement *placement = &abo->placement;
87 struct ttm_place *places = abo->placements;
88 u64 flags = abo->flags;
89 u32 c = 0;
90
91 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
92 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
93
94 places[c].fpfn = 0;
95 places[c].lpfn = 0;
96 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
97 TTM_PL_FLAG_VRAM;
98
99 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
100 places[c].lpfn = visible_pfn;
101 else
102 places[c].flags |= TTM_PL_FLAG_TOPDOWN;
103
104 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
105 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
106 c++;
107 }
108
109 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
110 places[c].fpfn = 0;
111 if (flags & AMDGPU_GEM_CREATE_SHADOW)
112 places[c].lpfn = adev->gmc.gart_size >> PAGE_SHIFT;
113 else
114 places[c].lpfn = 0;
115 places[c].flags = TTM_PL_FLAG_TT;
116 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
117 places[c].flags |= TTM_PL_FLAG_WC |
118 TTM_PL_FLAG_UNCACHED;
119 else
120 places[c].flags |= TTM_PL_FLAG_CACHED;
121 c++;
122 }
123
124 if (domain & AMDGPU_GEM_DOMAIN_CPU) {
125 places[c].fpfn = 0;
126 places[c].lpfn = 0;
127 places[c].flags = TTM_PL_FLAG_SYSTEM;
128 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
129 places[c].flags |= TTM_PL_FLAG_WC |
130 TTM_PL_FLAG_UNCACHED;
131 else
132 places[c].flags |= TTM_PL_FLAG_CACHED;
133 c++;
134 }
135
136 if (domain & AMDGPU_GEM_DOMAIN_GDS) {
137 places[c].fpfn = 0;
138 places[c].lpfn = 0;
139 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
140 c++;
141 }
142
143 if (domain & AMDGPU_GEM_DOMAIN_GWS) {
144 places[c].fpfn = 0;
145 places[c].lpfn = 0;
146 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
147 c++;
148 }
149
150 if (domain & AMDGPU_GEM_DOMAIN_OA) {
151 places[c].fpfn = 0;
152 places[c].lpfn = 0;
153 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
154 c++;
155 }
156
157 if (!c) {
158 places[c].fpfn = 0;
159 places[c].lpfn = 0;
160 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
161 c++;
162 }
163
164 placement->num_placement = c;
165 placement->placement = places;
166
167 placement->num_busy_placement = c;
168 placement->busy_placement = places;
169}
170
171/**
172 * amdgpu_bo_create_reserved - create reserved BO for kernel use
173 *
174 * @adev: amdgpu device object
175 * @size: size for the new BO
176 * @align: alignment for the new BO
177 * @domain: where to place it
178 * @bo_ptr: used to initialize BOs in structures
179 * @gpu_addr: GPU addr of the pinned BO
180 * @cpu_addr: optional CPU address mapping
181 *
182 * Allocates and pins a BO for kernel internal use, and returns it still
183 * reserved.
184 *
185 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
186 *
187 * Returns 0 on success, negative error code otherwise.
188 */
189int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
190 unsigned long size, int align,
191 u32 domain, struct amdgpu_bo **bo_ptr,
192 u64 *gpu_addr, void **cpu_addr)
193{
194 bool free = false;
195 int r;
196
197 if (!*bo_ptr) {
198 r = amdgpu_bo_create(adev, size, align, domain,
199 AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
200 AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
201 ttm_bo_type_kernel, NULL, bo_ptr);
202 if (r) {
203 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
204 r);
205 return r;
206 }
207 free = true;
208 }
209
210 r = amdgpu_bo_reserve(*bo_ptr, false);
211 if (r) {
212 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
213 goto error_free;
214 }
215
216 r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
217 if (r) {
218 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
219 goto error_unreserve;
220 }
221
222 if (cpu_addr) {
223 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
224 if (r) {
225 dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
226 goto error_unreserve;
227 }
228 }
229
230 return 0;
231
232error_unreserve:
233 amdgpu_bo_unreserve(*bo_ptr);
234
235error_free:
236 if (free)
237 amdgpu_bo_unref(bo_ptr);
238
239 return r;
240}
241
242/**
243 * amdgpu_bo_create_kernel - create BO for kernel use
244 *
245 * @adev: amdgpu device object
246 * @size: size for the new BO
247 * @align: alignment for the new BO
248 * @domain: where to place it
249 * @bo_ptr: used to initialize BOs in structures
250 * @gpu_addr: GPU addr of the pinned BO
251 * @cpu_addr: optional CPU address mapping
252 *
253 * Allocates and pins a BO for kernel internal use.
254 *
255 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
256 *
257 * Returns 0 on success, negative error code otherwise.
258 */
259int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
260 unsigned long size, int align,
261 u32 domain, struct amdgpu_bo **bo_ptr,
262 u64 *gpu_addr, void **cpu_addr)
263{
264 int r;
265
266 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
267 gpu_addr, cpu_addr);
268
269 if (r)
270 return r;
271
272 amdgpu_bo_unreserve(*bo_ptr);
273
274 return 0;
275}
276
277/**
278 * amdgpu_bo_free_kernel - free BO for kernel use
279 *
280 * @bo: amdgpu BO to free
281 *
282 * unmaps and unpin a BO for kernel internal use.
283 */
284void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
285 void **cpu_addr)
286{
287 if (*bo == NULL)
288 return;
289
290 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
291 if (cpu_addr)
292 amdgpu_bo_kunmap(*bo);
293
294 amdgpu_bo_unpin(*bo);
295 amdgpu_bo_unreserve(*bo);
296 }
297 amdgpu_bo_unref(bo);
298
299 if (gpu_addr)
300 *gpu_addr = 0;
301
302 if (cpu_addr)
303 *cpu_addr = NULL;
304}
305
306/* Validate bo size is bit bigger then the request domain */
307static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
308 unsigned long size, u32 domain)
309{
310 struct ttm_mem_type_manager *man = NULL;
311
312 /*
313 * If GTT is part of requested domains the check must succeed to
314 * allow fall back to GTT
315 */
316 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
317 man = &adev->mman.bdev.man[TTM_PL_TT];
318
319 if (size < (man->size << PAGE_SHIFT))
320 return true;
321 else
322 goto fail;
323 }
324
325 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
326 man = &adev->mman.bdev.man[TTM_PL_VRAM];
327
328 if (size < (man->size << PAGE_SHIFT))
329 return true;
330 else
331 goto fail;
332 }
333
334
335 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
336 return true;
337
338fail:
339 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
340 man->size << PAGE_SHIFT);
341 return false;
342}
343
344static int amdgpu_bo_do_create(struct amdgpu_device *adev, unsigned long size,
345 int byte_align, u32 domain,
346 u64 flags, enum ttm_bo_type type,
347 struct reservation_object *resv,
348 struct amdgpu_bo **bo_ptr)
349{
350 struct ttm_operation_ctx ctx = {
351 .interruptible = (type != ttm_bo_type_kernel),
352 .no_wait_gpu = false,
353 .resv = resv,
354 .flags = TTM_OPT_FLAG_ALLOW_RES_EVICT
355 };
356 struct amdgpu_bo *bo;
357 unsigned long page_align;
358 size_t acc_size;
359 int r;
360
361 page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
362 size = ALIGN(size, PAGE_SIZE);
363
364 if (!amdgpu_bo_validate_size(adev, size, domain))
365 return -ENOMEM;
366
367 *bo_ptr = NULL;
368
369 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
370 sizeof(struct amdgpu_bo));
371
372 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
373 if (bo == NULL)
374 return -ENOMEM;
375 drm_gem_private_object_init(adev->ddev, &bo->gem_base, size);
376 INIT_LIST_HEAD(&bo->shadow_list);
377 INIT_LIST_HEAD(&bo->va);
378 bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
379 AMDGPU_GEM_DOMAIN_GTT |
380 AMDGPU_GEM_DOMAIN_CPU |
381 AMDGPU_GEM_DOMAIN_GDS |
382 AMDGPU_GEM_DOMAIN_GWS |
383 AMDGPU_GEM_DOMAIN_OA);
384 bo->allowed_domains = bo->preferred_domains;
385 if (type != ttm_bo_type_kernel &&
386 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
387 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
388
389 bo->flags = flags;
390
391#ifdef CONFIG_X86_32
392 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
393 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
394 */
395 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
396#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
397 /* Don't try to enable write-combining when it can't work, or things
398 * may be slow
399 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
400 */
401
402#ifndef CONFIG_COMPILE_TEST
403#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
404 thanks to write-combining
405#endif
406
407 if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
408 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
409 "better performance thanks to write-combining\n");
410 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
411#else
412 /* For architectures that don't support WC memory,
413 * mask out the WC flag from the BO
414 */
415 if (!drm_arch_can_wc_memory())
416 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
417#endif
418
419 bo->tbo.bdev = &adev->mman.bdev;
420 amdgpu_ttm_placement_from_domain(bo, domain);
421
422 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
423 &bo->placement, page_align, &ctx, acc_size,
424 NULL, resv, &amdgpu_ttm_bo_destroy);
425 if (unlikely(r != 0))
426 return r;
427
428 if (adev->gmc.visible_vram_size < adev->gmc.real_vram_size &&
429 bo->tbo.mem.mem_type == TTM_PL_VRAM &&
430 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
431 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
432 ctx.bytes_moved);
433 else
434 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
435
436 if (type == ttm_bo_type_kernel)
437 bo->tbo.priority = 1;
438
439 if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
440 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
441 struct dma_fence *fence;
442
443 r = amdgpu_fill_buffer(bo, 0, bo->tbo.resv, &fence);
444 if (unlikely(r))
445 goto fail_unreserve;
446
447 amdgpu_bo_fence(bo, fence, false);
448 dma_fence_put(bo->tbo.moving);
449 bo->tbo.moving = dma_fence_get(fence);
450 dma_fence_put(fence);
451 }
452 if (!resv)
453 amdgpu_bo_unreserve(bo);
454 *bo_ptr = bo;
455
456 trace_amdgpu_bo_create(bo);
457
458 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
459 if (type == ttm_bo_type_device)
460 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
461
462 return 0;
463
464fail_unreserve:
465 if (!resv)
466 ww_mutex_unlock(&bo->tbo.resv->lock);
467 amdgpu_bo_unref(&bo);
468 return r;
469}
470
471static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
472 unsigned long size, int byte_align,
473 struct amdgpu_bo *bo)
474{
475 int r;
476
477 if (bo->shadow)
478 return 0;
479
480 r = amdgpu_bo_do_create(adev, size, byte_align, AMDGPU_GEM_DOMAIN_GTT,
481 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
482 AMDGPU_GEM_CREATE_SHADOW,
483 ttm_bo_type_kernel,
484 bo->tbo.resv, &bo->shadow);
485 if (!r) {
486 bo->shadow->parent = amdgpu_bo_ref(bo);
487 mutex_lock(&adev->shadow_list_lock);
488 list_add_tail(&bo->shadow_list, &adev->shadow_list);
489 mutex_unlock(&adev->shadow_list_lock);
490 }
491
492 return r;
493}
494
495int amdgpu_bo_create(struct amdgpu_device *adev, unsigned long size,
496 int byte_align, u32 domain,
497 u64 flags, enum ttm_bo_type type,
498 struct reservation_object *resv,
499 struct amdgpu_bo **bo_ptr)
500{
501 uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
502 int r;
503
504 r = amdgpu_bo_do_create(adev, size, byte_align, domain,
505 parent_flags, type, resv, bo_ptr);
506 if (r)
507 return r;
508
509 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
510 if (!resv)
511 WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
512 NULL));
513
514 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
515
516 if (!resv)
517 reservation_object_unlock((*bo_ptr)->tbo.resv);
518
519 if (r)
520 amdgpu_bo_unref(bo_ptr);
521 }
522
523 return r;
524}
525
526int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
527 struct amdgpu_ring *ring,
528 struct amdgpu_bo *bo,
529 struct reservation_object *resv,
530 struct dma_fence **fence,
531 bool direct)
532
533{
534 struct amdgpu_bo *shadow = bo->shadow;
535 uint64_t bo_addr, shadow_addr;
536 int r;
537
538 if (!shadow)
539 return -EINVAL;
540
541 bo_addr = amdgpu_bo_gpu_offset(bo);
542 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
543
544 r = reservation_object_reserve_shared(bo->tbo.resv);
545 if (r)
546 goto err;
547
548 r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
549 amdgpu_bo_size(bo), resv, fence,
550 direct, false);
551 if (!r)
552 amdgpu_bo_fence(bo, *fence, true);
553
554err:
555 return r;
556}
557
558int amdgpu_bo_validate(struct amdgpu_bo *bo)
559{
560 struct ttm_operation_ctx ctx = { false, false };
561 uint32_t domain;
562 int r;
563
564 if (bo->pin_count)
565 return 0;
566
567 domain = bo->preferred_domains;
568
569retry:
570 amdgpu_ttm_placement_from_domain(bo, domain);
571 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
572 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
573 domain = bo->allowed_domains;
574 goto retry;
575 }
576
577 return r;
578}
579
580int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
581 struct amdgpu_ring *ring,
582 struct amdgpu_bo *bo,
583 struct reservation_object *resv,
584 struct dma_fence **fence,
585 bool direct)
586
587{
588 struct amdgpu_bo *shadow = bo->shadow;
589 uint64_t bo_addr, shadow_addr;
590 int r;
591
592 if (!shadow)
593 return -EINVAL;
594
595 bo_addr = amdgpu_bo_gpu_offset(bo);
596 shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
597
598 r = reservation_object_reserve_shared(bo->tbo.resv);
599 if (r)
600 goto err;
601
602 r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
603 amdgpu_bo_size(bo), resv, fence,
604 direct, false);
605 if (!r)
606 amdgpu_bo_fence(bo, *fence, true);
607
608err:
609 return r;
610}
611
612int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
613{
614 void *kptr;
615 long r;
616
617 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
618 return -EPERM;
619
620 kptr = amdgpu_bo_kptr(bo);
621 if (kptr) {
622 if (ptr)
623 *ptr = kptr;
624 return 0;
625 }
626
627 r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
628 MAX_SCHEDULE_TIMEOUT);
629 if (r < 0)
630 return r;
631
632 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
633 if (r)
634 return r;
635
636 if (ptr)
637 *ptr = amdgpu_bo_kptr(bo);
638
639 return 0;
640}
641
642void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
643{
644 bool is_iomem;
645
646 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
647}
648
649void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
650{
651 if (bo->kmap.bo)
652 ttm_bo_kunmap(&bo->kmap);
653}
654
655struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
656{
657 if (bo == NULL)
658 return NULL;
659
660 ttm_bo_reference(&bo->tbo);
661 return bo;
662}
663
664void amdgpu_bo_unref(struct amdgpu_bo **bo)
665{
666 struct ttm_buffer_object *tbo;
667
668 if ((*bo) == NULL)
669 return;
670
671 tbo = &((*bo)->tbo);
672 ttm_bo_unref(&tbo);
673 if (tbo == NULL)
674 *bo = NULL;
675}
676
677int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
678 u64 min_offset, u64 max_offset,
679 u64 *gpu_addr)
680{
681 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
682 struct ttm_operation_ctx ctx = { false, false };
683 int r, i;
684
685 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
686 return -EPERM;
687
688 if (WARN_ON_ONCE(min_offset > max_offset))
689 return -EINVAL;
690
691 /* A shared bo cannot be migrated to VRAM */
692 if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
693 return -EINVAL;
694
695 if (bo->pin_count) {
696 uint32_t mem_type = bo->tbo.mem.mem_type;
697
698 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
699 return -EINVAL;
700
701 bo->pin_count++;
702 if (gpu_addr)
703 *gpu_addr = amdgpu_bo_gpu_offset(bo);
704
705 if (max_offset != 0) {
706 u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
707 WARN_ON_ONCE(max_offset <
708 (amdgpu_bo_gpu_offset(bo) - domain_start));
709 }
710
711 return 0;
712 }
713
714 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
715 /* force to pin into visible video ram */
716 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
717 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
718 amdgpu_ttm_placement_from_domain(bo, domain);
719 for (i = 0; i < bo->placement.num_placement; i++) {
720 unsigned fpfn, lpfn;
721
722 fpfn = min_offset >> PAGE_SHIFT;
723 lpfn = max_offset >> PAGE_SHIFT;
724
725 if (fpfn > bo->placements[i].fpfn)
726 bo->placements[i].fpfn = fpfn;
727 if (!bo->placements[i].lpfn ||
728 (lpfn && lpfn < bo->placements[i].lpfn))
729 bo->placements[i].lpfn = lpfn;
730 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
731 }
732
733 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
734 if (unlikely(r)) {
735 dev_err(adev->dev, "%p pin failed\n", bo);
736 goto error;
737 }
738
739 r = amdgpu_ttm_alloc_gart(&bo->tbo);
740 if (unlikely(r)) {
741 dev_err(adev->dev, "%p bind failed\n", bo);
742 goto error;
743 }
744
745 bo->pin_count = 1;
746 if (gpu_addr != NULL)
747 *gpu_addr = amdgpu_bo_gpu_offset(bo);
748
749 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
750 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
751 adev->vram_pin_size += amdgpu_bo_size(bo);
752 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
753 adev->invisible_pin_size += amdgpu_bo_size(bo);
754 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
755 adev->gart_pin_size += amdgpu_bo_size(bo);
756 }
757
758error:
759 return r;
760}
761
762int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
763{
764 return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
765}
766
767int amdgpu_bo_unpin(struct amdgpu_bo *bo)
768{
769 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
770 struct ttm_operation_ctx ctx = { false, false };
771 int r, i;
772
773 if (!bo->pin_count) {
774 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
775 return 0;
776 }
777 bo->pin_count--;
778 if (bo->pin_count)
779 return 0;
780 for (i = 0; i < bo->placement.num_placement; i++) {
781 bo->placements[i].lpfn = 0;
782 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
783 }
784 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
785 if (unlikely(r)) {
786 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
787 goto error;
788 }
789
790 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
791 adev->vram_pin_size -= amdgpu_bo_size(bo);
792 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
793 adev->invisible_pin_size -= amdgpu_bo_size(bo);
794 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
795 adev->gart_pin_size -= amdgpu_bo_size(bo);
796 }
797
798error:
799 return r;
800}
801
802int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
803{
804 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
805 if (0 && (adev->flags & AMD_IS_APU)) {
806 /* Useless to evict on IGP chips */
807 return 0;
808 }
809 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
810}
811
812static const char *amdgpu_vram_names[] = {
813 "UNKNOWN",
814 "GDDR1",
815 "DDR2",
816 "GDDR3",
817 "GDDR4",
818 "GDDR5",
819 "HBM",
820 "DDR3",
821 "DDR4",
822};
823
824int amdgpu_bo_init(struct amdgpu_device *adev)
825{
826 /* reserve PAT memory space to WC for VRAM */
827 arch_io_reserve_memtype_wc(adev->gmc.aper_base,
828 adev->gmc.aper_size);
829
830 /* Add an MTRR for the VRAM */
831 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
832 adev->gmc.aper_size);
833 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
834 adev->gmc.mc_vram_size >> 20,
835 (unsigned long long)adev->gmc.aper_size >> 20);
836 DRM_INFO("RAM width %dbits %s\n",
837 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
838 return amdgpu_ttm_init(adev);
839}
840
841void amdgpu_bo_fini(struct amdgpu_device *adev)
842{
843 amdgpu_ttm_fini(adev);
844 arch_phys_wc_del(adev->gmc.vram_mtrr);
845 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
846}
847
848int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
849 struct vm_area_struct *vma)
850{
851 return ttm_fbdev_mmap(vma, &bo->tbo);
852}
853
854int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
855{
856 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
857
858 if (adev->family <= AMDGPU_FAMILY_CZ &&
859 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
860 return -EINVAL;
861
862 bo->tiling_flags = tiling_flags;
863 return 0;
864}
865
866void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
867{
868 lockdep_assert_held(&bo->tbo.resv->lock.base);
869
870 if (tiling_flags)
871 *tiling_flags = bo->tiling_flags;
872}
873
874int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
875 uint32_t metadata_size, uint64_t flags)
876{
877 void *buffer;
878
879 if (!metadata_size) {
880 if (bo->metadata_size) {
881 kfree(bo->metadata);
882 bo->metadata = NULL;
883 bo->metadata_size = 0;
884 }
885 return 0;
886 }
887
888 if (metadata == NULL)
889 return -EINVAL;
890
891 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
892 if (buffer == NULL)
893 return -ENOMEM;
894
895 kfree(bo->metadata);
896 bo->metadata_flags = flags;
897 bo->metadata = buffer;
898 bo->metadata_size = metadata_size;
899
900 return 0;
901}
902
903int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
904 size_t buffer_size, uint32_t *metadata_size,
905 uint64_t *flags)
906{
907 if (!buffer && !metadata_size)
908 return -EINVAL;
909
910 if (buffer) {
911 if (buffer_size < bo->metadata_size)
912 return -EINVAL;
913
914 if (bo->metadata_size)
915 memcpy(buffer, bo->metadata, bo->metadata_size);
916 }
917
918 if (metadata_size)
919 *metadata_size = bo->metadata_size;
920 if (flags)
921 *flags = bo->metadata_flags;
922
923 return 0;
924}
925
926void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
927 bool evict,
928 struct ttm_mem_reg *new_mem)
929{
930 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
931 struct amdgpu_bo *abo;
932 struct ttm_mem_reg *old_mem = &bo->mem;
933
934 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
935 return;
936
937 abo = ttm_to_amdgpu_bo(bo);
938 amdgpu_vm_bo_invalidate(adev, abo, evict);
939
940 amdgpu_bo_kunmap(abo);
941
942 /* remember the eviction */
943 if (evict)
944 atomic64_inc(&adev->num_evictions);
945
946 /* update statistics */
947 if (!new_mem)
948 return;
949
950 /* move_notify is called before move happens */
951 trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
952}
953
954int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
955{
956 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
957 struct ttm_operation_ctx ctx = { false, false };
958 struct amdgpu_bo *abo;
959 unsigned long offset, size;
960 int r;
961
962 if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
963 return 0;
964
965 abo = ttm_to_amdgpu_bo(bo);
966
967 /* Remember that this BO was accessed by the CPU */
968 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
969
970 if (bo->mem.mem_type != TTM_PL_VRAM)
971 return 0;
972
973 size = bo->mem.num_pages << PAGE_SHIFT;
974 offset = bo->mem.start << PAGE_SHIFT;
975 if ((offset + size) <= adev->gmc.visible_vram_size)
976 return 0;
977
978 /* Can't move a pinned BO to visible VRAM */
979 if (abo->pin_count > 0)
980 return -EINVAL;
981
982 /* hurrah the memory is not visible ! */
983 atomic64_inc(&adev->num_vram_cpu_page_faults);
984 amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
985 AMDGPU_GEM_DOMAIN_GTT);
986
987 /* Avoid costly evictions; only set GTT as a busy placement */
988 abo->placement.num_busy_placement = 1;
989 abo->placement.busy_placement = &abo->placements[1];
990
991 r = ttm_bo_validate(bo, &abo->placement, &ctx);
992 if (unlikely(r != 0))
993 return r;
994
995 offset = bo->mem.start << PAGE_SHIFT;
996 /* this should never happen */
997 if (bo->mem.mem_type == TTM_PL_VRAM &&
998 (offset + size) > adev->gmc.visible_vram_size)
999 return -EINVAL;
1000
1001 return 0;
1002}
1003
1004/**
1005 * amdgpu_bo_fence - add fence to buffer object
1006 *
1007 * @bo: buffer object in question
1008 * @fence: fence to add
1009 * @shared: true if fence should be added shared
1010 *
1011 */
1012void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1013 bool shared)
1014{
1015 struct reservation_object *resv = bo->tbo.resv;
1016
1017 if (shared)
1018 reservation_object_add_shared_fence(resv, fence);
1019 else
1020 reservation_object_add_excl_fence(resv, fence);
1021}
1022
1023/**
1024 * amdgpu_bo_gpu_offset - return GPU offset of bo
1025 * @bo: amdgpu object for which we query the offset
1026 *
1027 * Returns current GPU offset of the object.
1028 *
1029 * Note: object should either be pinned or reserved when calling this
1030 * function, it might be useful to add check for this for debugging.
1031 */
1032u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1033{
1034 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1035 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1036 !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1037 WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1038 !bo->pin_count);
1039 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1040 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1041 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1042
1043 return bo->tbo.offset;
1044}
1/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
33#include <linux/slab.h>
34#include <linux/dma-buf.h>
35
36#include <drm/amdgpu_drm.h>
37#include <drm/drm_cache.h>
38#include "amdgpu.h"
39#include "amdgpu_trace.h"
40#include "amdgpu_amdkfd.h"
41
42/**
43 * DOC: amdgpu_object
44 *
45 * This defines the interfaces to operate on an &amdgpu_bo buffer object which
46 * represents memory used by driver (VRAM, system memory, etc.). The driver
47 * provides DRM/GEM APIs to userspace. DRM/GEM APIs then use these interfaces
48 * to create/destroy/set buffer object which are then managed by the kernel TTM
49 * memory manager.
50 * The interfaces are also used internally by kernel clients, including gfx,
51 * uvd, etc. for kernel managed allocations used by the GPU.
52 *
53 */
54
55/**
56 * amdgpu_bo_subtract_pin_size - Remove BO from pin_size accounting
57 *
58 * @bo: &amdgpu_bo buffer object
59 *
60 * This function is called when a BO stops being pinned, and updates the
61 * &amdgpu_device pin_size values accordingly.
62 */
63static void amdgpu_bo_subtract_pin_size(struct amdgpu_bo *bo)
64{
65 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
66
67 if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
68 atomic64_sub(amdgpu_bo_size(bo), &adev->vram_pin_size);
69 atomic64_sub(amdgpu_vram_mgr_bo_visible_size(bo),
70 &adev->visible_pin_size);
71 } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
72 atomic64_sub(amdgpu_bo_size(bo), &adev->gart_pin_size);
73 }
74}
75
76static void amdgpu_bo_destroy(struct ttm_buffer_object *tbo)
77{
78 struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
79 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
80
81 if (bo->pin_count > 0)
82 amdgpu_bo_subtract_pin_size(bo);
83
84 amdgpu_bo_kunmap(bo);
85
86 if (bo->tbo.base.import_attach)
87 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg);
88 drm_gem_object_release(&bo->tbo.base);
89 /* in case amdgpu_device_recover_vram got NULL of bo->parent */
90 if (!list_empty(&bo->shadow_list)) {
91 mutex_lock(&adev->shadow_list_lock);
92 list_del_init(&bo->shadow_list);
93 mutex_unlock(&adev->shadow_list_lock);
94 }
95 amdgpu_bo_unref(&bo->parent);
96
97 kfree(bo->metadata);
98 kfree(bo);
99}
100
101/**
102 * amdgpu_bo_is_amdgpu_bo - check if the buffer object is an &amdgpu_bo
103 * @bo: buffer object to be checked
104 *
105 * Uses destroy function associated with the object to determine if this is
106 * an &amdgpu_bo.
107 *
108 * Returns:
109 * true if the object belongs to &amdgpu_bo, false if not.
110 */
111bool amdgpu_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
112{
113 if (bo->destroy == &amdgpu_bo_destroy)
114 return true;
115 return false;
116}
117
118/**
119 * amdgpu_bo_placement_from_domain - set buffer's placement
120 * @abo: &amdgpu_bo buffer object whose placement is to be set
121 * @domain: requested domain
122 *
123 * Sets buffer's placement according to requested domain and the buffer's
124 * flags.
125 */
126void amdgpu_bo_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
127{
128 struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
129 struct ttm_placement *placement = &abo->placement;
130 struct ttm_place *places = abo->placements;
131 u64 flags = abo->flags;
132 u32 c = 0;
133
134 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
135 unsigned visible_pfn = adev->gmc.visible_vram_size >> PAGE_SHIFT;
136
137 places[c].fpfn = 0;
138 places[c].lpfn = 0;
139 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
140 TTM_PL_FLAG_VRAM;
141
142 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
143 places[c].lpfn = visible_pfn;
144 else
145 places[c].flags |= TTM_PL_FLAG_TOPDOWN;
146
147 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
148 places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
149 c++;
150 }
151
152 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
153 places[c].fpfn = 0;
154 places[c].lpfn = 0;
155 places[c].flags = TTM_PL_FLAG_TT;
156 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
157 places[c].flags |= TTM_PL_FLAG_WC |
158 TTM_PL_FLAG_UNCACHED;
159 else
160 places[c].flags |= TTM_PL_FLAG_CACHED;
161 c++;
162 }
163
164 if (domain & AMDGPU_GEM_DOMAIN_CPU) {
165 places[c].fpfn = 0;
166 places[c].lpfn = 0;
167 places[c].flags = TTM_PL_FLAG_SYSTEM;
168 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
169 places[c].flags |= TTM_PL_FLAG_WC |
170 TTM_PL_FLAG_UNCACHED;
171 else
172 places[c].flags |= TTM_PL_FLAG_CACHED;
173 c++;
174 }
175
176 if (domain & AMDGPU_GEM_DOMAIN_GDS) {
177 places[c].fpfn = 0;
178 places[c].lpfn = 0;
179 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
180 c++;
181 }
182
183 if (domain & AMDGPU_GEM_DOMAIN_GWS) {
184 places[c].fpfn = 0;
185 places[c].lpfn = 0;
186 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
187 c++;
188 }
189
190 if (domain & AMDGPU_GEM_DOMAIN_OA) {
191 places[c].fpfn = 0;
192 places[c].lpfn = 0;
193 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
194 c++;
195 }
196
197 if (!c) {
198 places[c].fpfn = 0;
199 places[c].lpfn = 0;
200 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
201 c++;
202 }
203
204 BUG_ON(c >= AMDGPU_BO_MAX_PLACEMENTS);
205
206 placement->num_placement = c;
207 placement->placement = places;
208
209 placement->num_busy_placement = c;
210 placement->busy_placement = places;
211}
212
213/**
214 * amdgpu_bo_create_reserved - create reserved BO for kernel use
215 *
216 * @adev: amdgpu device object
217 * @size: size for the new BO
218 * @align: alignment for the new BO
219 * @domain: where to place it
220 * @bo_ptr: used to initialize BOs in structures
221 * @gpu_addr: GPU addr of the pinned BO
222 * @cpu_addr: optional CPU address mapping
223 *
224 * Allocates and pins a BO for kernel internal use, and returns it still
225 * reserved.
226 *
227 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
228 *
229 * Returns:
230 * 0 on success, negative error code otherwise.
231 */
232int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
233 unsigned long size, int align,
234 u32 domain, struct amdgpu_bo **bo_ptr,
235 u64 *gpu_addr, void **cpu_addr)
236{
237 struct amdgpu_bo_param bp;
238 bool free = false;
239 int r;
240
241 if (!size) {
242 amdgpu_bo_unref(bo_ptr);
243 return 0;
244 }
245
246 memset(&bp, 0, sizeof(bp));
247 bp.size = size;
248 bp.byte_align = align;
249 bp.domain = domain;
250 bp.flags = cpu_addr ? AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
251 : AMDGPU_GEM_CREATE_NO_CPU_ACCESS;
252 bp.flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
253 bp.type = ttm_bo_type_kernel;
254 bp.resv = NULL;
255
256 if (!*bo_ptr) {
257 r = amdgpu_bo_create(adev, &bp, bo_ptr);
258 if (r) {
259 dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
260 r);
261 return r;
262 }
263 free = true;
264 }
265
266 r = amdgpu_bo_reserve(*bo_ptr, false);
267 if (r) {
268 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
269 goto error_free;
270 }
271
272 r = amdgpu_bo_pin(*bo_ptr, domain);
273 if (r) {
274 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
275 goto error_unreserve;
276 }
277
278 r = amdgpu_ttm_alloc_gart(&(*bo_ptr)->tbo);
279 if (r) {
280 dev_err(adev->dev, "%p bind failed\n", *bo_ptr);
281 goto error_unpin;
282 }
283
284 if (gpu_addr)
285 *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
286
287 if (cpu_addr) {
288 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
289 if (r) {
290 dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
291 goto error_unpin;
292 }
293 }
294
295 return 0;
296
297error_unpin:
298 amdgpu_bo_unpin(*bo_ptr);
299error_unreserve:
300 amdgpu_bo_unreserve(*bo_ptr);
301
302error_free:
303 if (free)
304 amdgpu_bo_unref(bo_ptr);
305
306 return r;
307}
308
309/**
310 * amdgpu_bo_create_kernel - create BO for kernel use
311 *
312 * @adev: amdgpu device object
313 * @size: size for the new BO
314 * @align: alignment for the new BO
315 * @domain: where to place it
316 * @bo_ptr: used to initialize BOs in structures
317 * @gpu_addr: GPU addr of the pinned BO
318 * @cpu_addr: optional CPU address mapping
319 *
320 * Allocates and pins a BO for kernel internal use.
321 *
322 * Note: For bo_ptr new BO is only created if bo_ptr points to NULL.
323 *
324 * Returns:
325 * 0 on success, negative error code otherwise.
326 */
327int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
328 unsigned long size, int align,
329 u32 domain, struct amdgpu_bo **bo_ptr,
330 u64 *gpu_addr, void **cpu_addr)
331{
332 int r;
333
334 r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
335 gpu_addr, cpu_addr);
336
337 if (r)
338 return r;
339
340 if (*bo_ptr)
341 amdgpu_bo_unreserve(*bo_ptr);
342
343 return 0;
344}
345
346/**
347 * amdgpu_bo_create_kernel_at - create BO for kernel use at specific location
348 *
349 * @adev: amdgpu device object
350 * @offset: offset of the BO
351 * @size: size of the BO
352 * @domain: where to place it
353 * @bo_ptr: used to initialize BOs in structures
354 * @cpu_addr: optional CPU address mapping
355 *
356 * Creates a kernel BO at a specific offset in the address space of the domain.
357 *
358 * Returns:
359 * 0 on success, negative error code otherwise.
360 */
361int amdgpu_bo_create_kernel_at(struct amdgpu_device *adev,
362 uint64_t offset, uint64_t size, uint32_t domain,
363 struct amdgpu_bo **bo_ptr, void **cpu_addr)
364{
365 struct ttm_operation_ctx ctx = { false, false };
366 unsigned int i;
367 int r;
368
369 offset &= PAGE_MASK;
370 size = ALIGN(size, PAGE_SIZE);
371
372 r = amdgpu_bo_create_reserved(adev, size, PAGE_SIZE, domain, bo_ptr,
373 NULL, cpu_addr);
374 if (r)
375 return r;
376
377 /*
378 * Remove the original mem node and create a new one at the request
379 * position.
380 */
381 if (cpu_addr)
382 amdgpu_bo_kunmap(*bo_ptr);
383
384 ttm_bo_mem_put(&(*bo_ptr)->tbo, &(*bo_ptr)->tbo.mem);
385
386 for (i = 0; i < (*bo_ptr)->placement.num_placement; ++i) {
387 (*bo_ptr)->placements[i].fpfn = offset >> PAGE_SHIFT;
388 (*bo_ptr)->placements[i].lpfn = (offset + size) >> PAGE_SHIFT;
389 }
390 r = ttm_bo_mem_space(&(*bo_ptr)->tbo, &(*bo_ptr)->placement,
391 &(*bo_ptr)->tbo.mem, &ctx);
392 if (r)
393 goto error;
394
395 if (cpu_addr) {
396 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
397 if (r)
398 goto error;
399 }
400
401 amdgpu_bo_unreserve(*bo_ptr);
402 return 0;
403
404error:
405 amdgpu_bo_unreserve(*bo_ptr);
406 amdgpu_bo_unref(bo_ptr);
407 return r;
408}
409
410/**
411 * amdgpu_bo_free_kernel - free BO for kernel use
412 *
413 * @bo: amdgpu BO to free
414 * @gpu_addr: pointer to where the BO's GPU memory space address was stored
415 * @cpu_addr: pointer to where the BO's CPU memory space address was stored
416 *
417 * unmaps and unpin a BO for kernel internal use.
418 */
419void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
420 void **cpu_addr)
421{
422 if (*bo == NULL)
423 return;
424
425 if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
426 if (cpu_addr)
427 amdgpu_bo_kunmap(*bo);
428
429 amdgpu_bo_unpin(*bo);
430 amdgpu_bo_unreserve(*bo);
431 }
432 amdgpu_bo_unref(bo);
433
434 if (gpu_addr)
435 *gpu_addr = 0;
436
437 if (cpu_addr)
438 *cpu_addr = NULL;
439}
440
441/* Validate bo size is bit bigger then the request domain */
442static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
443 unsigned long size, u32 domain)
444{
445 struct ttm_mem_type_manager *man = NULL;
446
447 /*
448 * If GTT is part of requested domains the check must succeed to
449 * allow fall back to GTT
450 */
451 if (domain & AMDGPU_GEM_DOMAIN_GTT) {
452 man = &adev->mman.bdev.man[TTM_PL_TT];
453
454 if (size < (man->size << PAGE_SHIFT))
455 return true;
456 else
457 goto fail;
458 }
459
460 if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
461 man = &adev->mman.bdev.man[TTM_PL_VRAM];
462
463 if (size < (man->size << PAGE_SHIFT))
464 return true;
465 else
466 goto fail;
467 }
468
469
470 /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
471 return true;
472
473fail:
474 DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
475 man->size << PAGE_SHIFT);
476 return false;
477}
478
479bool amdgpu_bo_support_uswc(u64 bo_flags)
480{
481
482#ifdef CONFIG_X86_32
483 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
484 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
485 */
486 return false;
487#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
488 /* Don't try to enable write-combining when it can't work, or things
489 * may be slow
490 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
491 */
492
493#ifndef CONFIG_COMPILE_TEST
494#warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
495 thanks to write-combining
496#endif
497
498 if (bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
499 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
500 "better performance thanks to write-combining\n");
501 return false;
502#else
503 /* For architectures that don't support WC memory,
504 * mask out the WC flag from the BO
505 */
506 if (!drm_arch_can_wc_memory())
507 return false;
508
509 return true;
510#endif
511}
512
513static int amdgpu_bo_do_create(struct amdgpu_device *adev,
514 struct amdgpu_bo_param *bp,
515 struct amdgpu_bo **bo_ptr)
516{
517 struct ttm_operation_ctx ctx = {
518 .interruptible = (bp->type != ttm_bo_type_kernel),
519 .no_wait_gpu = bp->no_wait_gpu,
520 .resv = bp->resv,
521 .flags = bp->type != ttm_bo_type_kernel ?
522 TTM_OPT_FLAG_ALLOW_RES_EVICT : 0
523 };
524 struct amdgpu_bo *bo;
525 unsigned long page_align, size = bp->size;
526 size_t acc_size;
527 int r;
528
529 /* Note that GDS/GWS/OA allocates 1 page per byte/resource. */
530 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA)) {
531 /* GWS and OA don't need any alignment. */
532 page_align = bp->byte_align;
533 size <<= PAGE_SHIFT;
534 } else if (bp->domain & AMDGPU_GEM_DOMAIN_GDS) {
535 /* Both size and alignment must be a multiple of 4. */
536 page_align = ALIGN(bp->byte_align, 4);
537 size = ALIGN(size, 4) << PAGE_SHIFT;
538 } else {
539 /* Memory should be aligned at least to a page size. */
540 page_align = ALIGN(bp->byte_align, PAGE_SIZE) >> PAGE_SHIFT;
541 size = ALIGN(size, PAGE_SIZE);
542 }
543
544 if (!amdgpu_bo_validate_size(adev, size, bp->domain))
545 return -ENOMEM;
546
547 *bo_ptr = NULL;
548
549 acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
550 sizeof(struct amdgpu_bo));
551
552 bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
553 if (bo == NULL)
554 return -ENOMEM;
555 drm_gem_private_object_init(adev->ddev, &bo->tbo.base, size);
556 INIT_LIST_HEAD(&bo->shadow_list);
557 bo->vm_bo = NULL;
558 bo->preferred_domains = bp->preferred_domain ? bp->preferred_domain :
559 bp->domain;
560 bo->allowed_domains = bo->preferred_domains;
561 if (bp->type != ttm_bo_type_kernel &&
562 bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
563 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
564
565 bo->flags = bp->flags;
566
567 if (!amdgpu_bo_support_uswc(bo->flags))
568 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
569
570 bo->tbo.bdev = &adev->mman.bdev;
571 if (bp->domain & (AMDGPU_GEM_DOMAIN_GWS | AMDGPU_GEM_DOMAIN_OA |
572 AMDGPU_GEM_DOMAIN_GDS))
573 amdgpu_bo_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
574 else
575 amdgpu_bo_placement_from_domain(bo, bp->domain);
576 if (bp->type == ttm_bo_type_kernel)
577 bo->tbo.priority = 1;
578
579 r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, bp->type,
580 &bo->placement, page_align, &ctx, acc_size,
581 NULL, bp->resv, &amdgpu_bo_destroy);
582 if (unlikely(r != 0))
583 return r;
584
585 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
586 bo->tbo.mem.mem_type == TTM_PL_VRAM &&
587 bo->tbo.mem.start < adev->gmc.visible_vram_size >> PAGE_SHIFT)
588 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
589 ctx.bytes_moved);
590 else
591 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
592
593 if (bp->flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
594 bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
595 struct dma_fence *fence;
596
597 r = amdgpu_fill_buffer(bo, 0, bo->tbo.base.resv, &fence);
598 if (unlikely(r))
599 goto fail_unreserve;
600
601 amdgpu_bo_fence(bo, fence, false);
602 dma_fence_put(bo->tbo.moving);
603 bo->tbo.moving = dma_fence_get(fence);
604 dma_fence_put(fence);
605 }
606 if (!bp->resv)
607 amdgpu_bo_unreserve(bo);
608 *bo_ptr = bo;
609
610 trace_amdgpu_bo_create(bo);
611
612 /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
613 if (bp->type == ttm_bo_type_device)
614 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
615
616 return 0;
617
618fail_unreserve:
619 if (!bp->resv)
620 dma_resv_unlock(bo->tbo.base.resv);
621 amdgpu_bo_unref(&bo);
622 return r;
623}
624
625static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
626 unsigned long size,
627 struct amdgpu_bo *bo)
628{
629 struct amdgpu_bo_param bp;
630 int r;
631
632 if (bo->shadow)
633 return 0;
634
635 memset(&bp, 0, sizeof(bp));
636 bp.size = size;
637 bp.domain = AMDGPU_GEM_DOMAIN_GTT;
638 bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC |
639 AMDGPU_GEM_CREATE_SHADOW;
640 bp.type = ttm_bo_type_kernel;
641 bp.resv = bo->tbo.base.resv;
642
643 r = amdgpu_bo_do_create(adev, &bp, &bo->shadow);
644 if (!r) {
645 bo->shadow->parent = amdgpu_bo_ref(bo);
646 mutex_lock(&adev->shadow_list_lock);
647 list_add_tail(&bo->shadow->shadow_list, &adev->shadow_list);
648 mutex_unlock(&adev->shadow_list_lock);
649 }
650
651 return r;
652}
653
654/**
655 * amdgpu_bo_create - create an &amdgpu_bo buffer object
656 * @adev: amdgpu device object
657 * @bp: parameters to be used for the buffer object
658 * @bo_ptr: pointer to the buffer object pointer
659 *
660 * Creates an &amdgpu_bo buffer object; and if requested, also creates a
661 * shadow object.
662 * Shadow object is used to backup the original buffer object, and is always
663 * in GTT.
664 *
665 * Returns:
666 * 0 for success or a negative error code on failure.
667 */
668int amdgpu_bo_create(struct amdgpu_device *adev,
669 struct amdgpu_bo_param *bp,
670 struct amdgpu_bo **bo_ptr)
671{
672 u64 flags = bp->flags;
673 int r;
674
675 bp->flags = bp->flags & ~AMDGPU_GEM_CREATE_SHADOW;
676 r = amdgpu_bo_do_create(adev, bp, bo_ptr);
677 if (r)
678 return r;
679
680 if ((flags & AMDGPU_GEM_CREATE_SHADOW) && !(adev->flags & AMD_IS_APU)) {
681 if (!bp->resv)
682 WARN_ON(dma_resv_lock((*bo_ptr)->tbo.base.resv,
683 NULL));
684
685 r = amdgpu_bo_create_shadow(adev, bp->size, *bo_ptr);
686
687 if (!bp->resv)
688 dma_resv_unlock((*bo_ptr)->tbo.base.resv);
689
690 if (r)
691 amdgpu_bo_unref(bo_ptr);
692 }
693
694 return r;
695}
696
697/**
698 * amdgpu_bo_validate - validate an &amdgpu_bo buffer object
699 * @bo: pointer to the buffer object
700 *
701 * Sets placement according to domain; and changes placement and caching
702 * policy of the buffer object according to the placement.
703 * This is used for validating shadow bos. It calls ttm_bo_validate() to
704 * make sure the buffer is resident where it needs to be.
705 *
706 * Returns:
707 * 0 for success or a negative error code on failure.
708 */
709int amdgpu_bo_validate(struct amdgpu_bo *bo)
710{
711 struct ttm_operation_ctx ctx = { false, false };
712 uint32_t domain;
713 int r;
714
715 if (bo->pin_count)
716 return 0;
717
718 domain = bo->preferred_domains;
719
720retry:
721 amdgpu_bo_placement_from_domain(bo, domain);
722 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
723 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
724 domain = bo->allowed_domains;
725 goto retry;
726 }
727
728 return r;
729}
730
731/**
732 * amdgpu_bo_restore_shadow - restore an &amdgpu_bo shadow
733 *
734 * @shadow: &amdgpu_bo shadow to be restored
735 * @fence: dma_fence associated with the operation
736 *
737 * Copies a buffer object's shadow content back to the object.
738 * This is used for recovering a buffer from its shadow in case of a gpu
739 * reset where vram context may be lost.
740 *
741 * Returns:
742 * 0 for success or a negative error code on failure.
743 */
744int amdgpu_bo_restore_shadow(struct amdgpu_bo *shadow, struct dma_fence **fence)
745
746{
747 struct amdgpu_device *adev = amdgpu_ttm_adev(shadow->tbo.bdev);
748 struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
749 uint64_t shadow_addr, parent_addr;
750
751 shadow_addr = amdgpu_bo_gpu_offset(shadow);
752 parent_addr = amdgpu_bo_gpu_offset(shadow->parent);
753
754 return amdgpu_copy_buffer(ring, shadow_addr, parent_addr,
755 amdgpu_bo_size(shadow), NULL, fence,
756 true, false, false);
757}
758
759/**
760 * amdgpu_bo_kmap - map an &amdgpu_bo buffer object
761 * @bo: &amdgpu_bo buffer object to be mapped
762 * @ptr: kernel virtual address to be returned
763 *
764 * Calls ttm_bo_kmap() to set up the kernel virtual mapping; calls
765 * amdgpu_bo_kptr() to get the kernel virtual address.
766 *
767 * Returns:
768 * 0 for success or a negative error code on failure.
769 */
770int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
771{
772 void *kptr;
773 long r;
774
775 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
776 return -EPERM;
777
778 kptr = amdgpu_bo_kptr(bo);
779 if (kptr) {
780 if (ptr)
781 *ptr = kptr;
782 return 0;
783 }
784
785 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv, false, false,
786 MAX_SCHEDULE_TIMEOUT);
787 if (r < 0)
788 return r;
789
790 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
791 if (r)
792 return r;
793
794 if (ptr)
795 *ptr = amdgpu_bo_kptr(bo);
796
797 return 0;
798}
799
800/**
801 * amdgpu_bo_kptr - returns a kernel virtual address of the buffer object
802 * @bo: &amdgpu_bo buffer object
803 *
804 * Calls ttm_kmap_obj_virtual() to get the kernel virtual address
805 *
806 * Returns:
807 * the virtual address of a buffer object area.
808 */
809void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
810{
811 bool is_iomem;
812
813 return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
814}
815
816/**
817 * amdgpu_bo_kunmap - unmap an &amdgpu_bo buffer object
818 * @bo: &amdgpu_bo buffer object to be unmapped
819 *
820 * Unmaps a kernel map set up by amdgpu_bo_kmap().
821 */
822void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
823{
824 if (bo->kmap.bo)
825 ttm_bo_kunmap(&bo->kmap);
826}
827
828/**
829 * amdgpu_bo_ref - reference an &amdgpu_bo buffer object
830 * @bo: &amdgpu_bo buffer object
831 *
832 * References the contained &ttm_buffer_object.
833 *
834 * Returns:
835 * a refcounted pointer to the &amdgpu_bo buffer object.
836 */
837struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
838{
839 if (bo == NULL)
840 return NULL;
841
842 ttm_bo_get(&bo->tbo);
843 return bo;
844}
845
846/**
847 * amdgpu_bo_unref - unreference an &amdgpu_bo buffer object
848 * @bo: &amdgpu_bo buffer object
849 *
850 * Unreferences the contained &ttm_buffer_object and clear the pointer
851 */
852void amdgpu_bo_unref(struct amdgpu_bo **bo)
853{
854 struct ttm_buffer_object *tbo;
855
856 if ((*bo) == NULL)
857 return;
858
859 tbo = &((*bo)->tbo);
860 ttm_bo_put(tbo);
861 *bo = NULL;
862}
863
864/**
865 * amdgpu_bo_pin_restricted - pin an &amdgpu_bo buffer object
866 * @bo: &amdgpu_bo buffer object to be pinned
867 * @domain: domain to be pinned to
868 * @min_offset: the start of requested address range
869 * @max_offset: the end of requested address range
870 *
871 * Pins the buffer object according to requested domain and address range. If
872 * the memory is unbound gart memory, binds the pages into gart table. Adjusts
873 * pin_count and pin_size accordingly.
874 *
875 * Pinning means to lock pages in memory along with keeping them at a fixed
876 * offset. It is required when a buffer can not be moved, for example, when
877 * a display buffer is being scanned out.
878 *
879 * Compared with amdgpu_bo_pin(), this function gives more flexibility on
880 * where to pin a buffer if there are specific restrictions on where a buffer
881 * must be located.
882 *
883 * Returns:
884 * 0 for success or a negative error code on failure.
885 */
886int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
887 u64 min_offset, u64 max_offset)
888{
889 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
890 struct ttm_operation_ctx ctx = { false, false };
891 int r, i;
892
893 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
894 return -EPERM;
895
896 if (WARN_ON_ONCE(min_offset > max_offset))
897 return -EINVAL;
898
899 /* A shared bo cannot be migrated to VRAM */
900 if (bo->prime_shared_count) {
901 if (domain & AMDGPU_GEM_DOMAIN_GTT)
902 domain = AMDGPU_GEM_DOMAIN_GTT;
903 else
904 return -EINVAL;
905 }
906
907 /* This assumes only APU display buffers are pinned with (VRAM|GTT).
908 * See function amdgpu_display_supported_domains()
909 */
910 domain = amdgpu_bo_get_preferred_pin_domain(adev, domain);
911
912 if (bo->pin_count) {
913 uint32_t mem_type = bo->tbo.mem.mem_type;
914
915 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
916 return -EINVAL;
917
918 bo->pin_count++;
919
920 if (max_offset != 0) {
921 u64 domain_start = amdgpu_ttm_domain_start(adev,
922 mem_type);
923 WARN_ON_ONCE(max_offset <
924 (amdgpu_bo_gpu_offset(bo) - domain_start));
925 }
926
927 return 0;
928 }
929
930 if (bo->tbo.base.import_attach)
931 dma_buf_pin(bo->tbo.base.import_attach);
932
933 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
934 /* force to pin into visible video ram */
935 if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
936 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
937 amdgpu_bo_placement_from_domain(bo, domain);
938 for (i = 0; i < bo->placement.num_placement; i++) {
939 unsigned fpfn, lpfn;
940
941 fpfn = min_offset >> PAGE_SHIFT;
942 lpfn = max_offset >> PAGE_SHIFT;
943
944 if (fpfn > bo->placements[i].fpfn)
945 bo->placements[i].fpfn = fpfn;
946 if (!bo->placements[i].lpfn ||
947 (lpfn && lpfn < bo->placements[i].lpfn))
948 bo->placements[i].lpfn = lpfn;
949 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
950 }
951
952 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
953 if (unlikely(r)) {
954 dev_err(adev->dev, "%p pin failed\n", bo);
955 goto error;
956 }
957
958 bo->pin_count = 1;
959
960 domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
961 if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
962 atomic64_add(amdgpu_bo_size(bo), &adev->vram_pin_size);
963 atomic64_add(amdgpu_vram_mgr_bo_visible_size(bo),
964 &adev->visible_pin_size);
965 } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
966 atomic64_add(amdgpu_bo_size(bo), &adev->gart_pin_size);
967 }
968
969error:
970 return r;
971}
972
973/**
974 * amdgpu_bo_pin - pin an &amdgpu_bo buffer object
975 * @bo: &amdgpu_bo buffer object to be pinned
976 * @domain: domain to be pinned to
977 *
978 * A simple wrapper to amdgpu_bo_pin_restricted().
979 * Provides a simpler API for buffers that do not have any strict restrictions
980 * on where a buffer must be located.
981 *
982 * Returns:
983 * 0 for success or a negative error code on failure.
984 */
985int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain)
986{
987 return amdgpu_bo_pin_restricted(bo, domain, 0, 0);
988}
989
990/**
991 * amdgpu_bo_unpin - unpin an &amdgpu_bo buffer object
992 * @bo: &amdgpu_bo buffer object to be unpinned
993 *
994 * Decreases the pin_count, and clears the flags if pin_count reaches 0.
995 * Changes placement and pin size accordingly.
996 *
997 * Returns:
998 * 0 for success or a negative error code on failure.
999 */
1000int amdgpu_bo_unpin(struct amdgpu_bo *bo)
1001{
1002 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1003 struct ttm_operation_ctx ctx = { false, false };
1004 int r, i;
1005
1006 if (WARN_ON_ONCE(!bo->pin_count)) {
1007 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
1008 return 0;
1009 }
1010 bo->pin_count--;
1011 if (bo->pin_count)
1012 return 0;
1013
1014 amdgpu_bo_subtract_pin_size(bo);
1015
1016 if (bo->tbo.base.import_attach)
1017 dma_buf_unpin(bo->tbo.base.import_attach);
1018
1019 for (i = 0; i < bo->placement.num_placement; i++) {
1020 bo->placements[i].lpfn = 0;
1021 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
1022 }
1023 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
1024 if (unlikely(r))
1025 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
1026
1027 return r;
1028}
1029
1030/**
1031 * amdgpu_bo_evict_vram - evict VRAM buffers
1032 * @adev: amdgpu device object
1033 *
1034 * Evicts all VRAM buffers on the lru list of the memory type.
1035 * Mainly used for evicting vram at suspend time.
1036 *
1037 * Returns:
1038 * 0 for success or a negative error code on failure.
1039 */
1040int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
1041{
1042 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
1043#ifndef CONFIG_HIBERNATION
1044 if (adev->flags & AMD_IS_APU) {
1045 /* Useless to evict on IGP chips */
1046 return 0;
1047 }
1048#endif
1049 return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
1050}
1051
1052static const char *amdgpu_vram_names[] = {
1053 "UNKNOWN",
1054 "GDDR1",
1055 "DDR2",
1056 "GDDR3",
1057 "GDDR4",
1058 "GDDR5",
1059 "HBM",
1060 "DDR3",
1061 "DDR4",
1062 "GDDR6",
1063};
1064
1065/**
1066 * amdgpu_bo_init - initialize memory manager
1067 * @adev: amdgpu device object
1068 *
1069 * Calls amdgpu_ttm_init() to initialize amdgpu memory manager.
1070 *
1071 * Returns:
1072 * 0 for success or a negative error code on failure.
1073 */
1074int amdgpu_bo_init(struct amdgpu_device *adev)
1075{
1076 /* reserve PAT memory space to WC for VRAM */
1077 arch_io_reserve_memtype_wc(adev->gmc.aper_base,
1078 adev->gmc.aper_size);
1079
1080 /* Add an MTRR for the VRAM */
1081 adev->gmc.vram_mtrr = arch_phys_wc_add(adev->gmc.aper_base,
1082 adev->gmc.aper_size);
1083 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
1084 adev->gmc.mc_vram_size >> 20,
1085 (unsigned long long)adev->gmc.aper_size >> 20);
1086 DRM_INFO("RAM width %dbits %s\n",
1087 adev->gmc.vram_width, amdgpu_vram_names[adev->gmc.vram_type]);
1088 return amdgpu_ttm_init(adev);
1089}
1090
1091/**
1092 * amdgpu_bo_late_init - late init
1093 * @adev: amdgpu device object
1094 *
1095 * Calls amdgpu_ttm_late_init() to free resources used earlier during
1096 * initialization.
1097 *
1098 * Returns:
1099 * 0 for success or a negative error code on failure.
1100 */
1101int amdgpu_bo_late_init(struct amdgpu_device *adev)
1102{
1103 amdgpu_ttm_late_init(adev);
1104
1105 return 0;
1106}
1107
1108/**
1109 * amdgpu_bo_fini - tear down memory manager
1110 * @adev: amdgpu device object
1111 *
1112 * Reverses amdgpu_bo_init() to tear down memory manager.
1113 */
1114void amdgpu_bo_fini(struct amdgpu_device *adev)
1115{
1116 amdgpu_ttm_fini(adev);
1117 arch_phys_wc_del(adev->gmc.vram_mtrr);
1118 arch_io_free_memtype_wc(adev->gmc.aper_base, adev->gmc.aper_size);
1119}
1120
1121/**
1122 * amdgpu_bo_fbdev_mmap - mmap fbdev memory
1123 * @bo: &amdgpu_bo buffer object
1124 * @vma: vma as input from the fbdev mmap method
1125 *
1126 * Calls ttm_fbdev_mmap() to mmap fbdev memory if it is backed by a bo.
1127 *
1128 * Returns:
1129 * 0 for success or a negative error code on failure.
1130 */
1131int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
1132 struct vm_area_struct *vma)
1133{
1134 if (vma->vm_pgoff != 0)
1135 return -EACCES;
1136
1137 return ttm_bo_mmap_obj(vma, &bo->tbo);
1138}
1139
1140/**
1141 * amdgpu_bo_set_tiling_flags - set tiling flags
1142 * @bo: &amdgpu_bo buffer object
1143 * @tiling_flags: new flags
1144 *
1145 * Sets buffer object's tiling flags with the new one. Used by GEM ioctl or
1146 * kernel driver to set the tiling flags on a buffer.
1147 *
1148 * Returns:
1149 * 0 for success or a negative error code on failure.
1150 */
1151int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
1152{
1153 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1154
1155 if (adev->family <= AMDGPU_FAMILY_CZ &&
1156 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
1157 return -EINVAL;
1158
1159 bo->tiling_flags = tiling_flags;
1160 return 0;
1161}
1162
1163/**
1164 * amdgpu_bo_get_tiling_flags - get tiling flags
1165 * @bo: &amdgpu_bo buffer object
1166 * @tiling_flags: returned flags
1167 *
1168 * Gets buffer object's tiling flags. Used by GEM ioctl or kernel driver to
1169 * set the tiling flags on a buffer.
1170 */
1171void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
1172{
1173 dma_resv_assert_held(bo->tbo.base.resv);
1174
1175 if (tiling_flags)
1176 *tiling_flags = bo->tiling_flags;
1177}
1178
1179/**
1180 * amdgpu_bo_set_metadata - set metadata
1181 * @bo: &amdgpu_bo buffer object
1182 * @metadata: new metadata
1183 * @metadata_size: size of the new metadata
1184 * @flags: flags of the new metadata
1185 *
1186 * Sets buffer object's metadata, its size and flags.
1187 * Used via GEM ioctl.
1188 *
1189 * Returns:
1190 * 0 for success or a negative error code on failure.
1191 */
1192int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
1193 uint32_t metadata_size, uint64_t flags)
1194{
1195 void *buffer;
1196
1197 if (!metadata_size) {
1198 if (bo->metadata_size) {
1199 kfree(bo->metadata);
1200 bo->metadata = NULL;
1201 bo->metadata_size = 0;
1202 }
1203 return 0;
1204 }
1205
1206 if (metadata == NULL)
1207 return -EINVAL;
1208
1209 buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
1210 if (buffer == NULL)
1211 return -ENOMEM;
1212
1213 kfree(bo->metadata);
1214 bo->metadata_flags = flags;
1215 bo->metadata = buffer;
1216 bo->metadata_size = metadata_size;
1217
1218 return 0;
1219}
1220
1221/**
1222 * amdgpu_bo_get_metadata - get metadata
1223 * @bo: &amdgpu_bo buffer object
1224 * @buffer: returned metadata
1225 * @buffer_size: size of the buffer
1226 * @metadata_size: size of the returned metadata
1227 * @flags: flags of the returned metadata
1228 *
1229 * Gets buffer object's metadata, its size and flags. buffer_size shall not be
1230 * less than metadata_size.
1231 * Used via GEM ioctl.
1232 *
1233 * Returns:
1234 * 0 for success or a negative error code on failure.
1235 */
1236int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
1237 size_t buffer_size, uint32_t *metadata_size,
1238 uint64_t *flags)
1239{
1240 if (!buffer && !metadata_size)
1241 return -EINVAL;
1242
1243 if (buffer) {
1244 if (buffer_size < bo->metadata_size)
1245 return -EINVAL;
1246
1247 if (bo->metadata_size)
1248 memcpy(buffer, bo->metadata, bo->metadata_size);
1249 }
1250
1251 if (metadata_size)
1252 *metadata_size = bo->metadata_size;
1253 if (flags)
1254 *flags = bo->metadata_flags;
1255
1256 return 0;
1257}
1258
1259/**
1260 * amdgpu_bo_move_notify - notification about a memory move
1261 * @bo: pointer to a buffer object
1262 * @evict: if this move is evicting the buffer from the graphics address space
1263 * @new_mem: new information of the bufer object
1264 *
1265 * Marks the corresponding &amdgpu_bo buffer object as invalid, also performs
1266 * bookkeeping.
1267 * TTM driver callback which is called when ttm moves a buffer.
1268 */
1269void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
1270 bool evict,
1271 struct ttm_mem_reg *new_mem)
1272{
1273 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1274 struct amdgpu_bo *abo;
1275 struct ttm_mem_reg *old_mem = &bo->mem;
1276
1277 if (!amdgpu_bo_is_amdgpu_bo(bo))
1278 return;
1279
1280 abo = ttm_to_amdgpu_bo(bo);
1281 amdgpu_vm_bo_invalidate(adev, abo, evict);
1282
1283 amdgpu_bo_kunmap(abo);
1284
1285 if (abo->tbo.base.dma_buf && !abo->tbo.base.import_attach &&
1286 bo->mem.mem_type != TTM_PL_SYSTEM)
1287 dma_buf_move_notify(abo->tbo.base.dma_buf);
1288
1289 /* remember the eviction */
1290 if (evict)
1291 atomic64_inc(&adev->num_evictions);
1292
1293 /* update statistics */
1294 if (!new_mem)
1295 return;
1296
1297 /* move_notify is called before move happens */
1298 trace_amdgpu_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
1299}
1300
1301/**
1302 * amdgpu_bo_move_notify - notification about a BO being released
1303 * @bo: pointer to a buffer object
1304 *
1305 * Wipes VRAM buffers whose contents should not be leaked before the
1306 * memory is released.
1307 */
1308void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
1309{
1310 struct dma_fence *fence = NULL;
1311 struct amdgpu_bo *abo;
1312 int r;
1313
1314 if (!amdgpu_bo_is_amdgpu_bo(bo))
1315 return;
1316
1317 abo = ttm_to_amdgpu_bo(bo);
1318
1319 if (abo->kfd_bo)
1320 amdgpu_amdkfd_unreserve_memory_limit(abo);
1321
1322 /* We only remove the fence if the resv has individualized. */
1323 WARN_ON_ONCE(bo->type == ttm_bo_type_kernel
1324 && bo->base.resv != &bo->base._resv);
1325 if (bo->base.resv == &bo->base._resv)
1326 amdgpu_amdkfd_remove_fence_on_pt_pd_bos(abo);
1327
1328 if (bo->mem.mem_type != TTM_PL_VRAM || !bo->mem.mm_node ||
1329 !(abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE))
1330 return;
1331
1332 dma_resv_lock(bo->base.resv, NULL);
1333
1334 r = amdgpu_fill_buffer(abo, AMDGPU_POISON, bo->base.resv, &fence);
1335 if (!WARN_ON(r)) {
1336 amdgpu_bo_fence(abo, fence, false);
1337 dma_fence_put(fence);
1338 }
1339
1340 dma_resv_unlock(bo->base.resv);
1341}
1342
1343/**
1344 * amdgpu_bo_fault_reserve_notify - notification about a memory fault
1345 * @bo: pointer to a buffer object
1346 *
1347 * Notifies the driver we are taking a fault on this BO and have reserved it,
1348 * also performs bookkeeping.
1349 * TTM driver callback for dealing with vm faults.
1350 *
1351 * Returns:
1352 * 0 for success or a negative error code on failure.
1353 */
1354int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
1355{
1356 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
1357 struct ttm_operation_ctx ctx = { false, false };
1358 struct amdgpu_bo *abo;
1359 unsigned long offset, size;
1360 int r;
1361
1362 if (!amdgpu_bo_is_amdgpu_bo(bo))
1363 return 0;
1364
1365 abo = ttm_to_amdgpu_bo(bo);
1366
1367 /* Remember that this BO was accessed by the CPU */
1368 abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
1369
1370 if (bo->mem.mem_type != TTM_PL_VRAM)
1371 return 0;
1372
1373 size = bo->mem.num_pages << PAGE_SHIFT;
1374 offset = bo->mem.start << PAGE_SHIFT;
1375 if ((offset + size) <= adev->gmc.visible_vram_size)
1376 return 0;
1377
1378 /* Can't move a pinned BO to visible VRAM */
1379 if (abo->pin_count > 0)
1380 return -EINVAL;
1381
1382 /* hurrah the memory is not visible ! */
1383 atomic64_inc(&adev->num_vram_cpu_page_faults);
1384 amdgpu_bo_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
1385 AMDGPU_GEM_DOMAIN_GTT);
1386
1387 /* Avoid costly evictions; only set GTT as a busy placement */
1388 abo->placement.num_busy_placement = 1;
1389 abo->placement.busy_placement = &abo->placements[1];
1390
1391 r = ttm_bo_validate(bo, &abo->placement, &ctx);
1392 if (unlikely(r != 0))
1393 return r;
1394
1395 offset = bo->mem.start << PAGE_SHIFT;
1396 /* this should never happen */
1397 if (bo->mem.mem_type == TTM_PL_VRAM &&
1398 (offset + size) > adev->gmc.visible_vram_size)
1399 return -EINVAL;
1400
1401 return 0;
1402}
1403
1404/**
1405 * amdgpu_bo_fence - add fence to buffer object
1406 *
1407 * @bo: buffer object in question
1408 * @fence: fence to add
1409 * @shared: true if fence should be added shared
1410 *
1411 */
1412void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1413 bool shared)
1414{
1415 struct dma_resv *resv = bo->tbo.base.resv;
1416
1417 if (shared)
1418 dma_resv_add_shared_fence(resv, fence);
1419 else
1420 dma_resv_add_excl_fence(resv, fence);
1421}
1422
1423/**
1424 * amdgpu_bo_sync_wait_resv - Wait for BO reservation fences
1425 *
1426 * @adev: amdgpu device pointer
1427 * @resv: reservation object to sync to
1428 * @sync_mode: synchronization mode
1429 * @owner: fence owner
1430 * @intr: Whether the wait is interruptible
1431 *
1432 * Extract the fences from the reservation object and waits for them to finish.
1433 *
1434 * Returns:
1435 * 0 on success, errno otherwise.
1436 */
1437int amdgpu_bo_sync_wait_resv(struct amdgpu_device *adev, struct dma_resv *resv,
1438 enum amdgpu_sync_mode sync_mode, void *owner,
1439 bool intr)
1440{
1441 struct amdgpu_sync sync;
1442 int r;
1443
1444 amdgpu_sync_create(&sync);
1445 amdgpu_sync_resv(adev, &sync, resv, sync_mode, owner);
1446 r = amdgpu_sync_wait(&sync, intr);
1447 amdgpu_sync_free(&sync);
1448 return r;
1449}
1450
1451/**
1452 * amdgpu_bo_sync_wait - Wrapper for amdgpu_bo_sync_wait_resv
1453 * @bo: buffer object to wait for
1454 * @owner: fence owner
1455 * @intr: Whether the wait is interruptible
1456 *
1457 * Wrapper to wait for fences in a BO.
1458 * Returns:
1459 * 0 on success, errno otherwise.
1460 */
1461int amdgpu_bo_sync_wait(struct amdgpu_bo *bo, void *owner, bool intr)
1462{
1463 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1464
1465 return amdgpu_bo_sync_wait_resv(adev, bo->tbo.base.resv,
1466 AMDGPU_SYNC_NE_OWNER, owner, intr);
1467}
1468
1469/**
1470 * amdgpu_bo_gpu_offset - return GPU offset of bo
1471 * @bo: amdgpu object for which we query the offset
1472 *
1473 * Note: object should either be pinned or reserved when calling this
1474 * function, it might be useful to add check for this for debugging.
1475 *
1476 * Returns:
1477 * current GPU offset of the object.
1478 */
1479u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1480{
1481 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1482 WARN_ON_ONCE(!dma_resv_is_locked(bo->tbo.base.resv) &&
1483 !bo->pin_count && bo->tbo.type != ttm_bo_type_kernel);
1484 WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1485 WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1486 !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1487
1488 return amdgpu_bo_gpu_offset_no_check(bo);
1489}
1490
1491/**
1492 * amdgpu_bo_gpu_offset_no_check - return GPU offset of bo
1493 * @bo: amdgpu object for which we query the offset
1494 *
1495 * Returns:
1496 * current GPU offset of the object without raising warnings.
1497 */
1498u64 amdgpu_bo_gpu_offset_no_check(struct amdgpu_bo *bo)
1499{
1500 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
1501 uint64_t offset;
1502
1503 offset = (bo->tbo.mem.start << PAGE_SHIFT) +
1504 amdgpu_ttm_domain_start(adev, bo->tbo.mem.mem_type);
1505
1506 return amdgpu_gmc_sign_extend(offset);
1507}
1508
1509/**
1510 * amdgpu_bo_get_preferred_pin_domain - get preferred domain for scanout
1511 * @adev: amdgpu device object
1512 * @domain: allowed :ref:`memory domains <amdgpu_memory_domains>`
1513 *
1514 * Returns:
1515 * Which of the allowed domains is preferred for pinning the BO for scanout.
1516 */
1517uint32_t amdgpu_bo_get_preferred_pin_domain(struct amdgpu_device *adev,
1518 uint32_t domain)
1519{
1520 if (domain == (AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT)) {
1521 domain = AMDGPU_GEM_DOMAIN_VRAM;
1522 if (adev->gmc.real_vram_size <= AMDGPU_SG_THRESHOLD)
1523 domain = AMDGPU_GEM_DOMAIN_GTT;
1524 }
1525 return domain;
1526}