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1#include <linux/clocksource.h>
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/export.h>
5#include <linux/delay.h>
6#include <linux/errno.h>
7#include <linux/i8253.h>
8#include <linux/slab.h>
9#include <linux/hpet.h>
10#include <linux/init.h>
11#include <linux/cpu.h>
12#include <linux/pm.h>
13#include <linux/io.h>
14
15#include <asm/cpufeature.h>
16#include <asm/irqdomain.h>
17#include <asm/fixmap.h>
18#include <asm/hpet.h>
19#include <asm/time.h>
20
21#define HPET_MASK CLOCKSOURCE_MASK(32)
22
23/* FSEC = 10^-15
24 NSEC = 10^-9 */
25#define FSEC_PER_NSEC 1000000L
26
27#define HPET_DEV_USED_BIT 2
28#define HPET_DEV_USED (1 << HPET_DEV_USED_BIT)
29#define HPET_DEV_VALID 0x8
30#define HPET_DEV_FSB_CAP 0x1000
31#define HPET_DEV_PERI_CAP 0x2000
32
33#define HPET_MIN_CYCLES 128
34#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
35
36/*
37 * HPET address is set in acpi/boot.c, when an ACPI entry exists
38 */
39unsigned long hpet_address;
40u8 hpet_blockid; /* OS timer block num */
41bool hpet_msi_disable;
42
43#ifdef CONFIG_PCI_MSI
44static unsigned int hpet_num_timers;
45#endif
46static void __iomem *hpet_virt_address;
47
48struct hpet_dev {
49 struct clock_event_device evt;
50 unsigned int num;
51 int cpu;
52 unsigned int irq;
53 unsigned int flags;
54 char name[10];
55};
56
57static inline struct hpet_dev *EVT_TO_HPET_DEV(struct clock_event_device *evtdev)
58{
59 return container_of(evtdev, struct hpet_dev, evt);
60}
61
62inline unsigned int hpet_readl(unsigned int a)
63{
64 return readl(hpet_virt_address + a);
65}
66
67static inline void hpet_writel(unsigned int d, unsigned int a)
68{
69 writel(d, hpet_virt_address + a);
70}
71
72#ifdef CONFIG_X86_64
73#include <asm/pgtable.h>
74#endif
75
76static inline void hpet_set_mapping(void)
77{
78 hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
79}
80
81static inline void hpet_clear_mapping(void)
82{
83 iounmap(hpet_virt_address);
84 hpet_virt_address = NULL;
85}
86
87/*
88 * HPET command line enable / disable
89 */
90bool boot_hpet_disable;
91bool hpet_force_user;
92static bool hpet_verbose;
93
94static int __init hpet_setup(char *str)
95{
96 while (str) {
97 char *next = strchr(str, ',');
98
99 if (next)
100 *next++ = 0;
101 if (!strncmp("disable", str, 7))
102 boot_hpet_disable = true;
103 if (!strncmp("force", str, 5))
104 hpet_force_user = true;
105 if (!strncmp("verbose", str, 7))
106 hpet_verbose = true;
107 str = next;
108 }
109 return 1;
110}
111__setup("hpet=", hpet_setup);
112
113static int __init disable_hpet(char *str)
114{
115 boot_hpet_disable = true;
116 return 1;
117}
118__setup("nohpet", disable_hpet);
119
120static inline int is_hpet_capable(void)
121{
122 return !boot_hpet_disable && hpet_address;
123}
124
125/*
126 * HPET timer interrupt enable / disable
127 */
128static bool hpet_legacy_int_enabled;
129
130/**
131 * is_hpet_enabled - check whether the hpet timer interrupt is enabled
132 */
133int is_hpet_enabled(void)
134{
135 return is_hpet_capable() && hpet_legacy_int_enabled;
136}
137EXPORT_SYMBOL_GPL(is_hpet_enabled);
138
139static void _hpet_print_config(const char *function, int line)
140{
141 u32 i, timers, l, h;
142 printk(KERN_INFO "hpet: %s(%d):\n", function, line);
143 l = hpet_readl(HPET_ID);
144 h = hpet_readl(HPET_PERIOD);
145 timers = ((l & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
146 printk(KERN_INFO "hpet: ID: 0x%x, PERIOD: 0x%x\n", l, h);
147 l = hpet_readl(HPET_CFG);
148 h = hpet_readl(HPET_STATUS);
149 printk(KERN_INFO "hpet: CFG: 0x%x, STATUS: 0x%x\n", l, h);
150 l = hpet_readl(HPET_COUNTER);
151 h = hpet_readl(HPET_COUNTER+4);
152 printk(KERN_INFO "hpet: COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
153
154 for (i = 0; i < timers; i++) {
155 l = hpet_readl(HPET_Tn_CFG(i));
156 h = hpet_readl(HPET_Tn_CFG(i)+4);
157 printk(KERN_INFO "hpet: T%d: CFG_l: 0x%x, CFG_h: 0x%x\n",
158 i, l, h);
159 l = hpet_readl(HPET_Tn_CMP(i));
160 h = hpet_readl(HPET_Tn_CMP(i)+4);
161 printk(KERN_INFO "hpet: T%d: CMP_l: 0x%x, CMP_h: 0x%x\n",
162 i, l, h);
163 l = hpet_readl(HPET_Tn_ROUTE(i));
164 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
165 printk(KERN_INFO "hpet: T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n",
166 i, l, h);
167 }
168}
169
170#define hpet_print_config() \
171do { \
172 if (hpet_verbose) \
173 _hpet_print_config(__func__, __LINE__); \
174} while (0)
175
176/*
177 * When the hpet driver (/dev/hpet) is enabled, we need to reserve
178 * timer 0 and timer 1 in case of RTC emulation.
179 */
180#ifdef CONFIG_HPET
181
182static void hpet_reserve_msi_timers(struct hpet_data *hd);
183
184static void hpet_reserve_platform_timers(unsigned int id)
185{
186 struct hpet __iomem *hpet = hpet_virt_address;
187 struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
188 unsigned int nrtimers, i;
189 struct hpet_data hd;
190
191 nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
192
193 memset(&hd, 0, sizeof(hd));
194 hd.hd_phys_address = hpet_address;
195 hd.hd_address = hpet;
196 hd.hd_nirqs = nrtimers;
197 hpet_reserve_timer(&hd, 0);
198
199#ifdef CONFIG_HPET_EMULATE_RTC
200 hpet_reserve_timer(&hd, 1);
201#endif
202
203 /*
204 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
205 * is wrong for i8259!) not the output IRQ. Many BIOS writers
206 * don't bother configuring *any* comparator interrupts.
207 */
208 hd.hd_irq[0] = HPET_LEGACY_8254;
209 hd.hd_irq[1] = HPET_LEGACY_RTC;
210
211 for (i = 2; i < nrtimers; timer++, i++) {
212 hd.hd_irq[i] = (readl(&timer->hpet_config) &
213 Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
214 }
215
216 hpet_reserve_msi_timers(&hd);
217
218 hpet_alloc(&hd);
219
220}
221#else
222static void hpet_reserve_platform_timers(unsigned int id) { }
223#endif
224
225/*
226 * Common hpet info
227 */
228static unsigned long hpet_freq;
229
230static struct clock_event_device hpet_clockevent;
231
232static void hpet_stop_counter(void)
233{
234 u32 cfg = hpet_readl(HPET_CFG);
235 cfg &= ~HPET_CFG_ENABLE;
236 hpet_writel(cfg, HPET_CFG);
237}
238
239static void hpet_reset_counter(void)
240{
241 hpet_writel(0, HPET_COUNTER);
242 hpet_writel(0, HPET_COUNTER + 4);
243}
244
245static void hpet_start_counter(void)
246{
247 unsigned int cfg = hpet_readl(HPET_CFG);
248 cfg |= HPET_CFG_ENABLE;
249 hpet_writel(cfg, HPET_CFG);
250}
251
252static void hpet_restart_counter(void)
253{
254 hpet_stop_counter();
255 hpet_reset_counter();
256 hpet_start_counter();
257}
258
259static void hpet_resume_device(void)
260{
261 force_hpet_resume();
262}
263
264static void hpet_resume_counter(struct clocksource *cs)
265{
266 hpet_resume_device();
267 hpet_restart_counter();
268}
269
270static void hpet_enable_legacy_int(void)
271{
272 unsigned int cfg = hpet_readl(HPET_CFG);
273
274 cfg |= HPET_CFG_LEGACY;
275 hpet_writel(cfg, HPET_CFG);
276 hpet_legacy_int_enabled = true;
277}
278
279static void hpet_legacy_clockevent_register(void)
280{
281 /* Start HPET legacy interrupts */
282 hpet_enable_legacy_int();
283
284 /*
285 * Start hpet with the boot cpu mask and make it
286 * global after the IO_APIC has been initialized.
287 */
288 hpet_clockevent.cpumask = cpumask_of(boot_cpu_data.cpu_index);
289 clockevents_config_and_register(&hpet_clockevent, hpet_freq,
290 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
291 global_clock_event = &hpet_clockevent;
292 printk(KERN_DEBUG "hpet clockevent registered\n");
293}
294
295static int hpet_set_periodic(struct clock_event_device *evt, int timer)
296{
297 unsigned int cfg, cmp, now;
298 uint64_t delta;
299
300 hpet_stop_counter();
301 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
302 delta >>= evt->shift;
303 now = hpet_readl(HPET_COUNTER);
304 cmp = now + (unsigned int)delta;
305 cfg = hpet_readl(HPET_Tn_CFG(timer));
306 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
307 HPET_TN_32BIT;
308 hpet_writel(cfg, HPET_Tn_CFG(timer));
309 hpet_writel(cmp, HPET_Tn_CMP(timer));
310 udelay(1);
311 /*
312 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
313 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
314 * bit is automatically cleared after the first write.
315 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
316 * Publication # 24674)
317 */
318 hpet_writel((unsigned int)delta, HPET_Tn_CMP(timer));
319 hpet_start_counter();
320 hpet_print_config();
321
322 return 0;
323}
324
325static int hpet_set_oneshot(struct clock_event_device *evt, int timer)
326{
327 unsigned int cfg;
328
329 cfg = hpet_readl(HPET_Tn_CFG(timer));
330 cfg &= ~HPET_TN_PERIODIC;
331 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
332 hpet_writel(cfg, HPET_Tn_CFG(timer));
333
334 return 0;
335}
336
337static int hpet_shutdown(struct clock_event_device *evt, int timer)
338{
339 unsigned int cfg;
340
341 cfg = hpet_readl(HPET_Tn_CFG(timer));
342 cfg &= ~HPET_TN_ENABLE;
343 hpet_writel(cfg, HPET_Tn_CFG(timer));
344
345 return 0;
346}
347
348static int hpet_resume(struct clock_event_device *evt)
349{
350 hpet_enable_legacy_int();
351 hpet_print_config();
352 return 0;
353}
354
355static int hpet_next_event(unsigned long delta,
356 struct clock_event_device *evt, int timer)
357{
358 u32 cnt;
359 s32 res;
360
361 cnt = hpet_readl(HPET_COUNTER);
362 cnt += (u32) delta;
363 hpet_writel(cnt, HPET_Tn_CMP(timer));
364
365 /*
366 * HPETs are a complete disaster. The compare register is
367 * based on a equal comparison and neither provides a less
368 * than or equal functionality (which would require to take
369 * the wraparound into account) nor a simple count down event
370 * mode. Further the write to the comparator register is
371 * delayed internally up to two HPET clock cycles in certain
372 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
373 * longer delays. We worked around that by reading back the
374 * compare register, but that required another workaround for
375 * ICH9,10 chips where the first readout after write can
376 * return the old stale value. We already had a minimum
377 * programming delta of 5us enforced, but a NMI or SMI hitting
378 * between the counter readout and the comparator write can
379 * move us behind that point easily. Now instead of reading
380 * the compare register back several times, we make the ETIME
381 * decision based on the following: Return ETIME if the
382 * counter value after the write is less than HPET_MIN_CYCLES
383 * away from the event or if the counter is already ahead of
384 * the event. The minimum programming delta for the generic
385 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
386 */
387 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
388
389 return res < HPET_MIN_CYCLES ? -ETIME : 0;
390}
391
392static int hpet_legacy_shutdown(struct clock_event_device *evt)
393{
394 return hpet_shutdown(evt, 0);
395}
396
397static int hpet_legacy_set_oneshot(struct clock_event_device *evt)
398{
399 return hpet_set_oneshot(evt, 0);
400}
401
402static int hpet_legacy_set_periodic(struct clock_event_device *evt)
403{
404 return hpet_set_periodic(evt, 0);
405}
406
407static int hpet_legacy_resume(struct clock_event_device *evt)
408{
409 return hpet_resume(evt);
410}
411
412static int hpet_legacy_next_event(unsigned long delta,
413 struct clock_event_device *evt)
414{
415 return hpet_next_event(delta, evt, 0);
416}
417
418/*
419 * The hpet clock event device
420 */
421static struct clock_event_device hpet_clockevent = {
422 .name = "hpet",
423 .features = CLOCK_EVT_FEAT_PERIODIC |
424 CLOCK_EVT_FEAT_ONESHOT,
425 .set_state_periodic = hpet_legacy_set_periodic,
426 .set_state_oneshot = hpet_legacy_set_oneshot,
427 .set_state_shutdown = hpet_legacy_shutdown,
428 .tick_resume = hpet_legacy_resume,
429 .set_next_event = hpet_legacy_next_event,
430 .irq = 0,
431 .rating = 50,
432};
433
434/*
435 * HPET MSI Support
436 */
437#ifdef CONFIG_PCI_MSI
438
439static DEFINE_PER_CPU(struct hpet_dev *, cpu_hpet_dev);
440static struct hpet_dev *hpet_devs;
441static struct irq_domain *hpet_domain;
442
443void hpet_msi_unmask(struct irq_data *data)
444{
445 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
446 unsigned int cfg;
447
448 /* unmask it */
449 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
450 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
451 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
452}
453
454void hpet_msi_mask(struct irq_data *data)
455{
456 struct hpet_dev *hdev = irq_data_get_irq_handler_data(data);
457 unsigned int cfg;
458
459 /* mask it */
460 cfg = hpet_readl(HPET_Tn_CFG(hdev->num));
461 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
462 hpet_writel(cfg, HPET_Tn_CFG(hdev->num));
463}
464
465void hpet_msi_write(struct hpet_dev *hdev, struct msi_msg *msg)
466{
467 hpet_writel(msg->data, HPET_Tn_ROUTE(hdev->num));
468 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hdev->num) + 4);
469}
470
471void hpet_msi_read(struct hpet_dev *hdev, struct msi_msg *msg)
472{
473 msg->data = hpet_readl(HPET_Tn_ROUTE(hdev->num));
474 msg->address_lo = hpet_readl(HPET_Tn_ROUTE(hdev->num) + 4);
475 msg->address_hi = 0;
476}
477
478static int hpet_msi_shutdown(struct clock_event_device *evt)
479{
480 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
481
482 return hpet_shutdown(evt, hdev->num);
483}
484
485static int hpet_msi_set_oneshot(struct clock_event_device *evt)
486{
487 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
488
489 return hpet_set_oneshot(evt, hdev->num);
490}
491
492static int hpet_msi_set_periodic(struct clock_event_device *evt)
493{
494 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
495
496 return hpet_set_periodic(evt, hdev->num);
497}
498
499static int hpet_msi_resume(struct clock_event_device *evt)
500{
501 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
502 struct irq_data *data = irq_get_irq_data(hdev->irq);
503 struct msi_msg msg;
504
505 /* Restore the MSI msg and unmask the interrupt */
506 irq_chip_compose_msi_msg(data, &msg);
507 hpet_msi_write(hdev, &msg);
508 hpet_msi_unmask(data);
509 return 0;
510}
511
512static int hpet_msi_next_event(unsigned long delta,
513 struct clock_event_device *evt)
514{
515 struct hpet_dev *hdev = EVT_TO_HPET_DEV(evt);
516 return hpet_next_event(delta, evt, hdev->num);
517}
518
519static irqreturn_t hpet_interrupt_handler(int irq, void *data)
520{
521 struct hpet_dev *dev = (struct hpet_dev *)data;
522 struct clock_event_device *hevt = &dev->evt;
523
524 if (!hevt->event_handler) {
525 printk(KERN_INFO "Spurious HPET timer interrupt on HPET timer %d\n",
526 dev->num);
527 return IRQ_HANDLED;
528 }
529
530 hevt->event_handler(hevt);
531 return IRQ_HANDLED;
532}
533
534static int hpet_setup_irq(struct hpet_dev *dev)
535{
536
537 if (request_irq(dev->irq, hpet_interrupt_handler,
538 IRQF_TIMER | IRQF_NOBALANCING,
539 dev->name, dev))
540 return -1;
541
542 disable_irq(dev->irq);
543 irq_set_affinity(dev->irq, cpumask_of(dev->cpu));
544 enable_irq(dev->irq);
545
546 printk(KERN_DEBUG "hpet: %s irq %d for MSI\n",
547 dev->name, dev->irq);
548
549 return 0;
550}
551
552/* This should be called in specific @cpu */
553static void init_one_hpet_msi_clockevent(struct hpet_dev *hdev, int cpu)
554{
555 struct clock_event_device *evt = &hdev->evt;
556
557 WARN_ON(cpu != smp_processor_id());
558 if (!(hdev->flags & HPET_DEV_VALID))
559 return;
560
561 hdev->cpu = cpu;
562 per_cpu(cpu_hpet_dev, cpu) = hdev;
563 evt->name = hdev->name;
564 hpet_setup_irq(hdev);
565 evt->irq = hdev->irq;
566
567 evt->rating = 110;
568 evt->features = CLOCK_EVT_FEAT_ONESHOT;
569 if (hdev->flags & HPET_DEV_PERI_CAP) {
570 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
571 evt->set_state_periodic = hpet_msi_set_periodic;
572 }
573
574 evt->set_state_shutdown = hpet_msi_shutdown;
575 evt->set_state_oneshot = hpet_msi_set_oneshot;
576 evt->tick_resume = hpet_msi_resume;
577 evt->set_next_event = hpet_msi_next_event;
578 evt->cpumask = cpumask_of(hdev->cpu);
579
580 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
581 0x7FFFFFFF);
582}
583
584#ifdef CONFIG_HPET
585/* Reserve at least one timer for userspace (/dev/hpet) */
586#define RESERVE_TIMERS 1
587#else
588#define RESERVE_TIMERS 0
589#endif
590
591static void hpet_msi_capability_lookup(unsigned int start_timer)
592{
593 unsigned int id;
594 unsigned int num_timers;
595 unsigned int num_timers_used = 0;
596 int i, irq;
597
598 if (hpet_msi_disable)
599 return;
600
601 if (boot_cpu_has(X86_FEATURE_ARAT))
602 return;
603 id = hpet_readl(HPET_ID);
604
605 num_timers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
606 num_timers++; /* Value read out starts from 0 */
607 hpet_print_config();
608
609 hpet_domain = hpet_create_irq_domain(hpet_blockid);
610 if (!hpet_domain)
611 return;
612
613 hpet_devs = kzalloc(sizeof(struct hpet_dev) * num_timers, GFP_KERNEL);
614 if (!hpet_devs)
615 return;
616
617 hpet_num_timers = num_timers;
618
619 for (i = start_timer; i < num_timers - RESERVE_TIMERS; i++) {
620 struct hpet_dev *hdev = &hpet_devs[num_timers_used];
621 unsigned int cfg = hpet_readl(HPET_Tn_CFG(i));
622
623 /* Only consider HPET timer with MSI support */
624 if (!(cfg & HPET_TN_FSB_CAP))
625 continue;
626
627 hdev->flags = 0;
628 if (cfg & HPET_TN_PERIODIC_CAP)
629 hdev->flags |= HPET_DEV_PERI_CAP;
630 sprintf(hdev->name, "hpet%d", i);
631 hdev->num = i;
632
633 irq = hpet_assign_irq(hpet_domain, hdev, hdev->num);
634 if (irq <= 0)
635 continue;
636
637 hdev->irq = irq;
638 hdev->flags |= HPET_DEV_FSB_CAP;
639 hdev->flags |= HPET_DEV_VALID;
640 num_timers_used++;
641 if (num_timers_used == num_possible_cpus())
642 break;
643 }
644
645 printk(KERN_INFO "HPET: %d timers in total, %d timers will be used for per-cpu timer\n",
646 num_timers, num_timers_used);
647}
648
649#ifdef CONFIG_HPET
650static void hpet_reserve_msi_timers(struct hpet_data *hd)
651{
652 int i;
653
654 if (!hpet_devs)
655 return;
656
657 for (i = 0; i < hpet_num_timers; i++) {
658 struct hpet_dev *hdev = &hpet_devs[i];
659
660 if (!(hdev->flags & HPET_DEV_VALID))
661 continue;
662
663 hd->hd_irq[hdev->num] = hdev->irq;
664 hpet_reserve_timer(hd, hdev->num);
665 }
666}
667#endif
668
669static struct hpet_dev *hpet_get_unused_timer(void)
670{
671 int i;
672
673 if (!hpet_devs)
674 return NULL;
675
676 for (i = 0; i < hpet_num_timers; i++) {
677 struct hpet_dev *hdev = &hpet_devs[i];
678
679 if (!(hdev->flags & HPET_DEV_VALID))
680 continue;
681 if (test_and_set_bit(HPET_DEV_USED_BIT,
682 (unsigned long *)&hdev->flags))
683 continue;
684 return hdev;
685 }
686 return NULL;
687}
688
689struct hpet_work_struct {
690 struct delayed_work work;
691 struct completion complete;
692};
693
694static void hpet_work(struct work_struct *w)
695{
696 struct hpet_dev *hdev;
697 int cpu = smp_processor_id();
698 struct hpet_work_struct *hpet_work;
699
700 hpet_work = container_of(w, struct hpet_work_struct, work.work);
701
702 hdev = hpet_get_unused_timer();
703 if (hdev)
704 init_one_hpet_msi_clockevent(hdev, cpu);
705
706 complete(&hpet_work->complete);
707}
708
709static int hpet_cpuhp_online(unsigned int cpu)
710{
711 struct hpet_work_struct work;
712
713 INIT_DELAYED_WORK_ONSTACK(&work.work, hpet_work);
714 init_completion(&work.complete);
715 /* FIXME: add schedule_work_on() */
716 schedule_delayed_work_on(cpu, &work.work, 0);
717 wait_for_completion(&work.complete);
718 destroy_delayed_work_on_stack(&work.work);
719 return 0;
720}
721
722static int hpet_cpuhp_dead(unsigned int cpu)
723{
724 struct hpet_dev *hdev = per_cpu(cpu_hpet_dev, cpu);
725
726 if (!hdev)
727 return 0;
728 free_irq(hdev->irq, hdev);
729 hdev->flags &= ~HPET_DEV_USED;
730 per_cpu(cpu_hpet_dev, cpu) = NULL;
731 return 0;
732}
733#else
734
735static void hpet_msi_capability_lookup(unsigned int start_timer)
736{
737 return;
738}
739
740#ifdef CONFIG_HPET
741static void hpet_reserve_msi_timers(struct hpet_data *hd)
742{
743 return;
744}
745#endif
746
747#define hpet_cpuhp_online NULL
748#define hpet_cpuhp_dead NULL
749
750#endif
751
752/*
753 * Clock source related code
754 */
755#if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
756/*
757 * Reading the HPET counter is a very slow operation. If a large number of
758 * CPUs are trying to access the HPET counter simultaneously, it can cause
759 * massive delay and slow down system performance dramatically. This may
760 * happen when HPET is the default clock source instead of TSC. For a
761 * really large system with hundreds of CPUs, the slowdown may be so
762 * severe that it may actually crash the system because of a NMI watchdog
763 * soft lockup, for example.
764 *
765 * If multiple CPUs are trying to access the HPET counter at the same time,
766 * we don't actually need to read the counter multiple times. Instead, the
767 * other CPUs can use the counter value read by the first CPU in the group.
768 *
769 * This special feature is only enabled on x86-64 systems. It is unlikely
770 * that 32-bit x86 systems will have enough CPUs to require this feature
771 * with its associated locking overhead. And we also need 64-bit atomic
772 * read.
773 *
774 * The lock and the hpet value are stored together and can be read in a
775 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
776 * is 32 bits in size.
777 */
778union hpet_lock {
779 struct {
780 arch_spinlock_t lock;
781 u32 value;
782 };
783 u64 lockval;
784};
785
786static union hpet_lock hpet __cacheline_aligned = {
787 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, },
788};
789
790static u64 read_hpet(struct clocksource *cs)
791{
792 unsigned long flags;
793 union hpet_lock old, new;
794
795 BUILD_BUG_ON(sizeof(union hpet_lock) != 8);
796
797 /*
798 * Read HPET directly if in NMI.
799 */
800 if (in_nmi())
801 return (u64)hpet_readl(HPET_COUNTER);
802
803 /*
804 * Read the current state of the lock and HPET value atomically.
805 */
806 old.lockval = READ_ONCE(hpet.lockval);
807
808 if (arch_spin_is_locked(&old.lock))
809 goto contended;
810
811 local_irq_save(flags);
812 if (arch_spin_trylock(&hpet.lock)) {
813 new.value = hpet_readl(HPET_COUNTER);
814 /*
815 * Use WRITE_ONCE() to prevent store tearing.
816 */
817 WRITE_ONCE(hpet.value, new.value);
818 arch_spin_unlock(&hpet.lock);
819 local_irq_restore(flags);
820 return (u64)new.value;
821 }
822 local_irq_restore(flags);
823
824contended:
825 /*
826 * Contended case
827 * --------------
828 * Wait until the HPET value change or the lock is free to indicate
829 * its value is up-to-date.
830 *
831 * It is possible that old.value has already contained the latest
832 * HPET value while the lock holder was in the process of releasing
833 * the lock. Checking for lock state change will enable us to return
834 * the value immediately instead of waiting for the next HPET reader
835 * to come along.
836 */
837 do {
838 cpu_relax();
839 new.lockval = READ_ONCE(hpet.lockval);
840 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock));
841
842 return (u64)new.value;
843}
844#else
845/*
846 * For UP or 32-bit.
847 */
848static u64 read_hpet(struct clocksource *cs)
849{
850 return (u64)hpet_readl(HPET_COUNTER);
851}
852#endif
853
854static struct clocksource clocksource_hpet = {
855 .name = "hpet",
856 .rating = 250,
857 .read = read_hpet,
858 .mask = HPET_MASK,
859 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
860 .resume = hpet_resume_counter,
861};
862
863static int hpet_clocksource_register(void)
864{
865 u64 start, now;
866 u64 t1;
867
868 /* Start the counter */
869 hpet_restart_counter();
870
871 /* Verify whether hpet counter works */
872 t1 = hpet_readl(HPET_COUNTER);
873 start = rdtsc();
874
875 /*
876 * We don't know the TSC frequency yet, but waiting for
877 * 200000 TSC cycles is safe:
878 * 4 GHz == 50us
879 * 1 GHz == 200us
880 */
881 do {
882 rep_nop();
883 now = rdtsc();
884 } while ((now - start) < 200000UL);
885
886 if (t1 == hpet_readl(HPET_COUNTER)) {
887 printk(KERN_WARNING
888 "HPET counter not counting. HPET disabled\n");
889 return -ENODEV;
890 }
891
892 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
893 return 0;
894}
895
896static u32 *hpet_boot_cfg;
897
898/**
899 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
900 */
901int __init hpet_enable(void)
902{
903 u32 hpet_period, cfg, id;
904 u64 freq;
905 unsigned int i, last;
906
907 if (!is_hpet_capable())
908 return 0;
909
910 hpet_set_mapping();
911
912 /*
913 * Read the period and check for a sane value:
914 */
915 hpet_period = hpet_readl(HPET_PERIOD);
916
917 /*
918 * AMD SB700 based systems with spread spectrum enabled use a
919 * SMM based HPET emulation to provide proper frequency
920 * setting. The SMM code is initialized with the first HPET
921 * register access and takes some time to complete. During
922 * this time the config register reads 0xffffffff. We check
923 * for max. 1000 loops whether the config register reads a non
924 * 0xffffffff value to make sure that HPET is up and running
925 * before we go further. A counting loop is safe, as the HPET
926 * access takes thousands of CPU cycles. On non SB700 based
927 * machines this check is only done once and has no side
928 * effects.
929 */
930 for (i = 0; hpet_readl(HPET_CFG) == 0xFFFFFFFF; i++) {
931 if (i == 1000) {
932 printk(KERN_WARNING
933 "HPET config register value = 0xFFFFFFFF. "
934 "Disabling HPET\n");
935 goto out_nohpet;
936 }
937 }
938
939 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
940 goto out_nohpet;
941
942 /*
943 * The period is a femto seconds value. Convert it to a
944 * frequency.
945 */
946 freq = FSEC_PER_SEC;
947 do_div(freq, hpet_period);
948 hpet_freq = freq;
949
950 /*
951 * Read the HPET ID register to retrieve the IRQ routing
952 * information and the number of channels
953 */
954 id = hpet_readl(HPET_ID);
955 hpet_print_config();
956
957 last = (id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT;
958
959#ifdef CONFIG_HPET_EMULATE_RTC
960 /*
961 * The legacy routing mode needs at least two channels, tick timer
962 * and the rtc emulation channel.
963 */
964 if (!last)
965 goto out_nohpet;
966#endif
967
968 cfg = hpet_readl(HPET_CFG);
969 hpet_boot_cfg = kmalloc((last + 2) * sizeof(*hpet_boot_cfg),
970 GFP_KERNEL);
971 if (hpet_boot_cfg)
972 *hpet_boot_cfg = cfg;
973 else
974 pr_warn("HPET initial state will not be saved\n");
975 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
976 hpet_writel(cfg, HPET_CFG);
977 if (cfg)
978 pr_warn("HPET: Unrecognized bits %#x set in global cfg\n",
979 cfg);
980
981 for (i = 0; i <= last; ++i) {
982 cfg = hpet_readl(HPET_Tn_CFG(i));
983 if (hpet_boot_cfg)
984 hpet_boot_cfg[i + 1] = cfg;
985 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
986 hpet_writel(cfg, HPET_Tn_CFG(i));
987 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
988 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
989 | HPET_TN_FSB | HPET_TN_FSB_CAP);
990 if (cfg)
991 pr_warn("HPET: Unrecognized bits %#x set in cfg#%u\n",
992 cfg, i);
993 }
994 hpet_print_config();
995
996 if (hpet_clocksource_register())
997 goto out_nohpet;
998
999 if (id & HPET_ID_LEGSUP) {
1000 hpet_legacy_clockevent_register();
1001 return 1;
1002 }
1003 return 0;
1004
1005out_nohpet:
1006 hpet_clear_mapping();
1007 hpet_address = 0;
1008 return 0;
1009}
1010
1011/*
1012 * Needs to be late, as the reserve_timer code calls kalloc !
1013 *
1014 * Not a problem on i386 as hpet_enable is called from late_time_init,
1015 * but on x86_64 it is necessary !
1016 */
1017static __init int hpet_late_init(void)
1018{
1019 int ret;
1020
1021 if (boot_hpet_disable)
1022 return -ENODEV;
1023
1024 if (!hpet_address) {
1025 if (!force_hpet_address)
1026 return -ENODEV;
1027
1028 hpet_address = force_hpet_address;
1029 hpet_enable();
1030 }
1031
1032 if (!hpet_virt_address)
1033 return -ENODEV;
1034
1035 if (hpet_readl(HPET_ID) & HPET_ID_LEGSUP)
1036 hpet_msi_capability_lookup(2);
1037 else
1038 hpet_msi_capability_lookup(0);
1039
1040 hpet_reserve_platform_timers(hpet_readl(HPET_ID));
1041 hpet_print_config();
1042
1043 if (hpet_msi_disable)
1044 return 0;
1045
1046 if (boot_cpu_has(X86_FEATURE_ARAT))
1047 return 0;
1048
1049 /* This notifier should be called after workqueue is ready */
1050 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online",
1051 hpet_cpuhp_online, NULL);
1052 if (ret)
1053 return ret;
1054 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL,
1055 hpet_cpuhp_dead);
1056 if (ret)
1057 goto err_cpuhp;
1058 return 0;
1059
1060err_cpuhp:
1061 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE);
1062 return ret;
1063}
1064fs_initcall(hpet_late_init);
1065
1066void hpet_disable(void)
1067{
1068 if (is_hpet_capable() && hpet_virt_address) {
1069 unsigned int cfg = hpet_readl(HPET_CFG), id, last;
1070
1071 if (hpet_boot_cfg)
1072 cfg = *hpet_boot_cfg;
1073 else if (hpet_legacy_int_enabled) {
1074 cfg &= ~HPET_CFG_LEGACY;
1075 hpet_legacy_int_enabled = false;
1076 }
1077 cfg &= ~HPET_CFG_ENABLE;
1078 hpet_writel(cfg, HPET_CFG);
1079
1080 if (!hpet_boot_cfg)
1081 return;
1082
1083 id = hpet_readl(HPET_ID);
1084 last = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT);
1085
1086 for (id = 0; id <= last; ++id)
1087 hpet_writel(hpet_boot_cfg[id + 1], HPET_Tn_CFG(id));
1088
1089 if (*hpet_boot_cfg & HPET_CFG_ENABLE)
1090 hpet_writel(*hpet_boot_cfg, HPET_CFG);
1091 }
1092}
1093
1094#ifdef CONFIG_HPET_EMULATE_RTC
1095
1096/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
1097 * is enabled, we support RTC interrupt functionality in software.
1098 * RTC has 3 kinds of interrupts:
1099 * 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
1100 * is updated
1101 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1102 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1103 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
1104 * (1) and (2) above are implemented using polling at a frequency of
1105 * 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
1106 * overhead. (DEFAULT_RTC_INT_FREQ)
1107 * For (3), we use interrupts at 64Hz or user specified periodic
1108 * frequency, whichever is higher.
1109 */
1110#include <linux/mc146818rtc.h>
1111#include <linux/rtc.h>
1112
1113#define DEFAULT_RTC_INT_FREQ 64
1114#define DEFAULT_RTC_SHIFT 6
1115#define RTC_NUM_INTS 1
1116
1117static unsigned long hpet_rtc_flags;
1118static int hpet_prev_update_sec;
1119static struct rtc_time hpet_alarm_time;
1120static unsigned long hpet_pie_count;
1121static u32 hpet_t1_cmp;
1122static u32 hpet_default_delta;
1123static u32 hpet_pie_delta;
1124static unsigned long hpet_pie_limit;
1125
1126static rtc_irq_handler irq_handler;
1127
1128/*
1129 * Check that the hpet counter c1 is ahead of the c2
1130 */
1131static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1132{
1133 return (s32)(c2 - c1) < 0;
1134}
1135
1136/*
1137 * Registers a IRQ handler.
1138 */
1139int hpet_register_irq_handler(rtc_irq_handler handler)
1140{
1141 if (!is_hpet_enabled())
1142 return -ENODEV;
1143 if (irq_handler)
1144 return -EBUSY;
1145
1146 irq_handler = handler;
1147
1148 return 0;
1149}
1150EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1151
1152/*
1153 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1154 * and does cleanup.
1155 */
1156void hpet_unregister_irq_handler(rtc_irq_handler handler)
1157{
1158 if (!is_hpet_enabled())
1159 return;
1160
1161 irq_handler = NULL;
1162 hpet_rtc_flags = 0;
1163}
1164EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1165
1166/*
1167 * Timer 1 for RTC emulation. We use one shot mode, as periodic mode
1168 * is not supported by all HPET implementations for timer 1.
1169 *
1170 * hpet_rtc_timer_init() is called when the rtc is initialized.
1171 */
1172int hpet_rtc_timer_init(void)
1173{
1174 unsigned int cfg, cnt, delta;
1175 unsigned long flags;
1176
1177 if (!is_hpet_enabled())
1178 return 0;
1179
1180 if (!hpet_default_delta) {
1181 uint64_t clc;
1182
1183 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1184 clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
1185 hpet_default_delta = clc;
1186 }
1187
1188 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1189 delta = hpet_default_delta;
1190 else
1191 delta = hpet_pie_delta;
1192
1193 local_irq_save(flags);
1194
1195 cnt = delta + hpet_readl(HPET_COUNTER);
1196 hpet_writel(cnt, HPET_T1_CMP);
1197 hpet_t1_cmp = cnt;
1198
1199 cfg = hpet_readl(HPET_T1_CFG);
1200 cfg &= ~HPET_TN_PERIODIC;
1201 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1202 hpet_writel(cfg, HPET_T1_CFG);
1203
1204 local_irq_restore(flags);
1205
1206 return 1;
1207}
1208EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1209
1210static void hpet_disable_rtc_channel(void)
1211{
1212 u32 cfg = hpet_readl(HPET_T1_CFG);
1213 cfg &= ~HPET_TN_ENABLE;
1214 hpet_writel(cfg, HPET_T1_CFG);
1215}
1216
1217/*
1218 * The functions below are called from rtc driver.
1219 * Return 0 if HPET is not being used.
1220 * Otherwise do the necessary changes and return 1.
1221 */
1222int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1223{
1224 if (!is_hpet_enabled())
1225 return 0;
1226
1227 hpet_rtc_flags &= ~bit_mask;
1228 if (unlikely(!hpet_rtc_flags))
1229 hpet_disable_rtc_channel();
1230
1231 return 1;
1232}
1233EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1234
1235int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1236{
1237 unsigned long oldbits = hpet_rtc_flags;
1238
1239 if (!is_hpet_enabled())
1240 return 0;
1241
1242 hpet_rtc_flags |= bit_mask;
1243
1244 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1245 hpet_prev_update_sec = -1;
1246
1247 if (!oldbits)
1248 hpet_rtc_timer_init();
1249
1250 return 1;
1251}
1252EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1253
1254int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
1255 unsigned char sec)
1256{
1257 if (!is_hpet_enabled())
1258 return 0;
1259
1260 hpet_alarm_time.tm_hour = hrs;
1261 hpet_alarm_time.tm_min = min;
1262 hpet_alarm_time.tm_sec = sec;
1263
1264 return 1;
1265}
1266EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1267
1268int hpet_set_periodic_freq(unsigned long freq)
1269{
1270 uint64_t clc;
1271
1272 if (!is_hpet_enabled())
1273 return 0;
1274
1275 if (freq <= DEFAULT_RTC_INT_FREQ)
1276 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1277 else {
1278 clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
1279 do_div(clc, freq);
1280 clc >>= hpet_clockevent.shift;
1281 hpet_pie_delta = clc;
1282 hpet_pie_limit = 0;
1283 }
1284 return 1;
1285}
1286EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1287
1288int hpet_rtc_dropped_irq(void)
1289{
1290 return is_hpet_enabled();
1291}
1292EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1293
1294static void hpet_rtc_timer_reinit(void)
1295{
1296 unsigned int delta;
1297 int lost_ints = -1;
1298
1299 if (unlikely(!hpet_rtc_flags))
1300 hpet_disable_rtc_channel();
1301
1302 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1303 delta = hpet_default_delta;
1304 else
1305 delta = hpet_pie_delta;
1306
1307 /*
1308 * Increment the comparator value until we are ahead of the
1309 * current count.
1310 */
1311 do {
1312 hpet_t1_cmp += delta;
1313 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1314 lost_ints++;
1315 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1316
1317 if (lost_ints) {
1318 if (hpet_rtc_flags & RTC_PIE)
1319 hpet_pie_count += lost_ints;
1320 if (printk_ratelimit())
1321 printk(KERN_WARNING "hpet1: lost %d rtc interrupts\n",
1322 lost_ints);
1323 }
1324}
1325
1326irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1327{
1328 struct rtc_time curr_time;
1329 unsigned long rtc_int_flag = 0;
1330
1331 hpet_rtc_timer_reinit();
1332 memset(&curr_time, 0, sizeof(struct rtc_time));
1333
1334 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1335 mc146818_get_time(&curr_time);
1336
1337 if (hpet_rtc_flags & RTC_UIE &&
1338 curr_time.tm_sec != hpet_prev_update_sec) {
1339 if (hpet_prev_update_sec >= 0)
1340 rtc_int_flag = RTC_UF;
1341 hpet_prev_update_sec = curr_time.tm_sec;
1342 }
1343
1344 if (hpet_rtc_flags & RTC_PIE &&
1345 ++hpet_pie_count >= hpet_pie_limit) {
1346 rtc_int_flag |= RTC_PF;
1347 hpet_pie_count = 0;
1348 }
1349
1350 if (hpet_rtc_flags & RTC_AIE &&
1351 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1352 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1353 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1354 rtc_int_flag |= RTC_AF;
1355
1356 if (rtc_int_flag) {
1357 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1358 if (irq_handler)
1359 irq_handler(rtc_int_flag, dev_id);
1360 }
1361 return IRQ_HANDLED;
1362}
1363EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1364#endif
1// SPDX-License-Identifier: GPL-2.0-only
2#include <linux/clockchips.h>
3#include <linux/interrupt.h>
4#include <linux/export.h>
5#include <linux/delay.h>
6#include <linux/hpet.h>
7#include <linux/cpu.h>
8#include <linux/irq.h>
9
10#include <asm/hpet.h>
11#include <asm/time.h>
12
13#undef pr_fmt
14#define pr_fmt(fmt) "hpet: " fmt
15
16enum hpet_mode {
17 HPET_MODE_UNUSED,
18 HPET_MODE_LEGACY,
19 HPET_MODE_CLOCKEVT,
20 HPET_MODE_DEVICE,
21};
22
23struct hpet_channel {
24 struct clock_event_device evt;
25 unsigned int num;
26 unsigned int cpu;
27 unsigned int irq;
28 unsigned int in_use;
29 enum hpet_mode mode;
30 unsigned int boot_cfg;
31 char name[10];
32};
33
34struct hpet_base {
35 unsigned int nr_channels;
36 unsigned int nr_clockevents;
37 unsigned int boot_cfg;
38 struct hpet_channel *channels;
39};
40
41#define HPET_MASK CLOCKSOURCE_MASK(32)
42
43#define HPET_MIN_CYCLES 128
44#define HPET_MIN_PROG_DELTA (HPET_MIN_CYCLES + (HPET_MIN_CYCLES >> 1))
45
46/*
47 * HPET address is set in acpi/boot.c, when an ACPI entry exists
48 */
49unsigned long hpet_address;
50u8 hpet_blockid; /* OS timer block num */
51bool hpet_msi_disable;
52
53#ifdef CONFIG_PCI_MSI
54static DEFINE_PER_CPU(struct hpet_channel *, cpu_hpet_channel);
55static struct irq_domain *hpet_domain;
56#endif
57
58static void __iomem *hpet_virt_address;
59
60static struct hpet_base hpet_base;
61
62static bool hpet_legacy_int_enabled;
63static unsigned long hpet_freq;
64
65bool boot_hpet_disable;
66bool hpet_force_user;
67static bool hpet_verbose;
68
69static inline
70struct hpet_channel *clockevent_to_channel(struct clock_event_device *evt)
71{
72 return container_of(evt, struct hpet_channel, evt);
73}
74
75inline unsigned int hpet_readl(unsigned int a)
76{
77 return readl(hpet_virt_address + a);
78}
79
80static inline void hpet_writel(unsigned int d, unsigned int a)
81{
82 writel(d, hpet_virt_address + a);
83}
84
85static inline void hpet_set_mapping(void)
86{
87 hpet_virt_address = ioremap(hpet_address, HPET_MMAP_SIZE);
88}
89
90static inline void hpet_clear_mapping(void)
91{
92 iounmap(hpet_virt_address);
93 hpet_virt_address = NULL;
94}
95
96/*
97 * HPET command line enable / disable
98 */
99static int __init hpet_setup(char *str)
100{
101 while (str) {
102 char *next = strchr(str, ',');
103
104 if (next)
105 *next++ = 0;
106 if (!strncmp("disable", str, 7))
107 boot_hpet_disable = true;
108 if (!strncmp("force", str, 5))
109 hpet_force_user = true;
110 if (!strncmp("verbose", str, 7))
111 hpet_verbose = true;
112 str = next;
113 }
114 return 1;
115}
116__setup("hpet=", hpet_setup);
117
118static int __init disable_hpet(char *str)
119{
120 boot_hpet_disable = true;
121 return 1;
122}
123__setup("nohpet", disable_hpet);
124
125static inline int is_hpet_capable(void)
126{
127 return !boot_hpet_disable && hpet_address;
128}
129
130/**
131 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
132 */
133int is_hpet_enabled(void)
134{
135 return is_hpet_capable() && hpet_legacy_int_enabled;
136}
137EXPORT_SYMBOL_GPL(is_hpet_enabled);
138
139static void _hpet_print_config(const char *function, int line)
140{
141 u32 i, id, period, cfg, status, channels, l, h;
142
143 pr_info("%s(%d):\n", function, line);
144
145 id = hpet_readl(HPET_ID);
146 period = hpet_readl(HPET_PERIOD);
147 pr_info("ID: 0x%x, PERIOD: 0x%x\n", id, period);
148
149 cfg = hpet_readl(HPET_CFG);
150 status = hpet_readl(HPET_STATUS);
151 pr_info("CFG: 0x%x, STATUS: 0x%x\n", cfg, status);
152
153 l = hpet_readl(HPET_COUNTER);
154 h = hpet_readl(HPET_COUNTER+4);
155 pr_info("COUNTER_l: 0x%x, COUNTER_h: 0x%x\n", l, h);
156
157 channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
158
159 for (i = 0; i < channels; i++) {
160 l = hpet_readl(HPET_Tn_CFG(i));
161 h = hpet_readl(HPET_Tn_CFG(i)+4);
162 pr_info("T%d: CFG_l: 0x%x, CFG_h: 0x%x\n", i, l, h);
163
164 l = hpet_readl(HPET_Tn_CMP(i));
165 h = hpet_readl(HPET_Tn_CMP(i)+4);
166 pr_info("T%d: CMP_l: 0x%x, CMP_h: 0x%x\n", i, l, h);
167
168 l = hpet_readl(HPET_Tn_ROUTE(i));
169 h = hpet_readl(HPET_Tn_ROUTE(i)+4);
170 pr_info("T%d ROUTE_l: 0x%x, ROUTE_h: 0x%x\n", i, l, h);
171 }
172}
173
174#define hpet_print_config() \
175do { \
176 if (hpet_verbose) \
177 _hpet_print_config(__func__, __LINE__); \
178} while (0)
179
180/*
181 * When the HPET driver (/dev/hpet) is enabled, we need to reserve
182 * timer 0 and timer 1 in case of RTC emulation.
183 */
184#ifdef CONFIG_HPET
185
186static void __init hpet_reserve_platform_timers(void)
187{
188 struct hpet_data hd;
189 unsigned int i;
190
191 memset(&hd, 0, sizeof(hd));
192 hd.hd_phys_address = hpet_address;
193 hd.hd_address = hpet_virt_address;
194 hd.hd_nirqs = hpet_base.nr_channels;
195
196 /*
197 * NOTE that hd_irq[] reflects IOAPIC input pins (LEGACY_8254
198 * is wrong for i8259!) not the output IRQ. Many BIOS writers
199 * don't bother configuring *any* comparator interrupts.
200 */
201 hd.hd_irq[0] = HPET_LEGACY_8254;
202 hd.hd_irq[1] = HPET_LEGACY_RTC;
203
204 for (i = 0; i < hpet_base.nr_channels; i++) {
205 struct hpet_channel *hc = hpet_base.channels + i;
206
207 if (i >= 2)
208 hd.hd_irq[i] = hc->irq;
209
210 switch (hc->mode) {
211 case HPET_MODE_UNUSED:
212 case HPET_MODE_DEVICE:
213 hc->mode = HPET_MODE_DEVICE;
214 break;
215 case HPET_MODE_CLOCKEVT:
216 case HPET_MODE_LEGACY:
217 hpet_reserve_timer(&hd, hc->num);
218 break;
219 }
220 }
221
222 hpet_alloc(&hd);
223}
224
225static void __init hpet_select_device_channel(void)
226{
227 int i;
228
229 for (i = 0; i < hpet_base.nr_channels; i++) {
230 struct hpet_channel *hc = hpet_base.channels + i;
231
232 /* Associate the first unused channel to /dev/hpet */
233 if (hc->mode == HPET_MODE_UNUSED) {
234 hc->mode = HPET_MODE_DEVICE;
235 return;
236 }
237 }
238}
239
240#else
241static inline void hpet_reserve_platform_timers(void) { }
242static inline void hpet_select_device_channel(void) {}
243#endif
244
245/* Common HPET functions */
246static void hpet_stop_counter(void)
247{
248 u32 cfg = hpet_readl(HPET_CFG);
249
250 cfg &= ~HPET_CFG_ENABLE;
251 hpet_writel(cfg, HPET_CFG);
252}
253
254static void hpet_reset_counter(void)
255{
256 hpet_writel(0, HPET_COUNTER);
257 hpet_writel(0, HPET_COUNTER + 4);
258}
259
260static void hpet_start_counter(void)
261{
262 unsigned int cfg = hpet_readl(HPET_CFG);
263
264 cfg |= HPET_CFG_ENABLE;
265 hpet_writel(cfg, HPET_CFG);
266}
267
268static void hpet_restart_counter(void)
269{
270 hpet_stop_counter();
271 hpet_reset_counter();
272 hpet_start_counter();
273}
274
275static void hpet_resume_device(void)
276{
277 force_hpet_resume();
278}
279
280static void hpet_resume_counter(struct clocksource *cs)
281{
282 hpet_resume_device();
283 hpet_restart_counter();
284}
285
286static void hpet_enable_legacy_int(void)
287{
288 unsigned int cfg = hpet_readl(HPET_CFG);
289
290 cfg |= HPET_CFG_LEGACY;
291 hpet_writel(cfg, HPET_CFG);
292 hpet_legacy_int_enabled = true;
293}
294
295static int hpet_clkevt_set_state_periodic(struct clock_event_device *evt)
296{
297 unsigned int channel = clockevent_to_channel(evt)->num;
298 unsigned int cfg, cmp, now;
299 uint64_t delta;
300
301 hpet_stop_counter();
302 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult;
303 delta >>= evt->shift;
304 now = hpet_readl(HPET_COUNTER);
305 cmp = now + (unsigned int)delta;
306 cfg = hpet_readl(HPET_Tn_CFG(channel));
307 cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC | HPET_TN_SETVAL |
308 HPET_TN_32BIT;
309 hpet_writel(cfg, HPET_Tn_CFG(channel));
310 hpet_writel(cmp, HPET_Tn_CMP(channel));
311 udelay(1);
312 /*
313 * HPET on AMD 81xx needs a second write (with HPET_TN_SETVAL
314 * cleared) to T0_CMP to set the period. The HPET_TN_SETVAL
315 * bit is automatically cleared after the first write.
316 * (See AMD-8111 HyperTransport I/O Hub Data Sheet,
317 * Publication # 24674)
318 */
319 hpet_writel((unsigned int)delta, HPET_Tn_CMP(channel));
320 hpet_start_counter();
321 hpet_print_config();
322
323 return 0;
324}
325
326static int hpet_clkevt_set_state_oneshot(struct clock_event_device *evt)
327{
328 unsigned int channel = clockevent_to_channel(evt)->num;
329 unsigned int cfg;
330
331 cfg = hpet_readl(HPET_Tn_CFG(channel));
332 cfg &= ~HPET_TN_PERIODIC;
333 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
334 hpet_writel(cfg, HPET_Tn_CFG(channel));
335
336 return 0;
337}
338
339static int hpet_clkevt_set_state_shutdown(struct clock_event_device *evt)
340{
341 unsigned int channel = clockevent_to_channel(evt)->num;
342 unsigned int cfg;
343
344 cfg = hpet_readl(HPET_Tn_CFG(channel));
345 cfg &= ~HPET_TN_ENABLE;
346 hpet_writel(cfg, HPET_Tn_CFG(channel));
347
348 return 0;
349}
350
351static int hpet_clkevt_legacy_resume(struct clock_event_device *evt)
352{
353 hpet_enable_legacy_int();
354 hpet_print_config();
355 return 0;
356}
357
358static int
359hpet_clkevt_set_next_event(unsigned long delta, struct clock_event_device *evt)
360{
361 unsigned int channel = clockevent_to_channel(evt)->num;
362 u32 cnt;
363 s32 res;
364
365 cnt = hpet_readl(HPET_COUNTER);
366 cnt += (u32) delta;
367 hpet_writel(cnt, HPET_Tn_CMP(channel));
368
369 /*
370 * HPETs are a complete disaster. The compare register is
371 * based on a equal comparison and neither provides a less
372 * than or equal functionality (which would require to take
373 * the wraparound into account) nor a simple count down event
374 * mode. Further the write to the comparator register is
375 * delayed internally up to two HPET clock cycles in certain
376 * chipsets (ATI, ICH9,10). Some newer AMD chipsets have even
377 * longer delays. We worked around that by reading back the
378 * compare register, but that required another workaround for
379 * ICH9,10 chips where the first readout after write can
380 * return the old stale value. We already had a minimum
381 * programming delta of 5us enforced, but a NMI or SMI hitting
382 * between the counter readout and the comparator write can
383 * move us behind that point easily. Now instead of reading
384 * the compare register back several times, we make the ETIME
385 * decision based on the following: Return ETIME if the
386 * counter value after the write is less than HPET_MIN_CYCLES
387 * away from the event or if the counter is already ahead of
388 * the event. The minimum programming delta for the generic
389 * clockevents code is set to 1.5 * HPET_MIN_CYCLES.
390 */
391 res = (s32)(cnt - hpet_readl(HPET_COUNTER));
392
393 return res < HPET_MIN_CYCLES ? -ETIME : 0;
394}
395
396static void hpet_init_clockevent(struct hpet_channel *hc, unsigned int rating)
397{
398 struct clock_event_device *evt = &hc->evt;
399
400 evt->rating = rating;
401 evt->irq = hc->irq;
402 evt->name = hc->name;
403 evt->cpumask = cpumask_of(hc->cpu);
404 evt->set_state_oneshot = hpet_clkevt_set_state_oneshot;
405 evt->set_next_event = hpet_clkevt_set_next_event;
406 evt->set_state_shutdown = hpet_clkevt_set_state_shutdown;
407
408 evt->features = CLOCK_EVT_FEAT_ONESHOT;
409 if (hc->boot_cfg & HPET_TN_PERIODIC) {
410 evt->features |= CLOCK_EVT_FEAT_PERIODIC;
411 evt->set_state_periodic = hpet_clkevt_set_state_periodic;
412 }
413}
414
415static void __init hpet_legacy_clockevent_register(struct hpet_channel *hc)
416{
417 /*
418 * Start HPET with the boot CPU's cpumask and make it global after
419 * the IO_APIC has been initialized.
420 */
421 hc->cpu = boot_cpu_data.cpu_index;
422 strncpy(hc->name, "hpet", sizeof(hc->name));
423 hpet_init_clockevent(hc, 50);
424
425 hc->evt.tick_resume = hpet_clkevt_legacy_resume;
426
427 /*
428 * Legacy horrors and sins from the past. HPET used periodic mode
429 * unconditionally forever on the legacy channel 0. Removing the
430 * below hack and using the conditional in hpet_init_clockevent()
431 * makes at least Qemu and one hardware machine fail to boot.
432 * There are two issues which cause the boot failure:
433 *
434 * #1 After the timer delivery test in IOAPIC and the IOAPIC setup
435 * the next interrupt is not delivered despite the HPET channel
436 * being programmed correctly. Reprogramming the HPET after
437 * switching to IOAPIC makes it work again. After fixing this,
438 * the next issue surfaces:
439 *
440 * #2 Due to the unconditional periodic mode availability the Local
441 * APIC timer calibration can hijack the global clockevents
442 * event handler without causing damage. Using oneshot at this
443 * stage makes if hang because the HPET does not get
444 * reprogrammed due to the handler hijacking. Duh, stupid me!
445 *
446 * Both issues require major surgery and especially the kick HPET
447 * again after enabling IOAPIC results in really nasty hackery.
448 * This 'assume periodic works' magic has survived since HPET
449 * support got added, so it's questionable whether this should be
450 * fixed. Both Qemu and the failing hardware machine support
451 * periodic mode despite the fact that both don't advertise it in
452 * the configuration register and both need that extra kick after
453 * switching to IOAPIC. Seems to be a feature...
454 */
455 hc->evt.features |= CLOCK_EVT_FEAT_PERIODIC;
456 hc->evt.set_state_periodic = hpet_clkevt_set_state_periodic;
457
458 /* Start HPET legacy interrupts */
459 hpet_enable_legacy_int();
460
461 clockevents_config_and_register(&hc->evt, hpet_freq,
462 HPET_MIN_PROG_DELTA, 0x7FFFFFFF);
463 global_clock_event = &hc->evt;
464 pr_debug("Clockevent registered\n");
465}
466
467/*
468 * HPET MSI Support
469 */
470#ifdef CONFIG_PCI_MSI
471
472void hpet_msi_unmask(struct irq_data *data)
473{
474 struct hpet_channel *hc = irq_data_get_irq_handler_data(data);
475 unsigned int cfg;
476
477 cfg = hpet_readl(HPET_Tn_CFG(hc->num));
478 cfg |= HPET_TN_ENABLE | HPET_TN_FSB;
479 hpet_writel(cfg, HPET_Tn_CFG(hc->num));
480}
481
482void hpet_msi_mask(struct irq_data *data)
483{
484 struct hpet_channel *hc = irq_data_get_irq_handler_data(data);
485 unsigned int cfg;
486
487 cfg = hpet_readl(HPET_Tn_CFG(hc->num));
488 cfg &= ~(HPET_TN_ENABLE | HPET_TN_FSB);
489 hpet_writel(cfg, HPET_Tn_CFG(hc->num));
490}
491
492void hpet_msi_write(struct hpet_channel *hc, struct msi_msg *msg)
493{
494 hpet_writel(msg->data, HPET_Tn_ROUTE(hc->num));
495 hpet_writel(msg->address_lo, HPET_Tn_ROUTE(hc->num) + 4);
496}
497
498static int hpet_clkevt_msi_resume(struct clock_event_device *evt)
499{
500 struct hpet_channel *hc = clockevent_to_channel(evt);
501 struct irq_data *data = irq_get_irq_data(hc->irq);
502 struct msi_msg msg;
503
504 /* Restore the MSI msg and unmask the interrupt */
505 irq_chip_compose_msi_msg(data, &msg);
506 hpet_msi_write(hc, &msg);
507 hpet_msi_unmask(data);
508 return 0;
509}
510
511static irqreturn_t hpet_msi_interrupt_handler(int irq, void *data)
512{
513 struct hpet_channel *hc = data;
514 struct clock_event_device *evt = &hc->evt;
515
516 if (!evt->event_handler) {
517 pr_info("Spurious interrupt HPET channel %d\n", hc->num);
518 return IRQ_HANDLED;
519 }
520
521 evt->event_handler(evt);
522 return IRQ_HANDLED;
523}
524
525static int hpet_setup_msi_irq(struct hpet_channel *hc)
526{
527 if (request_irq(hc->irq, hpet_msi_interrupt_handler,
528 IRQF_TIMER | IRQF_NOBALANCING,
529 hc->name, hc))
530 return -1;
531
532 disable_irq(hc->irq);
533 irq_set_affinity(hc->irq, cpumask_of(hc->cpu));
534 enable_irq(hc->irq);
535
536 pr_debug("%s irq %u for MSI\n", hc->name, hc->irq);
537
538 return 0;
539}
540
541/* Invoked from the hotplug callback on @cpu */
542static void init_one_hpet_msi_clockevent(struct hpet_channel *hc, int cpu)
543{
544 struct clock_event_device *evt = &hc->evt;
545
546 hc->cpu = cpu;
547 per_cpu(cpu_hpet_channel, cpu) = hc;
548 hpet_setup_msi_irq(hc);
549
550 hpet_init_clockevent(hc, 110);
551 evt->tick_resume = hpet_clkevt_msi_resume;
552
553 clockevents_config_and_register(evt, hpet_freq, HPET_MIN_PROG_DELTA,
554 0x7FFFFFFF);
555}
556
557static struct hpet_channel *hpet_get_unused_clockevent(void)
558{
559 int i;
560
561 for (i = 0; i < hpet_base.nr_channels; i++) {
562 struct hpet_channel *hc = hpet_base.channels + i;
563
564 if (hc->mode != HPET_MODE_CLOCKEVT || hc->in_use)
565 continue;
566 hc->in_use = 1;
567 return hc;
568 }
569 return NULL;
570}
571
572static int hpet_cpuhp_online(unsigned int cpu)
573{
574 struct hpet_channel *hc = hpet_get_unused_clockevent();
575
576 if (hc)
577 init_one_hpet_msi_clockevent(hc, cpu);
578 return 0;
579}
580
581static int hpet_cpuhp_dead(unsigned int cpu)
582{
583 struct hpet_channel *hc = per_cpu(cpu_hpet_channel, cpu);
584
585 if (!hc)
586 return 0;
587 free_irq(hc->irq, hc);
588 hc->in_use = 0;
589 per_cpu(cpu_hpet_channel, cpu) = NULL;
590 return 0;
591}
592
593static void __init hpet_select_clockevents(void)
594{
595 unsigned int i;
596
597 hpet_base.nr_clockevents = 0;
598
599 /* No point if MSI is disabled or CPU has an Always Runing APIC Timer */
600 if (hpet_msi_disable || boot_cpu_has(X86_FEATURE_ARAT))
601 return;
602
603 hpet_print_config();
604
605 hpet_domain = hpet_create_irq_domain(hpet_blockid);
606 if (!hpet_domain)
607 return;
608
609 for (i = 0; i < hpet_base.nr_channels; i++) {
610 struct hpet_channel *hc = hpet_base.channels + i;
611 int irq;
612
613 if (hc->mode != HPET_MODE_UNUSED)
614 continue;
615
616 /* Only consider HPET channel with MSI support */
617 if (!(hc->boot_cfg & HPET_TN_FSB_CAP))
618 continue;
619
620 sprintf(hc->name, "hpet%d", i);
621
622 irq = hpet_assign_irq(hpet_domain, hc, hc->num);
623 if (irq <= 0)
624 continue;
625
626 hc->irq = irq;
627 hc->mode = HPET_MODE_CLOCKEVT;
628
629 if (++hpet_base.nr_clockevents == num_possible_cpus())
630 break;
631 }
632
633 pr_info("%d channels of %d reserved for per-cpu timers\n",
634 hpet_base.nr_channels, hpet_base.nr_clockevents);
635}
636
637#else
638
639static inline void hpet_select_clockevents(void) { }
640
641#define hpet_cpuhp_online NULL
642#define hpet_cpuhp_dead NULL
643
644#endif
645
646/*
647 * Clock source related code
648 */
649#if defined(CONFIG_SMP) && defined(CONFIG_64BIT)
650/*
651 * Reading the HPET counter is a very slow operation. If a large number of
652 * CPUs are trying to access the HPET counter simultaneously, it can cause
653 * massive delays and slow down system performance dramatically. This may
654 * happen when HPET is the default clock source instead of TSC. For a
655 * really large system with hundreds of CPUs, the slowdown may be so
656 * severe, that it can actually crash the system because of a NMI watchdog
657 * soft lockup, for example.
658 *
659 * If multiple CPUs are trying to access the HPET counter at the same time,
660 * we don't actually need to read the counter multiple times. Instead, the
661 * other CPUs can use the counter value read by the first CPU in the group.
662 *
663 * This special feature is only enabled on x86-64 systems. It is unlikely
664 * that 32-bit x86 systems will have enough CPUs to require this feature
665 * with its associated locking overhead. We also need 64-bit atomic read.
666 *
667 * The lock and the HPET value are stored together and can be read in a
668 * single atomic 64-bit read. It is explicitly assumed that arch_spinlock_t
669 * is 32 bits in size.
670 */
671union hpet_lock {
672 struct {
673 arch_spinlock_t lock;
674 u32 value;
675 };
676 u64 lockval;
677};
678
679static union hpet_lock hpet __cacheline_aligned = {
680 { .lock = __ARCH_SPIN_LOCK_UNLOCKED, },
681};
682
683static u64 read_hpet(struct clocksource *cs)
684{
685 unsigned long flags;
686 union hpet_lock old, new;
687
688 BUILD_BUG_ON(sizeof(union hpet_lock) != 8);
689
690 /*
691 * Read HPET directly if in NMI.
692 */
693 if (in_nmi())
694 return (u64)hpet_readl(HPET_COUNTER);
695
696 /*
697 * Read the current state of the lock and HPET value atomically.
698 */
699 old.lockval = READ_ONCE(hpet.lockval);
700
701 if (arch_spin_is_locked(&old.lock))
702 goto contended;
703
704 local_irq_save(flags);
705 if (arch_spin_trylock(&hpet.lock)) {
706 new.value = hpet_readl(HPET_COUNTER);
707 /*
708 * Use WRITE_ONCE() to prevent store tearing.
709 */
710 WRITE_ONCE(hpet.value, new.value);
711 arch_spin_unlock(&hpet.lock);
712 local_irq_restore(flags);
713 return (u64)new.value;
714 }
715 local_irq_restore(flags);
716
717contended:
718 /*
719 * Contended case
720 * --------------
721 * Wait until the HPET value change or the lock is free to indicate
722 * its value is up-to-date.
723 *
724 * It is possible that old.value has already contained the latest
725 * HPET value while the lock holder was in the process of releasing
726 * the lock. Checking for lock state change will enable us to return
727 * the value immediately instead of waiting for the next HPET reader
728 * to come along.
729 */
730 do {
731 cpu_relax();
732 new.lockval = READ_ONCE(hpet.lockval);
733 } while ((new.value == old.value) && arch_spin_is_locked(&new.lock));
734
735 return (u64)new.value;
736}
737#else
738/*
739 * For UP or 32-bit.
740 */
741static u64 read_hpet(struct clocksource *cs)
742{
743 return (u64)hpet_readl(HPET_COUNTER);
744}
745#endif
746
747static struct clocksource clocksource_hpet = {
748 .name = "hpet",
749 .rating = 250,
750 .read = read_hpet,
751 .mask = HPET_MASK,
752 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
753 .resume = hpet_resume_counter,
754};
755
756/*
757 * AMD SB700 based systems with spread spectrum enabled use a SMM based
758 * HPET emulation to provide proper frequency setting.
759 *
760 * On such systems the SMM code is initialized with the first HPET register
761 * access and takes some time to complete. During this time the config
762 * register reads 0xffffffff. We check for max 1000 loops whether the
763 * config register reads a non-0xffffffff value to make sure that the
764 * HPET is up and running before we proceed any further.
765 *
766 * A counting loop is safe, as the HPET access takes thousands of CPU cycles.
767 *
768 * On non-SB700 based machines this check is only done once and has no
769 * side effects.
770 */
771static bool __init hpet_cfg_working(void)
772{
773 int i;
774
775 for (i = 0; i < 1000; i++) {
776 if (hpet_readl(HPET_CFG) != 0xFFFFFFFF)
777 return true;
778 }
779
780 pr_warn("Config register invalid. Disabling HPET\n");
781 return false;
782}
783
784static bool __init hpet_counting(void)
785{
786 u64 start, now, t1;
787
788 hpet_restart_counter();
789
790 t1 = hpet_readl(HPET_COUNTER);
791 start = rdtsc();
792
793 /*
794 * We don't know the TSC frequency yet, but waiting for
795 * 200000 TSC cycles is safe:
796 * 4 GHz == 50us
797 * 1 GHz == 200us
798 */
799 do {
800 if (t1 != hpet_readl(HPET_COUNTER))
801 return true;
802 now = rdtsc();
803 } while ((now - start) < 200000UL);
804
805 pr_warn("Counter not counting. HPET disabled\n");
806 return false;
807}
808
809/**
810 * hpet_enable - Try to setup the HPET timer. Returns 1 on success.
811 */
812int __init hpet_enable(void)
813{
814 u32 hpet_period, cfg, id, irq;
815 unsigned int i, channels;
816 struct hpet_channel *hc;
817 u64 freq;
818
819 if (!is_hpet_capable())
820 return 0;
821
822 hpet_set_mapping();
823 if (!hpet_virt_address)
824 return 0;
825
826 /* Validate that the config register is working */
827 if (!hpet_cfg_working())
828 goto out_nohpet;
829
830 /*
831 * Read the period and check for a sane value:
832 */
833 hpet_period = hpet_readl(HPET_PERIOD);
834 if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
835 goto out_nohpet;
836
837 /* The period is a femtoseconds value. Convert it to a frequency. */
838 freq = FSEC_PER_SEC;
839 do_div(freq, hpet_period);
840 hpet_freq = freq;
841
842 /*
843 * Read the HPET ID register to retrieve the IRQ routing
844 * information and the number of channels
845 */
846 id = hpet_readl(HPET_ID);
847 hpet_print_config();
848
849 /* This is the HPET channel number which is zero based */
850 channels = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
851
852 /*
853 * The legacy routing mode needs at least two channels, tick timer
854 * and the rtc emulation channel.
855 */
856 if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC) && channels < 2)
857 goto out_nohpet;
858
859 hc = kcalloc(channels, sizeof(*hc), GFP_KERNEL);
860 if (!hc) {
861 pr_warn("Disabling HPET.\n");
862 goto out_nohpet;
863 }
864 hpet_base.channels = hc;
865 hpet_base.nr_channels = channels;
866
867 /* Read, store and sanitize the global configuration */
868 cfg = hpet_readl(HPET_CFG);
869 hpet_base.boot_cfg = cfg;
870 cfg &= ~(HPET_CFG_ENABLE | HPET_CFG_LEGACY);
871 hpet_writel(cfg, HPET_CFG);
872 if (cfg)
873 pr_warn("Global config: Unknown bits %#x\n", cfg);
874
875 /* Read, store and sanitize the per channel configuration */
876 for (i = 0; i < channels; i++, hc++) {
877 hc->num = i;
878
879 cfg = hpet_readl(HPET_Tn_CFG(i));
880 hc->boot_cfg = cfg;
881 irq = (cfg & Tn_INT_ROUTE_CNF_MASK) >> Tn_INT_ROUTE_CNF_SHIFT;
882 hc->irq = irq;
883
884 cfg &= ~(HPET_TN_ENABLE | HPET_TN_LEVEL | HPET_TN_FSB);
885 hpet_writel(cfg, HPET_Tn_CFG(i));
886
887 cfg &= ~(HPET_TN_PERIODIC | HPET_TN_PERIODIC_CAP
888 | HPET_TN_64BIT_CAP | HPET_TN_32BIT | HPET_TN_ROUTE
889 | HPET_TN_FSB | HPET_TN_FSB_CAP);
890 if (cfg)
891 pr_warn("Channel #%u config: Unknown bits %#x\n", i, cfg);
892 }
893 hpet_print_config();
894
895 /*
896 * Validate that the counter is counting. This needs to be done
897 * after sanitizing the config registers to properly deal with
898 * force enabled HPETs.
899 */
900 if (!hpet_counting())
901 goto out_nohpet;
902
903 clocksource_register_hz(&clocksource_hpet, (u32)hpet_freq);
904
905 if (id & HPET_ID_LEGSUP) {
906 hpet_legacy_clockevent_register(&hpet_base.channels[0]);
907 hpet_base.channels[0].mode = HPET_MODE_LEGACY;
908 if (IS_ENABLED(CONFIG_HPET_EMULATE_RTC))
909 hpet_base.channels[1].mode = HPET_MODE_LEGACY;
910 return 1;
911 }
912 return 0;
913
914out_nohpet:
915 kfree(hpet_base.channels);
916 hpet_base.channels = NULL;
917 hpet_base.nr_channels = 0;
918 hpet_clear_mapping();
919 hpet_address = 0;
920 return 0;
921}
922
923/*
924 * The late initialization runs after the PCI quirks have been invoked
925 * which might have detected a system on which the HPET can be enforced.
926 *
927 * Also, the MSI machinery is not working yet when the HPET is initialized
928 * early.
929 *
930 * If the HPET is enabled, then:
931 *
932 * 1) Reserve one channel for /dev/hpet if CONFIG_HPET=y
933 * 2) Reserve up to num_possible_cpus() channels as per CPU clockevents
934 * 3) Setup /dev/hpet if CONFIG_HPET=y
935 * 4) Register hotplug callbacks when clockevents are available
936 */
937static __init int hpet_late_init(void)
938{
939 int ret;
940
941 if (!hpet_address) {
942 if (!force_hpet_address)
943 return -ENODEV;
944
945 hpet_address = force_hpet_address;
946 hpet_enable();
947 }
948
949 if (!hpet_virt_address)
950 return -ENODEV;
951
952 hpet_select_device_channel();
953 hpet_select_clockevents();
954 hpet_reserve_platform_timers();
955 hpet_print_config();
956
957 if (!hpet_base.nr_clockevents)
958 return 0;
959
960 ret = cpuhp_setup_state(CPUHP_AP_X86_HPET_ONLINE, "x86/hpet:online",
961 hpet_cpuhp_online, NULL);
962 if (ret)
963 return ret;
964 ret = cpuhp_setup_state(CPUHP_X86_HPET_DEAD, "x86/hpet:dead", NULL,
965 hpet_cpuhp_dead);
966 if (ret)
967 goto err_cpuhp;
968 return 0;
969
970err_cpuhp:
971 cpuhp_remove_state(CPUHP_AP_X86_HPET_ONLINE);
972 return ret;
973}
974fs_initcall(hpet_late_init);
975
976void hpet_disable(void)
977{
978 unsigned int i;
979 u32 cfg;
980
981 if (!is_hpet_capable() || !hpet_virt_address)
982 return;
983
984 /* Restore boot configuration with the enable bit cleared */
985 cfg = hpet_base.boot_cfg;
986 cfg &= ~HPET_CFG_ENABLE;
987 hpet_writel(cfg, HPET_CFG);
988
989 /* Restore the channel boot configuration */
990 for (i = 0; i < hpet_base.nr_channels; i++)
991 hpet_writel(hpet_base.channels[i].boot_cfg, HPET_Tn_CFG(i));
992
993 /* If the HPET was enabled at boot time, reenable it */
994 if (hpet_base.boot_cfg & HPET_CFG_ENABLE)
995 hpet_writel(hpet_base.boot_cfg, HPET_CFG);
996}
997
998#ifdef CONFIG_HPET_EMULATE_RTC
999
1000/*
1001 * HPET in LegacyReplacement mode eats up the RTC interrupt line. When HPET
1002 * is enabled, we support RTC interrupt functionality in software.
1003 *
1004 * RTC has 3 kinds of interrupts:
1005 *
1006 * 1) Update Interrupt - generate an interrupt, every second, when the
1007 * RTC clock is updated
1008 * 2) Alarm Interrupt - generate an interrupt at a specific time of day
1009 * 3) Periodic Interrupt - generate periodic interrupt, with frequencies
1010 * 2Hz-8192Hz (2Hz-64Hz for non-root user) (all frequencies in powers of 2)
1011 *
1012 * (1) and (2) above are implemented using polling at a frequency of 64 Hz:
1013 * DEFAULT_RTC_INT_FREQ.
1014 *
1015 * The exact frequency is a tradeoff between accuracy and interrupt overhead.
1016 *
1017 * For (3), we use interrupts at 64 Hz, or the user specified periodic frequency,
1018 * if it's higher.
1019 */
1020#include <linux/mc146818rtc.h>
1021#include <linux/rtc.h>
1022
1023#define DEFAULT_RTC_INT_FREQ 64
1024#define DEFAULT_RTC_SHIFT 6
1025#define RTC_NUM_INTS 1
1026
1027static unsigned long hpet_rtc_flags;
1028static int hpet_prev_update_sec;
1029static struct rtc_time hpet_alarm_time;
1030static unsigned long hpet_pie_count;
1031static u32 hpet_t1_cmp;
1032static u32 hpet_default_delta;
1033static u32 hpet_pie_delta;
1034static unsigned long hpet_pie_limit;
1035
1036static rtc_irq_handler irq_handler;
1037
1038/*
1039 * Check that the HPET counter c1 is ahead of c2
1040 */
1041static inline int hpet_cnt_ahead(u32 c1, u32 c2)
1042{
1043 return (s32)(c2 - c1) < 0;
1044}
1045
1046/*
1047 * Registers a IRQ handler.
1048 */
1049int hpet_register_irq_handler(rtc_irq_handler handler)
1050{
1051 if (!is_hpet_enabled())
1052 return -ENODEV;
1053 if (irq_handler)
1054 return -EBUSY;
1055
1056 irq_handler = handler;
1057
1058 return 0;
1059}
1060EXPORT_SYMBOL_GPL(hpet_register_irq_handler);
1061
1062/*
1063 * Deregisters the IRQ handler registered with hpet_register_irq_handler()
1064 * and does cleanup.
1065 */
1066void hpet_unregister_irq_handler(rtc_irq_handler handler)
1067{
1068 if (!is_hpet_enabled())
1069 return;
1070
1071 irq_handler = NULL;
1072 hpet_rtc_flags = 0;
1073}
1074EXPORT_SYMBOL_GPL(hpet_unregister_irq_handler);
1075
1076/*
1077 * Channel 1 for RTC emulation. We use one shot mode, as periodic mode
1078 * is not supported by all HPET implementations for channel 1.
1079 *
1080 * hpet_rtc_timer_init() is called when the rtc is initialized.
1081 */
1082int hpet_rtc_timer_init(void)
1083{
1084 unsigned int cfg, cnt, delta;
1085 unsigned long flags;
1086
1087 if (!is_hpet_enabled())
1088 return 0;
1089
1090 if (!hpet_default_delta) {
1091 struct clock_event_device *evt = &hpet_base.channels[0].evt;
1092 uint64_t clc;
1093
1094 clc = (uint64_t) evt->mult * NSEC_PER_SEC;
1095 clc >>= evt->shift + DEFAULT_RTC_SHIFT;
1096 hpet_default_delta = clc;
1097 }
1098
1099 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1100 delta = hpet_default_delta;
1101 else
1102 delta = hpet_pie_delta;
1103
1104 local_irq_save(flags);
1105
1106 cnt = delta + hpet_readl(HPET_COUNTER);
1107 hpet_writel(cnt, HPET_T1_CMP);
1108 hpet_t1_cmp = cnt;
1109
1110 cfg = hpet_readl(HPET_T1_CFG);
1111 cfg &= ~HPET_TN_PERIODIC;
1112 cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
1113 hpet_writel(cfg, HPET_T1_CFG);
1114
1115 local_irq_restore(flags);
1116
1117 return 1;
1118}
1119EXPORT_SYMBOL_GPL(hpet_rtc_timer_init);
1120
1121static void hpet_disable_rtc_channel(void)
1122{
1123 u32 cfg = hpet_readl(HPET_T1_CFG);
1124
1125 cfg &= ~HPET_TN_ENABLE;
1126 hpet_writel(cfg, HPET_T1_CFG);
1127}
1128
1129/*
1130 * The functions below are called from rtc driver.
1131 * Return 0 if HPET is not being used.
1132 * Otherwise do the necessary changes and return 1.
1133 */
1134int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
1135{
1136 if (!is_hpet_enabled())
1137 return 0;
1138
1139 hpet_rtc_flags &= ~bit_mask;
1140 if (unlikely(!hpet_rtc_flags))
1141 hpet_disable_rtc_channel();
1142
1143 return 1;
1144}
1145EXPORT_SYMBOL_GPL(hpet_mask_rtc_irq_bit);
1146
1147int hpet_set_rtc_irq_bit(unsigned long bit_mask)
1148{
1149 unsigned long oldbits = hpet_rtc_flags;
1150
1151 if (!is_hpet_enabled())
1152 return 0;
1153
1154 hpet_rtc_flags |= bit_mask;
1155
1156 if ((bit_mask & RTC_UIE) && !(oldbits & RTC_UIE))
1157 hpet_prev_update_sec = -1;
1158
1159 if (!oldbits)
1160 hpet_rtc_timer_init();
1161
1162 return 1;
1163}
1164EXPORT_SYMBOL_GPL(hpet_set_rtc_irq_bit);
1165
1166int hpet_set_alarm_time(unsigned char hrs, unsigned char min, unsigned char sec)
1167{
1168 if (!is_hpet_enabled())
1169 return 0;
1170
1171 hpet_alarm_time.tm_hour = hrs;
1172 hpet_alarm_time.tm_min = min;
1173 hpet_alarm_time.tm_sec = sec;
1174
1175 return 1;
1176}
1177EXPORT_SYMBOL_GPL(hpet_set_alarm_time);
1178
1179int hpet_set_periodic_freq(unsigned long freq)
1180{
1181 uint64_t clc;
1182
1183 if (!is_hpet_enabled())
1184 return 0;
1185
1186 if (freq <= DEFAULT_RTC_INT_FREQ) {
1187 hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
1188 } else {
1189 struct clock_event_device *evt = &hpet_base.channels[0].evt;
1190
1191 clc = (uint64_t) evt->mult * NSEC_PER_SEC;
1192 do_div(clc, freq);
1193 clc >>= evt->shift;
1194 hpet_pie_delta = clc;
1195 hpet_pie_limit = 0;
1196 }
1197
1198 return 1;
1199}
1200EXPORT_SYMBOL_GPL(hpet_set_periodic_freq);
1201
1202int hpet_rtc_dropped_irq(void)
1203{
1204 return is_hpet_enabled();
1205}
1206EXPORT_SYMBOL_GPL(hpet_rtc_dropped_irq);
1207
1208static void hpet_rtc_timer_reinit(void)
1209{
1210 unsigned int delta;
1211 int lost_ints = -1;
1212
1213 if (unlikely(!hpet_rtc_flags))
1214 hpet_disable_rtc_channel();
1215
1216 if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
1217 delta = hpet_default_delta;
1218 else
1219 delta = hpet_pie_delta;
1220
1221 /*
1222 * Increment the comparator value until we are ahead of the
1223 * current count.
1224 */
1225 do {
1226 hpet_t1_cmp += delta;
1227 hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
1228 lost_ints++;
1229 } while (!hpet_cnt_ahead(hpet_t1_cmp, hpet_readl(HPET_COUNTER)));
1230
1231 if (lost_ints) {
1232 if (hpet_rtc_flags & RTC_PIE)
1233 hpet_pie_count += lost_ints;
1234 if (printk_ratelimit())
1235 pr_warn("Lost %d RTC interrupts\n", lost_ints);
1236 }
1237}
1238
1239irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
1240{
1241 struct rtc_time curr_time;
1242 unsigned long rtc_int_flag = 0;
1243
1244 hpet_rtc_timer_reinit();
1245 memset(&curr_time, 0, sizeof(struct rtc_time));
1246
1247 if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
1248 mc146818_get_time(&curr_time);
1249
1250 if (hpet_rtc_flags & RTC_UIE &&
1251 curr_time.tm_sec != hpet_prev_update_sec) {
1252 if (hpet_prev_update_sec >= 0)
1253 rtc_int_flag = RTC_UF;
1254 hpet_prev_update_sec = curr_time.tm_sec;
1255 }
1256
1257 if (hpet_rtc_flags & RTC_PIE && ++hpet_pie_count >= hpet_pie_limit) {
1258 rtc_int_flag |= RTC_PF;
1259 hpet_pie_count = 0;
1260 }
1261
1262 if (hpet_rtc_flags & RTC_AIE &&
1263 (curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
1264 (curr_time.tm_min == hpet_alarm_time.tm_min) &&
1265 (curr_time.tm_hour == hpet_alarm_time.tm_hour))
1266 rtc_int_flag |= RTC_AF;
1267
1268 if (rtc_int_flag) {
1269 rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
1270 if (irq_handler)
1271 irq_handler(rtc_int_flag, dev_id);
1272 }
1273 return IRQ_HANDLED;
1274}
1275EXPORT_SYMBOL_GPL(hpet_rtc_interrupt);
1276#endif