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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Transactional memory support routines to reclaim and recheckpoint
4 * transactional process state.
5 *
6 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
7 */
8
9#include <asm/asm-offsets.h>
10#include <asm/ppc_asm.h>
11#include <asm/ppc-opcode.h>
12#include <asm/ptrace.h>
13#include <asm/reg.h>
14#include <asm/bug.h>
15
16#ifdef CONFIG_VSX
17/* See fpu.S, this is borrowed from there */
18#define __SAVE_32FPRS_VSRS(n,c,base) \
19BEGIN_FTR_SECTION \
20 b 2f; \
21END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
22 SAVE_32FPRS(n,base); \
23 b 3f; \
242: SAVE_32VSRS(n,c,base); \
253:
26#define __REST_32FPRS_VSRS(n,c,base) \
27BEGIN_FTR_SECTION \
28 b 2f; \
29END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
30 REST_32FPRS(n,base); \
31 b 3f; \
322: REST_32VSRS(n,c,base); \
333:
34#else
35#define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
36#define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
37#endif
38#define SAVE_32FPRS_VSRS(n,c,base) \
39 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
40#define REST_32FPRS_VSRS(n,c,base) \
41 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
42
43/* Stack frame offsets for local variables. */
44#define TM_FRAME_L0 TM_FRAME_SIZE-16
45#define TM_FRAME_L1 TM_FRAME_SIZE-8
46
47
48/* In order to access the TM SPRs, TM must be enabled. So, do so: */
49_GLOBAL(tm_enable)
50 mfmsr r4
51 li r3, MSR_TM >> 32
52 sldi r3, r3, 32
53 and. r0, r4, r3
54 bne 1f
55 or r4, r4, r3
56 mtmsrd r4
571: blr
58
59_GLOBAL(tm_save_sprs)
60 mfspr r0, SPRN_TFHAR
61 std r0, THREAD_TM_TFHAR(r3)
62 mfspr r0, SPRN_TEXASR
63 std r0, THREAD_TM_TEXASR(r3)
64 mfspr r0, SPRN_TFIAR
65 std r0, THREAD_TM_TFIAR(r3)
66 blr
67
68_GLOBAL(tm_restore_sprs)
69 ld r0, THREAD_TM_TFHAR(r3)
70 mtspr SPRN_TFHAR, r0
71 ld r0, THREAD_TM_TEXASR(r3)
72 mtspr SPRN_TEXASR, r0
73 ld r0, THREAD_TM_TFIAR(r3)
74 mtspr SPRN_TFIAR, r0
75 blr
76
77 /* Passed an 8-bit failure cause as first argument. */
78_GLOBAL(tm_abort)
79 TABORT(R3)
80 blr
81
82/* void tm_reclaim(struct thread_struct *thread,
83 * uint8_t cause)
84 *
85 * - Performs a full reclaim. This destroys outstanding
86 * transactions and updates thread->regs.tm_ckpt_* with the
87 * original checkpointed state. Note that thread->regs is
88 * unchanged.
89 *
90 * Purpose is to both abort transactions of, and preserve the state of,
91 * a transactions at a context switch. We preserve/restore both sets of process
92 * state to restore them when the thread's scheduled again. We continue in
93 * userland as though nothing happened, but when the transaction is resumed
94 * they will abort back to the checkpointed state we save out here.
95 *
96 * Call with IRQs off, stacks get all out of sync for some periods in here!
97 */
98_GLOBAL(tm_reclaim)
99 mfcr r5
100 mflr r0
101 stw r5, 8(r1)
102 std r0, 16(r1)
103 std r2, STK_GOT(r1)
104 stdu r1, -TM_FRAME_SIZE(r1)
105
106 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
107
108 std r3, STK_PARAM(R3)(r1)
109 SAVE_NVGPRS(r1)
110
111 /* We need to setup MSR for VSX register save instructions. */
112 mfmsr r14
113 mr r15, r14
114 ori r15, r15, MSR_FP
115 li r16, 0
116 ori r16, r16, MSR_EE /* IRQs hard off */
117 andc r15, r15, r16
118 oris r15, r15, MSR_VEC@h
119#ifdef CONFIG_VSX
120 BEGIN_FTR_SECTION
121 oris r15,r15, MSR_VSX@h
122 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
123#endif
124 mtmsrd r15
125 std r14, TM_FRAME_L0(r1)
126
127 /* Do sanity check on MSR to make sure we are suspended */
128 li r7, (MSR_TS_S)@higher
129 srdi r6, r14, 32
130 and r6, r6, r7
1311: tdeqi r6, 0
132 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
133
134 /* Stash the stack pointer away for use after reclaim */
135 std r1, PACAR1(r13)
136
137 /* Clear MSR RI since we are about to change r1, EE is already off. */
138 li r5, 0
139 mtmsrd r5, 1
140
141 /*
142 * BE CAREFUL HERE:
143 * At this point we can't take an SLB miss since we have MSR_RI
144 * off. Load only to/from the stack/paca which are in SLB bolted regions
145 * until we turn MSR RI back on.
146 *
147 * The moment we treclaim, ALL of our GPRs will switch
148 * to user register state. (FPRs, CCR etc. also!)
149 * Use an sprg and a tm_scratch in the PACA to shuffle.
150 */
151 TRECLAIM(R4) /* Cause in r4 */
152
153 /* ******************** GPRs ******************** */
154 /* Stash the checkpointed r13 away in the scratch SPR and get the real
155 * paca
156 */
157 SET_SCRATCH0(r13)
158 GET_PACA(r13)
159
160 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
161 * stack pointer back
162 */
163 std r1, PACATMSCRATCH(r13)
164 ld r1, PACAR1(r13)
165
166 /* Store the PPR in r11 and reset to decent value */
167 std r11, GPR11(r1) /* Temporary stash */
168
169 /* Reset MSR RI so we can take SLB faults again */
170 li r11, MSR_RI
171 mtmsrd r11, 1
172
173 mfspr r11, SPRN_PPR
174 HMT_MEDIUM
175
176 /* Now get some more GPRS free */
177 std r7, GPR7(r1) /* Temporary stash */
178 std r12, GPR12(r1) /* '' '' '' */
179 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
180
181 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
182
183 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
184
185 /* Make r7 look like an exception frame so that we
186 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
187 */
188 subi r7, r7, STACK_FRAME_OVERHEAD
189
190 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
191 SAVE_GPR(0, r7) /* user r0 */
192 SAVE_GPR(2, r7) /* user r2 */
193 SAVE_4GPRS(3, r7) /* user r3-r6 */
194 SAVE_GPR(8, r7) /* user r8 */
195 SAVE_GPR(9, r7) /* user r9 */
196 SAVE_GPR(10, r7) /* user r10 */
197 ld r3, PACATMSCRATCH(r13) /* user r1 */
198 ld r4, GPR7(r1) /* user r7 */
199 ld r5, GPR11(r1) /* user r11 */
200 ld r6, GPR12(r1) /* user r12 */
201 GET_SCRATCH0(8) /* user r13 */
202 std r3, GPR1(r7)
203 std r4, GPR7(r7)
204 std r5, GPR11(r7)
205 std r6, GPR12(r7)
206 std r8, GPR13(r7)
207
208 SAVE_NVGPRS(r7) /* user r14-r31 */
209
210 /* ******************** NIP ******************** */
211 mfspr r3, SPRN_TFHAR
212 std r3, _NIP(r7) /* Returns to failhandler */
213 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
214 * but is used in signal return to 'wind back' to the abort handler.
215 */
216
217 /* ******************** CR,LR,CCR,MSR ********** */
218 mfctr r3
219 mflr r4
220 mfcr r5
221 mfxer r6
222
223 std r3, _CTR(r7)
224 std r4, _LINK(r7)
225 std r5, _CCR(r7)
226 std r6, _XER(r7)
227
228
229 /* ******************** TAR, DSCR ********** */
230 mfspr r3, SPRN_TAR
231 mfspr r4, SPRN_DSCR
232
233 std r3, THREAD_TM_TAR(r12)
234 std r4, THREAD_TM_DSCR(r12)
235
236 /* MSR and flags: We don't change CRs, and we don't need to alter
237 * MSR.
238 */
239
240
241 /* ******************** FPR/VR/VSRs ************
242 * After reclaiming, capture the checkpointed FPRs/VRs.
243 *
244 * We enabled VEC/FP/VSX in the msr above, so we can execute these
245 * instructions!
246 */
247 mr r3, r12
248
249 /* Altivec (VEC/VMX/VR)*/
250 addi r7, r3, THREAD_CKVRSTATE
251 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
252 mfvscr v0
253 li r6, VRSTATE_VSCR
254 stvx v0, r7, r6
255
256 /* VRSAVE */
257 mfspr r0, SPRN_VRSAVE
258 std r0, THREAD_CKVRSAVE(r3)
259
260 /* Floating Point (FP) */
261 addi r7, r3, THREAD_CKFPSTATE
262 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
263 mffs fr0
264 stfd fr0,FPSTATE_FPSCR(r7)
265
266
267 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
268 * been updated by the treclaim, to explain to userland the failure
269 * cause (aborted).
270 */
271 mfspr r0, SPRN_TEXASR
272 mfspr r3, SPRN_TFHAR
273 mfspr r4, SPRN_TFIAR
274 std r0, THREAD_TM_TEXASR(r12)
275 std r3, THREAD_TM_TFHAR(r12)
276 std r4, THREAD_TM_TFIAR(r12)
277
278 /* AMR is checkpointed too, but is unsupported by Linux. */
279
280 /* Restore original MSR/IRQ state & clear TM mode */
281 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
282
283 li r15, 0
284 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
285 mtmsrd r14
286
287 REST_NVGPRS(r1)
288
289 addi r1, r1, TM_FRAME_SIZE
290 lwz r4, 8(r1)
291 ld r0, 16(r1)
292 mtcr r4
293 mtlr r0
294 ld r2, STK_GOT(r1)
295
296 /* Load CPU's default DSCR */
297 ld r0, PACA_DSCR_DEFAULT(r13)
298 mtspr SPRN_DSCR, r0
299
300 blr
301
302
303 /* void __tm_recheckpoint(struct thread_struct *thread,
304 * unsigned long orig_msr)
305 * - Restore the checkpointed register state saved by tm_reclaim
306 * when we switch_to a process.
307 *
308 * Call with IRQs off, stacks get all out of sync for
309 * some periods in here!
310 */
311_GLOBAL(__tm_recheckpoint)
312 mfcr r5
313 mflr r0
314 stw r5, 8(r1)
315 std r0, 16(r1)
316 std r2, STK_GOT(r1)
317 stdu r1, -TM_FRAME_SIZE(r1)
318
319 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
320 * This is used for backing up the NVGPRs:
321 */
322 SAVE_NVGPRS(r1)
323
324 /* Load complete register state from ts_ckpt* registers */
325
326 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
327
328 /* Make r7 look like an exception frame so that we
329 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
330 */
331 subi r7, r7, STACK_FRAME_OVERHEAD
332
333 /* We need to setup MSR for FP/VMX/VSX register save instructions. */
334 mfmsr r6
335 mr r5, r6
336 ori r5, r5, MSR_FP
337#ifdef CONFIG_ALTIVEC
338 oris r5, r5, MSR_VEC@h
339#endif
340#ifdef CONFIG_VSX
341 BEGIN_FTR_SECTION
342 oris r5,r5, MSR_VSX@h
343 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
344#endif
345 mtmsrd r5
346
347#ifdef CONFIG_ALTIVEC
348 /*
349 * FP and VEC registers: These are recheckpointed from
350 * thread.ckfp_state and thread.ckvr_state respectively. The
351 * thread.fp_state[] version holds the 'live' (transactional)
352 * and will be loaded subsequently by any FPUnavailable trap.
353 */
354 addi r8, r3, THREAD_CKVRSTATE
355 li r5, VRSTATE_VSCR
356 lvx v0, r8, r5
357 mtvscr v0
358 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
359 ld r5, THREAD_CKVRSAVE(r3)
360 mtspr SPRN_VRSAVE, r5
361#endif
362
363 addi r8, r3, THREAD_CKFPSTATE
364 lfd fr0, FPSTATE_FPSCR(r8)
365 MTFSF_L(fr0)
366 REST_32FPRS_VSRS(0, R4, R8)
367
368 mtmsr r6 /* FP/Vec off again! */
369
370restore_gprs:
371
372 /* ******************** CR,LR,CCR,MSR ********** */
373 ld r4, _CTR(r7)
374 ld r5, _LINK(r7)
375 ld r8, _XER(r7)
376
377 mtctr r4
378 mtlr r5
379 mtxer r8
380
381 /* ******************** TAR ******************** */
382 ld r4, THREAD_TM_TAR(r3)
383 mtspr SPRN_TAR, r4
384
385 /* Load up the PPR and DSCR in GPRs only at this stage */
386 ld r5, THREAD_TM_DSCR(r3)
387 ld r6, THREAD_TM_PPR(r3)
388
389 REST_GPR(0, r7) /* GPR0 */
390 REST_2GPRS(2, r7) /* GPR2-3 */
391 REST_GPR(4, r7) /* GPR4 */
392 REST_4GPRS(8, r7) /* GPR8-11 */
393 REST_2GPRS(12, r7) /* GPR12-13 */
394
395 REST_NVGPRS(r7) /* GPR14-31 */
396
397 /* Load up PPR and DSCR here so we don't run with user values for long
398 */
399 mtspr SPRN_DSCR, r5
400 mtspr SPRN_PPR, r6
401
402 /* Do final sanity check on TEXASR to make sure FS is set. Do this
403 * here before we load up the userspace r1 so any bugs we hit will get
404 * a call chain */
405 mfspr r5, SPRN_TEXASR
406 srdi r5, r5, 16
407 li r6, (TEXASR_FS)@h
408 and r6, r6, r5
4091: tdeqi r6, 0
410 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
411
412 /* Do final sanity check on MSR to make sure we are not transactional
413 * or suspended
414 */
415 mfmsr r6
416 li r5, (MSR_TS_MASK)@higher
417 srdi r6, r6, 32
418 and r6, r6, r5
4191: tdnei r6, 0
420 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
421
422 /* Restore CR */
423 ld r6, _CCR(r7)
424 mtcr r6
425
426 REST_GPR(6, r7)
427
428 /*
429 * Store r1 and r5 on the stack so that we can access them
430 * after we clear MSR RI.
431 */
432
433 REST_GPR(5, r7)
434 std r5, -8(r1)
435 ld r5, GPR1(r7)
436 std r5, -16(r1)
437
438 REST_GPR(7, r7)
439
440 /* Clear MSR RI since we are about to change r1. EE is already off */
441 li r5, 0
442 mtmsrd r5, 1
443
444 /*
445 * BE CAREFUL HERE:
446 * At this point we can't take an SLB miss since we have MSR_RI
447 * off. Load only to/from the stack/paca which are in SLB bolted regions
448 * until we turn MSR RI back on.
449 */
450
451 SET_SCRATCH0(r1)
452 ld r5, -8(r1)
453 ld r1, -16(r1)
454
455 /* Commit register state as checkpointed state: */
456 TRECHKPT
457
458 HMT_MEDIUM
459
460 /* Our transactional state has now changed.
461 *
462 * Now just get out of here. Transactional (current) state will be
463 * updated once restore is called on the return path in the _switch-ed
464 * -to process.
465 */
466
467 GET_PACA(r13)
468 GET_SCRATCH0(r1)
469
470 /* R1 is restored, so we are recoverable again. EE is still off */
471 li r4, MSR_RI
472 mtmsrd r4, 1
473
474 REST_NVGPRS(r1)
475
476 addi r1, r1, TM_FRAME_SIZE
477 lwz r4, 8(r1)
478 ld r0, 16(r1)
479 mtcr r4
480 mtlr r0
481 ld r2, STK_GOT(r1)
482
483 /* Load CPU's default DSCR */
484 ld r0, PACA_DSCR_DEFAULT(r13)
485 mtspr SPRN_DSCR, r0
486
487 blr
488
489 /* ****************************************************************** */
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Transactional memory support routines to reclaim and recheckpoint
4 * transactional process state.
5 *
6 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
7 */
8
9#include <asm/asm-offsets.h>
10#include <asm/ppc_asm.h>
11#include <asm/ppc-opcode.h>
12#include <asm/ptrace.h>
13#include <asm/reg.h>
14#include <asm/bug.h>
15#include <asm/export.h>
16#include <asm/feature-fixups.h>
17
18#ifdef CONFIG_VSX
19/* See fpu.S, this is borrowed from there */
20#define __SAVE_32FPRS_VSRS(n,c,base) \
21BEGIN_FTR_SECTION \
22 b 2f; \
23END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
24 SAVE_32FPRS(n,base); \
25 b 3f; \
262: SAVE_32VSRS(n,c,base); \
273:
28#define __REST_32FPRS_VSRS(n,c,base) \
29BEGIN_FTR_SECTION \
30 b 2f; \
31END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
32 REST_32FPRS(n,base); \
33 b 3f; \
342: REST_32VSRS(n,c,base); \
353:
36#else
37#define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
38#define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
39#endif
40#define SAVE_32FPRS_VSRS(n,c,base) \
41 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
42#define REST_32FPRS_VSRS(n,c,base) \
43 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
44
45/* Stack frame offsets for local variables. */
46#define TM_FRAME_L0 TM_FRAME_SIZE-16
47#define TM_FRAME_L1 TM_FRAME_SIZE-8
48
49
50/* In order to access the TM SPRs, TM must be enabled. So, do so: */
51_GLOBAL(tm_enable)
52 mfmsr r4
53 li r3, MSR_TM >> 32
54 sldi r3, r3, 32
55 and. r0, r4, r3
56 bne 1f
57 or r4, r4, r3
58 mtmsrd r4
591: blr
60EXPORT_SYMBOL_GPL(tm_enable);
61
62_GLOBAL(tm_disable)
63 mfmsr r4
64 li r3, MSR_TM >> 32
65 sldi r3, r3, 32
66 andc r4, r4, r3
67 mtmsrd r4
68 blr
69EXPORT_SYMBOL_GPL(tm_disable);
70
71_GLOBAL(tm_save_sprs)
72 mfspr r0, SPRN_TFHAR
73 std r0, THREAD_TM_TFHAR(r3)
74 mfspr r0, SPRN_TEXASR
75 std r0, THREAD_TM_TEXASR(r3)
76 mfspr r0, SPRN_TFIAR
77 std r0, THREAD_TM_TFIAR(r3)
78 blr
79
80_GLOBAL(tm_restore_sprs)
81 ld r0, THREAD_TM_TFHAR(r3)
82 mtspr SPRN_TFHAR, r0
83 ld r0, THREAD_TM_TEXASR(r3)
84 mtspr SPRN_TEXASR, r0
85 ld r0, THREAD_TM_TFIAR(r3)
86 mtspr SPRN_TFIAR, r0
87 blr
88
89 /* Passed an 8-bit failure cause as first argument. */
90_GLOBAL(tm_abort)
91 TABORT(R3)
92 blr
93EXPORT_SYMBOL_GPL(tm_abort);
94
95/*
96 * void tm_reclaim(struct thread_struct *thread,
97 * uint8_t cause)
98 *
99 * - Performs a full reclaim. This destroys outstanding
100 * transactions and updates thread.ckpt_regs, thread.ckfp_state and
101 * thread.ckvr_state with the original checkpointed state. Note that
102 * thread->regs is unchanged.
103 *
104 * Purpose is to both abort transactions of, and preserve the state of,
105 * a transactions at a context switch. We preserve/restore both sets of process
106 * state to restore them when the thread's scheduled again. We continue in
107 * userland as though nothing happened, but when the transaction is resumed
108 * they will abort back to the checkpointed state we save out here.
109 *
110 * Call with IRQs off, stacks get all out of sync for some periods in here!
111 */
112_GLOBAL(tm_reclaim)
113 mfcr r5
114 mflr r0
115 stw r5, 8(r1)
116 std r0, 16(r1)
117 std r2, STK_GOT(r1)
118 stdu r1, -TM_FRAME_SIZE(r1)
119
120 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
121
122 std r3, STK_PARAM(R3)(r1)
123 SAVE_NVGPRS(r1)
124
125 /* We need to setup MSR for VSX register save instructions. */
126 mfmsr r14
127 mr r15, r14
128 ori r15, r15, MSR_FP
129 li r16, 0
130 ori r16, r16, MSR_EE /* IRQs hard off */
131 andc r15, r15, r16
132 oris r15, r15, MSR_VEC@h
133#ifdef CONFIG_VSX
134 BEGIN_FTR_SECTION
135 oris r15,r15, MSR_VSX@h
136 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
137#endif
138 mtmsrd r15
139 std r14, TM_FRAME_L0(r1)
140
141 /* Do sanity check on MSR to make sure we are suspended */
142 li r7, (MSR_TS_S)@higher
143 srdi r6, r14, 32
144 and r6, r6, r7
1451: tdeqi r6, 0
146 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
147
148 /* Stash the stack pointer away for use after reclaim */
149 std r1, PACAR1(r13)
150
151 /* Clear MSR RI since we are about to use SCRATCH0, EE is already off */
152 li r5, 0
153 mtmsrd r5, 1
154
155 /*
156 * BE CAREFUL HERE:
157 * At this point we can't take an SLB miss since we have MSR_RI
158 * off. Load only to/from the stack/paca which are in SLB bolted regions
159 * until we turn MSR RI back on.
160 *
161 * The moment we treclaim, ALL of our GPRs will switch
162 * to user register state. (FPRs, CCR etc. also!)
163 * Use an sprg and a tm_scratch in the PACA to shuffle.
164 */
165 TRECLAIM(R4) /* Cause in r4 */
166
167 /*
168 * ******************** GPRs ********************
169 * Stash the checkpointed r13 in the scratch SPR and get the real paca.
170 */
171 SET_SCRATCH0(r13)
172 GET_PACA(r13)
173
174 /*
175 * Stash the checkpointed r1 away in paca->tm_scratch and get the real
176 * stack pointer back into r1.
177 */
178 std r1, PACATMSCRATCH(r13)
179 ld r1, PACAR1(r13)
180
181 std r11, GPR11(r1) /* Temporary stash */
182
183 /*
184 * Move the saved user r1 to the kernel stack in case PACATMSCRATCH is
185 * clobbered by an exception once we turn on MSR_RI below.
186 */
187 ld r11, PACATMSCRATCH(r13)
188 std r11, GPR1(r1)
189
190 /*
191 * Store r13 away so we can free up the scratch SPR for the SLB fault
192 * handler (needed once we start accessing the thread_struct).
193 */
194 GET_SCRATCH0(r11)
195 std r11, GPR13(r1)
196
197 /* Reset MSR RI so we can take SLB faults again */
198 li r11, MSR_RI
199 mtmsrd r11, 1
200
201 /* Store the PPR in r11 and reset to decent value */
202 mfspr r11, SPRN_PPR
203 HMT_MEDIUM
204
205 /* Now get some more GPRS free */
206 std r7, GPR7(r1) /* Temporary stash */
207 std r12, GPR12(r1) /* '' '' '' */
208 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
209
210 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
211
212 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
213
214 /*
215 * Make r7 look like an exception frame so that we can use the neat
216 * GPRx(n) macros. r7 is NOT a pt_regs ptr!
217 */
218 subi r7, r7, STACK_FRAME_OVERHEAD
219
220 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
221 SAVE_GPR(0, r7) /* user r0 */
222 SAVE_GPR(2, r7) /* user r2 */
223 SAVE_4GPRS(3, r7) /* user r3-r6 */
224 SAVE_GPR(8, r7) /* user r8 */
225 SAVE_GPR(9, r7) /* user r9 */
226 SAVE_GPR(10, r7) /* user r10 */
227 ld r3, GPR1(r1) /* user r1 */
228 ld r4, GPR7(r1) /* user r7 */
229 ld r5, GPR11(r1) /* user r11 */
230 ld r6, GPR12(r1) /* user r12 */
231 ld r8, GPR13(r1) /* user r13 */
232 std r3, GPR1(r7)
233 std r4, GPR7(r7)
234 std r5, GPR11(r7)
235 std r6, GPR12(r7)
236 std r8, GPR13(r7)
237
238 SAVE_NVGPRS(r7) /* user r14-r31 */
239
240 /* ******************** NIP ******************** */
241 mfspr r3, SPRN_TFHAR
242 std r3, _NIP(r7) /* Returns to failhandler */
243 /*
244 * The checkpointed NIP is ignored when rescheduling/rechkpting,
245 * but is used in signal return to 'wind back' to the abort handler.
246 */
247
248 /* ******************** CR,LR,CCR,MSR ********** */
249 mfctr r3
250 mflr r4
251 mfcr r5
252 mfxer r6
253
254 std r3, _CTR(r7)
255 std r4, _LINK(r7)
256 std r5, _CCR(r7)
257 std r6, _XER(r7)
258
259
260 /* ******************** TAR, DSCR ********** */
261 mfspr r3, SPRN_TAR
262 mfspr r4, SPRN_DSCR
263
264 std r3, THREAD_TM_TAR(r12)
265 std r4, THREAD_TM_DSCR(r12)
266
267 /*
268 * MSR and flags: We don't change CRs, and we don't need to alter MSR.
269 */
270
271
272 /*
273 * ******************** FPR/VR/VSRs ************
274 * After reclaiming, capture the checkpointed FPRs/VRs.
275 *
276 * We enabled VEC/FP/VSX in the msr above, so we can execute these
277 * instructions!
278 */
279 mr r3, r12
280
281 /* Altivec (VEC/VMX/VR)*/
282 addi r7, r3, THREAD_CKVRSTATE
283 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 ckvr_state */
284 mfvscr v0
285 li r6, VRSTATE_VSCR
286 stvx v0, r7, r6
287
288 /* VRSAVE */
289 mfspr r0, SPRN_VRSAVE
290 std r0, THREAD_CKVRSAVE(r3)
291
292 /* Floating Point (FP) */
293 addi r7, r3, THREAD_CKFPSTATE
294 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 ckfp_state */
295 mffs fr0
296 stfd fr0,FPSTATE_FPSCR(r7)
297
298
299 /*
300 * TM regs, incl TEXASR -- these live in thread_struct. Note they've
301 * been updated by the treclaim, to explain to userland the failure
302 * cause (aborted).
303 */
304 mfspr r0, SPRN_TEXASR
305 mfspr r3, SPRN_TFHAR
306 mfspr r4, SPRN_TFIAR
307 std r0, THREAD_TM_TEXASR(r12)
308 std r3, THREAD_TM_TFHAR(r12)
309 std r4, THREAD_TM_TFIAR(r12)
310
311 /* AMR is checkpointed too, but is unsupported by Linux. */
312
313 /* Restore original MSR/IRQ state & clear TM mode */
314 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
315
316 li r15, 0
317 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
318 mtmsrd r14
319
320 REST_NVGPRS(r1)
321
322 addi r1, r1, TM_FRAME_SIZE
323 lwz r4, 8(r1)
324 ld r0, 16(r1)
325 mtcr r4
326 mtlr r0
327 ld r2, STK_GOT(r1)
328
329 /* Load CPU's default DSCR */
330 ld r0, PACA_DSCR_DEFAULT(r13)
331 mtspr SPRN_DSCR, r0
332
333 blr
334
335
336 /*
337 * void __tm_recheckpoint(struct thread_struct *thread)
338 * - Restore the checkpointed register state saved by tm_reclaim
339 * when we switch_to a process.
340 *
341 * Call with IRQs off, stacks get all out of sync for
342 * some periods in here!
343 */
344_GLOBAL(__tm_recheckpoint)
345 mfcr r5
346 mflr r0
347 stw r5, 8(r1)
348 std r0, 16(r1)
349 std r2, STK_GOT(r1)
350 stdu r1, -TM_FRAME_SIZE(r1)
351
352 /*
353 * We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
354 * This is used for backing up the NVGPRs:
355 */
356 SAVE_NVGPRS(r1)
357
358 /* Load complete register state from ts_ckpt* registers */
359
360 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
361
362 /*
363 * Make r7 look like an exception frame so that we can use the neat
364 * GPRx(n) macros. r7 is now NOT a pt_regs ptr!
365 */
366 subi r7, r7, STACK_FRAME_OVERHEAD
367
368 /* We need to setup MSR for FP/VMX/VSX register save instructions. */
369 mfmsr r6
370 mr r5, r6
371 ori r5, r5, MSR_FP
372#ifdef CONFIG_ALTIVEC
373 oris r5, r5, MSR_VEC@h
374#endif
375#ifdef CONFIG_VSX
376 BEGIN_FTR_SECTION
377 oris r5,r5, MSR_VSX@h
378 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
379#endif
380 mtmsrd r5
381
382#ifdef CONFIG_ALTIVEC
383 /*
384 * FP and VEC registers: These are recheckpointed from
385 * thread.ckfp_state and thread.ckvr_state respectively. The
386 * thread.fp_state[] version holds the 'live' (transactional)
387 * and will be loaded subsequently by any FPUnavailable trap.
388 */
389 addi r8, r3, THREAD_CKVRSTATE
390 li r5, VRSTATE_VSCR
391 lvx v0, r8, r5
392 mtvscr v0
393 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
394 ld r5, THREAD_CKVRSAVE(r3)
395 mtspr SPRN_VRSAVE, r5
396#endif
397
398 addi r8, r3, THREAD_CKFPSTATE
399 lfd fr0, FPSTATE_FPSCR(r8)
400 MTFSF_L(fr0)
401 REST_32FPRS_VSRS(0, R4, R8)
402
403 mtmsr r6 /* FP/Vec off again! */
404
405restore_gprs:
406
407 /* ******************** CR,LR,CCR,MSR ********** */
408 ld r4, _CTR(r7)
409 ld r5, _LINK(r7)
410 ld r8, _XER(r7)
411
412 mtctr r4
413 mtlr r5
414 mtxer r8
415
416 /* ******************** TAR ******************** */
417 ld r4, THREAD_TM_TAR(r3)
418 mtspr SPRN_TAR, r4
419
420 /* Load up the PPR and DSCR in GPRs only at this stage */
421 ld r5, THREAD_TM_DSCR(r3)
422 ld r6, THREAD_TM_PPR(r3)
423
424 REST_GPR(0, r7) /* GPR0 */
425 REST_2GPRS(2, r7) /* GPR2-3 */
426 REST_GPR(4, r7) /* GPR4 */
427 REST_4GPRS(8, r7) /* GPR8-11 */
428 REST_2GPRS(12, r7) /* GPR12-13 */
429
430 REST_NVGPRS(r7) /* GPR14-31 */
431
432 /* Load up PPR and DSCR here so we don't run with user values for long */
433 mtspr SPRN_DSCR, r5
434 mtspr SPRN_PPR, r6
435
436 /*
437 * Do final sanity check on TEXASR to make sure FS is set. Do this
438 * here before we load up the userspace r1 so any bugs we hit will get
439 * a call chain.
440 */
441 mfspr r5, SPRN_TEXASR
442 srdi r5, r5, 16
443 li r6, (TEXASR_FS)@h
444 and r6, r6, r5
4451: tdeqi r6, 0
446 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
447
448 /*
449 * Do final sanity check on MSR to make sure we are not transactional
450 * or suspended.
451 */
452 mfmsr r6
453 li r5, (MSR_TS_MASK)@higher
454 srdi r6, r6, 32
455 and r6, r6, r5
4561: tdnei r6, 0
457 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
458
459 /* Restore CR */
460 ld r6, _CCR(r7)
461 mtcr r6
462
463 REST_GPR(6, r7)
464
465 /*
466 * Store r1 and r5 on the stack so that we can access them after we
467 * clear MSR RI.
468 */
469
470 REST_GPR(5, r7)
471 std r5, -8(r1)
472 ld r5, GPR1(r7)
473 std r5, -16(r1)
474
475 REST_GPR(7, r7)
476
477 /* Clear MSR RI since we are about to use SCRATCH0. EE is already off */
478 li r5, 0
479 mtmsrd r5, 1
480
481 /*
482 * BE CAREFUL HERE:
483 * At this point we can't take an SLB miss since we have MSR_RI
484 * off. Load only to/from the stack/paca which are in SLB bolted regions
485 * until we turn MSR RI back on.
486 */
487
488 SET_SCRATCH0(r1)
489 ld r5, -8(r1)
490 ld r1, -16(r1)
491
492 /* Commit register state as checkpointed state: */
493 TRECHKPT
494
495 HMT_MEDIUM
496
497 /*
498 * Our transactional state has now changed.
499 *
500 * Now just get out of here. Transactional (current) state will be
501 * updated once restore is called on the return path in the _switch-ed
502 * -to process.
503 */
504
505 GET_PACA(r13)
506 GET_SCRATCH0(r1)
507
508 /* R1 is restored, so we are recoverable again. EE is still off */
509 li r4, MSR_RI
510 mtmsrd r4, 1
511
512 REST_NVGPRS(r1)
513
514 addi r1, r1, TM_FRAME_SIZE
515 lwz r4, 8(r1)
516 ld r0, 16(r1)
517 mtcr r4
518 mtlr r0
519 ld r2, STK_GOT(r1)
520
521 /* Load CPU's default DSCR */
522 ld r0, PACA_DSCR_DEFAULT(r13)
523 mtspr SPRN_DSCR, r0
524
525 blr
526
527 /* ****************************************************************** */