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1/*
2 * Copyright 2017, Nicholas Piggin, IBM Corporation
3 * Licensed under GPLv2.
4 */
5
6#define pr_fmt(fmt) "dt-cpu-ftrs: " fmt
7
8#include <linux/export.h>
9#include <linux/init.h>
10#include <linux/jump_label.h>
11#include <linux/libfdt.h>
12#include <linux/memblock.h>
13#include <linux/printk.h>
14#include <linux/sched.h>
15#include <linux/string.h>
16#include <linux/threads.h>
17
18#include <asm/cputable.h>
19#include <asm/dt_cpu_ftrs.h>
20#include <asm/mmu.h>
21#include <asm/oprofile_impl.h>
22#include <asm/prom.h>
23#include <asm/setup.h>
24
25
26/* Device-tree visible constants follow */
27#define ISA_V2_07B 2070
28#define ISA_V3_0B 3000
29
30#define USABLE_PR (1U << 0)
31#define USABLE_OS (1U << 1)
32#define USABLE_HV (1U << 2)
33
34#define HV_SUPPORT_HFSCR (1U << 0)
35#define OS_SUPPORT_FSCR (1U << 0)
36
37/* For parsing, we define all bits set as "NONE" case */
38#define HV_SUPPORT_NONE 0xffffffffU
39#define OS_SUPPORT_NONE 0xffffffffU
40
41struct dt_cpu_feature {
42 const char *name;
43 uint32_t isa;
44 uint32_t usable_privilege;
45 uint32_t hv_support;
46 uint32_t os_support;
47 uint32_t hfscr_bit_nr;
48 uint32_t fscr_bit_nr;
49 uint32_t hwcap_bit_nr;
50 /* fdt parsing */
51 unsigned long node;
52 int enabled;
53 int disabled;
54};
55
56#define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8)
57
58#define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \
59 PPC_FEATURE_ARCH_2_06 |\
60 PPC_FEATURE_ICACHE_SNOOP)
61#define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \
62 PPC_FEATURE2_ISEL)
63/*
64 * Set up the base CPU
65 */
66
67extern long __machine_check_early_realmode_p8(struct pt_regs *regs);
68extern long __machine_check_early_realmode_p9(struct pt_regs *regs);
69
70static int hv_mode;
71
72static struct {
73 u64 lpcr;
74 u64 lpcr_clear;
75 u64 hfscr;
76 u64 fscr;
77} system_registers;
78
79static void (*init_pmu_registers)(void);
80
81static void __restore_cpu_cpufeatures(void)
82{
83 u64 lpcr;
84
85 /*
86 * LPCR is restored by the power on engine already. It can be changed
87 * after early init e.g., by radix enable, and we have no unified API
88 * for saving and restoring such SPRs.
89 *
90 * This ->restore hook should really be removed from idle and register
91 * restore moved directly into the idle restore code, because this code
92 * doesn't know how idle is implemented or what it needs restored here.
93 *
94 * The best we can do to accommodate secondary boot and idle restore
95 * for now is "or" LPCR with existing.
96 */
97 lpcr = mfspr(SPRN_LPCR);
98 lpcr |= system_registers.lpcr;
99 lpcr &= ~system_registers.lpcr_clear;
100 mtspr(SPRN_LPCR, lpcr);
101 if (hv_mode) {
102 mtspr(SPRN_LPID, 0);
103 mtspr(SPRN_HFSCR, system_registers.hfscr);
104 mtspr(SPRN_PCR, 0);
105 }
106 mtspr(SPRN_FSCR, system_registers.fscr);
107
108 if (init_pmu_registers)
109 init_pmu_registers();
110}
111
112static char dt_cpu_name[64];
113
114static struct cpu_spec __initdata base_cpu_spec = {
115 .cpu_name = NULL,
116 .cpu_features = CPU_FTRS_DT_CPU_BASE,
117 .cpu_user_features = COMMON_USER_BASE,
118 .cpu_user_features2 = COMMON_USER2_BASE,
119 .mmu_features = 0,
120 .icache_bsize = 32, /* minimum block size, fixed by */
121 .dcache_bsize = 32, /* cache info init. */
122 .num_pmcs = 0,
123 .pmc_type = PPC_PMC_DEFAULT,
124 .oprofile_cpu_type = NULL,
125 .oprofile_type = PPC_OPROFILE_INVALID,
126 .cpu_setup = NULL,
127 .cpu_restore = __restore_cpu_cpufeatures,
128 .machine_check_early = NULL,
129 .platform = NULL,
130};
131
132static void __init cpufeatures_setup_cpu(void)
133{
134 set_cur_cpu_spec(&base_cpu_spec);
135
136 cur_cpu_spec->pvr_mask = -1;
137 cur_cpu_spec->pvr_value = mfspr(SPRN_PVR);
138
139 /* Initialize the base environment -- clear FSCR/HFSCR. */
140 hv_mode = !!(mfmsr() & MSR_HV);
141 if (hv_mode) {
142 /* CPU_FTR_HVMODE is used early in PACA setup */
143 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
144 mtspr(SPRN_HFSCR, 0);
145 }
146 mtspr(SPRN_FSCR, 0);
147
148 /*
149 * LPCR does not get cleared, to match behaviour with secondaries
150 * in __restore_cpu_cpufeatures. Once the idle code is fixed, this
151 * could clear LPCR too.
152 */
153}
154
155static int __init feat_try_enable_unknown(struct dt_cpu_feature *f)
156{
157 if (f->hv_support == HV_SUPPORT_NONE) {
158 } else if (f->hv_support & HV_SUPPORT_HFSCR) {
159 u64 hfscr = mfspr(SPRN_HFSCR);
160 hfscr |= 1UL << f->hfscr_bit_nr;
161 mtspr(SPRN_HFSCR, hfscr);
162 } else {
163 /* Does not have a known recipe */
164 return 0;
165 }
166
167 if (f->os_support == OS_SUPPORT_NONE) {
168 } else if (f->os_support & OS_SUPPORT_FSCR) {
169 u64 fscr = mfspr(SPRN_FSCR);
170 fscr |= 1UL << f->fscr_bit_nr;
171 mtspr(SPRN_FSCR, fscr);
172 } else {
173 /* Does not have a known recipe */
174 return 0;
175 }
176
177 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
178 uint32_t word = f->hwcap_bit_nr / 32;
179 uint32_t bit = f->hwcap_bit_nr % 32;
180
181 if (word == 0)
182 cur_cpu_spec->cpu_user_features |= 1U << bit;
183 else if (word == 1)
184 cur_cpu_spec->cpu_user_features2 |= 1U << bit;
185 else
186 pr_err("%s could not advertise to user (no hwcap bits)\n", f->name);
187 }
188
189 return 1;
190}
191
192static int __init feat_enable(struct dt_cpu_feature *f)
193{
194 if (f->hv_support != HV_SUPPORT_NONE) {
195 if (f->hfscr_bit_nr != -1) {
196 u64 hfscr = mfspr(SPRN_HFSCR);
197 hfscr |= 1UL << f->hfscr_bit_nr;
198 mtspr(SPRN_HFSCR, hfscr);
199 }
200 }
201
202 if (f->os_support != OS_SUPPORT_NONE) {
203 if (f->fscr_bit_nr != -1) {
204 u64 fscr = mfspr(SPRN_FSCR);
205 fscr |= 1UL << f->fscr_bit_nr;
206 mtspr(SPRN_FSCR, fscr);
207 }
208 }
209
210 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
211 uint32_t word = f->hwcap_bit_nr / 32;
212 uint32_t bit = f->hwcap_bit_nr % 32;
213
214 if (word == 0)
215 cur_cpu_spec->cpu_user_features |= 1U << bit;
216 else if (word == 1)
217 cur_cpu_spec->cpu_user_features2 |= 1U << bit;
218 else
219 pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name);
220 }
221
222 return 1;
223}
224
225static int __init feat_disable(struct dt_cpu_feature *f)
226{
227 return 0;
228}
229
230static int __init feat_enable_hv(struct dt_cpu_feature *f)
231{
232 u64 lpcr;
233
234 if (!hv_mode) {
235 pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n");
236 return 0;
237 }
238
239 mtspr(SPRN_LPID, 0);
240
241 lpcr = mfspr(SPRN_LPCR);
242 lpcr &= ~LPCR_LPES0; /* HV external interrupts */
243 mtspr(SPRN_LPCR, lpcr);
244
245 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
246
247 return 1;
248}
249
250static int __init feat_enable_le(struct dt_cpu_feature *f)
251{
252 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE;
253 return 1;
254}
255
256static int __init feat_enable_smt(struct dt_cpu_feature *f)
257{
258 cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
259 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT;
260 return 1;
261}
262
263static int __init feat_enable_idle_nap(struct dt_cpu_feature *f)
264{
265 u64 lpcr;
266
267 /* Set PECE wakeup modes for ISA 207 */
268 lpcr = mfspr(SPRN_LPCR);
269 lpcr |= LPCR_PECE0;
270 lpcr |= LPCR_PECE1;
271 lpcr |= LPCR_PECE2;
272 mtspr(SPRN_LPCR, lpcr);
273
274 return 1;
275}
276
277static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f)
278{
279 cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN;
280
281 return 1;
282}
283
284static int __init feat_enable_idle_stop(struct dt_cpu_feature *f)
285{
286 u64 lpcr;
287
288 /* Set PECE wakeup modes for ISAv3.0B */
289 lpcr = mfspr(SPRN_LPCR);
290 lpcr |= LPCR_PECE0;
291 lpcr |= LPCR_PECE1;
292 lpcr |= LPCR_PECE2;
293 mtspr(SPRN_LPCR, lpcr);
294
295 return 1;
296}
297
298static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f)
299{
300 u64 lpcr;
301
302 lpcr = mfspr(SPRN_LPCR);
303 lpcr &= ~LPCR_ISL;
304
305 /* VRMASD */
306 lpcr |= LPCR_VPM0;
307 lpcr &= ~LPCR_VPM1;
308 lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */
309 mtspr(SPRN_LPCR, lpcr);
310
311 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
312 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
313
314 return 1;
315}
316
317static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
318{
319 u64 lpcr;
320
321 system_registers.lpcr_clear |= (LPCR_ISL | LPCR_UPRT | LPCR_HR);
322 lpcr = mfspr(SPRN_LPCR);
323 lpcr &= ~(LPCR_ISL | LPCR_UPRT | LPCR_HR);
324 mtspr(SPRN_LPCR, lpcr);
325
326 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
327 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
328
329 return 1;
330}
331
332
333static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f)
334{
335#ifdef CONFIG_PPC_RADIX_MMU
336 cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX;
337 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
338 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
339
340 return 1;
341#endif
342 return 0;
343}
344
345static int __init feat_enable_dscr(struct dt_cpu_feature *f)
346{
347 u64 lpcr;
348
349 feat_enable(f);
350
351 lpcr = mfspr(SPRN_LPCR);
352 lpcr &= ~LPCR_DPFD;
353 lpcr |= (4UL << LPCR_DPFD_SH);
354 mtspr(SPRN_LPCR, lpcr);
355
356 return 1;
357}
358
359static void hfscr_pmu_enable(void)
360{
361 u64 hfscr = mfspr(SPRN_HFSCR);
362 hfscr |= PPC_BIT(60);
363 mtspr(SPRN_HFSCR, hfscr);
364}
365
366static void init_pmu_power8(void)
367{
368 if (hv_mode) {
369 mtspr(SPRN_MMCRC, 0);
370 mtspr(SPRN_MMCRH, 0);
371 }
372
373 mtspr(SPRN_MMCRA, 0);
374 mtspr(SPRN_MMCR0, 0);
375 mtspr(SPRN_MMCR1, 0);
376 mtspr(SPRN_MMCR2, 0);
377 mtspr(SPRN_MMCRS, 0);
378}
379
380static int __init feat_enable_mce_power8(struct dt_cpu_feature *f)
381{
382 cur_cpu_spec->platform = "power8";
383 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8;
384
385 return 1;
386}
387
388static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f)
389{
390 hfscr_pmu_enable();
391
392 init_pmu_power8();
393 init_pmu_registers = init_pmu_power8;
394
395 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
396 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
397 if (pvr_version_is(PVR_POWER8E))
398 cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG;
399
400 cur_cpu_spec->num_pmcs = 6;
401 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
402 cur_cpu_spec->oprofile_cpu_type = "ppc64/power8";
403
404 return 1;
405}
406
407static void init_pmu_power9(void)
408{
409 if (hv_mode)
410 mtspr(SPRN_MMCRC, 0);
411
412 mtspr(SPRN_MMCRA, 0);
413 mtspr(SPRN_MMCR0, 0);
414 mtspr(SPRN_MMCR1, 0);
415 mtspr(SPRN_MMCR2, 0);
416}
417
418static int __init feat_enable_mce_power9(struct dt_cpu_feature *f)
419{
420 cur_cpu_spec->platform = "power9";
421 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9;
422
423 return 1;
424}
425
426static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f)
427{
428 hfscr_pmu_enable();
429
430 init_pmu_power9();
431 init_pmu_registers = init_pmu_power9;
432
433 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
434 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
435
436 cur_cpu_spec->num_pmcs = 6;
437 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
438 cur_cpu_spec->oprofile_cpu_type = "ppc64/power9";
439
440 return 1;
441}
442
443static int __init feat_enable_tm(struct dt_cpu_feature *f)
444{
445#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
446 feat_enable(f);
447 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC;
448 return 1;
449#endif
450 return 0;
451}
452
453static int __init feat_enable_fp(struct dt_cpu_feature *f)
454{
455 feat_enable(f);
456 cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE;
457
458 return 1;
459}
460
461static int __init feat_enable_vector(struct dt_cpu_feature *f)
462{
463#ifdef CONFIG_ALTIVEC
464 feat_enable(f);
465 cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC;
466 cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY;
467 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC;
468
469 return 1;
470#endif
471 return 0;
472}
473
474static int __init feat_enable_vsx(struct dt_cpu_feature *f)
475{
476#ifdef CONFIG_VSX
477 feat_enable(f);
478 cur_cpu_spec->cpu_features |= CPU_FTR_VSX;
479 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX;
480
481 return 1;
482#endif
483 return 0;
484}
485
486static int __init feat_enable_purr(struct dt_cpu_feature *f)
487{
488 cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR;
489
490 return 1;
491}
492
493static int __init feat_enable_ebb(struct dt_cpu_feature *f)
494{
495 /*
496 * PPC_FEATURE2_EBB is enabled in PMU init code because it has
497 * historically been related to the PMU facility. This may have
498 * to be decoupled if EBB becomes more generic. For now, follow
499 * existing convention.
500 */
501 f->hwcap_bit_nr = -1;
502 feat_enable(f);
503
504 return 1;
505}
506
507static int __init feat_enable_dbell(struct dt_cpu_feature *f)
508{
509 u64 lpcr;
510
511 /* P9 has an HFSCR for privileged state */
512 feat_enable(f);
513
514 cur_cpu_spec->cpu_features |= CPU_FTR_DBELL;
515
516 lpcr = mfspr(SPRN_LPCR);
517 lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */
518 mtspr(SPRN_LPCR, lpcr);
519
520 return 1;
521}
522
523static int __init feat_enable_hvi(struct dt_cpu_feature *f)
524{
525 u64 lpcr;
526
527 /*
528 * POWER9 XIVE interrupts including in OPAL XICS compatibility
529 * are always delivered as hypervisor virtualization interrupts (HVI)
530 * rather than EE.
531 *
532 * However LPES0 is not set here, in the chance that an EE does get
533 * delivered to the host somehow, the EE handler would not expect it
534 * to be delivered in LPES0 mode (e.g., using SRR[01]). This could
535 * happen if there is a bug in interrupt controller code, or IC is
536 * misconfigured in systemsim.
537 */
538
539 lpcr = mfspr(SPRN_LPCR);
540 lpcr |= LPCR_HVICE; /* enable hvi interrupts */
541 lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */
542 lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */
543 mtspr(SPRN_LPCR, lpcr);
544
545 return 1;
546}
547
548static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
549{
550 cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE;
551
552 return 1;
553}
554
555struct dt_cpu_feature_match {
556 const char *name;
557 int (*enable)(struct dt_cpu_feature *f);
558 u64 cpu_ftr_bit_mask;
559};
560
561static struct dt_cpu_feature_match __initdata
562 dt_cpu_feature_match_table[] = {
563 {"hypervisor", feat_enable_hv, 0},
564 {"big-endian", feat_enable, 0},
565 {"little-endian", feat_enable_le, CPU_FTR_REAL_LE},
566 {"smt", feat_enable_smt, 0},
567 {"interrupt-facilities", feat_enable, 0},
568 {"timer-facilities", feat_enable, 0},
569 {"timer-facilities-v3", feat_enable, 0},
570 {"debug-facilities", feat_enable, 0},
571 {"come-from-address-register", feat_enable, CPU_FTR_CFAR},
572 {"branch-tracing", feat_enable, 0},
573 {"floating-point", feat_enable_fp, 0},
574 {"vector", feat_enable_vector, 0},
575 {"vector-scalar", feat_enable_vsx, 0},
576 {"vector-scalar-v3", feat_enable, 0},
577 {"decimal-floating-point", feat_enable, 0},
578 {"decimal-integer", feat_enable, 0},
579 {"quadword-load-store", feat_enable, 0},
580 {"vector-crypto", feat_enable, 0},
581 {"mmu-hash", feat_enable_mmu_hash, 0},
582 {"mmu-radix", feat_enable_mmu_radix, 0},
583 {"mmu-hash-v3", feat_enable_mmu_hash_v3, 0},
584 {"virtual-page-class-key-protection", feat_enable, 0},
585 {"transactional-memory", feat_enable_tm, CPU_FTR_TM},
586 {"transactional-memory-v3", feat_enable_tm, 0},
587 {"tm-suspend-hypervisor-assist", feat_enable, CPU_FTR_P9_TM_HV_ASSIST},
588 {"tm-suspend-xer-so-bug", feat_enable, CPU_FTR_P9_TM_XER_SO_BUG},
589 {"idle-nap", feat_enable_idle_nap, 0},
590 {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0},
591 {"idle-stop", feat_enable_idle_stop, 0},
592 {"machine-check-power8", feat_enable_mce_power8, 0},
593 {"performance-monitor-power8", feat_enable_pmu_power8, 0},
594 {"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR},
595 {"event-based-branch", feat_enable_ebb, 0},
596 {"target-address-register", feat_enable, 0},
597 {"branch-history-rolling-buffer", feat_enable, 0},
598 {"control-register", feat_enable, CPU_FTR_CTRL},
599 {"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL},
600 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},
601 {"processor-utilization-of-resources-register", feat_enable_purr, 0},
602 {"no-execute", feat_enable, 0},
603 {"strong-access-ordering", feat_enable, CPU_FTR_SAO},
604 {"cache-inhibited-large-page", feat_enable_large_ci, 0},
605 {"coprocessor-icswx", feat_enable, 0},
606 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0},
607 {"program-priority-register", feat_enable, CPU_FTR_HAS_PPR},
608 {"wait", feat_enable, 0},
609 {"atomic-memory-operations", feat_enable, 0},
610 {"branch-v3", feat_enable, 0},
611 {"copy-paste", feat_enable, 0},
612 {"decimal-floating-point-v3", feat_enable, 0},
613 {"decimal-integer-v3", feat_enable, 0},
614 {"fixed-point-v3", feat_enable, 0},
615 {"floating-point-v3", feat_enable, 0},
616 {"group-start-register", feat_enable, 0},
617 {"pc-relative-addressing", feat_enable, 0},
618 {"machine-check-power9", feat_enable_mce_power9, 0},
619 {"performance-monitor-power9", feat_enable_pmu_power9, 0},
620 {"event-based-branch-v3", feat_enable, 0},
621 {"random-number-generator", feat_enable, 0},
622 {"system-call-vectored", feat_disable, 0},
623 {"trace-interrupt-v3", feat_enable, 0},
624 {"vector-v3", feat_enable, 0},
625 {"vector-binary128", feat_enable, 0},
626 {"vector-binary16", feat_enable, 0},
627 {"wait-v3", feat_enable, 0},
628};
629
630static bool __initdata using_dt_cpu_ftrs;
631static bool __initdata enable_unknown = true;
632
633static int __init dt_cpu_ftrs_parse(char *str)
634{
635 if (!str)
636 return 0;
637
638 if (!strcmp(str, "off"))
639 using_dt_cpu_ftrs = false;
640 else if (!strcmp(str, "known"))
641 enable_unknown = false;
642 else
643 return 1;
644
645 return 0;
646}
647early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse);
648
649static void __init cpufeatures_setup_start(u32 isa)
650{
651 pr_info("setup for ISA %d\n", isa);
652
653 if (isa >= 3000) {
654 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300;
655 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00;
656 }
657}
658
659static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f)
660{
661 const struct dt_cpu_feature_match *m;
662 bool known = false;
663 int i;
664
665 for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) {
666 m = &dt_cpu_feature_match_table[i];
667 if (!strcmp(f->name, m->name)) {
668 known = true;
669 if (m->enable(f))
670 break;
671
672 pr_info("not enabling: %s (disabled or unsupported by kernel)\n",
673 f->name);
674 return false;
675 }
676 }
677
678 if (!known && enable_unknown) {
679 if (!feat_try_enable_unknown(f)) {
680 pr_info("not enabling: %s (unknown and unsupported by kernel)\n",
681 f->name);
682 return false;
683 }
684 }
685
686 if (m->cpu_ftr_bit_mask)
687 cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask;
688
689 if (known)
690 pr_debug("enabling: %s\n", f->name);
691 else
692 pr_debug("enabling: %s (unknown)\n", f->name);
693
694 return true;
695}
696
697static __init void cpufeatures_cpu_quirks(void)
698{
699 int version = mfspr(SPRN_PVR);
700
701 /*
702 * Not all quirks can be derived from the cpufeatures device tree.
703 */
704 if ((version & 0xffffff00) == 0x004e0100)
705 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD1;
706 else if ((version & 0xffffefff) == 0x004e0200)
707 ; /* DD2.0 has no feature flag */
708 else if ((version & 0xffffefff) == 0x004e0201)
709 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
710 else if ((version & 0xffffefff) == 0x004e0202) {
711 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_HV_ASSIST;
712 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_XER_SO_BUG;
713 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
714 } else /* DD2.1 and up have DD2_1 */
715 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
716
717 if ((version & 0xffff0000) == 0x004e0000) {
718 cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR);
719 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_BUG;
720 }
721
722 /*
723 * PKEY was not in the initial base or feature node
724 * specification, but it should become optional in the next
725 * cpu feature version sequence.
726 */
727 cur_cpu_spec->cpu_features |= CPU_FTR_PKEY;
728}
729
730static void __init cpufeatures_setup_finished(void)
731{
732 cpufeatures_cpu_quirks();
733
734 if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) {
735 pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n");
736 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
737 }
738
739 /* Make sure powerpc_base_platform is non-NULL */
740 powerpc_base_platform = cur_cpu_spec->platform;
741
742 system_registers.lpcr = mfspr(SPRN_LPCR);
743 system_registers.hfscr = mfspr(SPRN_HFSCR);
744 system_registers.fscr = mfspr(SPRN_FSCR);
745
746 pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
747 cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
748}
749
750static int __init disabled_on_cmdline(void)
751{
752 unsigned long root, chosen;
753 const char *p;
754
755 root = of_get_flat_dt_root();
756 chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
757 if (chosen == -FDT_ERR_NOTFOUND)
758 return false;
759
760 p = of_get_flat_dt_prop(chosen, "bootargs", NULL);
761 if (!p)
762 return false;
763
764 if (strstr(p, "dt_cpu_ftrs=off"))
765 return true;
766
767 return false;
768}
769
770static int __init fdt_find_cpu_features(unsigned long node, const char *uname,
771 int depth, void *data)
772{
773 if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")
774 && of_get_flat_dt_prop(node, "isa", NULL))
775 return 1;
776
777 return 0;
778}
779
780bool __init dt_cpu_ftrs_in_use(void)
781{
782 return using_dt_cpu_ftrs;
783}
784
785bool __init dt_cpu_ftrs_init(void *fdt)
786{
787 using_dt_cpu_ftrs = false;
788
789 /* Setup and verify the FDT, if it fails we just bail */
790 if (!early_init_dt_verify(fdt))
791 return false;
792
793 if (!of_scan_flat_dt(fdt_find_cpu_features, NULL))
794 return false;
795
796 if (disabled_on_cmdline())
797 return false;
798
799 cpufeatures_setup_cpu();
800
801 using_dt_cpu_ftrs = true;
802 return true;
803}
804
805static int nr_dt_cpu_features;
806static struct dt_cpu_feature *dt_cpu_features;
807
808static int __init process_cpufeatures_node(unsigned long node,
809 const char *uname, int i)
810{
811 const __be32 *prop;
812 struct dt_cpu_feature *f;
813 int len;
814
815 f = &dt_cpu_features[i];
816 memset(f, 0, sizeof(struct dt_cpu_feature));
817
818 f->node = node;
819
820 f->name = uname;
821
822 prop = of_get_flat_dt_prop(node, "isa", &len);
823 if (!prop) {
824 pr_warn("%s: missing isa property\n", uname);
825 return 0;
826 }
827 f->isa = be32_to_cpup(prop);
828
829 prop = of_get_flat_dt_prop(node, "usable-privilege", &len);
830 if (!prop) {
831 pr_warn("%s: missing usable-privilege property", uname);
832 return 0;
833 }
834 f->usable_privilege = be32_to_cpup(prop);
835
836 prop = of_get_flat_dt_prop(node, "hv-support", &len);
837 if (prop)
838 f->hv_support = be32_to_cpup(prop);
839 else
840 f->hv_support = HV_SUPPORT_NONE;
841
842 prop = of_get_flat_dt_prop(node, "os-support", &len);
843 if (prop)
844 f->os_support = be32_to_cpup(prop);
845 else
846 f->os_support = OS_SUPPORT_NONE;
847
848 prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len);
849 if (prop)
850 f->hfscr_bit_nr = be32_to_cpup(prop);
851 else
852 f->hfscr_bit_nr = -1;
853 prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len);
854 if (prop)
855 f->fscr_bit_nr = be32_to_cpup(prop);
856 else
857 f->fscr_bit_nr = -1;
858 prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len);
859 if (prop)
860 f->hwcap_bit_nr = be32_to_cpup(prop);
861 else
862 f->hwcap_bit_nr = -1;
863
864 if (f->usable_privilege & USABLE_HV) {
865 if (!(mfmsr() & MSR_HV)) {
866 pr_warn("%s: HV feature passed to guest\n", uname);
867 return 0;
868 }
869
870 if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) {
871 pr_warn("%s: unwanted hfscr_bit_nr\n", uname);
872 return 0;
873 }
874
875 if (f->hv_support == HV_SUPPORT_HFSCR) {
876 if (f->hfscr_bit_nr == -1) {
877 pr_warn("%s: missing hfscr_bit_nr\n", uname);
878 return 0;
879 }
880 }
881 } else {
882 if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) {
883 pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname);
884 return 0;
885 }
886 }
887
888 if (f->usable_privilege & USABLE_OS) {
889 if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) {
890 pr_warn("%s: unwanted fscr_bit_nr\n", uname);
891 return 0;
892 }
893
894 if (f->os_support == OS_SUPPORT_FSCR) {
895 if (f->fscr_bit_nr == -1) {
896 pr_warn("%s: missing fscr_bit_nr\n", uname);
897 return 0;
898 }
899 }
900 } else {
901 if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) {
902 pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname);
903 return 0;
904 }
905 }
906
907 if (!(f->usable_privilege & USABLE_PR)) {
908 if (f->hwcap_bit_nr != -1) {
909 pr_warn("%s: unwanted hwcap_bit_nr\n", uname);
910 return 0;
911 }
912 }
913
914 /* Do all the independent features in the first pass */
915 if (!of_get_flat_dt_prop(node, "dependencies", &len)) {
916 if (cpufeatures_process_feature(f))
917 f->enabled = 1;
918 else
919 f->disabled = 1;
920 }
921
922 return 0;
923}
924
925static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f)
926{
927 const __be32 *prop;
928 int len;
929 int nr_deps;
930 int i;
931
932 if (f->enabled || f->disabled)
933 return;
934
935 prop = of_get_flat_dt_prop(f->node, "dependencies", &len);
936 if (!prop) {
937 pr_warn("%s: missing dependencies property", f->name);
938 return;
939 }
940
941 nr_deps = len / sizeof(int);
942
943 for (i = 0; i < nr_deps; i++) {
944 unsigned long phandle = be32_to_cpu(prop[i]);
945 int j;
946
947 for (j = 0; j < nr_dt_cpu_features; j++) {
948 struct dt_cpu_feature *d = &dt_cpu_features[j];
949
950 if (of_get_flat_dt_phandle(d->node) == phandle) {
951 cpufeatures_deps_enable(d);
952 if (d->disabled) {
953 f->disabled = 1;
954 return;
955 }
956 }
957 }
958 }
959
960 if (cpufeatures_process_feature(f))
961 f->enabled = 1;
962 else
963 f->disabled = 1;
964}
965
966static int __init scan_cpufeatures_subnodes(unsigned long node,
967 const char *uname,
968 void *data)
969{
970 int *count = data;
971
972 process_cpufeatures_node(node, uname, *count);
973
974 (*count)++;
975
976 return 0;
977}
978
979static int __init count_cpufeatures_subnodes(unsigned long node,
980 const char *uname,
981 void *data)
982{
983 int *count = data;
984
985 (*count)++;
986
987 return 0;
988}
989
990static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char
991 *uname, int depth, void *data)
992{
993 const __be32 *prop;
994 int count, i;
995 u32 isa;
996
997 /* We are scanning "ibm,powerpc-cpu-features" nodes only */
998 if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features"))
999 return 0;
1000
1001 prop = of_get_flat_dt_prop(node, "isa", NULL);
1002 if (!prop)
1003 /* We checked before, "can't happen" */
1004 return 0;
1005
1006 isa = be32_to_cpup(prop);
1007
1008 /* Count and allocate space for cpu features */
1009 of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes,
1010 &nr_dt_cpu_features);
1011 dt_cpu_features = __va(
1012 memblock_alloc(sizeof(struct dt_cpu_feature)*
1013 nr_dt_cpu_features, PAGE_SIZE));
1014
1015 cpufeatures_setup_start(isa);
1016
1017 /* Scan nodes into dt_cpu_features and enable those without deps */
1018 count = 0;
1019 of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count);
1020
1021 /* Recursive enable remaining features with dependencies */
1022 for (i = 0; i < nr_dt_cpu_features; i++) {
1023 struct dt_cpu_feature *f = &dt_cpu_features[i];
1024
1025 cpufeatures_deps_enable(f);
1026 }
1027
1028 prop = of_get_flat_dt_prop(node, "display-name", NULL);
1029 if (prop && strlen((char *)prop) != 0) {
1030 strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name));
1031 cur_cpu_spec->cpu_name = dt_cpu_name;
1032 }
1033
1034 cpufeatures_setup_finished();
1035
1036 memblock_free(__pa(dt_cpu_features),
1037 sizeof(struct dt_cpu_feature)*nr_dt_cpu_features);
1038
1039 return 0;
1040}
1041
1042void __init dt_cpu_ftrs_scan(void)
1043{
1044 if (!using_dt_cpu_ftrs)
1045 return;
1046
1047 of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL);
1048}
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright 2017, Nicholas Piggin, IBM Corporation
4 */
5
6#define pr_fmt(fmt) "dt-cpu-ftrs: " fmt
7
8#include <linux/export.h>
9#include <linux/init.h>
10#include <linux/jump_label.h>
11#include <linux/libfdt.h>
12#include <linux/memblock.h>
13#include <linux/printk.h>
14#include <linux/sched.h>
15#include <linux/string.h>
16#include <linux/threads.h>
17
18#include <asm/cputable.h>
19#include <asm/dt_cpu_ftrs.h>
20#include <asm/mmu.h>
21#include <asm/oprofile_impl.h>
22#include <asm/prom.h>
23#include <asm/setup.h>
24
25
26/* Device-tree visible constants follow */
27#define ISA_V3_0B 3000
28#define ISA_V3_1 3100
29
30#define USABLE_PR (1U << 0)
31#define USABLE_OS (1U << 1)
32#define USABLE_HV (1U << 2)
33
34#define HV_SUPPORT_HFSCR (1U << 0)
35#define OS_SUPPORT_FSCR (1U << 0)
36
37/* For parsing, we define all bits set as "NONE" case */
38#define HV_SUPPORT_NONE 0xffffffffU
39#define OS_SUPPORT_NONE 0xffffffffU
40
41struct dt_cpu_feature {
42 const char *name;
43 uint32_t isa;
44 uint32_t usable_privilege;
45 uint32_t hv_support;
46 uint32_t os_support;
47 uint32_t hfscr_bit_nr;
48 uint32_t fscr_bit_nr;
49 uint32_t hwcap_bit_nr;
50 /* fdt parsing */
51 unsigned long node;
52 int enabled;
53 int disabled;
54};
55
56#define MMU_FTRS_HASH_BASE (MMU_FTRS_POWER8)
57
58#define COMMON_USER_BASE (PPC_FEATURE_32 | PPC_FEATURE_64 | \
59 PPC_FEATURE_ARCH_2_06 |\
60 PPC_FEATURE_ICACHE_SNOOP)
61#define COMMON_USER2_BASE (PPC_FEATURE2_ARCH_2_07 | \
62 PPC_FEATURE2_ISEL)
63/*
64 * Set up the base CPU
65 */
66
67static int hv_mode;
68
69static struct {
70 u64 lpcr;
71 u64 lpcr_clear;
72 u64 hfscr;
73 u64 fscr;
74 u64 pcr;
75} system_registers;
76
77static void (*init_pmu_registers)(void);
78
79static void __restore_cpu_cpufeatures(void)
80{
81 u64 lpcr;
82
83 /*
84 * LPCR is restored by the power on engine already. It can be changed
85 * after early init e.g., by radix enable, and we have no unified API
86 * for saving and restoring such SPRs.
87 *
88 * This ->restore hook should really be removed from idle and register
89 * restore moved directly into the idle restore code, because this code
90 * doesn't know how idle is implemented or what it needs restored here.
91 *
92 * The best we can do to accommodate secondary boot and idle restore
93 * for now is "or" LPCR with existing.
94 */
95 lpcr = mfspr(SPRN_LPCR);
96 lpcr |= system_registers.lpcr;
97 lpcr &= ~system_registers.lpcr_clear;
98 mtspr(SPRN_LPCR, lpcr);
99 if (hv_mode) {
100 mtspr(SPRN_LPID, 0);
101 mtspr(SPRN_HFSCR, system_registers.hfscr);
102 mtspr(SPRN_PCR, system_registers.pcr);
103 }
104 mtspr(SPRN_FSCR, system_registers.fscr);
105
106 if (init_pmu_registers)
107 init_pmu_registers();
108}
109
110static char dt_cpu_name[64];
111
112static struct cpu_spec __initdata base_cpu_spec = {
113 .cpu_name = NULL,
114 .cpu_features = CPU_FTRS_DT_CPU_BASE,
115 .cpu_user_features = COMMON_USER_BASE,
116 .cpu_user_features2 = COMMON_USER2_BASE,
117 .mmu_features = 0,
118 .icache_bsize = 32, /* minimum block size, fixed by */
119 .dcache_bsize = 32, /* cache info init. */
120 .num_pmcs = 0,
121 .pmc_type = PPC_PMC_DEFAULT,
122 .oprofile_cpu_type = NULL,
123 .oprofile_type = PPC_OPROFILE_INVALID,
124 .cpu_setup = NULL,
125 .cpu_restore = __restore_cpu_cpufeatures,
126 .machine_check_early = NULL,
127 .platform = NULL,
128};
129
130static void __init cpufeatures_setup_cpu(void)
131{
132 set_cur_cpu_spec(&base_cpu_spec);
133
134 cur_cpu_spec->pvr_mask = -1;
135 cur_cpu_spec->pvr_value = mfspr(SPRN_PVR);
136
137 /* Initialize the base environment -- clear FSCR/HFSCR. */
138 hv_mode = !!(mfmsr() & MSR_HV);
139 if (hv_mode) {
140 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
141 mtspr(SPRN_HFSCR, 0);
142 }
143 mtspr(SPRN_FSCR, 0);
144 mtspr(SPRN_PCR, PCR_MASK);
145
146 /*
147 * LPCR does not get cleared, to match behaviour with secondaries
148 * in __restore_cpu_cpufeatures. Once the idle code is fixed, this
149 * could clear LPCR too.
150 */
151}
152
153static int __init feat_try_enable_unknown(struct dt_cpu_feature *f)
154{
155 if (f->hv_support == HV_SUPPORT_NONE) {
156 } else if (f->hv_support & HV_SUPPORT_HFSCR) {
157 u64 hfscr = mfspr(SPRN_HFSCR);
158 hfscr |= 1UL << f->hfscr_bit_nr;
159 mtspr(SPRN_HFSCR, hfscr);
160 } else {
161 /* Does not have a known recipe */
162 return 0;
163 }
164
165 if (f->os_support == OS_SUPPORT_NONE) {
166 } else if (f->os_support & OS_SUPPORT_FSCR) {
167 u64 fscr = mfspr(SPRN_FSCR);
168 fscr |= 1UL << f->fscr_bit_nr;
169 mtspr(SPRN_FSCR, fscr);
170 } else {
171 /* Does not have a known recipe */
172 return 0;
173 }
174
175 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
176 uint32_t word = f->hwcap_bit_nr / 32;
177 uint32_t bit = f->hwcap_bit_nr % 32;
178
179 if (word == 0)
180 cur_cpu_spec->cpu_user_features |= 1U << bit;
181 else if (word == 1)
182 cur_cpu_spec->cpu_user_features2 |= 1U << bit;
183 else
184 pr_err("%s could not advertise to user (no hwcap bits)\n", f->name);
185 }
186
187 return 1;
188}
189
190static int __init feat_enable(struct dt_cpu_feature *f)
191{
192 if (f->hv_support != HV_SUPPORT_NONE) {
193 if (f->hfscr_bit_nr != -1) {
194 u64 hfscr = mfspr(SPRN_HFSCR);
195 hfscr |= 1UL << f->hfscr_bit_nr;
196 mtspr(SPRN_HFSCR, hfscr);
197 }
198 }
199
200 if (f->os_support != OS_SUPPORT_NONE) {
201 if (f->fscr_bit_nr != -1) {
202 u64 fscr = mfspr(SPRN_FSCR);
203 fscr |= 1UL << f->fscr_bit_nr;
204 mtspr(SPRN_FSCR, fscr);
205 }
206 }
207
208 if ((f->usable_privilege & USABLE_PR) && (f->hwcap_bit_nr != -1)) {
209 uint32_t word = f->hwcap_bit_nr / 32;
210 uint32_t bit = f->hwcap_bit_nr % 32;
211
212 if (word == 0)
213 cur_cpu_spec->cpu_user_features |= 1U << bit;
214 else if (word == 1)
215 cur_cpu_spec->cpu_user_features2 |= 1U << bit;
216 else
217 pr_err("CPU feature: %s could not advertise to user (no hwcap bits)\n", f->name);
218 }
219
220 return 1;
221}
222
223static int __init feat_disable(struct dt_cpu_feature *f)
224{
225 return 0;
226}
227
228static int __init feat_enable_hv(struct dt_cpu_feature *f)
229{
230 u64 lpcr;
231
232 if (!hv_mode) {
233 pr_err("CPU feature hypervisor present in device tree but HV mode not enabled in the CPU. Ignoring.\n");
234 return 0;
235 }
236
237 mtspr(SPRN_LPID, 0);
238
239 lpcr = mfspr(SPRN_LPCR);
240 lpcr &= ~LPCR_LPES0; /* HV external interrupts */
241 mtspr(SPRN_LPCR, lpcr);
242
243 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
244
245 return 1;
246}
247
248static int __init feat_enable_le(struct dt_cpu_feature *f)
249{
250 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_TRUE_LE;
251 return 1;
252}
253
254static int __init feat_enable_smt(struct dt_cpu_feature *f)
255{
256 cur_cpu_spec->cpu_features |= CPU_FTR_SMT;
257 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_SMT;
258 return 1;
259}
260
261static int __init feat_enable_idle_nap(struct dt_cpu_feature *f)
262{
263 u64 lpcr;
264
265 /* Set PECE wakeup modes for ISA 207 */
266 lpcr = mfspr(SPRN_LPCR);
267 lpcr |= LPCR_PECE0;
268 lpcr |= LPCR_PECE1;
269 lpcr |= LPCR_PECE2;
270 mtspr(SPRN_LPCR, lpcr);
271
272 return 1;
273}
274
275static int __init feat_enable_align_dsisr(struct dt_cpu_feature *f)
276{
277 cur_cpu_spec->cpu_features &= ~CPU_FTR_NODSISRALIGN;
278
279 return 1;
280}
281
282static int __init feat_enable_idle_stop(struct dt_cpu_feature *f)
283{
284 u64 lpcr;
285
286 /* Set PECE wakeup modes for ISAv3.0B */
287 lpcr = mfspr(SPRN_LPCR);
288 lpcr |= LPCR_PECE0;
289 lpcr |= LPCR_PECE1;
290 lpcr |= LPCR_PECE2;
291 mtspr(SPRN_LPCR, lpcr);
292
293 return 1;
294}
295
296static int __init feat_enable_mmu_hash(struct dt_cpu_feature *f)
297{
298 u64 lpcr;
299
300 lpcr = mfspr(SPRN_LPCR);
301 lpcr &= ~LPCR_ISL;
302
303 /* VRMASD */
304 lpcr |= LPCR_VPM0;
305 lpcr &= ~LPCR_VPM1;
306 lpcr |= 0x10UL << LPCR_VRMASD_SH; /* L=1 LP=00 */
307 mtspr(SPRN_LPCR, lpcr);
308
309 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
310 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
311
312 return 1;
313}
314
315static int __init feat_enable_mmu_hash_v3(struct dt_cpu_feature *f)
316{
317 u64 lpcr;
318
319 system_registers.lpcr_clear |= (LPCR_ISL | LPCR_UPRT | LPCR_HR);
320 lpcr = mfspr(SPRN_LPCR);
321 lpcr &= ~(LPCR_ISL | LPCR_UPRT | LPCR_HR);
322 mtspr(SPRN_LPCR, lpcr);
323
324 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
325 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
326
327 return 1;
328}
329
330
331static int __init feat_enable_mmu_radix(struct dt_cpu_feature *f)
332{
333#ifdef CONFIG_PPC_RADIX_MMU
334 cur_cpu_spec->mmu_features |= MMU_FTR_TYPE_RADIX;
335 cur_cpu_spec->mmu_features |= MMU_FTRS_HASH_BASE;
336 cur_cpu_spec->mmu_features |= MMU_FTR_GTSE;
337 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_MMU;
338
339 return 1;
340#endif
341 return 0;
342}
343
344static int __init feat_enable_dscr(struct dt_cpu_feature *f)
345{
346 u64 lpcr;
347
348 /*
349 * Linux relies on FSCR[DSCR] being clear, so that we can take the
350 * facility unavailable interrupt and track the task's usage of DSCR.
351 * See facility_unavailable_exception().
352 * Clear the bit here so that feat_enable() doesn't set it.
353 */
354 f->fscr_bit_nr = -1;
355
356 feat_enable(f);
357
358 lpcr = mfspr(SPRN_LPCR);
359 lpcr &= ~LPCR_DPFD;
360 lpcr |= (4UL << LPCR_DPFD_SH);
361 mtspr(SPRN_LPCR, lpcr);
362
363 return 1;
364}
365
366static void hfscr_pmu_enable(void)
367{
368 u64 hfscr = mfspr(SPRN_HFSCR);
369 hfscr |= PPC_BIT(60);
370 mtspr(SPRN_HFSCR, hfscr);
371}
372
373static void init_pmu_power8(void)
374{
375 if (hv_mode) {
376 mtspr(SPRN_MMCRC, 0);
377 mtspr(SPRN_MMCRH, 0);
378 }
379
380 mtspr(SPRN_MMCRA, 0);
381 mtspr(SPRN_MMCR0, 0);
382 mtspr(SPRN_MMCR1, 0);
383 mtspr(SPRN_MMCR2, 0);
384 mtspr(SPRN_MMCRS, 0);
385}
386
387static int __init feat_enable_mce_power8(struct dt_cpu_feature *f)
388{
389 cur_cpu_spec->platform = "power8";
390 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p8;
391
392 return 1;
393}
394
395static int __init feat_enable_pmu_power8(struct dt_cpu_feature *f)
396{
397 hfscr_pmu_enable();
398
399 init_pmu_power8();
400 init_pmu_registers = init_pmu_power8;
401
402 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
403 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
404 if (pvr_version_is(PVR_POWER8E))
405 cur_cpu_spec->cpu_features |= CPU_FTR_PMAO_BUG;
406
407 cur_cpu_spec->num_pmcs = 6;
408 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
409 cur_cpu_spec->oprofile_cpu_type = "ppc64/power8";
410
411 return 1;
412}
413
414static void init_pmu_power9(void)
415{
416 if (hv_mode)
417 mtspr(SPRN_MMCRC, 0);
418
419 mtspr(SPRN_MMCRA, 0);
420 mtspr(SPRN_MMCR0, 0);
421 mtspr(SPRN_MMCR1, 0);
422 mtspr(SPRN_MMCR2, 0);
423}
424
425static int __init feat_enable_mce_power9(struct dt_cpu_feature *f)
426{
427 cur_cpu_spec->platform = "power9";
428 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p9;
429
430 return 1;
431}
432
433static int __init feat_enable_pmu_power9(struct dt_cpu_feature *f)
434{
435 hfscr_pmu_enable();
436
437 init_pmu_power9();
438 init_pmu_registers = init_pmu_power9;
439
440 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
441 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
442
443 cur_cpu_spec->num_pmcs = 6;
444 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
445 cur_cpu_spec->oprofile_cpu_type = "ppc64/power9";
446
447 return 1;
448}
449
450static void init_pmu_power10(void)
451{
452 init_pmu_power9();
453
454 mtspr(SPRN_MMCR3, 0);
455 mtspr(SPRN_MMCRA, MMCRA_BHRB_DISABLE);
456}
457
458static int __init feat_enable_pmu_power10(struct dt_cpu_feature *f)
459{
460 hfscr_pmu_enable();
461
462 init_pmu_power10();
463 init_pmu_registers = init_pmu_power10;
464
465 cur_cpu_spec->cpu_features |= CPU_FTR_MMCRA;
466 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_PSERIES_PERFMON_COMPAT;
467
468 cur_cpu_spec->num_pmcs = 6;
469 cur_cpu_spec->pmc_type = PPC_PMC_IBM;
470 cur_cpu_spec->oprofile_cpu_type = "ppc64/power10";
471
472 return 1;
473}
474
475static int __init feat_enable_mce_power10(struct dt_cpu_feature *f)
476{
477 cur_cpu_spec->platform = "power10";
478 cur_cpu_spec->machine_check_early = __machine_check_early_realmode_p10;
479
480 return 1;
481}
482
483static int __init feat_enable_tm(struct dt_cpu_feature *f)
484{
485#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
486 feat_enable(f);
487 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NOSC;
488 return 1;
489#endif
490 return 0;
491}
492
493static int __init feat_enable_fp(struct dt_cpu_feature *f)
494{
495 feat_enable(f);
496 cur_cpu_spec->cpu_features &= ~CPU_FTR_FPU_UNAVAILABLE;
497
498 return 1;
499}
500
501static int __init feat_enable_vector(struct dt_cpu_feature *f)
502{
503#ifdef CONFIG_ALTIVEC
504 feat_enable(f);
505 cur_cpu_spec->cpu_features |= CPU_FTR_ALTIVEC;
506 cur_cpu_spec->cpu_features |= CPU_FTR_VMX_COPY;
507 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_ALTIVEC;
508
509 return 1;
510#endif
511 return 0;
512}
513
514static int __init feat_enable_vsx(struct dt_cpu_feature *f)
515{
516#ifdef CONFIG_VSX
517 feat_enable(f);
518 cur_cpu_spec->cpu_features |= CPU_FTR_VSX;
519 cur_cpu_spec->cpu_user_features |= PPC_FEATURE_HAS_VSX;
520
521 return 1;
522#endif
523 return 0;
524}
525
526static int __init feat_enable_purr(struct dt_cpu_feature *f)
527{
528 cur_cpu_spec->cpu_features |= CPU_FTR_PURR | CPU_FTR_SPURR;
529
530 return 1;
531}
532
533static int __init feat_enable_ebb(struct dt_cpu_feature *f)
534{
535 /*
536 * PPC_FEATURE2_EBB is enabled in PMU init code because it has
537 * historically been related to the PMU facility. This may have
538 * to be decoupled if EBB becomes more generic. For now, follow
539 * existing convention.
540 */
541 f->hwcap_bit_nr = -1;
542 feat_enable(f);
543
544 return 1;
545}
546
547static int __init feat_enable_dbell(struct dt_cpu_feature *f)
548{
549 u64 lpcr;
550
551 /* P9 has an HFSCR for privileged state */
552 feat_enable(f);
553
554 cur_cpu_spec->cpu_features |= CPU_FTR_DBELL;
555
556 lpcr = mfspr(SPRN_LPCR);
557 lpcr |= LPCR_PECEDH; /* hyp doorbell wakeup */
558 mtspr(SPRN_LPCR, lpcr);
559
560 return 1;
561}
562
563static int __init feat_enable_hvi(struct dt_cpu_feature *f)
564{
565 u64 lpcr;
566
567 /*
568 * POWER9 XIVE interrupts including in OPAL XICS compatibility
569 * are always delivered as hypervisor virtualization interrupts (HVI)
570 * rather than EE.
571 *
572 * However LPES0 is not set here, in the chance that an EE does get
573 * delivered to the host somehow, the EE handler would not expect it
574 * to be delivered in LPES0 mode (e.g., using SRR[01]). This could
575 * happen if there is a bug in interrupt controller code, or IC is
576 * misconfigured in systemsim.
577 */
578
579 lpcr = mfspr(SPRN_LPCR);
580 lpcr |= LPCR_HVICE; /* enable hvi interrupts */
581 lpcr |= LPCR_HEIC; /* disable ee interrupts when MSR_HV */
582 lpcr |= LPCR_PECE_HVEE; /* hvi can wake from stop */
583 mtspr(SPRN_LPCR, lpcr);
584
585 return 1;
586}
587
588static int __init feat_enable_large_ci(struct dt_cpu_feature *f)
589{
590 cur_cpu_spec->mmu_features |= MMU_FTR_CI_LARGE_PAGE;
591
592 return 1;
593}
594
595static int __init feat_enable_mma(struct dt_cpu_feature *f)
596{
597 u64 pcr;
598
599 feat_enable(f);
600 pcr = mfspr(SPRN_PCR);
601 pcr &= ~PCR_MMA_DIS;
602 mtspr(SPRN_PCR, pcr);
603
604 return 1;
605}
606
607struct dt_cpu_feature_match {
608 const char *name;
609 int (*enable)(struct dt_cpu_feature *f);
610 u64 cpu_ftr_bit_mask;
611};
612
613static struct dt_cpu_feature_match __initdata
614 dt_cpu_feature_match_table[] = {
615 {"hypervisor", feat_enable_hv, 0},
616 {"big-endian", feat_enable, 0},
617 {"little-endian", feat_enable_le, CPU_FTR_REAL_LE},
618 {"smt", feat_enable_smt, 0},
619 {"interrupt-facilities", feat_enable, 0},
620 {"system-call-vectored", feat_enable, 0},
621 {"timer-facilities", feat_enable, 0},
622 {"timer-facilities-v3", feat_enable, 0},
623 {"debug-facilities", feat_enable, 0},
624 {"come-from-address-register", feat_enable, CPU_FTR_CFAR},
625 {"branch-tracing", feat_enable, 0},
626 {"floating-point", feat_enable_fp, 0},
627 {"vector", feat_enable_vector, 0},
628 {"vector-scalar", feat_enable_vsx, 0},
629 {"vector-scalar-v3", feat_enable, 0},
630 {"decimal-floating-point", feat_enable, 0},
631 {"decimal-integer", feat_enable, 0},
632 {"quadword-load-store", feat_enable, 0},
633 {"vector-crypto", feat_enable, 0},
634 {"mmu-hash", feat_enable_mmu_hash, 0},
635 {"mmu-radix", feat_enable_mmu_radix, 0},
636 {"mmu-hash-v3", feat_enable_mmu_hash_v3, 0},
637 {"virtual-page-class-key-protection", feat_enable, 0},
638 {"transactional-memory", feat_enable_tm, CPU_FTR_TM},
639 {"transactional-memory-v3", feat_enable_tm, 0},
640 {"tm-suspend-hypervisor-assist", feat_enable, CPU_FTR_P9_TM_HV_ASSIST},
641 {"tm-suspend-xer-so-bug", feat_enable, CPU_FTR_P9_TM_XER_SO_BUG},
642 {"idle-nap", feat_enable_idle_nap, 0},
643 {"alignment-interrupt-dsisr", feat_enable_align_dsisr, 0},
644 {"idle-stop", feat_enable_idle_stop, 0},
645 {"machine-check-power8", feat_enable_mce_power8, 0},
646 {"performance-monitor-power8", feat_enable_pmu_power8, 0},
647 {"data-stream-control-register", feat_enable_dscr, CPU_FTR_DSCR},
648 {"event-based-branch", feat_enable_ebb, 0},
649 {"target-address-register", feat_enable, 0},
650 {"branch-history-rolling-buffer", feat_enable, 0},
651 {"control-register", feat_enable, CPU_FTR_CTRL},
652 {"processor-control-facility", feat_enable_dbell, CPU_FTR_DBELL},
653 {"processor-control-facility-v3", feat_enable_dbell, CPU_FTR_DBELL},
654 {"processor-utilization-of-resources-register", feat_enable_purr, 0},
655 {"no-execute", feat_enable, 0},
656 {"strong-access-ordering", feat_enable, CPU_FTR_SAO},
657 {"cache-inhibited-large-page", feat_enable_large_ci, 0},
658 {"coprocessor-icswx", feat_enable, 0},
659 {"hypervisor-virtualization-interrupt", feat_enable_hvi, 0},
660 {"program-priority-register", feat_enable, CPU_FTR_HAS_PPR},
661 {"wait", feat_enable, 0},
662 {"atomic-memory-operations", feat_enable, 0},
663 {"branch-v3", feat_enable, 0},
664 {"copy-paste", feat_enable, 0},
665 {"decimal-floating-point-v3", feat_enable, 0},
666 {"decimal-integer-v3", feat_enable, 0},
667 {"fixed-point-v3", feat_enable, 0},
668 {"floating-point-v3", feat_enable, 0},
669 {"group-start-register", feat_enable, 0},
670 {"pc-relative-addressing", feat_enable, 0},
671 {"machine-check-power9", feat_enable_mce_power9, 0},
672 {"machine-check-power10", feat_enable_mce_power10, 0},
673 {"performance-monitor-power9", feat_enable_pmu_power9, 0},
674 {"performance-monitor-power10", feat_enable_pmu_power10, 0},
675 {"event-based-branch-v3", feat_enable, 0},
676 {"random-number-generator", feat_enable, 0},
677 {"system-call-vectored", feat_disable, 0},
678 {"trace-interrupt-v3", feat_enable, 0},
679 {"vector-v3", feat_enable, 0},
680 {"vector-binary128", feat_enable, 0},
681 {"vector-binary16", feat_enable, 0},
682 {"wait-v3", feat_enable, 0},
683 {"prefix-instructions", feat_enable, 0},
684 {"matrix-multiply-assist", feat_enable_mma, 0},
685 {"debug-facilities-v31", feat_enable, CPU_FTR_DAWR1},
686};
687
688static bool __initdata using_dt_cpu_ftrs;
689static bool __initdata enable_unknown = true;
690
691static int __init dt_cpu_ftrs_parse(char *str)
692{
693 if (!str)
694 return 0;
695
696 if (!strcmp(str, "off"))
697 using_dt_cpu_ftrs = false;
698 else if (!strcmp(str, "known"))
699 enable_unknown = false;
700 else
701 return 1;
702
703 return 0;
704}
705early_param("dt_cpu_ftrs", dt_cpu_ftrs_parse);
706
707static void __init cpufeatures_setup_start(u32 isa)
708{
709 pr_info("setup for ISA %d\n", isa);
710
711 if (isa >= ISA_V3_0B) {
712 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_300;
713 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_00;
714 }
715
716 if (isa >= ISA_V3_1) {
717 cur_cpu_spec->cpu_features |= CPU_FTR_ARCH_31;
718 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_ARCH_3_1;
719 }
720}
721
722static bool __init cpufeatures_process_feature(struct dt_cpu_feature *f)
723{
724 const struct dt_cpu_feature_match *m;
725 bool known = false;
726 int i;
727
728 for (i = 0; i < ARRAY_SIZE(dt_cpu_feature_match_table); i++) {
729 m = &dt_cpu_feature_match_table[i];
730 if (!strcmp(f->name, m->name)) {
731 known = true;
732 if (m->enable(f)) {
733 cur_cpu_spec->cpu_features |= m->cpu_ftr_bit_mask;
734 break;
735 }
736
737 pr_info("not enabling: %s (disabled or unsupported by kernel)\n",
738 f->name);
739 return false;
740 }
741 }
742
743 if (!known && (!enable_unknown || !feat_try_enable_unknown(f))) {
744 pr_info("not enabling: %s (unknown and unsupported by kernel)\n",
745 f->name);
746 return false;
747 }
748
749 if (known)
750 pr_debug("enabling: %s\n", f->name);
751 else
752 pr_debug("enabling: %s (unknown)\n", f->name);
753
754 return true;
755}
756
757/*
758 * Handle POWER9 broadcast tlbie invalidation issue using
759 * cpu feature flag.
760 */
761static __init void update_tlbie_feature_flag(unsigned long pvr)
762{
763 if (PVR_VER(pvr) == PVR_POWER9) {
764 /*
765 * Set the tlbie feature flag for anything below
766 * Nimbus DD 2.3 and Cumulus DD 1.3
767 */
768 if ((pvr & 0xe000) == 0) {
769 /* Nimbus */
770 if ((pvr & 0xfff) < 0x203)
771 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
772 } else if ((pvr & 0xc000) == 0) {
773 /* Cumulus */
774 if ((pvr & 0xfff) < 0x103)
775 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
776 } else {
777 WARN_ONCE(1, "Unknown PVR");
778 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_STQ_BUG;
779 }
780
781 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TLBIE_ERAT_BUG;
782 }
783}
784
785static __init void cpufeatures_cpu_quirks(void)
786{
787 unsigned long version = mfspr(SPRN_PVR);
788
789 /*
790 * Not all quirks can be derived from the cpufeatures device tree.
791 */
792 if ((version & 0xffffefff) == 0x004e0200) {
793 /* DD2.0 has no feature flag */
794 cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG;
795 } else if ((version & 0xffffefff) == 0x004e0201) {
796 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
797 cur_cpu_spec->cpu_features |= CPU_FTR_P9_RADIX_PREFETCH_BUG;
798 } else if ((version & 0xffffefff) == 0x004e0202) {
799 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_HV_ASSIST;
800 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TM_XER_SO_BUG;
801 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
802 } else if ((version & 0xffff0000) == 0x004e0000) {
803 /* DD2.1 and up have DD2_1 */
804 cur_cpu_spec->cpu_features |= CPU_FTR_POWER9_DD2_1;
805 }
806
807 if ((version & 0xffff0000) == 0x004e0000) {
808 cur_cpu_spec->cpu_features &= ~(CPU_FTR_DAWR);
809 cur_cpu_spec->cpu_features |= CPU_FTR_P9_TIDR;
810 }
811
812 update_tlbie_feature_flag(version);
813}
814
815static void __init cpufeatures_setup_finished(void)
816{
817 cpufeatures_cpu_quirks();
818
819 if (hv_mode && !(cur_cpu_spec->cpu_features & CPU_FTR_HVMODE)) {
820 pr_err("hypervisor not present in device tree but HV mode is enabled in the CPU. Enabling.\n");
821 cur_cpu_spec->cpu_features |= CPU_FTR_HVMODE;
822 }
823
824 /* Make sure powerpc_base_platform is non-NULL */
825 powerpc_base_platform = cur_cpu_spec->platform;
826
827 system_registers.lpcr = mfspr(SPRN_LPCR);
828 system_registers.hfscr = mfspr(SPRN_HFSCR);
829 system_registers.fscr = mfspr(SPRN_FSCR);
830 system_registers.pcr = mfspr(SPRN_PCR);
831
832 pr_info("final cpu/mmu features = 0x%016lx 0x%08x\n",
833 cur_cpu_spec->cpu_features, cur_cpu_spec->mmu_features);
834}
835
836static int __init disabled_on_cmdline(void)
837{
838 unsigned long root, chosen;
839 const char *p;
840
841 root = of_get_flat_dt_root();
842 chosen = of_get_flat_dt_subnode_by_name(root, "chosen");
843 if (chosen == -FDT_ERR_NOTFOUND)
844 return false;
845
846 p = of_get_flat_dt_prop(chosen, "bootargs", NULL);
847 if (!p)
848 return false;
849
850 if (strstr(p, "dt_cpu_ftrs=off"))
851 return true;
852
853 return false;
854}
855
856static int __init fdt_find_cpu_features(unsigned long node, const char *uname,
857 int depth, void *data)
858{
859 if (of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features")
860 && of_get_flat_dt_prop(node, "isa", NULL))
861 return 1;
862
863 return 0;
864}
865
866bool __init dt_cpu_ftrs_in_use(void)
867{
868 return using_dt_cpu_ftrs;
869}
870
871bool __init dt_cpu_ftrs_init(void *fdt)
872{
873 using_dt_cpu_ftrs = false;
874
875 /* Setup and verify the FDT, if it fails we just bail */
876 if (!early_init_dt_verify(fdt))
877 return false;
878
879 if (!of_scan_flat_dt(fdt_find_cpu_features, NULL))
880 return false;
881
882 if (disabled_on_cmdline())
883 return false;
884
885 cpufeatures_setup_cpu();
886
887 using_dt_cpu_ftrs = true;
888 return true;
889}
890
891static int nr_dt_cpu_features;
892static struct dt_cpu_feature *dt_cpu_features;
893
894static int __init process_cpufeatures_node(unsigned long node,
895 const char *uname, int i)
896{
897 const __be32 *prop;
898 struct dt_cpu_feature *f;
899 int len;
900
901 f = &dt_cpu_features[i];
902
903 f->node = node;
904
905 f->name = uname;
906
907 prop = of_get_flat_dt_prop(node, "isa", &len);
908 if (!prop) {
909 pr_warn("%s: missing isa property\n", uname);
910 return 0;
911 }
912 f->isa = be32_to_cpup(prop);
913
914 prop = of_get_flat_dt_prop(node, "usable-privilege", &len);
915 if (!prop) {
916 pr_warn("%s: missing usable-privilege property", uname);
917 return 0;
918 }
919 f->usable_privilege = be32_to_cpup(prop);
920
921 prop = of_get_flat_dt_prop(node, "hv-support", &len);
922 if (prop)
923 f->hv_support = be32_to_cpup(prop);
924 else
925 f->hv_support = HV_SUPPORT_NONE;
926
927 prop = of_get_flat_dt_prop(node, "os-support", &len);
928 if (prop)
929 f->os_support = be32_to_cpup(prop);
930 else
931 f->os_support = OS_SUPPORT_NONE;
932
933 prop = of_get_flat_dt_prop(node, "hfscr-bit-nr", &len);
934 if (prop)
935 f->hfscr_bit_nr = be32_to_cpup(prop);
936 else
937 f->hfscr_bit_nr = -1;
938 prop = of_get_flat_dt_prop(node, "fscr-bit-nr", &len);
939 if (prop)
940 f->fscr_bit_nr = be32_to_cpup(prop);
941 else
942 f->fscr_bit_nr = -1;
943 prop = of_get_flat_dt_prop(node, "hwcap-bit-nr", &len);
944 if (prop)
945 f->hwcap_bit_nr = be32_to_cpup(prop);
946 else
947 f->hwcap_bit_nr = -1;
948
949 if (f->usable_privilege & USABLE_HV) {
950 if (!(mfmsr() & MSR_HV)) {
951 pr_warn("%s: HV feature passed to guest\n", uname);
952 return 0;
953 }
954
955 if (f->hv_support == HV_SUPPORT_NONE && f->hfscr_bit_nr != -1) {
956 pr_warn("%s: unwanted hfscr_bit_nr\n", uname);
957 return 0;
958 }
959
960 if (f->hv_support == HV_SUPPORT_HFSCR) {
961 if (f->hfscr_bit_nr == -1) {
962 pr_warn("%s: missing hfscr_bit_nr\n", uname);
963 return 0;
964 }
965 }
966 } else {
967 if (f->hv_support != HV_SUPPORT_NONE || f->hfscr_bit_nr != -1) {
968 pr_warn("%s: unwanted hv_support/hfscr_bit_nr\n", uname);
969 return 0;
970 }
971 }
972
973 if (f->usable_privilege & USABLE_OS) {
974 if (f->os_support == OS_SUPPORT_NONE && f->fscr_bit_nr != -1) {
975 pr_warn("%s: unwanted fscr_bit_nr\n", uname);
976 return 0;
977 }
978
979 if (f->os_support == OS_SUPPORT_FSCR) {
980 if (f->fscr_bit_nr == -1) {
981 pr_warn("%s: missing fscr_bit_nr\n", uname);
982 return 0;
983 }
984 }
985 } else {
986 if (f->os_support != OS_SUPPORT_NONE || f->fscr_bit_nr != -1) {
987 pr_warn("%s: unwanted os_support/fscr_bit_nr\n", uname);
988 return 0;
989 }
990 }
991
992 if (!(f->usable_privilege & USABLE_PR)) {
993 if (f->hwcap_bit_nr != -1) {
994 pr_warn("%s: unwanted hwcap_bit_nr\n", uname);
995 return 0;
996 }
997 }
998
999 /* Do all the independent features in the first pass */
1000 if (!of_get_flat_dt_prop(node, "dependencies", &len)) {
1001 if (cpufeatures_process_feature(f))
1002 f->enabled = 1;
1003 else
1004 f->disabled = 1;
1005 }
1006
1007 return 0;
1008}
1009
1010static void __init cpufeatures_deps_enable(struct dt_cpu_feature *f)
1011{
1012 const __be32 *prop;
1013 int len;
1014 int nr_deps;
1015 int i;
1016
1017 if (f->enabled || f->disabled)
1018 return;
1019
1020 prop = of_get_flat_dt_prop(f->node, "dependencies", &len);
1021 if (!prop) {
1022 pr_warn("%s: missing dependencies property", f->name);
1023 return;
1024 }
1025
1026 nr_deps = len / sizeof(int);
1027
1028 for (i = 0; i < nr_deps; i++) {
1029 unsigned long phandle = be32_to_cpu(prop[i]);
1030 int j;
1031
1032 for (j = 0; j < nr_dt_cpu_features; j++) {
1033 struct dt_cpu_feature *d = &dt_cpu_features[j];
1034
1035 if (of_get_flat_dt_phandle(d->node) == phandle) {
1036 cpufeatures_deps_enable(d);
1037 if (d->disabled) {
1038 f->disabled = 1;
1039 return;
1040 }
1041 }
1042 }
1043 }
1044
1045 if (cpufeatures_process_feature(f))
1046 f->enabled = 1;
1047 else
1048 f->disabled = 1;
1049}
1050
1051static int __init scan_cpufeatures_subnodes(unsigned long node,
1052 const char *uname,
1053 void *data)
1054{
1055 int *count = data;
1056
1057 process_cpufeatures_node(node, uname, *count);
1058
1059 (*count)++;
1060
1061 return 0;
1062}
1063
1064static int __init count_cpufeatures_subnodes(unsigned long node,
1065 const char *uname,
1066 void *data)
1067{
1068 int *count = data;
1069
1070 (*count)++;
1071
1072 return 0;
1073}
1074
1075static int __init dt_cpu_ftrs_scan_callback(unsigned long node, const char
1076 *uname, int depth, void *data)
1077{
1078 const __be32 *prop;
1079 int count, i;
1080 u32 isa;
1081
1082 /* We are scanning "ibm,powerpc-cpu-features" nodes only */
1083 if (!of_flat_dt_is_compatible(node, "ibm,powerpc-cpu-features"))
1084 return 0;
1085
1086 prop = of_get_flat_dt_prop(node, "isa", NULL);
1087 if (!prop)
1088 /* We checked before, "can't happen" */
1089 return 0;
1090
1091 isa = be32_to_cpup(prop);
1092
1093 /* Count and allocate space for cpu features */
1094 of_scan_flat_dt_subnodes(node, count_cpufeatures_subnodes,
1095 &nr_dt_cpu_features);
1096 dt_cpu_features = memblock_alloc(sizeof(struct dt_cpu_feature) * nr_dt_cpu_features, PAGE_SIZE);
1097 if (!dt_cpu_features)
1098 panic("%s: Failed to allocate %zu bytes align=0x%lx\n",
1099 __func__,
1100 sizeof(struct dt_cpu_feature) * nr_dt_cpu_features,
1101 PAGE_SIZE);
1102
1103 cpufeatures_setup_start(isa);
1104
1105 /* Scan nodes into dt_cpu_features and enable those without deps */
1106 count = 0;
1107 of_scan_flat_dt_subnodes(node, scan_cpufeatures_subnodes, &count);
1108
1109 /* Recursive enable remaining features with dependencies */
1110 for (i = 0; i < nr_dt_cpu_features; i++) {
1111 struct dt_cpu_feature *f = &dt_cpu_features[i];
1112
1113 cpufeatures_deps_enable(f);
1114 }
1115
1116 prop = of_get_flat_dt_prop(node, "display-name", NULL);
1117 if (prop && strlen((char *)prop) != 0) {
1118 strlcpy(dt_cpu_name, (char *)prop, sizeof(dt_cpu_name));
1119 cur_cpu_spec->cpu_name = dt_cpu_name;
1120 }
1121
1122 cpufeatures_setup_finished();
1123
1124 memblock_free(__pa(dt_cpu_features),
1125 sizeof(struct dt_cpu_feature)*nr_dt_cpu_features);
1126
1127 return 0;
1128}
1129
1130void __init dt_cpu_ftrs_scan(void)
1131{
1132 if (!using_dt_cpu_ftrs)
1133 return;
1134
1135 of_scan_flat_dt(dt_cpu_ftrs_scan_callback, NULL);
1136}