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1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/delay.h>
37#include <linux/init.h>
38#include <linux/sched/task_stack.h>
39#include <linux/smp.h>
40#include <linux/irq.h>
41
42#include <asm/mmu_context.h>
43
44#include <asm/netlogic/interrupt.h>
45#include <asm/netlogic/mips-extns.h>
46#include <asm/netlogic/haldefs.h>
47#include <asm/netlogic/common.h>
48
49#if defined(CONFIG_CPU_XLP)
50#include <asm/netlogic/xlp-hal/iomap.h>
51#include <asm/netlogic/xlp-hal/xlp.h>
52#include <asm/netlogic/xlp-hal/pic.h>
53#elif defined(CONFIG_CPU_XLR)
54#include <asm/netlogic/xlr/iomap.h>
55#include <asm/netlogic/xlr/pic.h>
56#include <asm/netlogic/xlr/xlr.h>
57#else
58#error "Unknown CPU"
59#endif
60
61void nlm_send_ipi_single(int logical_cpu, unsigned int action)
62{
63 unsigned int hwtid;
64 uint64_t picbase;
65
66 /* node id is part of hwtid, and needed for send_ipi */
67 hwtid = cpu_logical_map(logical_cpu);
68 picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
69
70 if (action & SMP_CALL_FUNCTION)
71 nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_FUNCTION, 0);
72 if (action & SMP_RESCHEDULE_YOURSELF)
73 nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_RESCHEDULE, 0);
74}
75
76void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
77{
78 int cpu;
79
80 for_each_cpu(cpu, mask) {
81 nlm_send_ipi_single(cpu, action);
82 }
83}
84
85/* IRQ_IPI_SMP_FUNCTION Handler */
86void nlm_smp_function_ipi_handler(struct irq_desc *desc)
87{
88 unsigned int irq = irq_desc_get_irq(desc);
89 clear_c0_eimr(irq);
90 ack_c0_eirr(irq);
91 generic_smp_call_function_interrupt();
92 set_c0_eimr(irq);
93}
94
95/* IRQ_IPI_SMP_RESCHEDULE handler */
96void nlm_smp_resched_ipi_handler(struct irq_desc *desc)
97{
98 unsigned int irq = irq_desc_get_irq(desc);
99 clear_c0_eimr(irq);
100 ack_c0_eirr(irq);
101 scheduler_ipi();
102 set_c0_eimr(irq);
103}
104
105/*
106 * Called before going into mips code, early cpu init
107 */
108void nlm_early_init_secondary(int cpu)
109{
110 change_c0_config(CONF_CM_CMASK, 0x3);
111#ifdef CONFIG_CPU_XLP
112 xlp_mmu_init();
113#endif
114 write_c0_ebase(nlm_current_node()->ebase);
115}
116
117/*
118 * Code to run on secondary just after probing the CPU
119 */
120static void nlm_init_secondary(void)
121{
122 int hwtid;
123
124 hwtid = hard_smp_processor_id();
125 cpu_set_core(¤t_cpu_data, hwtid / NLM_THREADS_PER_CORE);
126 current_cpu_data.package = nlm_nodeid();
127 nlm_percpu_init(hwtid);
128 nlm_smp_irq_init(hwtid);
129}
130
131void nlm_prepare_cpus(unsigned int max_cpus)
132{
133 /* declare we are SMT capable */
134 smp_num_siblings = nlm_threads_per_core;
135}
136
137void nlm_smp_finish(void)
138{
139 local_irq_enable();
140}
141
142/*
143 * Boot all other cpus in the system, initialize them, and bring them into
144 * the boot function
145 */
146unsigned long nlm_next_gp;
147unsigned long nlm_next_sp;
148static cpumask_t phys_cpu_present_mask;
149
150int nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
151{
152 uint64_t picbase;
153 int hwtid;
154
155 hwtid = cpu_logical_map(logical_cpu);
156 picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
157
158 nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
159 nlm_next_gp = (unsigned long)task_thread_info(idle);
160
161 /* barrier for sp/gp store above */
162 __sync();
163 nlm_pic_send_ipi(picbase, hwtid, 1, 1); /* NMI */
164
165 return 0;
166}
167
168void __init nlm_smp_setup(void)
169{
170 unsigned int boot_cpu;
171 int num_cpus, i, ncore, node;
172 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
173
174 boot_cpu = hard_smp_processor_id();
175 cpumask_clear(&phys_cpu_present_mask);
176
177 cpumask_set_cpu(boot_cpu, &phys_cpu_present_mask);
178 __cpu_number_map[boot_cpu] = 0;
179 __cpu_logical_map[0] = boot_cpu;
180 set_cpu_possible(0, true);
181
182 num_cpus = 1;
183 for (i = 0; i < NR_CPUS; i++) {
184 /*
185 * cpu_ready array is not set for the boot_cpu,
186 * it is only set for ASPs (see smpboot.S)
187 */
188 if (cpu_ready[i]) {
189 cpumask_set_cpu(i, &phys_cpu_present_mask);
190 __cpu_number_map[i] = num_cpus;
191 __cpu_logical_map[num_cpus] = i;
192 set_cpu_possible(num_cpus, true);
193 node = nlm_hwtid_to_node(i);
194 cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
195 ++num_cpus;
196 }
197 }
198
199 pr_info("Physical CPU mask: %*pb\n",
200 cpumask_pr_args(&phys_cpu_present_mask));
201 pr_info("Possible CPU mask: %*pb\n",
202 cpumask_pr_args(cpu_possible_mask));
203
204 /* check with the cores we have woken up */
205 for (ncore = 0, i = 0; i < NLM_NR_NODES; i++)
206 ncore += hweight32(nlm_get_node(i)->coremask);
207
208 pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore,
209 nlm_threads_per_core, num_cpus);
210
211 /* switch NMI handler to boot CPUs */
212 nlm_set_nmi_handler(nlm_boot_secondary_cpus);
213}
214
215static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
216{
217 uint32_t core0_thr_mask, core_thr_mask;
218 int threadmode, i, j;
219
220 core0_thr_mask = 0;
221 for (i = 0; i < NLM_THREADS_PER_CORE; i++)
222 if (cpumask_test_cpu(i, wakeup_mask))
223 core0_thr_mask |= (1 << i);
224 switch (core0_thr_mask) {
225 case 1:
226 nlm_threads_per_core = 1;
227 threadmode = 0;
228 break;
229 case 3:
230 nlm_threads_per_core = 2;
231 threadmode = 2;
232 break;
233 case 0xf:
234 nlm_threads_per_core = 4;
235 threadmode = 3;
236 break;
237 default:
238 goto unsupp;
239 }
240
241 /* Verify other cores CPU masks */
242 for (i = 0; i < NR_CPUS; i += NLM_THREADS_PER_CORE) {
243 core_thr_mask = 0;
244 for (j = 0; j < NLM_THREADS_PER_CORE; j++)
245 if (cpumask_test_cpu(i + j, wakeup_mask))
246 core_thr_mask |= (1 << j);
247 if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask)
248 goto unsupp;
249 }
250 return threadmode;
251
252unsupp:
253 panic("Unsupported CPU mask %*pb", cpumask_pr_args(wakeup_mask));
254 return 0;
255}
256
257int nlm_wakeup_secondary_cpus(void)
258{
259 u32 *reset_data;
260 int threadmode;
261
262 /* verify the mask and setup core config variables */
263 threadmode = nlm_parse_cpumask(&nlm_cpumask);
264
265 /* Setup CPU init parameters */
266 reset_data = nlm_get_boot_data(BOOT_THREAD_MODE);
267 *reset_data = threadmode;
268
269#ifdef CONFIG_CPU_XLP
270 xlp_wakeup_secondary_cpus();
271#else
272 xlr_wakeup_secondary_cpus();
273#endif
274 return 0;
275}
276
277const struct plat_smp_ops nlm_smp_ops = {
278 .send_ipi_single = nlm_send_ipi_single,
279 .send_ipi_mask = nlm_send_ipi_mask,
280 .init_secondary = nlm_init_secondary,
281 .smp_finish = nlm_smp_finish,
282 .boot_secondary = nlm_boot_secondary,
283 .smp_setup = nlm_smp_setup,
284 .prepare_cpus = nlm_prepare_cpus,
285};
1/*
2 * Copyright 2003-2011 NetLogic Microsystems, Inc. (NetLogic). All rights
3 * reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the NetLogic
9 * license below:
10 *
11 * Redistribution and use in source and binary forms, with or without
12 * modification, are permitted provided that the following conditions
13 * are met:
14 *
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in
19 * the documentation and/or other materials provided with the
20 * distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY NETLOGIC ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
29 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
31 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
32 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33 */
34
35#include <linux/kernel.h>
36#include <linux/delay.h>
37#include <linux/init.h>
38#include <linux/sched/task_stack.h>
39#include <linux/smp.h>
40#include <linux/irq.h>
41
42#include <asm/mmu_context.h>
43
44#include <asm/netlogic/interrupt.h>
45#include <asm/netlogic/mips-extns.h>
46#include <asm/netlogic/haldefs.h>
47#include <asm/netlogic/common.h>
48
49#if defined(CONFIG_CPU_XLP)
50#include <asm/netlogic/xlp-hal/iomap.h>
51#include <asm/netlogic/xlp-hal/xlp.h>
52#include <asm/netlogic/xlp-hal/pic.h>
53#elif defined(CONFIG_CPU_XLR)
54#include <asm/netlogic/xlr/iomap.h>
55#include <asm/netlogic/xlr/pic.h>
56#include <asm/netlogic/xlr/xlr.h>
57#else
58#error "Unknown CPU"
59#endif
60
61void nlm_send_ipi_single(int logical_cpu, unsigned int action)
62{
63 unsigned int hwtid;
64 uint64_t picbase;
65
66 /* node id is part of hwtid, and needed for send_ipi */
67 hwtid = cpu_logical_map(logical_cpu);
68 picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
69
70 if (action & SMP_CALL_FUNCTION)
71 nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_FUNCTION, 0);
72 if (action & SMP_RESCHEDULE_YOURSELF)
73 nlm_pic_send_ipi(picbase, hwtid, IRQ_IPI_SMP_RESCHEDULE, 0);
74}
75
76void nlm_send_ipi_mask(const struct cpumask *mask, unsigned int action)
77{
78 int cpu;
79
80 for_each_cpu(cpu, mask) {
81 nlm_send_ipi_single(cpu, action);
82 }
83}
84
85/* IRQ_IPI_SMP_FUNCTION Handler */
86void nlm_smp_function_ipi_handler(struct irq_desc *desc)
87{
88 unsigned int irq = irq_desc_get_irq(desc);
89 clear_c0_eimr(irq);
90 ack_c0_eirr(irq);
91 generic_smp_call_function_interrupt();
92 set_c0_eimr(irq);
93}
94
95/* IRQ_IPI_SMP_RESCHEDULE handler */
96void nlm_smp_resched_ipi_handler(struct irq_desc *desc)
97{
98 unsigned int irq = irq_desc_get_irq(desc);
99 clear_c0_eimr(irq);
100 ack_c0_eirr(irq);
101 scheduler_ipi();
102 set_c0_eimr(irq);
103}
104
105/*
106 * Called before going into mips code, early cpu init
107 */
108void nlm_early_init_secondary(int cpu)
109{
110 change_c0_config(CONF_CM_CMASK, 0x3);
111#ifdef CONFIG_CPU_XLP
112 xlp_mmu_init();
113#endif
114 write_c0_ebase(nlm_current_node()->ebase);
115}
116
117/*
118 * Code to run on secondary just after probing the CPU
119 */
120static void nlm_init_secondary(void)
121{
122 int hwtid;
123
124 hwtid = hard_smp_processor_id();
125 cpu_set_core(¤t_cpu_data, hwtid / NLM_THREADS_PER_CORE);
126 current_cpu_data.package = nlm_nodeid();
127 nlm_percpu_init(hwtid);
128 nlm_smp_irq_init(hwtid);
129}
130
131void nlm_prepare_cpus(unsigned int max_cpus)
132{
133 /* declare we are SMT capable */
134 smp_num_siblings = nlm_threads_per_core;
135}
136
137void nlm_smp_finish(void)
138{
139 local_irq_enable();
140}
141
142/*
143 * Boot all other cpus in the system, initialize them, and bring them into
144 * the boot function
145 */
146unsigned long nlm_next_gp;
147unsigned long nlm_next_sp;
148static cpumask_t phys_cpu_present_mask;
149
150int nlm_boot_secondary(int logical_cpu, struct task_struct *idle)
151{
152 uint64_t picbase;
153 int hwtid;
154
155 hwtid = cpu_logical_map(logical_cpu);
156 picbase = nlm_get_node(nlm_hwtid_to_node(hwtid))->picbase;
157
158 nlm_next_sp = (unsigned long)__KSTK_TOS(idle);
159 nlm_next_gp = (unsigned long)task_thread_info(idle);
160
161 /* barrier for sp/gp store above */
162 __sync();
163 nlm_pic_send_ipi(picbase, hwtid, 1, 1); /* NMI */
164
165 return 0;
166}
167
168void __init nlm_smp_setup(void)
169{
170 unsigned int boot_cpu;
171 int num_cpus, i, ncore, node;
172 volatile u32 *cpu_ready = nlm_get_boot_data(BOOT_CPU_READY);
173
174 boot_cpu = hard_smp_processor_id();
175 cpumask_clear(&phys_cpu_present_mask);
176
177 cpumask_set_cpu(boot_cpu, &phys_cpu_present_mask);
178 __cpu_number_map[boot_cpu] = 0;
179 __cpu_logical_map[0] = boot_cpu;
180 set_cpu_possible(0, true);
181
182 num_cpus = 1;
183 for (i = 0; i < NR_CPUS; i++) {
184 /*
185 * cpu_ready array is not set for the boot_cpu,
186 * it is only set for ASPs (see smpboot.S)
187 */
188 if (cpu_ready[i]) {
189 cpumask_set_cpu(i, &phys_cpu_present_mask);
190 __cpu_number_map[i] = num_cpus;
191 __cpu_logical_map[num_cpus] = i;
192 set_cpu_possible(num_cpus, true);
193 node = nlm_hwtid_to_node(i);
194 cpumask_set_cpu(num_cpus, &nlm_get_node(node)->cpumask);
195 ++num_cpus;
196 }
197 }
198
199 pr_info("Physical CPU mask: %*pb\n",
200 cpumask_pr_args(&phys_cpu_present_mask));
201 pr_info("Possible CPU mask: %*pb\n",
202 cpumask_pr_args(cpu_possible_mask));
203
204 /* check with the cores we have woken up */
205 for (ncore = 0, i = 0; i < NLM_NR_NODES; i++)
206 ncore += hweight32(nlm_get_node(i)->coremask);
207
208 pr_info("Detected (%dc%dt) %d Slave CPU(s)\n", ncore,
209 nlm_threads_per_core, num_cpus);
210
211 /* switch NMI handler to boot CPUs */
212 nlm_set_nmi_handler(nlm_boot_secondary_cpus);
213}
214
215static int nlm_parse_cpumask(cpumask_t *wakeup_mask)
216{
217 uint32_t core0_thr_mask, core_thr_mask;
218 int threadmode, i, j;
219
220 core0_thr_mask = 0;
221 for (i = 0; i < NLM_THREADS_PER_CORE; i++)
222 if (cpumask_test_cpu(i, wakeup_mask))
223 core0_thr_mask |= (1 << i);
224 switch (core0_thr_mask) {
225 case 1:
226 nlm_threads_per_core = 1;
227 threadmode = 0;
228 break;
229 case 3:
230 nlm_threads_per_core = 2;
231 threadmode = 2;
232 break;
233 case 0xf:
234 nlm_threads_per_core = 4;
235 threadmode = 3;
236 break;
237 default:
238 goto unsupp;
239 }
240
241 /* Verify other cores CPU masks */
242 for (i = 0; i < NR_CPUS; i += NLM_THREADS_PER_CORE) {
243 core_thr_mask = 0;
244 for (j = 0; j < NLM_THREADS_PER_CORE; j++)
245 if (cpumask_test_cpu(i + j, wakeup_mask))
246 core_thr_mask |= (1 << j);
247 if (core_thr_mask != 0 && core_thr_mask != core0_thr_mask)
248 goto unsupp;
249 }
250 return threadmode;
251
252unsupp:
253 panic("Unsupported CPU mask %*pb", cpumask_pr_args(wakeup_mask));
254 return 0;
255}
256
257int nlm_wakeup_secondary_cpus(void)
258{
259 u32 *reset_data;
260 int threadmode;
261
262 /* verify the mask and setup core config variables */
263 threadmode = nlm_parse_cpumask(&nlm_cpumask);
264
265 /* Setup CPU init parameters */
266 reset_data = nlm_get_boot_data(BOOT_THREAD_MODE);
267 *reset_data = threadmode;
268
269#ifdef CONFIG_CPU_XLP
270 xlp_wakeup_secondary_cpus();
271#else
272 xlr_wakeup_secondary_cpus();
273#endif
274 return 0;
275}
276
277const struct plat_smp_ops nlm_smp_ops = {
278 .send_ipi_single = nlm_send_ipi_single,
279 .send_ipi_mask = nlm_send_ipi_mask,
280 .init_secondary = nlm_init_secondary,
281 .smp_finish = nlm_smp_finish,
282 .boot_secondary = nlm_boot_secondary,
283 .smp_setup = nlm_smp_setup,
284 .prepare_cpus = nlm_prepare_cpus,
285};