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1/*
2 * Linux performance counter support for MIPS.
3 *
4 * Copyright (C) 2010 MIPS Technologies, Inc.
5 * Copyright (C) 2011 Cavium Networks, Inc.
6 * Author: Deng-Cheng Zhu
7 *
8 * This code is based on the implementation for ARM, which is in turn
9 * based on the sparc64 perf event code and the x86 code. Performance
10 * counter access is based on the MIPS Oprofile code. And the callchain
11 * support references the code of MIPS stacktrace.c.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/cpumask.h>
19#include <linux/interrupt.h>
20#include <linux/smp.h>
21#include <linux/kernel.h>
22#include <linux/perf_event.h>
23#include <linux/uaccess.h>
24
25#include <asm/irq.h>
26#include <asm/irq_regs.h>
27#include <asm/stacktrace.h>
28#include <asm/time.h> /* For perf_irq */
29
30#define MIPS_MAX_HWEVENTS 4
31#define MIPS_TCS_PER_COUNTER 2
32#define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1)
33
34struct cpu_hw_events {
35 /* Array of events on this cpu. */
36 struct perf_event *events[MIPS_MAX_HWEVENTS];
37
38 /*
39 * Set the bit (indexed by the counter number) when the counter
40 * is used for an event.
41 */
42 unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
43
44 /*
45 * Software copy of the control register for each performance counter.
46 * MIPS CPUs vary in performance counters. They use this differently,
47 * and even may not use it.
48 */
49 unsigned int saved_ctrl[MIPS_MAX_HWEVENTS];
50};
51DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
52 .saved_ctrl = {0},
53};
54
55/* The description of MIPS performance events. */
56struct mips_perf_event {
57 unsigned int event_id;
58 /*
59 * MIPS performance counters are indexed starting from 0.
60 * CNTR_EVEN indicates the indexes of the counters to be used are
61 * even numbers.
62 */
63 unsigned int cntr_mask;
64 #define CNTR_EVEN 0x55555555
65 #define CNTR_ODD 0xaaaaaaaa
66 #define CNTR_ALL 0xffffffff
67#ifdef CONFIG_MIPS_MT_SMP
68 enum {
69 T = 0,
70 V = 1,
71 P = 2,
72 } range;
73#else
74 #define T
75 #define V
76 #define P
77#endif
78};
79
80static struct mips_perf_event raw_event;
81static DEFINE_MUTEX(raw_event_mutex);
82
83#define C(x) PERF_COUNT_HW_CACHE_##x
84
85struct mips_pmu {
86 u64 max_period;
87 u64 valid_count;
88 u64 overflow;
89 const char *name;
90 int irq;
91 u64 (*read_counter)(unsigned int idx);
92 void (*write_counter)(unsigned int idx, u64 val);
93 const struct mips_perf_event *(*map_raw_event)(u64 config);
94 const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
95 const struct mips_perf_event (*cache_event_map)
96 [PERF_COUNT_HW_CACHE_MAX]
97 [PERF_COUNT_HW_CACHE_OP_MAX]
98 [PERF_COUNT_HW_CACHE_RESULT_MAX];
99 unsigned int num_counters;
100};
101
102static struct mips_pmu mipspmu;
103
104#define M_PERFCTL_EVENT(event) (((event) << MIPS_PERFCTRL_EVENT_S) & \
105 MIPS_PERFCTRL_EVENT)
106#define M_PERFCTL_VPEID(vpe) ((vpe) << MIPS_PERFCTRL_VPEID_S)
107
108#ifdef CONFIG_CPU_BMIPS5000
109#define M_PERFCTL_MT_EN(filter) 0
110#else /* !CONFIG_CPU_BMIPS5000 */
111#define M_PERFCTL_MT_EN(filter) (filter)
112#endif /* CONFIG_CPU_BMIPS5000 */
113
114#define M_TC_EN_ALL M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_ALL)
115#define M_TC_EN_VPE M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_VPE)
116#define M_TC_EN_TC M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_TC)
117
118#define M_PERFCTL_COUNT_EVENT_WHENEVER (MIPS_PERFCTRL_EXL | \
119 MIPS_PERFCTRL_K | \
120 MIPS_PERFCTRL_U | \
121 MIPS_PERFCTRL_S | \
122 MIPS_PERFCTRL_IE)
123
124#ifdef CONFIG_MIPS_MT_SMP
125#define M_PERFCTL_CONFIG_MASK 0x3fff801f
126#else
127#define M_PERFCTL_CONFIG_MASK 0x1f
128#endif
129
130
131#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
132static int cpu_has_mipsmt_pertccounters;
133
134static DEFINE_RWLOCK(pmuint_rwlock);
135
136#if defined(CONFIG_CPU_BMIPS5000)
137#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
138 0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK))
139#else
140/*
141 * FIXME: For VSMP, vpe_id() is redefined for Perf-events, because
142 * cpu_data[cpuid].vpe_id reports 0 for _both_ CPUs.
143 */
144#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
145 0 : smp_processor_id())
146#endif
147
148/* Copied from op_model_mipsxx.c */
149static unsigned int vpe_shift(void)
150{
151 if (num_possible_cpus() > 1)
152 return 1;
153
154 return 0;
155}
156
157static unsigned int counters_total_to_per_cpu(unsigned int counters)
158{
159 return counters >> vpe_shift();
160}
161
162#else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
163#define vpe_id() 0
164
165#endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
166
167static void resume_local_counters(void);
168static void pause_local_counters(void);
169static irqreturn_t mipsxx_pmu_handle_irq(int, void *);
170static int mipsxx_pmu_handle_shared_irq(void);
171
172static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)
173{
174 if (vpe_id() == 1)
175 idx = (idx + 2) & 3;
176 return idx;
177}
178
179static u64 mipsxx_pmu_read_counter(unsigned int idx)
180{
181 idx = mipsxx_pmu_swizzle_perf_idx(idx);
182
183 switch (idx) {
184 case 0:
185 /*
186 * The counters are unsigned, we must cast to truncate
187 * off the high bits.
188 */
189 return (u32)read_c0_perfcntr0();
190 case 1:
191 return (u32)read_c0_perfcntr1();
192 case 2:
193 return (u32)read_c0_perfcntr2();
194 case 3:
195 return (u32)read_c0_perfcntr3();
196 default:
197 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
198 return 0;
199 }
200}
201
202static u64 mipsxx_pmu_read_counter_64(unsigned int idx)
203{
204 idx = mipsxx_pmu_swizzle_perf_idx(idx);
205
206 switch (idx) {
207 case 0:
208 return read_c0_perfcntr0_64();
209 case 1:
210 return read_c0_perfcntr1_64();
211 case 2:
212 return read_c0_perfcntr2_64();
213 case 3:
214 return read_c0_perfcntr3_64();
215 default:
216 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
217 return 0;
218 }
219}
220
221static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
222{
223 idx = mipsxx_pmu_swizzle_perf_idx(idx);
224
225 switch (idx) {
226 case 0:
227 write_c0_perfcntr0(val);
228 return;
229 case 1:
230 write_c0_perfcntr1(val);
231 return;
232 case 2:
233 write_c0_perfcntr2(val);
234 return;
235 case 3:
236 write_c0_perfcntr3(val);
237 return;
238 }
239}
240
241static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)
242{
243 idx = mipsxx_pmu_swizzle_perf_idx(idx);
244
245 switch (idx) {
246 case 0:
247 write_c0_perfcntr0_64(val);
248 return;
249 case 1:
250 write_c0_perfcntr1_64(val);
251 return;
252 case 2:
253 write_c0_perfcntr2_64(val);
254 return;
255 case 3:
256 write_c0_perfcntr3_64(val);
257 return;
258 }
259}
260
261static unsigned int mipsxx_pmu_read_control(unsigned int idx)
262{
263 idx = mipsxx_pmu_swizzle_perf_idx(idx);
264
265 switch (idx) {
266 case 0:
267 return read_c0_perfctrl0();
268 case 1:
269 return read_c0_perfctrl1();
270 case 2:
271 return read_c0_perfctrl2();
272 case 3:
273 return read_c0_perfctrl3();
274 default:
275 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
276 return 0;
277 }
278}
279
280static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
281{
282 idx = mipsxx_pmu_swizzle_perf_idx(idx);
283
284 switch (idx) {
285 case 0:
286 write_c0_perfctrl0(val);
287 return;
288 case 1:
289 write_c0_perfctrl1(val);
290 return;
291 case 2:
292 write_c0_perfctrl2(val);
293 return;
294 case 3:
295 write_c0_perfctrl3(val);
296 return;
297 }
298}
299
300static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
301 struct hw_perf_event *hwc)
302{
303 int i;
304
305 /*
306 * We only need to care the counter mask. The range has been
307 * checked definitely.
308 */
309 unsigned long cntr_mask = (hwc->event_base >> 8) & 0xffff;
310
311 for (i = mipspmu.num_counters - 1; i >= 0; i--) {
312 /*
313 * Note that some MIPS perf events can be counted by both
314 * even and odd counters, wheresas many other are only by
315 * even _or_ odd counters. This introduces an issue that
316 * when the former kind of event takes the counter the
317 * latter kind of event wants to use, then the "counter
318 * allocation" for the latter event will fail. In fact if
319 * they can be dynamically swapped, they both feel happy.
320 * But here we leave this issue alone for now.
321 */
322 if (test_bit(i, &cntr_mask) &&
323 !test_and_set_bit(i, cpuc->used_mask))
324 return i;
325 }
326
327 return -EAGAIN;
328}
329
330static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
331{
332 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
333
334 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
335
336 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
337 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
338 /* Make sure interrupt enabled. */
339 MIPS_PERFCTRL_IE;
340 if (IS_ENABLED(CONFIG_CPU_BMIPS5000))
341 /* enable the counter for the calling thread */
342 cpuc->saved_ctrl[idx] |=
343 (1 << (12 + vpe_id())) | BRCM_PERFCTRL_TC;
344
345 /*
346 * We do not actually let the counter run. Leave it until start().
347 */
348}
349
350static void mipsxx_pmu_disable_event(int idx)
351{
352 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
353 unsigned long flags;
354
355 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
356
357 local_irq_save(flags);
358 cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
359 ~M_PERFCTL_COUNT_EVENT_WHENEVER;
360 mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
361 local_irq_restore(flags);
362}
363
364static int mipspmu_event_set_period(struct perf_event *event,
365 struct hw_perf_event *hwc,
366 int idx)
367{
368 u64 left = local64_read(&hwc->period_left);
369 u64 period = hwc->sample_period;
370 int ret = 0;
371
372 if (unlikely((left + period) & (1ULL << 63))) {
373 /* left underflowed by more than period. */
374 left = period;
375 local64_set(&hwc->period_left, left);
376 hwc->last_period = period;
377 ret = 1;
378 } else if (unlikely((left + period) <= period)) {
379 /* left underflowed by less than period. */
380 left += period;
381 local64_set(&hwc->period_left, left);
382 hwc->last_period = period;
383 ret = 1;
384 }
385
386 if (left > mipspmu.max_period) {
387 left = mipspmu.max_period;
388 local64_set(&hwc->period_left, left);
389 }
390
391 local64_set(&hwc->prev_count, mipspmu.overflow - left);
392
393 mipspmu.write_counter(idx, mipspmu.overflow - left);
394
395 perf_event_update_userpage(event);
396
397 return ret;
398}
399
400static void mipspmu_event_update(struct perf_event *event,
401 struct hw_perf_event *hwc,
402 int idx)
403{
404 u64 prev_raw_count, new_raw_count;
405 u64 delta;
406
407again:
408 prev_raw_count = local64_read(&hwc->prev_count);
409 new_raw_count = mipspmu.read_counter(idx);
410
411 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
412 new_raw_count) != prev_raw_count)
413 goto again;
414
415 delta = new_raw_count - prev_raw_count;
416
417 local64_add(delta, &event->count);
418 local64_sub(delta, &hwc->period_left);
419}
420
421static void mipspmu_start(struct perf_event *event, int flags)
422{
423 struct hw_perf_event *hwc = &event->hw;
424
425 if (flags & PERF_EF_RELOAD)
426 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
427
428 hwc->state = 0;
429
430 /* Set the period for the event. */
431 mipspmu_event_set_period(event, hwc, hwc->idx);
432
433 /* Enable the event. */
434 mipsxx_pmu_enable_event(hwc, hwc->idx);
435}
436
437static void mipspmu_stop(struct perf_event *event, int flags)
438{
439 struct hw_perf_event *hwc = &event->hw;
440
441 if (!(hwc->state & PERF_HES_STOPPED)) {
442 /* We are working on a local event. */
443 mipsxx_pmu_disable_event(hwc->idx);
444 barrier();
445 mipspmu_event_update(event, hwc, hwc->idx);
446 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
447 }
448}
449
450static int mipspmu_add(struct perf_event *event, int flags)
451{
452 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
453 struct hw_perf_event *hwc = &event->hw;
454 int idx;
455 int err = 0;
456
457 perf_pmu_disable(event->pmu);
458
459 /* To look for a free counter for this event. */
460 idx = mipsxx_pmu_alloc_counter(cpuc, hwc);
461 if (idx < 0) {
462 err = idx;
463 goto out;
464 }
465
466 /*
467 * If there is an event in the counter we are going to use then
468 * make sure it is disabled.
469 */
470 event->hw.idx = idx;
471 mipsxx_pmu_disable_event(idx);
472 cpuc->events[idx] = event;
473
474 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
475 if (flags & PERF_EF_START)
476 mipspmu_start(event, PERF_EF_RELOAD);
477
478 /* Propagate our changes to the userspace mapping. */
479 perf_event_update_userpage(event);
480
481out:
482 perf_pmu_enable(event->pmu);
483 return err;
484}
485
486static void mipspmu_del(struct perf_event *event, int flags)
487{
488 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
489 struct hw_perf_event *hwc = &event->hw;
490 int idx = hwc->idx;
491
492 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
493
494 mipspmu_stop(event, PERF_EF_UPDATE);
495 cpuc->events[idx] = NULL;
496 clear_bit(idx, cpuc->used_mask);
497
498 perf_event_update_userpage(event);
499}
500
501static void mipspmu_read(struct perf_event *event)
502{
503 struct hw_perf_event *hwc = &event->hw;
504
505 /* Don't read disabled counters! */
506 if (hwc->idx < 0)
507 return;
508
509 mipspmu_event_update(event, hwc, hwc->idx);
510}
511
512static void mipspmu_enable(struct pmu *pmu)
513{
514#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
515 write_unlock(&pmuint_rwlock);
516#endif
517 resume_local_counters();
518}
519
520/*
521 * MIPS performance counters can be per-TC. The control registers can
522 * not be directly accessed across CPUs. Hence if we want to do global
523 * control, we need cross CPU calls. on_each_cpu() can help us, but we
524 * can not make sure this function is called with interrupts enabled. So
525 * here we pause local counters and then grab a rwlock and leave the
526 * counters on other CPUs alone. If any counter interrupt raises while
527 * we own the write lock, simply pause local counters on that CPU and
528 * spin in the handler. Also we know we won't be switched to another
529 * CPU after pausing local counters and before grabbing the lock.
530 */
531static void mipspmu_disable(struct pmu *pmu)
532{
533 pause_local_counters();
534#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
535 write_lock(&pmuint_rwlock);
536#endif
537}
538
539static atomic_t active_events = ATOMIC_INIT(0);
540static DEFINE_MUTEX(pmu_reserve_mutex);
541static int (*save_perf_irq)(void);
542
543static int mipspmu_get_irq(void)
544{
545 int err;
546
547 if (mipspmu.irq >= 0) {
548 /* Request my own irq handler. */
549 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
550 IRQF_PERCPU | IRQF_NOBALANCING |
551 IRQF_NO_THREAD | IRQF_NO_SUSPEND |
552 IRQF_SHARED,
553 "mips_perf_pmu", &mipspmu);
554 if (err) {
555 pr_warn("Unable to request IRQ%d for MIPS performance counters!\n",
556 mipspmu.irq);
557 }
558 } else if (cp0_perfcount_irq < 0) {
559 /*
560 * We are sharing the irq number with the timer interrupt.
561 */
562 save_perf_irq = perf_irq;
563 perf_irq = mipsxx_pmu_handle_shared_irq;
564 err = 0;
565 } else {
566 pr_warn("The platform hasn't properly defined its interrupt controller\n");
567 err = -ENOENT;
568 }
569
570 return err;
571}
572
573static void mipspmu_free_irq(void)
574{
575 if (mipspmu.irq >= 0)
576 free_irq(mipspmu.irq, &mipspmu);
577 else if (cp0_perfcount_irq < 0)
578 perf_irq = save_perf_irq;
579}
580
581/*
582 * mipsxx/rm9000/loongson2 have different performance counters, they have
583 * specific low-level init routines.
584 */
585static void reset_counters(void *arg);
586static int __hw_perf_event_init(struct perf_event *event);
587
588static void hw_perf_event_destroy(struct perf_event *event)
589{
590 if (atomic_dec_and_mutex_lock(&active_events,
591 &pmu_reserve_mutex)) {
592 /*
593 * We must not call the destroy function with interrupts
594 * disabled.
595 */
596 on_each_cpu(reset_counters,
597 (void *)(long)mipspmu.num_counters, 1);
598 mipspmu_free_irq();
599 mutex_unlock(&pmu_reserve_mutex);
600 }
601}
602
603static int mipspmu_event_init(struct perf_event *event)
604{
605 int err = 0;
606
607 /* does not support taken branch sampling */
608 if (has_branch_stack(event))
609 return -EOPNOTSUPP;
610
611 switch (event->attr.type) {
612 case PERF_TYPE_RAW:
613 case PERF_TYPE_HARDWARE:
614 case PERF_TYPE_HW_CACHE:
615 break;
616
617 default:
618 return -ENOENT;
619 }
620
621 if (event->cpu >= 0 && !cpu_online(event->cpu))
622 return -ENODEV;
623
624 if (!atomic_inc_not_zero(&active_events)) {
625 mutex_lock(&pmu_reserve_mutex);
626 if (atomic_read(&active_events) == 0)
627 err = mipspmu_get_irq();
628
629 if (!err)
630 atomic_inc(&active_events);
631 mutex_unlock(&pmu_reserve_mutex);
632 }
633
634 if (err)
635 return err;
636
637 return __hw_perf_event_init(event);
638}
639
640static struct pmu pmu = {
641 .pmu_enable = mipspmu_enable,
642 .pmu_disable = mipspmu_disable,
643 .event_init = mipspmu_event_init,
644 .add = mipspmu_add,
645 .del = mipspmu_del,
646 .start = mipspmu_start,
647 .stop = mipspmu_stop,
648 .read = mipspmu_read,
649};
650
651static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
652{
653/*
654 * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
655 * event_id.
656 */
657#ifdef CONFIG_MIPS_MT_SMP
658 return ((unsigned int)pev->range << 24) |
659 (pev->cntr_mask & 0xffff00) |
660 (pev->event_id & 0xff);
661#else
662 return (pev->cntr_mask & 0xffff00) |
663 (pev->event_id & 0xff);
664#endif
665}
666
667static const struct mips_perf_event *mipspmu_map_general_event(int idx)
668{
669
670 if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)
671 return ERR_PTR(-EOPNOTSUPP);
672 return &(*mipspmu.general_event_map)[idx];
673}
674
675static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
676{
677 unsigned int cache_type, cache_op, cache_result;
678 const struct mips_perf_event *pev;
679
680 cache_type = (config >> 0) & 0xff;
681 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
682 return ERR_PTR(-EINVAL);
683
684 cache_op = (config >> 8) & 0xff;
685 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
686 return ERR_PTR(-EINVAL);
687
688 cache_result = (config >> 16) & 0xff;
689 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
690 return ERR_PTR(-EINVAL);
691
692 pev = &((*mipspmu.cache_event_map)
693 [cache_type]
694 [cache_op]
695 [cache_result]);
696
697 if (pev->cntr_mask == 0)
698 return ERR_PTR(-EOPNOTSUPP);
699
700 return pev;
701
702}
703
704static int validate_group(struct perf_event *event)
705{
706 struct perf_event *sibling, *leader = event->group_leader;
707 struct cpu_hw_events fake_cpuc;
708
709 memset(&fake_cpuc, 0, sizeof(fake_cpuc));
710
711 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
712 return -EINVAL;
713
714 for_each_sibling_event(sibling, leader) {
715 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
716 return -EINVAL;
717 }
718
719 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
720 return -EINVAL;
721
722 return 0;
723}
724
725/* This is needed by specific irq handlers in perf_event_*.c */
726static void handle_associated_event(struct cpu_hw_events *cpuc,
727 int idx, struct perf_sample_data *data,
728 struct pt_regs *regs)
729{
730 struct perf_event *event = cpuc->events[idx];
731 struct hw_perf_event *hwc = &event->hw;
732
733 mipspmu_event_update(event, hwc, idx);
734 data->period = event->hw.last_period;
735 if (!mipspmu_event_set_period(event, hwc, idx))
736 return;
737
738 if (perf_event_overflow(event, data, regs))
739 mipsxx_pmu_disable_event(idx);
740}
741
742
743static int __n_counters(void)
744{
745 if (!cpu_has_perf)
746 return 0;
747 if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
748 return 1;
749 if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
750 return 2;
751 if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
752 return 3;
753
754 return 4;
755}
756
757static int n_counters(void)
758{
759 int counters;
760
761 switch (current_cpu_type()) {
762 case CPU_R10000:
763 counters = 2;
764 break;
765
766 case CPU_R12000:
767 case CPU_R14000:
768 case CPU_R16000:
769 counters = 4;
770 break;
771
772 default:
773 counters = __n_counters();
774 }
775
776 return counters;
777}
778
779static void reset_counters(void *arg)
780{
781 int counters = (int)(long)arg;
782 switch (counters) {
783 case 4:
784 mipsxx_pmu_write_control(3, 0);
785 mipspmu.write_counter(3, 0);
786 case 3:
787 mipsxx_pmu_write_control(2, 0);
788 mipspmu.write_counter(2, 0);
789 case 2:
790 mipsxx_pmu_write_control(1, 0);
791 mipspmu.write_counter(1, 0);
792 case 1:
793 mipsxx_pmu_write_control(0, 0);
794 mipspmu.write_counter(0, 0);
795 }
796}
797
798/* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */
799static const struct mips_perf_event mipsxxcore_event_map
800 [PERF_COUNT_HW_MAX] = {
801 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
802 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
803 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
804 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
805};
806
807/* 74K/proAptiv core has different branch event code. */
808static const struct mips_perf_event mipsxxcore_event_map2
809 [PERF_COUNT_HW_MAX] = {
810 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
811 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
812 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
813 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
814};
815
816static const struct mips_perf_event i6x00_event_map[PERF_COUNT_HW_MAX] = {
817 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD },
818 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD },
819 /* These only count dcache, not icache */
820 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x45, CNTR_EVEN | CNTR_ODD },
821 [PERF_COUNT_HW_CACHE_MISSES] = { 0x48, CNTR_EVEN | CNTR_ODD },
822 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD },
823 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x16, CNTR_EVEN | CNTR_ODD },
824};
825
826static const struct mips_perf_event loongson3_event_map[PERF_COUNT_HW_MAX] = {
827 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },
828 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
829 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN },
830 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },
831};
832
833static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
834 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
835 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
836 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
837 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL },
838 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
839 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
840 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
841};
842
843static const struct mips_perf_event bmips5000_event_map
844 [PERF_COUNT_HW_MAX] = {
845 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
846 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
847 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
848};
849
850static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
851 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
852 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */
853 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
854 [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
855 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
856 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
857};
858
859/* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */
860static const struct mips_perf_event mipsxxcore_cache_map
861 [PERF_COUNT_HW_CACHE_MAX]
862 [PERF_COUNT_HW_CACHE_OP_MAX]
863 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
864[C(L1D)] = {
865 /*
866 * Like some other architectures (e.g. ARM), the performance
867 * counters don't differentiate between read and write
868 * accesses/misses, so this isn't strictly correct, but it's the
869 * best we can do. Writes and reads get combined.
870 */
871 [C(OP_READ)] = {
872 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
873 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
874 },
875 [C(OP_WRITE)] = {
876 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
877 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
878 },
879},
880[C(L1I)] = {
881 [C(OP_READ)] = {
882 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
883 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
884 },
885 [C(OP_WRITE)] = {
886 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
887 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
888 },
889 [C(OP_PREFETCH)] = {
890 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
891 /*
892 * Note that MIPS has only "hit" events countable for
893 * the prefetch operation.
894 */
895 },
896},
897[C(LL)] = {
898 [C(OP_READ)] = {
899 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
900 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
901 },
902 [C(OP_WRITE)] = {
903 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
904 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
905 },
906},
907[C(DTLB)] = {
908 [C(OP_READ)] = {
909 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
910 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
911 },
912 [C(OP_WRITE)] = {
913 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
914 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
915 },
916},
917[C(ITLB)] = {
918 [C(OP_READ)] = {
919 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
920 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
921 },
922 [C(OP_WRITE)] = {
923 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
924 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
925 },
926},
927[C(BPU)] = {
928 /* Using the same code for *HW_BRANCH* */
929 [C(OP_READ)] = {
930 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
931 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
932 },
933 [C(OP_WRITE)] = {
934 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
935 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
936 },
937},
938};
939
940/* 74K/proAptiv core has completely different cache event map. */
941static const struct mips_perf_event mipsxxcore_cache_map2
942 [PERF_COUNT_HW_CACHE_MAX]
943 [PERF_COUNT_HW_CACHE_OP_MAX]
944 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
945[C(L1D)] = {
946 /*
947 * Like some other architectures (e.g. ARM), the performance
948 * counters don't differentiate between read and write
949 * accesses/misses, so this isn't strictly correct, but it's the
950 * best we can do. Writes and reads get combined.
951 */
952 [C(OP_READ)] = {
953 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
954 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
955 },
956 [C(OP_WRITE)] = {
957 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
958 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
959 },
960},
961[C(L1I)] = {
962 [C(OP_READ)] = {
963 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
964 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
965 },
966 [C(OP_WRITE)] = {
967 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
968 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
969 },
970 [C(OP_PREFETCH)] = {
971 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
972 /*
973 * Note that MIPS has only "hit" events countable for
974 * the prefetch operation.
975 */
976 },
977},
978[C(LL)] = {
979 [C(OP_READ)] = {
980 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
981 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
982 },
983 [C(OP_WRITE)] = {
984 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
985 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
986 },
987},
988/*
989 * 74K core does not have specific DTLB events. proAptiv core has
990 * "speculative" DTLB events which are numbered 0x63 (even/odd) and
991 * not included here. One can use raw events if really needed.
992 */
993[C(ITLB)] = {
994 [C(OP_READ)] = {
995 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
996 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
997 },
998 [C(OP_WRITE)] = {
999 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1000 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1001 },
1002},
1003[C(BPU)] = {
1004 /* Using the same code for *HW_BRANCH* */
1005 [C(OP_READ)] = {
1006 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1007 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1008 },
1009 [C(OP_WRITE)] = {
1010 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1011 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1012 },
1013},
1014};
1015
1016static const struct mips_perf_event i6x00_cache_map
1017 [PERF_COUNT_HW_CACHE_MAX]
1018 [PERF_COUNT_HW_CACHE_OP_MAX]
1019 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1020[C(L1D)] = {
1021 [C(OP_READ)] = {
1022 [C(RESULT_ACCESS)] = { 0x46, CNTR_EVEN | CNTR_ODD },
1023 [C(RESULT_MISS)] = { 0x49, CNTR_EVEN | CNTR_ODD },
1024 },
1025 [C(OP_WRITE)] = {
1026 [C(RESULT_ACCESS)] = { 0x47, CNTR_EVEN | CNTR_ODD },
1027 [C(RESULT_MISS)] = { 0x4a, CNTR_EVEN | CNTR_ODD },
1028 },
1029},
1030[C(L1I)] = {
1031 [C(OP_READ)] = {
1032 [C(RESULT_ACCESS)] = { 0x84, CNTR_EVEN | CNTR_ODD },
1033 [C(RESULT_MISS)] = { 0x85, CNTR_EVEN | CNTR_ODD },
1034 },
1035},
1036[C(DTLB)] = {
1037 /* Can't distinguish read & write */
1038 [C(OP_READ)] = {
1039 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1040 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1041 },
1042 [C(OP_WRITE)] = {
1043 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1044 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1045 },
1046},
1047[C(BPU)] = {
1048 /* Conditional branches / mispredicted */
1049 [C(OP_READ)] = {
1050 [C(RESULT_ACCESS)] = { 0x15, CNTR_EVEN | CNTR_ODD },
1051 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN | CNTR_ODD },
1052 },
1053},
1054};
1055
1056static const struct mips_perf_event loongson3_cache_map
1057 [PERF_COUNT_HW_CACHE_MAX]
1058 [PERF_COUNT_HW_CACHE_OP_MAX]
1059 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1060[C(L1D)] = {
1061 /*
1062 * Like some other architectures (e.g. ARM), the performance
1063 * counters don't differentiate between read and write
1064 * accesses/misses, so this isn't strictly correct, but it's the
1065 * best we can do. Writes and reads get combined.
1066 */
1067 [C(OP_READ)] = {
1068 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1069 },
1070 [C(OP_WRITE)] = {
1071 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1072 },
1073},
1074[C(L1I)] = {
1075 [C(OP_READ)] = {
1076 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1077 },
1078 [C(OP_WRITE)] = {
1079 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1080 },
1081},
1082[C(DTLB)] = {
1083 [C(OP_READ)] = {
1084 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1085 },
1086 [C(OP_WRITE)] = {
1087 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1088 },
1089},
1090[C(ITLB)] = {
1091 [C(OP_READ)] = {
1092 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1093 },
1094 [C(OP_WRITE)] = {
1095 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1096 },
1097},
1098[C(BPU)] = {
1099 /* Using the same code for *HW_BRANCH* */
1100 [C(OP_READ)] = {
1101 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1102 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1103 },
1104 [C(OP_WRITE)] = {
1105 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN },
1106 [C(RESULT_MISS)] = { 0x02, CNTR_ODD },
1107 },
1108},
1109};
1110
1111/* BMIPS5000 */
1112static const struct mips_perf_event bmips5000_cache_map
1113 [PERF_COUNT_HW_CACHE_MAX]
1114 [PERF_COUNT_HW_CACHE_OP_MAX]
1115 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1116[C(L1D)] = {
1117 /*
1118 * Like some other architectures (e.g. ARM), the performance
1119 * counters don't differentiate between read and write
1120 * accesses/misses, so this isn't strictly correct, but it's the
1121 * best we can do. Writes and reads get combined.
1122 */
1123 [C(OP_READ)] = {
1124 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1125 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1126 },
1127 [C(OP_WRITE)] = {
1128 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1129 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1130 },
1131},
1132[C(L1I)] = {
1133 [C(OP_READ)] = {
1134 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1135 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1136 },
1137 [C(OP_WRITE)] = {
1138 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1139 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1140 },
1141 [C(OP_PREFETCH)] = {
1142 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },
1143 /*
1144 * Note that MIPS has only "hit" events countable for
1145 * the prefetch operation.
1146 */
1147 },
1148},
1149[C(LL)] = {
1150 [C(OP_READ)] = {
1151 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1152 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1153 },
1154 [C(OP_WRITE)] = {
1155 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1156 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1157 },
1158},
1159[C(BPU)] = {
1160 /* Using the same code for *HW_BRANCH* */
1161 [C(OP_READ)] = {
1162 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1163 },
1164 [C(OP_WRITE)] = {
1165 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1166 },
1167},
1168};
1169
1170
1171static const struct mips_perf_event octeon_cache_map
1172 [PERF_COUNT_HW_CACHE_MAX]
1173 [PERF_COUNT_HW_CACHE_OP_MAX]
1174 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1175[C(L1D)] = {
1176 [C(OP_READ)] = {
1177 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
1178 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
1179 },
1180 [C(OP_WRITE)] = {
1181 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1182 },
1183},
1184[C(L1I)] = {
1185 [C(OP_READ)] = {
1186 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1187 },
1188 [C(OP_PREFETCH)] = {
1189 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1190 },
1191},
1192[C(DTLB)] = {
1193 /*
1194 * Only general DTLB misses are counted use the same event for
1195 * read and write.
1196 */
1197 [C(OP_READ)] = {
1198 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1199 },
1200 [C(OP_WRITE)] = {
1201 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1202 },
1203},
1204[C(ITLB)] = {
1205 [C(OP_READ)] = {
1206 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },
1207 },
1208},
1209};
1210
1211static const struct mips_perf_event xlp_cache_map
1212 [PERF_COUNT_HW_CACHE_MAX]
1213 [PERF_COUNT_HW_CACHE_OP_MAX]
1214 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1215[C(L1D)] = {
1216 [C(OP_READ)] = {
1217 [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
1218 [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
1219 },
1220 [C(OP_WRITE)] = {
1221 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1222 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1223 },
1224},
1225[C(L1I)] = {
1226 [C(OP_READ)] = {
1227 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1228 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1229 },
1230},
1231[C(LL)] = {
1232 [C(OP_READ)] = {
1233 [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
1234 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
1235 },
1236 [C(OP_WRITE)] = {
1237 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1238 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1239 },
1240},
1241[C(DTLB)] = {
1242 /*
1243 * Only general DTLB misses are counted use the same event for
1244 * read and write.
1245 */
1246 [C(OP_READ)] = {
1247 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1248 },
1249 [C(OP_WRITE)] = {
1250 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1251 },
1252},
1253[C(ITLB)] = {
1254 [C(OP_READ)] = {
1255 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1256 },
1257 [C(OP_WRITE)] = {
1258 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1259 },
1260},
1261[C(BPU)] = {
1262 [C(OP_READ)] = {
1263 [C(RESULT_MISS)] = { 0x25, CNTR_ALL },
1264 },
1265},
1266};
1267
1268#ifdef CONFIG_MIPS_MT_SMP
1269static void check_and_calc_range(struct perf_event *event,
1270 const struct mips_perf_event *pev)
1271{
1272 struct hw_perf_event *hwc = &event->hw;
1273
1274 if (event->cpu >= 0) {
1275 if (pev->range > V) {
1276 /*
1277 * The user selected an event that is processor
1278 * wide, while expecting it to be VPE wide.
1279 */
1280 hwc->config_base |= M_TC_EN_ALL;
1281 } else {
1282 /*
1283 * FIXME: cpu_data[event->cpu].vpe_id reports 0
1284 * for both CPUs.
1285 */
1286 hwc->config_base |= M_PERFCTL_VPEID(event->cpu);
1287 hwc->config_base |= M_TC_EN_VPE;
1288 }
1289 } else
1290 hwc->config_base |= M_TC_EN_ALL;
1291}
1292#else
1293static void check_and_calc_range(struct perf_event *event,
1294 const struct mips_perf_event *pev)
1295{
1296}
1297#endif
1298
1299static int __hw_perf_event_init(struct perf_event *event)
1300{
1301 struct perf_event_attr *attr = &event->attr;
1302 struct hw_perf_event *hwc = &event->hw;
1303 const struct mips_perf_event *pev;
1304 int err;
1305
1306 /* Returning MIPS event descriptor for generic perf event. */
1307 if (PERF_TYPE_HARDWARE == event->attr.type) {
1308 if (event->attr.config >= PERF_COUNT_HW_MAX)
1309 return -EINVAL;
1310 pev = mipspmu_map_general_event(event->attr.config);
1311 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
1312 pev = mipspmu_map_cache_event(event->attr.config);
1313 } else if (PERF_TYPE_RAW == event->attr.type) {
1314 /* We are working on the global raw event. */
1315 mutex_lock(&raw_event_mutex);
1316 pev = mipspmu.map_raw_event(event->attr.config);
1317 } else {
1318 /* The event type is not (yet) supported. */
1319 return -EOPNOTSUPP;
1320 }
1321
1322 if (IS_ERR(pev)) {
1323 if (PERF_TYPE_RAW == event->attr.type)
1324 mutex_unlock(&raw_event_mutex);
1325 return PTR_ERR(pev);
1326 }
1327
1328 /*
1329 * We allow max flexibility on how each individual counter shared
1330 * by the single CPU operates (the mode exclusion and the range).
1331 */
1332 hwc->config_base = MIPS_PERFCTRL_IE;
1333
1334 /* Calculate range bits and validate it. */
1335 if (num_possible_cpus() > 1)
1336 check_and_calc_range(event, pev);
1337
1338 hwc->event_base = mipspmu_perf_event_encode(pev);
1339 if (PERF_TYPE_RAW == event->attr.type)
1340 mutex_unlock(&raw_event_mutex);
1341
1342 if (!attr->exclude_user)
1343 hwc->config_base |= MIPS_PERFCTRL_U;
1344 if (!attr->exclude_kernel) {
1345 hwc->config_base |= MIPS_PERFCTRL_K;
1346 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
1347 hwc->config_base |= MIPS_PERFCTRL_EXL;
1348 }
1349 if (!attr->exclude_hv)
1350 hwc->config_base |= MIPS_PERFCTRL_S;
1351
1352 hwc->config_base &= M_PERFCTL_CONFIG_MASK;
1353 /*
1354 * The event can belong to another cpu. We do not assign a local
1355 * counter for it for now.
1356 */
1357 hwc->idx = -1;
1358 hwc->config = 0;
1359
1360 if (!hwc->sample_period) {
1361 hwc->sample_period = mipspmu.max_period;
1362 hwc->last_period = hwc->sample_period;
1363 local64_set(&hwc->period_left, hwc->sample_period);
1364 }
1365
1366 err = 0;
1367 if (event->group_leader != event)
1368 err = validate_group(event);
1369
1370 event->destroy = hw_perf_event_destroy;
1371
1372 if (err)
1373 event->destroy(event);
1374
1375 return err;
1376}
1377
1378static void pause_local_counters(void)
1379{
1380 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1381 int ctr = mipspmu.num_counters;
1382 unsigned long flags;
1383
1384 local_irq_save(flags);
1385 do {
1386 ctr--;
1387 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr);
1388 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] &
1389 ~M_PERFCTL_COUNT_EVENT_WHENEVER);
1390 } while (ctr > 0);
1391 local_irq_restore(flags);
1392}
1393
1394static void resume_local_counters(void)
1395{
1396 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1397 int ctr = mipspmu.num_counters;
1398
1399 do {
1400 ctr--;
1401 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]);
1402 } while (ctr > 0);
1403}
1404
1405static int mipsxx_pmu_handle_shared_irq(void)
1406{
1407 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1408 struct perf_sample_data data;
1409 unsigned int counters = mipspmu.num_counters;
1410 u64 counter;
1411 int handled = IRQ_NONE;
1412 struct pt_regs *regs;
1413
1414 if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
1415 return handled;
1416 /*
1417 * First we pause the local counters, so that when we are locked
1418 * here, the counters are all paused. When it gets locked due to
1419 * perf_disable(), the timer interrupt handler will be delayed.
1420 *
1421 * See also mipsxx_pmu_start().
1422 */
1423 pause_local_counters();
1424#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1425 read_lock(&pmuint_rwlock);
1426#endif
1427
1428 regs = get_irq_regs();
1429
1430 perf_sample_data_init(&data, 0, 0);
1431
1432 switch (counters) {
1433#define HANDLE_COUNTER(n) \
1434 case n + 1: \
1435 if (test_bit(n, cpuc->used_mask)) { \
1436 counter = mipspmu.read_counter(n); \
1437 if (counter & mipspmu.overflow) { \
1438 handle_associated_event(cpuc, n, &data, regs); \
1439 handled = IRQ_HANDLED; \
1440 } \
1441 }
1442 HANDLE_COUNTER(3)
1443 HANDLE_COUNTER(2)
1444 HANDLE_COUNTER(1)
1445 HANDLE_COUNTER(0)
1446 }
1447
1448#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1449 read_unlock(&pmuint_rwlock);
1450#endif
1451 resume_local_counters();
1452
1453 /*
1454 * Do all the work for the pending perf events. We can do this
1455 * in here because the performance counter interrupt is a regular
1456 * interrupt, not NMI.
1457 */
1458 if (handled == IRQ_HANDLED)
1459 irq_work_run();
1460
1461 return handled;
1462}
1463
1464static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1465{
1466 return mipsxx_pmu_handle_shared_irq();
1467}
1468
1469/* 24K */
1470#define IS_BOTH_COUNTERS_24K_EVENT(b) \
1471 ((b) == 0 || (b) == 1 || (b) == 11)
1472
1473/* 34K */
1474#define IS_BOTH_COUNTERS_34K_EVENT(b) \
1475 ((b) == 0 || (b) == 1 || (b) == 11)
1476#ifdef CONFIG_MIPS_MT_SMP
1477#define IS_RANGE_P_34K_EVENT(r, b) \
1478 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1479 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \
1480 (r) == 176 || ((b) >= 50 && (b) <= 55) || \
1481 ((b) >= 64 && (b) <= 67))
1482#define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
1483#endif
1484
1485/* 74K */
1486#define IS_BOTH_COUNTERS_74K_EVENT(b) \
1487 ((b) == 0 || (b) == 1)
1488
1489/* proAptiv */
1490#define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b) \
1491 ((b) == 0 || (b) == 1)
1492/* P5600 */
1493#define IS_BOTH_COUNTERS_P5600_EVENT(b) \
1494 ((b) == 0 || (b) == 1)
1495
1496/* 1004K */
1497#define IS_BOTH_COUNTERS_1004K_EVENT(b) \
1498 ((b) == 0 || (b) == 1 || (b) == 11)
1499#ifdef CONFIG_MIPS_MT_SMP
1500#define IS_RANGE_P_1004K_EVENT(r, b) \
1501 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1502 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \
1503 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \
1504 (r) == 188 || (b) == 61 || (b) == 62 || \
1505 ((b) >= 64 && (b) <= 67))
1506#define IS_RANGE_V_1004K_EVENT(r) ((r) == 47)
1507#endif
1508
1509/* interAptiv */
1510#define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b) \
1511 ((b) == 0 || (b) == 1 || (b) == 11)
1512#ifdef CONFIG_MIPS_MT_SMP
1513/* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */
1514#define IS_RANGE_P_INTERAPTIV_EVENT(r, b) \
1515 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1516 (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 || \
1517 (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 && \
1518 (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 || \
1519 ((b) >= 64 && (b) <= 67))
1520#define IS_RANGE_V_INTERAPTIV_EVENT(r) ((r) == 47 || (r) == 175)
1521#endif
1522
1523/* BMIPS5000 */
1524#define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b) \
1525 ((b) == 0 || (b) == 1)
1526
1527
1528/*
1529 * For most cores the user can use 0-255 raw events, where 0-127 for the events
1530 * of even counters, and 128-255 for odd counters. Note that bit 7 is used to
1531 * indicate the even/odd bank selector. So, for example, when user wants to take
1532 * the Event Num of 15 for odd counters (by referring to the user manual), then
1533 * 128 needs to be added to 15 as the input for the event config, i.e., 143 (0x8F)
1534 * to be used.
1535 *
1536 * Some newer cores have even more events, in which case the user can use raw
1537 * events 0-511, where 0-255 are for the events of even counters, and 256-511
1538 * are for odd counters, so bit 8 is used to indicate the even/odd bank selector.
1539 */
1540static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1541{
1542 /* currently most cores have 7-bit event numbers */
1543 unsigned int raw_id = config & 0xff;
1544 unsigned int base_id = raw_id & 0x7f;
1545
1546 switch (current_cpu_type()) {
1547 case CPU_24K:
1548 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1549 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1550 else
1551 raw_event.cntr_mask =
1552 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1553#ifdef CONFIG_MIPS_MT_SMP
1554 /*
1555 * This is actually doing nothing. Non-multithreading
1556 * CPUs will not check and calculate the range.
1557 */
1558 raw_event.range = P;
1559#endif
1560 break;
1561 case CPU_34K:
1562 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1563 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1564 else
1565 raw_event.cntr_mask =
1566 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1567#ifdef CONFIG_MIPS_MT_SMP
1568 if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
1569 raw_event.range = P;
1570 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
1571 raw_event.range = V;
1572 else
1573 raw_event.range = T;
1574#endif
1575 break;
1576 case CPU_74K:
1577 case CPU_1074K:
1578 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1579 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1580 else
1581 raw_event.cntr_mask =
1582 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1583#ifdef CONFIG_MIPS_MT_SMP
1584 raw_event.range = P;
1585#endif
1586 break;
1587 case CPU_PROAPTIV:
1588 if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id))
1589 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1590 else
1591 raw_event.cntr_mask =
1592 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1593#ifdef CONFIG_MIPS_MT_SMP
1594 raw_event.range = P;
1595#endif
1596 break;
1597 case CPU_P5600:
1598 case CPU_P6600:
1599 /* 8-bit event numbers */
1600 raw_id = config & 0x1ff;
1601 base_id = raw_id & 0xff;
1602 if (IS_BOTH_COUNTERS_P5600_EVENT(base_id))
1603 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1604 else
1605 raw_event.cntr_mask =
1606 raw_id > 255 ? CNTR_ODD : CNTR_EVEN;
1607#ifdef CONFIG_MIPS_MT_SMP
1608 raw_event.range = P;
1609#endif
1610 break;
1611 case CPU_I6400:
1612 case CPU_I6500:
1613 /* 8-bit event numbers */
1614 base_id = config & 0xff;
1615 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1616 break;
1617 case CPU_1004K:
1618 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1619 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1620 else
1621 raw_event.cntr_mask =
1622 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1623#ifdef CONFIG_MIPS_MT_SMP
1624 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
1625 raw_event.range = P;
1626 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
1627 raw_event.range = V;
1628 else
1629 raw_event.range = T;
1630#endif
1631 break;
1632 case CPU_INTERAPTIV:
1633 if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id))
1634 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1635 else
1636 raw_event.cntr_mask =
1637 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1638#ifdef CONFIG_MIPS_MT_SMP
1639 if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id))
1640 raw_event.range = P;
1641 else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id)))
1642 raw_event.range = V;
1643 else
1644 raw_event.range = T;
1645#endif
1646 break;
1647 case CPU_BMIPS5000:
1648 if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id))
1649 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1650 else
1651 raw_event.cntr_mask =
1652 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1653 break;
1654 case CPU_LOONGSON3:
1655 raw_event.cntr_mask = raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1656 break;
1657 }
1658
1659 raw_event.event_id = base_id;
1660
1661 return &raw_event;
1662}
1663
1664static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
1665{
1666 unsigned int raw_id = config & 0xff;
1667 unsigned int base_id = raw_id & 0x7f;
1668
1669
1670 raw_event.cntr_mask = CNTR_ALL;
1671 raw_event.event_id = base_id;
1672
1673 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
1674 if (base_id > 0x42)
1675 return ERR_PTR(-EOPNOTSUPP);
1676 } else {
1677 if (base_id > 0x3a)
1678 return ERR_PTR(-EOPNOTSUPP);
1679 }
1680
1681 switch (base_id) {
1682 case 0x00:
1683 case 0x0f:
1684 case 0x1e:
1685 case 0x1f:
1686 case 0x2f:
1687 case 0x34:
1688 case 0x3b ... 0x3f:
1689 return ERR_PTR(-EOPNOTSUPP);
1690 default:
1691 break;
1692 }
1693
1694 return &raw_event;
1695}
1696
1697static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config)
1698{
1699 unsigned int raw_id = config & 0xff;
1700
1701 /* Only 1-63 are defined */
1702 if ((raw_id < 0x01) || (raw_id > 0x3f))
1703 return ERR_PTR(-EOPNOTSUPP);
1704
1705 raw_event.cntr_mask = CNTR_ALL;
1706 raw_event.event_id = raw_id;
1707
1708 return &raw_event;
1709}
1710
1711static int __init
1712init_hw_perf_events(void)
1713{
1714 int counters, irq;
1715 int counter_bits;
1716
1717 pr_info("Performance counters: ");
1718
1719 counters = n_counters();
1720 if (counters == 0) {
1721 pr_cont("No available PMU.\n");
1722 return -ENODEV;
1723 }
1724
1725#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1726 cpu_has_mipsmt_pertccounters = read_c0_config7() & (1<<19);
1727 if (!cpu_has_mipsmt_pertccounters)
1728 counters = counters_total_to_per_cpu(counters);
1729#endif
1730
1731 if (get_c0_perfcount_int)
1732 irq = get_c0_perfcount_int();
1733 else if (cp0_perfcount_irq >= 0)
1734 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1735 else
1736 irq = -1;
1737
1738 mipspmu.map_raw_event = mipsxx_pmu_map_raw_event;
1739
1740 switch (current_cpu_type()) {
1741 case CPU_24K:
1742 mipspmu.name = "mips/24K";
1743 mipspmu.general_event_map = &mipsxxcore_event_map;
1744 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1745 break;
1746 case CPU_34K:
1747 mipspmu.name = "mips/34K";
1748 mipspmu.general_event_map = &mipsxxcore_event_map;
1749 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1750 break;
1751 case CPU_74K:
1752 mipspmu.name = "mips/74K";
1753 mipspmu.general_event_map = &mipsxxcore_event_map2;
1754 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1755 break;
1756 case CPU_PROAPTIV:
1757 mipspmu.name = "mips/proAptiv";
1758 mipspmu.general_event_map = &mipsxxcore_event_map2;
1759 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1760 break;
1761 case CPU_P5600:
1762 mipspmu.name = "mips/P5600";
1763 mipspmu.general_event_map = &mipsxxcore_event_map2;
1764 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1765 break;
1766 case CPU_P6600:
1767 mipspmu.name = "mips/P6600";
1768 mipspmu.general_event_map = &mipsxxcore_event_map2;
1769 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
1770 break;
1771 case CPU_I6400:
1772 mipspmu.name = "mips/I6400";
1773 mipspmu.general_event_map = &i6x00_event_map;
1774 mipspmu.cache_event_map = &i6x00_cache_map;
1775 break;
1776 case CPU_I6500:
1777 mipspmu.name = "mips/I6500";
1778 mipspmu.general_event_map = &i6x00_event_map;
1779 mipspmu.cache_event_map = &i6x00_cache_map;
1780 break;
1781 case CPU_1004K:
1782 mipspmu.name = "mips/1004K";
1783 mipspmu.general_event_map = &mipsxxcore_event_map;
1784 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1785 break;
1786 case CPU_1074K:
1787 mipspmu.name = "mips/1074K";
1788 mipspmu.general_event_map = &mipsxxcore_event_map;
1789 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1790 break;
1791 case CPU_INTERAPTIV:
1792 mipspmu.name = "mips/interAptiv";
1793 mipspmu.general_event_map = &mipsxxcore_event_map;
1794 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1795 break;
1796 case CPU_LOONGSON1:
1797 mipspmu.name = "mips/loongson1";
1798 mipspmu.general_event_map = &mipsxxcore_event_map;
1799 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1800 break;
1801 case CPU_LOONGSON3:
1802 mipspmu.name = "mips/loongson3";
1803 mipspmu.general_event_map = &loongson3_event_map;
1804 mipspmu.cache_event_map = &loongson3_cache_map;
1805 break;
1806 case CPU_CAVIUM_OCTEON:
1807 case CPU_CAVIUM_OCTEON_PLUS:
1808 case CPU_CAVIUM_OCTEON2:
1809 mipspmu.name = "octeon";
1810 mipspmu.general_event_map = &octeon_event_map;
1811 mipspmu.cache_event_map = &octeon_cache_map;
1812 mipspmu.map_raw_event = octeon_pmu_map_raw_event;
1813 break;
1814 case CPU_BMIPS5000:
1815 mipspmu.name = "BMIPS5000";
1816 mipspmu.general_event_map = &bmips5000_event_map;
1817 mipspmu.cache_event_map = &bmips5000_cache_map;
1818 break;
1819 case CPU_XLP:
1820 mipspmu.name = "xlp";
1821 mipspmu.general_event_map = &xlp_event_map;
1822 mipspmu.cache_event_map = &xlp_cache_map;
1823 mipspmu.map_raw_event = xlp_pmu_map_raw_event;
1824 break;
1825 default:
1826 pr_cont("Either hardware does not support performance "
1827 "counters, or not yet implemented.\n");
1828 return -ENODEV;
1829 }
1830
1831 mipspmu.num_counters = counters;
1832 mipspmu.irq = irq;
1833
1834 if (read_c0_perfctrl0() & MIPS_PERFCTRL_W) {
1835 mipspmu.max_period = (1ULL << 63) - 1;
1836 mipspmu.valid_count = (1ULL << 63) - 1;
1837 mipspmu.overflow = 1ULL << 63;
1838 mipspmu.read_counter = mipsxx_pmu_read_counter_64;
1839 mipspmu.write_counter = mipsxx_pmu_write_counter_64;
1840 counter_bits = 64;
1841 } else {
1842 mipspmu.max_period = (1ULL << 31) - 1;
1843 mipspmu.valid_count = (1ULL << 31) - 1;
1844 mipspmu.overflow = 1ULL << 31;
1845 mipspmu.read_counter = mipsxx_pmu_read_counter;
1846 mipspmu.write_counter = mipsxx_pmu_write_counter;
1847 counter_bits = 32;
1848 }
1849
1850 on_each_cpu(reset_counters, (void *)(long)counters, 1);
1851
1852 pr_cont("%s PMU enabled, %d %d-bit counters available to each "
1853 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
1854 irq < 0 ? " (share with timer interrupt)" : "");
1855
1856 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
1857
1858 return 0;
1859}
1860early_initcall(init_hw_perf_events);
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Linux performance counter support for MIPS.
4 *
5 * Copyright (C) 2010 MIPS Technologies, Inc.
6 * Copyright (C) 2011 Cavium Networks, Inc.
7 * Author: Deng-Cheng Zhu
8 *
9 * This code is based on the implementation for ARM, which is in turn
10 * based on the sparc64 perf event code and the x86 code. Performance
11 * counter access is based on the MIPS Oprofile code. And the callchain
12 * support references the code of MIPS stacktrace.c.
13 */
14
15#include <linux/cpumask.h>
16#include <linux/interrupt.h>
17#include <linux/smp.h>
18#include <linux/kernel.h>
19#include <linux/perf_event.h>
20#include <linux/uaccess.h>
21
22#include <asm/irq.h>
23#include <asm/irq_regs.h>
24#include <asm/stacktrace.h>
25#include <asm/time.h> /* For perf_irq */
26
27#define MIPS_MAX_HWEVENTS 4
28#define MIPS_TCS_PER_COUNTER 2
29#define MIPS_CPUID_TO_COUNTER_MASK (MIPS_TCS_PER_COUNTER - 1)
30
31struct cpu_hw_events {
32 /* Array of events on this cpu. */
33 struct perf_event *events[MIPS_MAX_HWEVENTS];
34
35 /*
36 * Set the bit (indexed by the counter number) when the counter
37 * is used for an event.
38 */
39 unsigned long used_mask[BITS_TO_LONGS(MIPS_MAX_HWEVENTS)];
40
41 /*
42 * Software copy of the control register for each performance counter.
43 * MIPS CPUs vary in performance counters. They use this differently,
44 * and even may not use it.
45 */
46 unsigned int saved_ctrl[MIPS_MAX_HWEVENTS];
47};
48DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events) = {
49 .saved_ctrl = {0},
50};
51
52/* The description of MIPS performance events. */
53struct mips_perf_event {
54 unsigned int event_id;
55 /*
56 * MIPS performance counters are indexed starting from 0.
57 * CNTR_EVEN indicates the indexes of the counters to be used are
58 * even numbers.
59 */
60 unsigned int cntr_mask;
61 #define CNTR_EVEN 0x55555555
62 #define CNTR_ODD 0xaaaaaaaa
63 #define CNTR_ALL 0xffffffff
64 enum {
65 T = 0,
66 V = 1,
67 P = 2,
68 } range;
69};
70
71static struct mips_perf_event raw_event;
72static DEFINE_MUTEX(raw_event_mutex);
73
74#define C(x) PERF_COUNT_HW_CACHE_##x
75
76struct mips_pmu {
77 u64 max_period;
78 u64 valid_count;
79 u64 overflow;
80 const char *name;
81 int irq;
82 u64 (*read_counter)(unsigned int idx);
83 void (*write_counter)(unsigned int idx, u64 val);
84 const struct mips_perf_event *(*map_raw_event)(u64 config);
85 const struct mips_perf_event (*general_event_map)[PERF_COUNT_HW_MAX];
86 const struct mips_perf_event (*cache_event_map)
87 [PERF_COUNT_HW_CACHE_MAX]
88 [PERF_COUNT_HW_CACHE_OP_MAX]
89 [PERF_COUNT_HW_CACHE_RESULT_MAX];
90 unsigned int num_counters;
91};
92
93static int counter_bits;
94static struct mips_pmu mipspmu;
95
96#define M_PERFCTL_EVENT(event) (((event) << MIPS_PERFCTRL_EVENT_S) & \
97 MIPS_PERFCTRL_EVENT)
98#define M_PERFCTL_VPEID(vpe) ((vpe) << MIPS_PERFCTRL_VPEID_S)
99
100#ifdef CONFIG_CPU_BMIPS5000
101#define M_PERFCTL_MT_EN(filter) 0
102#else /* !CONFIG_CPU_BMIPS5000 */
103#define M_PERFCTL_MT_EN(filter) (filter)
104#endif /* CONFIG_CPU_BMIPS5000 */
105
106#define M_TC_EN_ALL M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_ALL)
107#define M_TC_EN_VPE M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_VPE)
108#define M_TC_EN_TC M_PERFCTL_MT_EN(MIPS_PERFCTRL_MT_EN_TC)
109
110#define M_PERFCTL_COUNT_EVENT_WHENEVER (MIPS_PERFCTRL_EXL | \
111 MIPS_PERFCTRL_K | \
112 MIPS_PERFCTRL_U | \
113 MIPS_PERFCTRL_S | \
114 MIPS_PERFCTRL_IE)
115
116#ifdef CONFIG_MIPS_MT_SMP
117#define M_PERFCTL_CONFIG_MASK 0x3fff801f
118#else
119#define M_PERFCTL_CONFIG_MASK 0x1f
120#endif
121
122#define CNTR_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1))
123
124#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
125static DEFINE_RWLOCK(pmuint_rwlock);
126
127#if defined(CONFIG_CPU_BMIPS5000)
128#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
129 0 : (smp_processor_id() & MIPS_CPUID_TO_COUNTER_MASK))
130#else
131#define vpe_id() (cpu_has_mipsmt_pertccounters ? \
132 0 : cpu_vpe_id(¤t_cpu_data))
133#endif
134
135/* Copied from op_model_mipsxx.c */
136static unsigned int vpe_shift(void)
137{
138 if (num_possible_cpus() > 1)
139 return 1;
140
141 return 0;
142}
143
144static unsigned int counters_total_to_per_cpu(unsigned int counters)
145{
146 return counters >> vpe_shift();
147}
148
149#else /* !CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
150#define vpe_id() 0
151
152#endif /* CONFIG_MIPS_PERF_SHARED_TC_COUNTERS */
153
154static void resume_local_counters(void);
155static void pause_local_counters(void);
156static irqreturn_t mipsxx_pmu_handle_irq(int, void *);
157static int mipsxx_pmu_handle_shared_irq(void);
158
159/* 0: Not Loongson-3
160 * 1: Loongson-3A1000/3B1000/3B1500
161 * 2: Loongson-3A2000/3A3000
162 * 3: Loongson-3A4000+
163 */
164
165#define LOONGSON_PMU_TYPE0 0
166#define LOONGSON_PMU_TYPE1 1
167#define LOONGSON_PMU_TYPE2 2
168#define LOONGSON_PMU_TYPE3 3
169
170static inline int get_loongson3_pmu_type(void)
171{
172 if (boot_cpu_type() != CPU_LOONGSON64)
173 return LOONGSON_PMU_TYPE0;
174 if ((boot_cpu_data.processor_id & PRID_COMP_MASK) == PRID_COMP_LEGACY)
175 return LOONGSON_PMU_TYPE1;
176 if ((boot_cpu_data.processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64C)
177 return LOONGSON_PMU_TYPE2;
178 if ((boot_cpu_data.processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64G)
179 return LOONGSON_PMU_TYPE3;
180
181 return LOONGSON_PMU_TYPE0;
182}
183
184static unsigned int mipsxx_pmu_swizzle_perf_idx(unsigned int idx)
185{
186 if (vpe_id() == 1)
187 idx = (idx + 2) & 3;
188 return idx;
189}
190
191static u64 mipsxx_pmu_read_counter(unsigned int idx)
192{
193 idx = mipsxx_pmu_swizzle_perf_idx(idx);
194
195 switch (idx) {
196 case 0:
197 /*
198 * The counters are unsigned, we must cast to truncate
199 * off the high bits.
200 */
201 return (u32)read_c0_perfcntr0();
202 case 1:
203 return (u32)read_c0_perfcntr1();
204 case 2:
205 return (u32)read_c0_perfcntr2();
206 case 3:
207 return (u32)read_c0_perfcntr3();
208 default:
209 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
210 return 0;
211 }
212}
213
214static u64 mipsxx_pmu_read_counter_64(unsigned int idx)
215{
216 u64 mask = CNTR_BIT_MASK(counter_bits);
217 idx = mipsxx_pmu_swizzle_perf_idx(idx);
218
219 switch (idx) {
220 case 0:
221 return read_c0_perfcntr0_64() & mask;
222 case 1:
223 return read_c0_perfcntr1_64() & mask;
224 case 2:
225 return read_c0_perfcntr2_64() & mask;
226 case 3:
227 return read_c0_perfcntr3_64() & mask;
228 default:
229 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
230 return 0;
231 }
232}
233
234static void mipsxx_pmu_write_counter(unsigned int idx, u64 val)
235{
236 idx = mipsxx_pmu_swizzle_perf_idx(idx);
237
238 switch (idx) {
239 case 0:
240 write_c0_perfcntr0(val);
241 return;
242 case 1:
243 write_c0_perfcntr1(val);
244 return;
245 case 2:
246 write_c0_perfcntr2(val);
247 return;
248 case 3:
249 write_c0_perfcntr3(val);
250 return;
251 }
252}
253
254static void mipsxx_pmu_write_counter_64(unsigned int idx, u64 val)
255{
256 val &= CNTR_BIT_MASK(counter_bits);
257 idx = mipsxx_pmu_swizzle_perf_idx(idx);
258
259 switch (idx) {
260 case 0:
261 write_c0_perfcntr0_64(val);
262 return;
263 case 1:
264 write_c0_perfcntr1_64(val);
265 return;
266 case 2:
267 write_c0_perfcntr2_64(val);
268 return;
269 case 3:
270 write_c0_perfcntr3_64(val);
271 return;
272 }
273}
274
275static unsigned int mipsxx_pmu_read_control(unsigned int idx)
276{
277 idx = mipsxx_pmu_swizzle_perf_idx(idx);
278
279 switch (idx) {
280 case 0:
281 return read_c0_perfctrl0();
282 case 1:
283 return read_c0_perfctrl1();
284 case 2:
285 return read_c0_perfctrl2();
286 case 3:
287 return read_c0_perfctrl3();
288 default:
289 WARN_ONCE(1, "Invalid performance counter number (%d)\n", idx);
290 return 0;
291 }
292}
293
294static void mipsxx_pmu_write_control(unsigned int idx, unsigned int val)
295{
296 idx = mipsxx_pmu_swizzle_perf_idx(idx);
297
298 switch (idx) {
299 case 0:
300 write_c0_perfctrl0(val);
301 return;
302 case 1:
303 write_c0_perfctrl1(val);
304 return;
305 case 2:
306 write_c0_perfctrl2(val);
307 return;
308 case 3:
309 write_c0_perfctrl3(val);
310 return;
311 }
312}
313
314static int mipsxx_pmu_alloc_counter(struct cpu_hw_events *cpuc,
315 struct hw_perf_event *hwc)
316{
317 int i;
318 unsigned long cntr_mask;
319
320 /*
321 * We only need to care the counter mask. The range has been
322 * checked definitely.
323 */
324 if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
325 cntr_mask = (hwc->event_base >> 10) & 0xffff;
326 else
327 cntr_mask = (hwc->event_base >> 8) & 0xffff;
328
329 for (i = mipspmu.num_counters - 1; i >= 0; i--) {
330 /*
331 * Note that some MIPS perf events can be counted by both
332 * even and odd counters, wheresas many other are only by
333 * even _or_ odd counters. This introduces an issue that
334 * when the former kind of event takes the counter the
335 * latter kind of event wants to use, then the "counter
336 * allocation" for the latter event will fail. In fact if
337 * they can be dynamically swapped, they both feel happy.
338 * But here we leave this issue alone for now.
339 */
340 if (test_bit(i, &cntr_mask) &&
341 !test_and_set_bit(i, cpuc->used_mask))
342 return i;
343 }
344
345 return -EAGAIN;
346}
347
348static void mipsxx_pmu_enable_event(struct hw_perf_event *evt, int idx)
349{
350 struct perf_event *event = container_of(evt, struct perf_event, hw);
351 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
352 unsigned int range = evt->event_base >> 24;
353
354 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
355
356 if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
357 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0x3ff) |
358 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
359 /* Make sure interrupt enabled. */
360 MIPS_PERFCTRL_IE;
361 else
362 cpuc->saved_ctrl[idx] = M_PERFCTL_EVENT(evt->event_base & 0xff) |
363 (evt->config_base & M_PERFCTL_CONFIG_MASK) |
364 /* Make sure interrupt enabled. */
365 MIPS_PERFCTRL_IE;
366
367 if (IS_ENABLED(CONFIG_CPU_BMIPS5000)) {
368 /* enable the counter for the calling thread */
369 cpuc->saved_ctrl[idx] |=
370 (1 << (12 + vpe_id())) | BRCM_PERFCTRL_TC;
371 } else if (IS_ENABLED(CONFIG_MIPS_MT_SMP) && range > V) {
372 /* The counter is processor wide. Set it up to count all TCs. */
373 pr_debug("Enabling perf counter for all TCs\n");
374 cpuc->saved_ctrl[idx] |= M_TC_EN_ALL;
375 } else {
376 unsigned int cpu, ctrl;
377
378 /*
379 * Set up the counter for a particular CPU when event->cpu is
380 * a valid CPU number. Otherwise set up the counter for the CPU
381 * scheduling this thread.
382 */
383 cpu = (event->cpu >= 0) ? event->cpu : smp_processor_id();
384
385 ctrl = M_PERFCTL_VPEID(cpu_vpe_id(&cpu_data[cpu]));
386 ctrl |= M_TC_EN_VPE;
387 cpuc->saved_ctrl[idx] |= ctrl;
388 pr_debug("Enabling perf counter for CPU%d\n", cpu);
389 }
390 /*
391 * We do not actually let the counter run. Leave it until start().
392 */
393}
394
395static void mipsxx_pmu_disable_event(int idx)
396{
397 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
398 unsigned long flags;
399
400 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
401
402 local_irq_save(flags);
403 cpuc->saved_ctrl[idx] = mipsxx_pmu_read_control(idx) &
404 ~M_PERFCTL_COUNT_EVENT_WHENEVER;
405 mipsxx_pmu_write_control(idx, cpuc->saved_ctrl[idx]);
406 local_irq_restore(flags);
407}
408
409static int mipspmu_event_set_period(struct perf_event *event,
410 struct hw_perf_event *hwc,
411 int idx)
412{
413 u64 left = local64_read(&hwc->period_left);
414 u64 period = hwc->sample_period;
415 int ret = 0;
416
417 if (unlikely((left + period) & (1ULL << 63))) {
418 /* left underflowed by more than period. */
419 left = period;
420 local64_set(&hwc->period_left, left);
421 hwc->last_period = period;
422 ret = 1;
423 } else if (unlikely((left + period) <= period)) {
424 /* left underflowed by less than period. */
425 left += period;
426 local64_set(&hwc->period_left, left);
427 hwc->last_period = period;
428 ret = 1;
429 }
430
431 if (left > mipspmu.max_period) {
432 left = mipspmu.max_period;
433 local64_set(&hwc->period_left, left);
434 }
435
436 local64_set(&hwc->prev_count, mipspmu.overflow - left);
437
438 if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
439 mipsxx_pmu_write_control(idx,
440 M_PERFCTL_EVENT(hwc->event_base & 0x3ff));
441
442 mipspmu.write_counter(idx, mipspmu.overflow - left);
443
444 perf_event_update_userpage(event);
445
446 return ret;
447}
448
449static void mipspmu_event_update(struct perf_event *event,
450 struct hw_perf_event *hwc,
451 int idx)
452{
453 u64 prev_raw_count, new_raw_count;
454 u64 delta;
455
456again:
457 prev_raw_count = local64_read(&hwc->prev_count);
458 new_raw_count = mipspmu.read_counter(idx);
459
460 if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
461 new_raw_count) != prev_raw_count)
462 goto again;
463
464 delta = new_raw_count - prev_raw_count;
465
466 local64_add(delta, &event->count);
467 local64_sub(delta, &hwc->period_left);
468}
469
470static void mipspmu_start(struct perf_event *event, int flags)
471{
472 struct hw_perf_event *hwc = &event->hw;
473
474 if (flags & PERF_EF_RELOAD)
475 WARN_ON_ONCE(!(hwc->state & PERF_HES_UPTODATE));
476
477 hwc->state = 0;
478
479 /* Set the period for the event. */
480 mipspmu_event_set_period(event, hwc, hwc->idx);
481
482 /* Enable the event. */
483 mipsxx_pmu_enable_event(hwc, hwc->idx);
484}
485
486static void mipspmu_stop(struct perf_event *event, int flags)
487{
488 struct hw_perf_event *hwc = &event->hw;
489
490 if (!(hwc->state & PERF_HES_STOPPED)) {
491 /* We are working on a local event. */
492 mipsxx_pmu_disable_event(hwc->idx);
493 barrier();
494 mipspmu_event_update(event, hwc, hwc->idx);
495 hwc->state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
496 }
497}
498
499static int mipspmu_add(struct perf_event *event, int flags)
500{
501 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
502 struct hw_perf_event *hwc = &event->hw;
503 int idx;
504 int err = 0;
505
506 perf_pmu_disable(event->pmu);
507
508 /* To look for a free counter for this event. */
509 idx = mipsxx_pmu_alloc_counter(cpuc, hwc);
510 if (idx < 0) {
511 err = idx;
512 goto out;
513 }
514
515 /*
516 * If there is an event in the counter we are going to use then
517 * make sure it is disabled.
518 */
519 event->hw.idx = idx;
520 mipsxx_pmu_disable_event(idx);
521 cpuc->events[idx] = event;
522
523 hwc->state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
524 if (flags & PERF_EF_START)
525 mipspmu_start(event, PERF_EF_RELOAD);
526
527 /* Propagate our changes to the userspace mapping. */
528 perf_event_update_userpage(event);
529
530out:
531 perf_pmu_enable(event->pmu);
532 return err;
533}
534
535static void mipspmu_del(struct perf_event *event, int flags)
536{
537 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
538 struct hw_perf_event *hwc = &event->hw;
539 int idx = hwc->idx;
540
541 WARN_ON(idx < 0 || idx >= mipspmu.num_counters);
542
543 mipspmu_stop(event, PERF_EF_UPDATE);
544 cpuc->events[idx] = NULL;
545 clear_bit(idx, cpuc->used_mask);
546
547 perf_event_update_userpage(event);
548}
549
550static void mipspmu_read(struct perf_event *event)
551{
552 struct hw_perf_event *hwc = &event->hw;
553
554 /* Don't read disabled counters! */
555 if (hwc->idx < 0)
556 return;
557
558 mipspmu_event_update(event, hwc, hwc->idx);
559}
560
561static void mipspmu_enable(struct pmu *pmu)
562{
563#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
564 write_unlock(&pmuint_rwlock);
565#endif
566 resume_local_counters();
567}
568
569/*
570 * MIPS performance counters can be per-TC. The control registers can
571 * not be directly accessed across CPUs. Hence if we want to do global
572 * control, we need cross CPU calls. on_each_cpu() can help us, but we
573 * can not make sure this function is called with interrupts enabled. So
574 * here we pause local counters and then grab a rwlock and leave the
575 * counters on other CPUs alone. If any counter interrupt raises while
576 * we own the write lock, simply pause local counters on that CPU and
577 * spin in the handler. Also we know we won't be switched to another
578 * CPU after pausing local counters and before grabbing the lock.
579 */
580static void mipspmu_disable(struct pmu *pmu)
581{
582 pause_local_counters();
583#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
584 write_lock(&pmuint_rwlock);
585#endif
586}
587
588static atomic_t active_events = ATOMIC_INIT(0);
589static DEFINE_MUTEX(pmu_reserve_mutex);
590static int (*save_perf_irq)(void);
591
592static int mipspmu_get_irq(void)
593{
594 int err;
595
596 if (mipspmu.irq >= 0) {
597 /* Request my own irq handler. */
598 err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq,
599 IRQF_PERCPU | IRQF_NOBALANCING |
600 IRQF_NO_THREAD | IRQF_NO_SUSPEND |
601 IRQF_SHARED,
602 "mips_perf_pmu", &mipspmu);
603 if (err) {
604 pr_warn("Unable to request IRQ%d for MIPS performance counters!\n",
605 mipspmu.irq);
606 }
607 } else if (cp0_perfcount_irq < 0) {
608 /*
609 * We are sharing the irq number with the timer interrupt.
610 */
611 save_perf_irq = perf_irq;
612 perf_irq = mipsxx_pmu_handle_shared_irq;
613 err = 0;
614 } else {
615 pr_warn("The platform hasn't properly defined its interrupt controller\n");
616 err = -ENOENT;
617 }
618
619 return err;
620}
621
622static void mipspmu_free_irq(void)
623{
624 if (mipspmu.irq >= 0)
625 free_irq(mipspmu.irq, &mipspmu);
626 else if (cp0_perfcount_irq < 0)
627 perf_irq = save_perf_irq;
628}
629
630/*
631 * mipsxx/rm9000/loongson2 have different performance counters, they have
632 * specific low-level init routines.
633 */
634static void reset_counters(void *arg);
635static int __hw_perf_event_init(struct perf_event *event);
636
637static void hw_perf_event_destroy(struct perf_event *event)
638{
639 if (atomic_dec_and_mutex_lock(&active_events,
640 &pmu_reserve_mutex)) {
641 /*
642 * We must not call the destroy function with interrupts
643 * disabled.
644 */
645 on_each_cpu(reset_counters,
646 (void *)(long)mipspmu.num_counters, 1);
647 mipspmu_free_irq();
648 mutex_unlock(&pmu_reserve_mutex);
649 }
650}
651
652static int mipspmu_event_init(struct perf_event *event)
653{
654 int err = 0;
655
656 /* does not support taken branch sampling */
657 if (has_branch_stack(event))
658 return -EOPNOTSUPP;
659
660 switch (event->attr.type) {
661 case PERF_TYPE_RAW:
662 case PERF_TYPE_HARDWARE:
663 case PERF_TYPE_HW_CACHE:
664 break;
665
666 default:
667 return -ENOENT;
668 }
669
670 if (event->cpu >= 0 && !cpu_online(event->cpu))
671 return -ENODEV;
672
673 if (!atomic_inc_not_zero(&active_events)) {
674 mutex_lock(&pmu_reserve_mutex);
675 if (atomic_read(&active_events) == 0)
676 err = mipspmu_get_irq();
677
678 if (!err)
679 atomic_inc(&active_events);
680 mutex_unlock(&pmu_reserve_mutex);
681 }
682
683 if (err)
684 return err;
685
686 return __hw_perf_event_init(event);
687}
688
689static struct pmu pmu = {
690 .pmu_enable = mipspmu_enable,
691 .pmu_disable = mipspmu_disable,
692 .event_init = mipspmu_event_init,
693 .add = mipspmu_add,
694 .del = mipspmu_del,
695 .start = mipspmu_start,
696 .stop = mipspmu_stop,
697 .read = mipspmu_read,
698};
699
700static unsigned int mipspmu_perf_event_encode(const struct mips_perf_event *pev)
701{
702/*
703 * Top 8 bits for range, next 16 bits for cntr_mask, lowest 8 bits for
704 * event_id.
705 */
706#ifdef CONFIG_MIPS_MT_SMP
707 if (num_possible_cpus() > 1)
708 return ((unsigned int)pev->range << 24) |
709 (pev->cntr_mask & 0xffff00) |
710 (pev->event_id & 0xff);
711 else
712#endif /* CONFIG_MIPS_MT_SMP */
713 {
714 if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2)
715 return (pev->cntr_mask & 0xfffc00) |
716 (pev->event_id & 0x3ff);
717 else
718 return (pev->cntr_mask & 0xffff00) |
719 (pev->event_id & 0xff);
720 }
721}
722
723static const struct mips_perf_event *mipspmu_map_general_event(int idx)
724{
725
726 if ((*mipspmu.general_event_map)[idx].cntr_mask == 0)
727 return ERR_PTR(-EOPNOTSUPP);
728 return &(*mipspmu.general_event_map)[idx];
729}
730
731static const struct mips_perf_event *mipspmu_map_cache_event(u64 config)
732{
733 unsigned int cache_type, cache_op, cache_result;
734 const struct mips_perf_event *pev;
735
736 cache_type = (config >> 0) & 0xff;
737 if (cache_type >= PERF_COUNT_HW_CACHE_MAX)
738 return ERR_PTR(-EINVAL);
739
740 cache_op = (config >> 8) & 0xff;
741 if (cache_op >= PERF_COUNT_HW_CACHE_OP_MAX)
742 return ERR_PTR(-EINVAL);
743
744 cache_result = (config >> 16) & 0xff;
745 if (cache_result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
746 return ERR_PTR(-EINVAL);
747
748 pev = &((*mipspmu.cache_event_map)
749 [cache_type]
750 [cache_op]
751 [cache_result]);
752
753 if (pev->cntr_mask == 0)
754 return ERR_PTR(-EOPNOTSUPP);
755
756 return pev;
757
758}
759
760static int validate_group(struct perf_event *event)
761{
762 struct perf_event *sibling, *leader = event->group_leader;
763 struct cpu_hw_events fake_cpuc;
764
765 memset(&fake_cpuc, 0, sizeof(fake_cpuc));
766
767 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &leader->hw) < 0)
768 return -EINVAL;
769
770 for_each_sibling_event(sibling, leader) {
771 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &sibling->hw) < 0)
772 return -EINVAL;
773 }
774
775 if (mipsxx_pmu_alloc_counter(&fake_cpuc, &event->hw) < 0)
776 return -EINVAL;
777
778 return 0;
779}
780
781/* This is needed by specific irq handlers in perf_event_*.c */
782static void handle_associated_event(struct cpu_hw_events *cpuc,
783 int idx, struct perf_sample_data *data,
784 struct pt_regs *regs)
785{
786 struct perf_event *event = cpuc->events[idx];
787 struct hw_perf_event *hwc = &event->hw;
788
789 mipspmu_event_update(event, hwc, idx);
790 data->period = event->hw.last_period;
791 if (!mipspmu_event_set_period(event, hwc, idx))
792 return;
793
794 if (perf_event_overflow(event, data, regs))
795 mipsxx_pmu_disable_event(idx);
796}
797
798
799static int __n_counters(void)
800{
801 if (!cpu_has_perf)
802 return 0;
803 if (!(read_c0_perfctrl0() & MIPS_PERFCTRL_M))
804 return 1;
805 if (!(read_c0_perfctrl1() & MIPS_PERFCTRL_M))
806 return 2;
807 if (!(read_c0_perfctrl2() & MIPS_PERFCTRL_M))
808 return 3;
809
810 return 4;
811}
812
813static int n_counters(void)
814{
815 int counters;
816
817 switch (current_cpu_type()) {
818 case CPU_R10000:
819 counters = 2;
820 break;
821
822 case CPU_R12000:
823 case CPU_R14000:
824 case CPU_R16000:
825 counters = 4;
826 break;
827
828 default:
829 counters = __n_counters();
830 }
831
832 return counters;
833}
834
835static void loongson3_reset_counters(void *arg)
836{
837 int counters = (int)(long)arg;
838
839 switch (counters) {
840 case 4:
841 mipsxx_pmu_write_control(3, 0);
842 mipspmu.write_counter(3, 0);
843 mipsxx_pmu_write_control(3, 127<<5);
844 mipspmu.write_counter(3, 0);
845 mipsxx_pmu_write_control(3, 191<<5);
846 mipspmu.write_counter(3, 0);
847 mipsxx_pmu_write_control(3, 255<<5);
848 mipspmu.write_counter(3, 0);
849 mipsxx_pmu_write_control(3, 319<<5);
850 mipspmu.write_counter(3, 0);
851 mipsxx_pmu_write_control(3, 383<<5);
852 mipspmu.write_counter(3, 0);
853 mipsxx_pmu_write_control(3, 575<<5);
854 mipspmu.write_counter(3, 0);
855 fallthrough;
856 case 3:
857 mipsxx_pmu_write_control(2, 0);
858 mipspmu.write_counter(2, 0);
859 mipsxx_pmu_write_control(2, 127<<5);
860 mipspmu.write_counter(2, 0);
861 mipsxx_pmu_write_control(2, 191<<5);
862 mipspmu.write_counter(2, 0);
863 mipsxx_pmu_write_control(2, 255<<5);
864 mipspmu.write_counter(2, 0);
865 mipsxx_pmu_write_control(2, 319<<5);
866 mipspmu.write_counter(2, 0);
867 mipsxx_pmu_write_control(2, 383<<5);
868 mipspmu.write_counter(2, 0);
869 mipsxx_pmu_write_control(2, 575<<5);
870 mipspmu.write_counter(2, 0);
871 fallthrough;
872 case 2:
873 mipsxx_pmu_write_control(1, 0);
874 mipspmu.write_counter(1, 0);
875 mipsxx_pmu_write_control(1, 127<<5);
876 mipspmu.write_counter(1, 0);
877 mipsxx_pmu_write_control(1, 191<<5);
878 mipspmu.write_counter(1, 0);
879 mipsxx_pmu_write_control(1, 255<<5);
880 mipspmu.write_counter(1, 0);
881 mipsxx_pmu_write_control(1, 319<<5);
882 mipspmu.write_counter(1, 0);
883 mipsxx_pmu_write_control(1, 383<<5);
884 mipspmu.write_counter(1, 0);
885 mipsxx_pmu_write_control(1, 575<<5);
886 mipspmu.write_counter(1, 0);
887 fallthrough;
888 case 1:
889 mipsxx_pmu_write_control(0, 0);
890 mipspmu.write_counter(0, 0);
891 mipsxx_pmu_write_control(0, 127<<5);
892 mipspmu.write_counter(0, 0);
893 mipsxx_pmu_write_control(0, 191<<5);
894 mipspmu.write_counter(0, 0);
895 mipsxx_pmu_write_control(0, 255<<5);
896 mipspmu.write_counter(0, 0);
897 mipsxx_pmu_write_control(0, 319<<5);
898 mipspmu.write_counter(0, 0);
899 mipsxx_pmu_write_control(0, 383<<5);
900 mipspmu.write_counter(0, 0);
901 mipsxx_pmu_write_control(0, 575<<5);
902 mipspmu.write_counter(0, 0);
903 break;
904 }
905}
906
907static void reset_counters(void *arg)
908{
909 int counters = (int)(long)arg;
910
911 if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2) {
912 loongson3_reset_counters(arg);
913 return;
914 }
915
916 switch (counters) {
917 case 4:
918 mipsxx_pmu_write_control(3, 0);
919 mipspmu.write_counter(3, 0);
920 fallthrough;
921 case 3:
922 mipsxx_pmu_write_control(2, 0);
923 mipspmu.write_counter(2, 0);
924 fallthrough;
925 case 2:
926 mipsxx_pmu_write_control(1, 0);
927 mipspmu.write_counter(1, 0);
928 fallthrough;
929 case 1:
930 mipsxx_pmu_write_control(0, 0);
931 mipspmu.write_counter(0, 0);
932 break;
933 }
934}
935
936/* 24K/34K/1004K/interAptiv/loongson1 cores share the same event map. */
937static const struct mips_perf_event mipsxxcore_event_map
938 [PERF_COUNT_HW_MAX] = {
939 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
940 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
941 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_EVEN, T },
942 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
943};
944
945/* 74K/proAptiv core has different branch event code. */
946static const struct mips_perf_event mipsxxcore_event_map2
947 [PERF_COUNT_HW_MAX] = {
948 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, P },
949 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
950 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x27, CNTR_EVEN, T },
951 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x27, CNTR_ODD, T },
952};
953
954static const struct mips_perf_event i6x00_event_map[PERF_COUNT_HW_MAX] = {
955 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD },
956 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD },
957 /* These only count dcache, not icache */
958 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x45, CNTR_EVEN | CNTR_ODD },
959 [PERF_COUNT_HW_CACHE_MISSES] = { 0x48, CNTR_EVEN | CNTR_ODD },
960 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x15, CNTR_EVEN | CNTR_ODD },
961 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x16, CNTR_EVEN | CNTR_ODD },
962};
963
964static const struct mips_perf_event loongson3_event_map1[PERF_COUNT_HW_MAX] = {
965 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN },
966 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x00, CNTR_ODD },
967 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x01, CNTR_EVEN },
968 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x01, CNTR_ODD },
969};
970
971static const struct mips_perf_event loongson3_event_map2[PERF_COUNT_HW_MAX] = {
972 [PERF_COUNT_HW_CPU_CYCLES] = { 0x80, CNTR_ALL },
973 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x81, CNTR_ALL },
974 [PERF_COUNT_HW_CACHE_MISSES] = { 0x18, CNTR_ALL },
975 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x94, CNTR_ALL },
976 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x9c, CNTR_ALL },
977};
978
979static const struct mips_perf_event loongson3_event_map3[PERF_COUNT_HW_MAX] = {
980 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_ALL },
981 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_ALL },
982 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x1c, CNTR_ALL },
983 [PERF_COUNT_HW_CACHE_MISSES] = { 0x1d, CNTR_ALL },
984 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x02, CNTR_ALL },
985 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x08, CNTR_ALL },
986};
987
988static const struct mips_perf_event octeon_event_map[PERF_COUNT_HW_MAX] = {
989 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
990 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x03, CNTR_ALL },
991 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x2b, CNTR_ALL },
992 [PERF_COUNT_HW_CACHE_MISSES] = { 0x2e, CNTR_ALL },
993 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x08, CNTR_ALL },
994 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x09, CNTR_ALL },
995 [PERF_COUNT_HW_BUS_CYCLES] = { 0x25, CNTR_ALL },
996};
997
998static const struct mips_perf_event bmips5000_event_map
999 [PERF_COUNT_HW_MAX] = {
1000 [PERF_COUNT_HW_CPU_CYCLES] = { 0x00, CNTR_EVEN | CNTR_ODD, T },
1001 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x01, CNTR_EVEN | CNTR_ODD, T },
1002 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x02, CNTR_ODD, T },
1003};
1004
1005static const struct mips_perf_event xlp_event_map[PERF_COUNT_HW_MAX] = {
1006 [PERF_COUNT_HW_CPU_CYCLES] = { 0x01, CNTR_ALL },
1007 [PERF_COUNT_HW_INSTRUCTIONS] = { 0x18, CNTR_ALL }, /* PAPI_TOT_INS */
1008 [PERF_COUNT_HW_CACHE_REFERENCES] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1009 [PERF_COUNT_HW_CACHE_MISSES] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1010 [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = { 0x1b, CNTR_ALL }, /* PAPI_BR_CN */
1011 [PERF_COUNT_HW_BRANCH_MISSES] = { 0x1c, CNTR_ALL }, /* PAPI_BR_MSP */
1012};
1013
1014/* 24K/34K/1004K/interAptiv/loongson1 cores share the same cache event map. */
1015static const struct mips_perf_event mipsxxcore_cache_map
1016 [PERF_COUNT_HW_CACHE_MAX]
1017 [PERF_COUNT_HW_CACHE_OP_MAX]
1018 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1019[C(L1D)] = {
1020 /*
1021 * Like some other architectures (e.g. ARM), the performance
1022 * counters don't differentiate between read and write
1023 * accesses/misses, so this isn't strictly correct, but it's the
1024 * best we can do. Writes and reads get combined.
1025 */
1026 [C(OP_READ)] = {
1027 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1028 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1029 },
1030 [C(OP_WRITE)] = {
1031 [C(RESULT_ACCESS)] = { 0x0a, CNTR_EVEN, T },
1032 [C(RESULT_MISS)] = { 0x0b, CNTR_EVEN | CNTR_ODD, T },
1033 },
1034},
1035[C(L1I)] = {
1036 [C(OP_READ)] = {
1037 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
1038 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
1039 },
1040 [C(OP_WRITE)] = {
1041 [C(RESULT_ACCESS)] = { 0x09, CNTR_EVEN, T },
1042 [C(RESULT_MISS)] = { 0x09, CNTR_ODD, T },
1043 },
1044 [C(OP_PREFETCH)] = {
1045 [C(RESULT_ACCESS)] = { 0x14, CNTR_EVEN, T },
1046 /*
1047 * Note that MIPS has only "hit" events countable for
1048 * the prefetch operation.
1049 */
1050 },
1051},
1052[C(LL)] = {
1053 [C(OP_READ)] = {
1054 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
1055 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
1056 },
1057 [C(OP_WRITE)] = {
1058 [C(RESULT_ACCESS)] = { 0x15, CNTR_ODD, P },
1059 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN, P },
1060 },
1061},
1062[C(DTLB)] = {
1063 [C(OP_READ)] = {
1064 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1065 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1066 },
1067 [C(OP_WRITE)] = {
1068 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1069 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1070 },
1071},
1072[C(ITLB)] = {
1073 [C(OP_READ)] = {
1074 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
1075 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
1076 },
1077 [C(OP_WRITE)] = {
1078 [C(RESULT_ACCESS)] = { 0x05, CNTR_EVEN, T },
1079 [C(RESULT_MISS)] = { 0x05, CNTR_ODD, T },
1080 },
1081},
1082[C(BPU)] = {
1083 /* Using the same code for *HW_BRANCH* */
1084 [C(OP_READ)] = {
1085 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
1086 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1087 },
1088 [C(OP_WRITE)] = {
1089 [C(RESULT_ACCESS)] = { 0x02, CNTR_EVEN, T },
1090 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1091 },
1092},
1093};
1094
1095/* 74K/proAptiv core has completely different cache event map. */
1096static const struct mips_perf_event mipsxxcore_cache_map2
1097 [PERF_COUNT_HW_CACHE_MAX]
1098 [PERF_COUNT_HW_CACHE_OP_MAX]
1099 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1100[C(L1D)] = {
1101 /*
1102 * Like some other architectures (e.g. ARM), the performance
1103 * counters don't differentiate between read and write
1104 * accesses/misses, so this isn't strictly correct, but it's the
1105 * best we can do. Writes and reads get combined.
1106 */
1107 [C(OP_READ)] = {
1108 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
1109 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
1110 },
1111 [C(OP_WRITE)] = {
1112 [C(RESULT_ACCESS)] = { 0x17, CNTR_ODD, T },
1113 [C(RESULT_MISS)] = { 0x18, CNTR_ODD, T },
1114 },
1115},
1116[C(L1I)] = {
1117 [C(OP_READ)] = {
1118 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1119 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1120 },
1121 [C(OP_WRITE)] = {
1122 [C(RESULT_ACCESS)] = { 0x06, CNTR_EVEN, T },
1123 [C(RESULT_MISS)] = { 0x06, CNTR_ODD, T },
1124 },
1125 [C(OP_PREFETCH)] = {
1126 [C(RESULT_ACCESS)] = { 0x34, CNTR_EVEN, T },
1127 /*
1128 * Note that MIPS has only "hit" events countable for
1129 * the prefetch operation.
1130 */
1131 },
1132},
1133[C(LL)] = {
1134 [C(OP_READ)] = {
1135 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
1136 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
1137 },
1138 [C(OP_WRITE)] = {
1139 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ODD, P },
1140 [C(RESULT_MISS)] = { 0x1d, CNTR_EVEN, P },
1141 },
1142},
1143/*
1144 * 74K core does not have specific DTLB events. proAptiv core has
1145 * "speculative" DTLB events which are numbered 0x63 (even/odd) and
1146 * not included here. One can use raw events if really needed.
1147 */
1148[C(ITLB)] = {
1149 [C(OP_READ)] = {
1150 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1151 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1152 },
1153 [C(OP_WRITE)] = {
1154 [C(RESULT_ACCESS)] = { 0x04, CNTR_EVEN, T },
1155 [C(RESULT_MISS)] = { 0x04, CNTR_ODD, T },
1156 },
1157},
1158[C(BPU)] = {
1159 /* Using the same code for *HW_BRANCH* */
1160 [C(OP_READ)] = {
1161 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1162 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1163 },
1164 [C(OP_WRITE)] = {
1165 [C(RESULT_ACCESS)] = { 0x27, CNTR_EVEN, T },
1166 [C(RESULT_MISS)] = { 0x27, CNTR_ODD, T },
1167 },
1168},
1169};
1170
1171static const struct mips_perf_event i6x00_cache_map
1172 [PERF_COUNT_HW_CACHE_MAX]
1173 [PERF_COUNT_HW_CACHE_OP_MAX]
1174 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1175[C(L1D)] = {
1176 [C(OP_READ)] = {
1177 [C(RESULT_ACCESS)] = { 0x46, CNTR_EVEN | CNTR_ODD },
1178 [C(RESULT_MISS)] = { 0x49, CNTR_EVEN | CNTR_ODD },
1179 },
1180 [C(OP_WRITE)] = {
1181 [C(RESULT_ACCESS)] = { 0x47, CNTR_EVEN | CNTR_ODD },
1182 [C(RESULT_MISS)] = { 0x4a, CNTR_EVEN | CNTR_ODD },
1183 },
1184},
1185[C(L1I)] = {
1186 [C(OP_READ)] = {
1187 [C(RESULT_ACCESS)] = { 0x84, CNTR_EVEN | CNTR_ODD },
1188 [C(RESULT_MISS)] = { 0x85, CNTR_EVEN | CNTR_ODD },
1189 },
1190},
1191[C(DTLB)] = {
1192 /* Can't distinguish read & write */
1193 [C(OP_READ)] = {
1194 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1195 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1196 },
1197 [C(OP_WRITE)] = {
1198 [C(RESULT_ACCESS)] = { 0x40, CNTR_EVEN | CNTR_ODD },
1199 [C(RESULT_MISS)] = { 0x41, CNTR_EVEN | CNTR_ODD },
1200 },
1201},
1202[C(BPU)] = {
1203 /* Conditional branches / mispredicted */
1204 [C(OP_READ)] = {
1205 [C(RESULT_ACCESS)] = { 0x15, CNTR_EVEN | CNTR_ODD },
1206 [C(RESULT_MISS)] = { 0x16, CNTR_EVEN | CNTR_ODD },
1207 },
1208},
1209};
1210
1211static const struct mips_perf_event loongson3_cache_map1
1212 [PERF_COUNT_HW_CACHE_MAX]
1213 [PERF_COUNT_HW_CACHE_OP_MAX]
1214 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1215[C(L1D)] = {
1216 /*
1217 * Like some other architectures (e.g. ARM), the performance
1218 * counters don't differentiate between read and write
1219 * accesses/misses, so this isn't strictly correct, but it's the
1220 * best we can do. Writes and reads get combined.
1221 */
1222 [C(OP_READ)] = {
1223 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1224 },
1225 [C(OP_WRITE)] = {
1226 [C(RESULT_MISS)] = { 0x04, CNTR_ODD },
1227 },
1228},
1229[C(L1I)] = {
1230 [C(OP_READ)] = {
1231 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1232 },
1233 [C(OP_WRITE)] = {
1234 [C(RESULT_MISS)] = { 0x04, CNTR_EVEN },
1235 },
1236},
1237[C(DTLB)] = {
1238 [C(OP_READ)] = {
1239 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1240 },
1241 [C(OP_WRITE)] = {
1242 [C(RESULT_MISS)] = { 0x09, CNTR_ODD },
1243 },
1244},
1245[C(ITLB)] = {
1246 [C(OP_READ)] = {
1247 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1248 },
1249 [C(OP_WRITE)] = {
1250 [C(RESULT_MISS)] = { 0x0c, CNTR_ODD },
1251 },
1252},
1253[C(BPU)] = {
1254 /* Using the same code for *HW_BRANCH* */
1255 [C(OP_READ)] = {
1256 [C(RESULT_ACCESS)] = { 0x01, CNTR_EVEN },
1257 [C(RESULT_MISS)] = { 0x01, CNTR_ODD },
1258 },
1259 [C(OP_WRITE)] = {
1260 [C(RESULT_ACCESS)] = { 0x01, CNTR_EVEN },
1261 [C(RESULT_MISS)] = { 0x01, CNTR_ODD },
1262 },
1263},
1264};
1265
1266static const struct mips_perf_event loongson3_cache_map2
1267 [PERF_COUNT_HW_CACHE_MAX]
1268 [PERF_COUNT_HW_CACHE_OP_MAX]
1269 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1270[C(L1D)] = {
1271 /*
1272 * Like some other architectures (e.g. ARM), the performance
1273 * counters don't differentiate between read and write
1274 * accesses/misses, so this isn't strictly correct, but it's the
1275 * best we can do. Writes and reads get combined.
1276 */
1277 [C(OP_READ)] = {
1278 [C(RESULT_ACCESS)] = { 0x156, CNTR_ALL },
1279 },
1280 [C(OP_WRITE)] = {
1281 [C(RESULT_ACCESS)] = { 0x155, CNTR_ALL },
1282 [C(RESULT_MISS)] = { 0x153, CNTR_ALL },
1283 },
1284},
1285[C(L1I)] = {
1286 [C(OP_READ)] = {
1287 [C(RESULT_MISS)] = { 0x18, CNTR_ALL },
1288 },
1289 [C(OP_WRITE)] = {
1290 [C(RESULT_MISS)] = { 0x18, CNTR_ALL },
1291 },
1292},
1293[C(LL)] = {
1294 [C(OP_READ)] = {
1295 [C(RESULT_ACCESS)] = { 0x1b6, CNTR_ALL },
1296 },
1297 [C(OP_WRITE)] = {
1298 [C(RESULT_ACCESS)] = { 0x1b7, CNTR_ALL },
1299 },
1300 [C(OP_PREFETCH)] = {
1301 [C(RESULT_ACCESS)] = { 0x1bf, CNTR_ALL },
1302 },
1303},
1304[C(DTLB)] = {
1305 [C(OP_READ)] = {
1306 [C(RESULT_MISS)] = { 0x92, CNTR_ALL },
1307 },
1308 [C(OP_WRITE)] = {
1309 [C(RESULT_MISS)] = { 0x92, CNTR_ALL },
1310 },
1311},
1312[C(ITLB)] = {
1313 [C(OP_READ)] = {
1314 [C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
1315 },
1316 [C(OP_WRITE)] = {
1317 [C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
1318 },
1319},
1320[C(BPU)] = {
1321 /* Using the same code for *HW_BRANCH* */
1322 [C(OP_READ)] = {
1323 [C(RESULT_ACCESS)] = { 0x94, CNTR_ALL },
1324 [C(RESULT_MISS)] = { 0x9c, CNTR_ALL },
1325 },
1326},
1327};
1328
1329static const struct mips_perf_event loongson3_cache_map3
1330 [PERF_COUNT_HW_CACHE_MAX]
1331 [PERF_COUNT_HW_CACHE_OP_MAX]
1332 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1333[C(L1D)] = {
1334 /*
1335 * Like some other architectures (e.g. ARM), the performance
1336 * counters don't differentiate between read and write
1337 * accesses/misses, so this isn't strictly correct, but it's the
1338 * best we can do. Writes and reads get combined.
1339 */
1340 [C(OP_READ)] = {
1341 [C(RESULT_ACCESS)] = { 0x1e, CNTR_ALL },
1342 [C(RESULT_MISS)] = { 0x1f, CNTR_ALL },
1343 },
1344 [C(OP_PREFETCH)] = {
1345 [C(RESULT_ACCESS)] = { 0xaa, CNTR_ALL },
1346 [C(RESULT_MISS)] = { 0xa9, CNTR_ALL },
1347 },
1348},
1349[C(L1I)] = {
1350 [C(OP_READ)] = {
1351 [C(RESULT_ACCESS)] = { 0x1c, CNTR_ALL },
1352 [C(RESULT_MISS)] = { 0x1d, CNTR_ALL },
1353 },
1354},
1355[C(LL)] = {
1356 [C(OP_READ)] = {
1357 [C(RESULT_ACCESS)] = { 0x2e, CNTR_ALL },
1358 [C(RESULT_MISS)] = { 0x2f, CNTR_ALL },
1359 },
1360},
1361[C(DTLB)] = {
1362 [C(OP_READ)] = {
1363 [C(RESULT_ACCESS)] = { 0x14, CNTR_ALL },
1364 [C(RESULT_MISS)] = { 0x1b, CNTR_ALL },
1365 },
1366},
1367[C(ITLB)] = {
1368 [C(OP_READ)] = {
1369 [C(RESULT_MISS)] = { 0x1a, CNTR_ALL },
1370 },
1371},
1372[C(BPU)] = {
1373 /* Using the same code for *HW_BRANCH* */
1374 [C(OP_READ)] = {
1375 [C(RESULT_ACCESS)] = { 0x02, CNTR_ALL },
1376 [C(RESULT_MISS)] = { 0x08, CNTR_ALL },
1377 },
1378},
1379};
1380
1381/* BMIPS5000 */
1382static const struct mips_perf_event bmips5000_cache_map
1383 [PERF_COUNT_HW_CACHE_MAX]
1384 [PERF_COUNT_HW_CACHE_OP_MAX]
1385 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1386[C(L1D)] = {
1387 /*
1388 * Like some other architectures (e.g. ARM), the performance
1389 * counters don't differentiate between read and write
1390 * accesses/misses, so this isn't strictly correct, but it's the
1391 * best we can do. Writes and reads get combined.
1392 */
1393 [C(OP_READ)] = {
1394 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1395 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1396 },
1397 [C(OP_WRITE)] = {
1398 [C(RESULT_ACCESS)] = { 12, CNTR_EVEN, T },
1399 [C(RESULT_MISS)] = { 12, CNTR_ODD, T },
1400 },
1401},
1402[C(L1I)] = {
1403 [C(OP_READ)] = {
1404 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1405 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1406 },
1407 [C(OP_WRITE)] = {
1408 [C(RESULT_ACCESS)] = { 10, CNTR_EVEN, T },
1409 [C(RESULT_MISS)] = { 10, CNTR_ODD, T },
1410 },
1411 [C(OP_PREFETCH)] = {
1412 [C(RESULT_ACCESS)] = { 23, CNTR_EVEN, T },
1413 /*
1414 * Note that MIPS has only "hit" events countable for
1415 * the prefetch operation.
1416 */
1417 },
1418},
1419[C(LL)] = {
1420 [C(OP_READ)] = {
1421 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1422 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1423 },
1424 [C(OP_WRITE)] = {
1425 [C(RESULT_ACCESS)] = { 28, CNTR_EVEN, P },
1426 [C(RESULT_MISS)] = { 28, CNTR_ODD, P },
1427 },
1428},
1429[C(BPU)] = {
1430 /* Using the same code for *HW_BRANCH* */
1431 [C(OP_READ)] = {
1432 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1433 },
1434 [C(OP_WRITE)] = {
1435 [C(RESULT_MISS)] = { 0x02, CNTR_ODD, T },
1436 },
1437},
1438};
1439
1440static const struct mips_perf_event octeon_cache_map
1441 [PERF_COUNT_HW_CACHE_MAX]
1442 [PERF_COUNT_HW_CACHE_OP_MAX]
1443 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1444[C(L1D)] = {
1445 [C(OP_READ)] = {
1446 [C(RESULT_ACCESS)] = { 0x2b, CNTR_ALL },
1447 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL },
1448 },
1449 [C(OP_WRITE)] = {
1450 [C(RESULT_ACCESS)] = { 0x30, CNTR_ALL },
1451 },
1452},
1453[C(L1I)] = {
1454 [C(OP_READ)] = {
1455 [C(RESULT_ACCESS)] = { 0x18, CNTR_ALL },
1456 },
1457 [C(OP_PREFETCH)] = {
1458 [C(RESULT_ACCESS)] = { 0x19, CNTR_ALL },
1459 },
1460},
1461[C(DTLB)] = {
1462 /*
1463 * Only general DTLB misses are counted use the same event for
1464 * read and write.
1465 */
1466 [C(OP_READ)] = {
1467 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1468 },
1469 [C(OP_WRITE)] = {
1470 [C(RESULT_MISS)] = { 0x35, CNTR_ALL },
1471 },
1472},
1473[C(ITLB)] = {
1474 [C(OP_READ)] = {
1475 [C(RESULT_MISS)] = { 0x37, CNTR_ALL },
1476 },
1477},
1478};
1479
1480static const struct mips_perf_event xlp_cache_map
1481 [PERF_COUNT_HW_CACHE_MAX]
1482 [PERF_COUNT_HW_CACHE_OP_MAX]
1483 [PERF_COUNT_HW_CACHE_RESULT_MAX] = {
1484[C(L1D)] = {
1485 [C(OP_READ)] = {
1486 [C(RESULT_ACCESS)] = { 0x31, CNTR_ALL }, /* PAPI_L1_DCR */
1487 [C(RESULT_MISS)] = { 0x30, CNTR_ALL }, /* PAPI_L1_LDM */
1488 },
1489 [C(OP_WRITE)] = {
1490 [C(RESULT_ACCESS)] = { 0x2f, CNTR_ALL }, /* PAPI_L1_DCW */
1491 [C(RESULT_MISS)] = { 0x2e, CNTR_ALL }, /* PAPI_L1_STM */
1492 },
1493},
1494[C(L1I)] = {
1495 [C(OP_READ)] = {
1496 [C(RESULT_ACCESS)] = { 0x04, CNTR_ALL }, /* PAPI_L1_ICA */
1497 [C(RESULT_MISS)] = { 0x07, CNTR_ALL }, /* PAPI_L1_ICM */
1498 },
1499},
1500[C(LL)] = {
1501 [C(OP_READ)] = {
1502 [C(RESULT_ACCESS)] = { 0x35, CNTR_ALL }, /* PAPI_L2_DCR */
1503 [C(RESULT_MISS)] = { 0x37, CNTR_ALL }, /* PAPI_L2_LDM */
1504 },
1505 [C(OP_WRITE)] = {
1506 [C(RESULT_ACCESS)] = { 0x34, CNTR_ALL }, /* PAPI_L2_DCA */
1507 [C(RESULT_MISS)] = { 0x36, CNTR_ALL }, /* PAPI_L2_DCM */
1508 },
1509},
1510[C(DTLB)] = {
1511 /*
1512 * Only general DTLB misses are counted use the same event for
1513 * read and write.
1514 */
1515 [C(OP_READ)] = {
1516 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1517 },
1518 [C(OP_WRITE)] = {
1519 [C(RESULT_MISS)] = { 0x2d, CNTR_ALL }, /* PAPI_TLB_DM */
1520 },
1521},
1522[C(ITLB)] = {
1523 [C(OP_READ)] = {
1524 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1525 },
1526 [C(OP_WRITE)] = {
1527 [C(RESULT_MISS)] = { 0x08, CNTR_ALL }, /* PAPI_TLB_IM */
1528 },
1529},
1530[C(BPU)] = {
1531 [C(OP_READ)] = {
1532 [C(RESULT_MISS)] = { 0x25, CNTR_ALL },
1533 },
1534},
1535};
1536
1537static int __hw_perf_event_init(struct perf_event *event)
1538{
1539 struct perf_event_attr *attr = &event->attr;
1540 struct hw_perf_event *hwc = &event->hw;
1541 const struct mips_perf_event *pev;
1542 int err;
1543
1544 /* Returning MIPS event descriptor for generic perf event. */
1545 if (PERF_TYPE_HARDWARE == event->attr.type) {
1546 if (event->attr.config >= PERF_COUNT_HW_MAX)
1547 return -EINVAL;
1548 pev = mipspmu_map_general_event(event->attr.config);
1549 } else if (PERF_TYPE_HW_CACHE == event->attr.type) {
1550 pev = mipspmu_map_cache_event(event->attr.config);
1551 } else if (PERF_TYPE_RAW == event->attr.type) {
1552 /* We are working on the global raw event. */
1553 mutex_lock(&raw_event_mutex);
1554 pev = mipspmu.map_raw_event(event->attr.config);
1555 } else {
1556 /* The event type is not (yet) supported. */
1557 return -EOPNOTSUPP;
1558 }
1559
1560 if (IS_ERR(pev)) {
1561 if (PERF_TYPE_RAW == event->attr.type)
1562 mutex_unlock(&raw_event_mutex);
1563 return PTR_ERR(pev);
1564 }
1565
1566 /*
1567 * We allow max flexibility on how each individual counter shared
1568 * by the single CPU operates (the mode exclusion and the range).
1569 */
1570 hwc->config_base = MIPS_PERFCTRL_IE;
1571
1572 hwc->event_base = mipspmu_perf_event_encode(pev);
1573 if (PERF_TYPE_RAW == event->attr.type)
1574 mutex_unlock(&raw_event_mutex);
1575
1576 if (!attr->exclude_user)
1577 hwc->config_base |= MIPS_PERFCTRL_U;
1578 if (!attr->exclude_kernel) {
1579 hwc->config_base |= MIPS_PERFCTRL_K;
1580 /* MIPS kernel mode: KSU == 00b || EXL == 1 || ERL == 1 */
1581 hwc->config_base |= MIPS_PERFCTRL_EXL;
1582 }
1583 if (!attr->exclude_hv)
1584 hwc->config_base |= MIPS_PERFCTRL_S;
1585
1586 hwc->config_base &= M_PERFCTL_CONFIG_MASK;
1587 /*
1588 * The event can belong to another cpu. We do not assign a local
1589 * counter for it for now.
1590 */
1591 hwc->idx = -1;
1592 hwc->config = 0;
1593
1594 if (!hwc->sample_period) {
1595 hwc->sample_period = mipspmu.max_period;
1596 hwc->last_period = hwc->sample_period;
1597 local64_set(&hwc->period_left, hwc->sample_period);
1598 }
1599
1600 err = 0;
1601 if (event->group_leader != event)
1602 err = validate_group(event);
1603
1604 event->destroy = hw_perf_event_destroy;
1605
1606 if (err)
1607 event->destroy(event);
1608
1609 return err;
1610}
1611
1612static void pause_local_counters(void)
1613{
1614 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1615 int ctr = mipspmu.num_counters;
1616 unsigned long flags;
1617
1618 local_irq_save(flags);
1619 do {
1620 ctr--;
1621 cpuc->saved_ctrl[ctr] = mipsxx_pmu_read_control(ctr);
1622 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr] &
1623 ~M_PERFCTL_COUNT_EVENT_WHENEVER);
1624 } while (ctr > 0);
1625 local_irq_restore(flags);
1626}
1627
1628static void resume_local_counters(void)
1629{
1630 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1631 int ctr = mipspmu.num_counters;
1632
1633 do {
1634 ctr--;
1635 mipsxx_pmu_write_control(ctr, cpuc->saved_ctrl[ctr]);
1636 } while (ctr > 0);
1637}
1638
1639static int mipsxx_pmu_handle_shared_irq(void)
1640{
1641 struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
1642 struct perf_sample_data data;
1643 unsigned int counters = mipspmu.num_counters;
1644 u64 counter;
1645 int n, handled = IRQ_NONE;
1646 struct pt_regs *regs;
1647
1648 if (cpu_has_perf_cntr_intr_bit && !(read_c0_cause() & CAUSEF_PCI))
1649 return handled;
1650 /*
1651 * First we pause the local counters, so that when we are locked
1652 * here, the counters are all paused. When it gets locked due to
1653 * perf_disable(), the timer interrupt handler will be delayed.
1654 *
1655 * See also mipsxx_pmu_start().
1656 */
1657 pause_local_counters();
1658#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1659 read_lock(&pmuint_rwlock);
1660#endif
1661
1662 regs = get_irq_regs();
1663
1664 perf_sample_data_init(&data, 0, 0);
1665
1666 for (n = counters - 1; n >= 0; n--) {
1667 if (!test_bit(n, cpuc->used_mask))
1668 continue;
1669
1670 counter = mipspmu.read_counter(n);
1671 if (!(counter & mipspmu.overflow))
1672 continue;
1673
1674 handle_associated_event(cpuc, n, &data, regs);
1675 handled = IRQ_HANDLED;
1676 }
1677
1678#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1679 read_unlock(&pmuint_rwlock);
1680#endif
1681 resume_local_counters();
1682
1683 /*
1684 * Do all the work for the pending perf events. We can do this
1685 * in here because the performance counter interrupt is a regular
1686 * interrupt, not NMI.
1687 */
1688 if (handled == IRQ_HANDLED)
1689 irq_work_run();
1690
1691 return handled;
1692}
1693
1694static irqreturn_t mipsxx_pmu_handle_irq(int irq, void *dev)
1695{
1696 return mipsxx_pmu_handle_shared_irq();
1697}
1698
1699/* 24K */
1700#define IS_BOTH_COUNTERS_24K_EVENT(b) \
1701 ((b) == 0 || (b) == 1 || (b) == 11)
1702
1703/* 34K */
1704#define IS_BOTH_COUNTERS_34K_EVENT(b) \
1705 ((b) == 0 || (b) == 1 || (b) == 11)
1706#ifdef CONFIG_MIPS_MT_SMP
1707#define IS_RANGE_P_34K_EVENT(r, b) \
1708 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1709 (b) == 25 || (b) == 39 || (r) == 44 || (r) == 174 || \
1710 (r) == 176 || ((b) >= 50 && (b) <= 55) || \
1711 ((b) >= 64 && (b) <= 67))
1712#define IS_RANGE_V_34K_EVENT(r) ((r) == 47)
1713#endif
1714
1715/* 74K */
1716#define IS_BOTH_COUNTERS_74K_EVENT(b) \
1717 ((b) == 0 || (b) == 1)
1718
1719/* proAptiv */
1720#define IS_BOTH_COUNTERS_PROAPTIV_EVENT(b) \
1721 ((b) == 0 || (b) == 1)
1722/* P5600 */
1723#define IS_BOTH_COUNTERS_P5600_EVENT(b) \
1724 ((b) == 0 || (b) == 1)
1725
1726/* 1004K */
1727#define IS_BOTH_COUNTERS_1004K_EVENT(b) \
1728 ((b) == 0 || (b) == 1 || (b) == 11)
1729#ifdef CONFIG_MIPS_MT_SMP
1730#define IS_RANGE_P_1004K_EVENT(r, b) \
1731 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1732 (b) == 25 || (b) == 36 || (b) == 39 || (r) == 44 || \
1733 (r) == 174 || (r) == 176 || ((b) >= 50 && (b) <= 59) || \
1734 (r) == 188 || (b) == 61 || (b) == 62 || \
1735 ((b) >= 64 && (b) <= 67))
1736#define IS_RANGE_V_1004K_EVENT(r) ((r) == 47)
1737#endif
1738
1739/* interAptiv */
1740#define IS_BOTH_COUNTERS_INTERAPTIV_EVENT(b) \
1741 ((b) == 0 || (b) == 1 || (b) == 11)
1742#ifdef CONFIG_MIPS_MT_SMP
1743/* The P/V/T info is not provided for "(b) == 38" in SUM, assume P. */
1744#define IS_RANGE_P_INTERAPTIV_EVENT(r, b) \
1745 ((b) == 0 || (r) == 18 || (b) == 21 || (b) == 22 || \
1746 (b) == 25 || (b) == 36 || (b) == 38 || (b) == 39 || \
1747 (r) == 44 || (r) == 174 || (r) == 176 || ((b) >= 50 && \
1748 (b) <= 59) || (r) == 188 || (b) == 61 || (b) == 62 || \
1749 ((b) >= 64 && (b) <= 67))
1750#define IS_RANGE_V_INTERAPTIV_EVENT(r) ((r) == 47 || (r) == 175)
1751#endif
1752
1753/* BMIPS5000 */
1754#define IS_BOTH_COUNTERS_BMIPS5000_EVENT(b) \
1755 ((b) == 0 || (b) == 1)
1756
1757
1758/*
1759 * For most cores the user can use 0-255 raw events, where 0-127 for the events
1760 * of even counters, and 128-255 for odd counters. Note that bit 7 is used to
1761 * indicate the even/odd bank selector. So, for example, when user wants to take
1762 * the Event Num of 15 for odd counters (by referring to the user manual), then
1763 * 128 needs to be added to 15 as the input for the event config, i.e., 143 (0x8F)
1764 * to be used.
1765 *
1766 * Some newer cores have even more events, in which case the user can use raw
1767 * events 0-511, where 0-255 are for the events of even counters, and 256-511
1768 * are for odd counters, so bit 8 is used to indicate the even/odd bank selector.
1769 */
1770static const struct mips_perf_event *mipsxx_pmu_map_raw_event(u64 config)
1771{
1772 /* currently most cores have 7-bit event numbers */
1773 int pmu_type;
1774 unsigned int raw_id = config & 0xff;
1775 unsigned int base_id = raw_id & 0x7f;
1776
1777 switch (current_cpu_type()) {
1778 case CPU_24K:
1779 if (IS_BOTH_COUNTERS_24K_EVENT(base_id))
1780 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1781 else
1782 raw_event.cntr_mask =
1783 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1784#ifdef CONFIG_MIPS_MT_SMP
1785 /*
1786 * This is actually doing nothing. Non-multithreading
1787 * CPUs will not check and calculate the range.
1788 */
1789 raw_event.range = P;
1790#endif
1791 break;
1792 case CPU_34K:
1793 if (IS_BOTH_COUNTERS_34K_EVENT(base_id))
1794 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1795 else
1796 raw_event.cntr_mask =
1797 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1798#ifdef CONFIG_MIPS_MT_SMP
1799 if (IS_RANGE_P_34K_EVENT(raw_id, base_id))
1800 raw_event.range = P;
1801 else if (unlikely(IS_RANGE_V_34K_EVENT(raw_id)))
1802 raw_event.range = V;
1803 else
1804 raw_event.range = T;
1805#endif
1806 break;
1807 case CPU_74K:
1808 case CPU_1074K:
1809 if (IS_BOTH_COUNTERS_74K_EVENT(base_id))
1810 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1811 else
1812 raw_event.cntr_mask =
1813 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1814#ifdef CONFIG_MIPS_MT_SMP
1815 raw_event.range = P;
1816#endif
1817 break;
1818 case CPU_PROAPTIV:
1819 if (IS_BOTH_COUNTERS_PROAPTIV_EVENT(base_id))
1820 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1821 else
1822 raw_event.cntr_mask =
1823 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1824#ifdef CONFIG_MIPS_MT_SMP
1825 raw_event.range = P;
1826#endif
1827 break;
1828 case CPU_P5600:
1829 case CPU_P6600:
1830 /* 8-bit event numbers */
1831 raw_id = config & 0x1ff;
1832 base_id = raw_id & 0xff;
1833 if (IS_BOTH_COUNTERS_P5600_EVENT(base_id))
1834 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1835 else
1836 raw_event.cntr_mask =
1837 raw_id > 255 ? CNTR_ODD : CNTR_EVEN;
1838#ifdef CONFIG_MIPS_MT_SMP
1839 raw_event.range = P;
1840#endif
1841 break;
1842 case CPU_I6400:
1843 case CPU_I6500:
1844 /* 8-bit event numbers */
1845 base_id = config & 0xff;
1846 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1847 break;
1848 case CPU_1004K:
1849 if (IS_BOTH_COUNTERS_1004K_EVENT(base_id))
1850 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1851 else
1852 raw_event.cntr_mask =
1853 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1854#ifdef CONFIG_MIPS_MT_SMP
1855 if (IS_RANGE_P_1004K_EVENT(raw_id, base_id))
1856 raw_event.range = P;
1857 else if (unlikely(IS_RANGE_V_1004K_EVENT(raw_id)))
1858 raw_event.range = V;
1859 else
1860 raw_event.range = T;
1861#endif
1862 break;
1863 case CPU_INTERAPTIV:
1864 if (IS_BOTH_COUNTERS_INTERAPTIV_EVENT(base_id))
1865 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1866 else
1867 raw_event.cntr_mask =
1868 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1869#ifdef CONFIG_MIPS_MT_SMP
1870 if (IS_RANGE_P_INTERAPTIV_EVENT(raw_id, base_id))
1871 raw_event.range = P;
1872 else if (unlikely(IS_RANGE_V_INTERAPTIV_EVENT(raw_id)))
1873 raw_event.range = V;
1874 else
1875 raw_event.range = T;
1876#endif
1877 break;
1878 case CPU_BMIPS5000:
1879 if (IS_BOTH_COUNTERS_BMIPS5000_EVENT(base_id))
1880 raw_event.cntr_mask = CNTR_EVEN | CNTR_ODD;
1881 else
1882 raw_event.cntr_mask =
1883 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1884 break;
1885 case CPU_LOONGSON64:
1886 pmu_type = get_loongson3_pmu_type();
1887
1888 switch (pmu_type) {
1889 case LOONGSON_PMU_TYPE1:
1890 raw_event.cntr_mask =
1891 raw_id > 127 ? CNTR_ODD : CNTR_EVEN;
1892 break;
1893 case LOONGSON_PMU_TYPE2:
1894 base_id = config & 0x3ff;
1895 raw_event.cntr_mask = CNTR_ALL;
1896
1897 if ((base_id >= 1 && base_id < 28) ||
1898 (base_id >= 64 && base_id < 90) ||
1899 (base_id >= 128 && base_id < 164) ||
1900 (base_id >= 192 && base_id < 200) ||
1901 (base_id >= 256 && base_id < 275) ||
1902 (base_id >= 320 && base_id < 361) ||
1903 (base_id >= 384 && base_id < 574))
1904 break;
1905
1906 return ERR_PTR(-EOPNOTSUPP);
1907 case LOONGSON_PMU_TYPE3:
1908 base_id = raw_id;
1909 raw_event.cntr_mask = CNTR_ALL;
1910 break;
1911 }
1912 break;
1913 }
1914
1915 raw_event.event_id = base_id;
1916
1917 return &raw_event;
1918}
1919
1920static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config)
1921{
1922 unsigned int raw_id = config & 0xff;
1923 unsigned int base_id = raw_id & 0x7f;
1924
1925
1926 raw_event.cntr_mask = CNTR_ALL;
1927 raw_event.event_id = base_id;
1928
1929 if (current_cpu_type() == CPU_CAVIUM_OCTEON2) {
1930 if (base_id > 0x42)
1931 return ERR_PTR(-EOPNOTSUPP);
1932 } else {
1933 if (base_id > 0x3a)
1934 return ERR_PTR(-EOPNOTSUPP);
1935 }
1936
1937 switch (base_id) {
1938 case 0x00:
1939 case 0x0f:
1940 case 0x1e:
1941 case 0x1f:
1942 case 0x2f:
1943 case 0x34:
1944 case 0x3b ... 0x3f:
1945 return ERR_PTR(-EOPNOTSUPP);
1946 default:
1947 break;
1948 }
1949
1950 return &raw_event;
1951}
1952
1953static const struct mips_perf_event *xlp_pmu_map_raw_event(u64 config)
1954{
1955 unsigned int raw_id = config & 0xff;
1956
1957 /* Only 1-63 are defined */
1958 if ((raw_id < 0x01) || (raw_id > 0x3f))
1959 return ERR_PTR(-EOPNOTSUPP);
1960
1961 raw_event.cntr_mask = CNTR_ALL;
1962 raw_event.event_id = raw_id;
1963
1964 return &raw_event;
1965}
1966
1967static int __init
1968init_hw_perf_events(void)
1969{
1970 int counters, irq, pmu_type;
1971
1972 pr_info("Performance counters: ");
1973
1974 counters = n_counters();
1975 if (counters == 0) {
1976 pr_cont("No available PMU.\n");
1977 return -ENODEV;
1978 }
1979
1980#ifdef CONFIG_MIPS_PERF_SHARED_TC_COUNTERS
1981 if (!cpu_has_mipsmt_pertccounters)
1982 counters = counters_total_to_per_cpu(counters);
1983#endif
1984
1985 if (get_c0_perfcount_int)
1986 irq = get_c0_perfcount_int();
1987 else if (cp0_perfcount_irq >= 0)
1988 irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
1989 else
1990 irq = -1;
1991
1992 mipspmu.map_raw_event = mipsxx_pmu_map_raw_event;
1993
1994 switch (current_cpu_type()) {
1995 case CPU_24K:
1996 mipspmu.name = "mips/24K";
1997 mipspmu.general_event_map = &mipsxxcore_event_map;
1998 mipspmu.cache_event_map = &mipsxxcore_cache_map;
1999 break;
2000 case CPU_34K:
2001 mipspmu.name = "mips/34K";
2002 mipspmu.general_event_map = &mipsxxcore_event_map;
2003 mipspmu.cache_event_map = &mipsxxcore_cache_map;
2004 break;
2005 case CPU_74K:
2006 mipspmu.name = "mips/74K";
2007 mipspmu.general_event_map = &mipsxxcore_event_map2;
2008 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
2009 break;
2010 case CPU_PROAPTIV:
2011 mipspmu.name = "mips/proAptiv";
2012 mipspmu.general_event_map = &mipsxxcore_event_map2;
2013 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
2014 break;
2015 case CPU_P5600:
2016 mipspmu.name = "mips/P5600";
2017 mipspmu.general_event_map = &mipsxxcore_event_map2;
2018 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
2019 break;
2020 case CPU_P6600:
2021 mipspmu.name = "mips/P6600";
2022 mipspmu.general_event_map = &mipsxxcore_event_map2;
2023 mipspmu.cache_event_map = &mipsxxcore_cache_map2;
2024 break;
2025 case CPU_I6400:
2026 mipspmu.name = "mips/I6400";
2027 mipspmu.general_event_map = &i6x00_event_map;
2028 mipspmu.cache_event_map = &i6x00_cache_map;
2029 break;
2030 case CPU_I6500:
2031 mipspmu.name = "mips/I6500";
2032 mipspmu.general_event_map = &i6x00_event_map;
2033 mipspmu.cache_event_map = &i6x00_cache_map;
2034 break;
2035 case CPU_1004K:
2036 mipspmu.name = "mips/1004K";
2037 mipspmu.general_event_map = &mipsxxcore_event_map;
2038 mipspmu.cache_event_map = &mipsxxcore_cache_map;
2039 break;
2040 case CPU_1074K:
2041 mipspmu.name = "mips/1074K";
2042 mipspmu.general_event_map = &mipsxxcore_event_map;
2043 mipspmu.cache_event_map = &mipsxxcore_cache_map;
2044 break;
2045 case CPU_INTERAPTIV:
2046 mipspmu.name = "mips/interAptiv";
2047 mipspmu.general_event_map = &mipsxxcore_event_map;
2048 mipspmu.cache_event_map = &mipsxxcore_cache_map;
2049 break;
2050 case CPU_LOONGSON32:
2051 mipspmu.name = "mips/loongson1";
2052 mipspmu.general_event_map = &mipsxxcore_event_map;
2053 mipspmu.cache_event_map = &mipsxxcore_cache_map;
2054 break;
2055 case CPU_LOONGSON64:
2056 mipspmu.name = "mips/loongson3";
2057 pmu_type = get_loongson3_pmu_type();
2058
2059 switch (pmu_type) {
2060 case LOONGSON_PMU_TYPE1:
2061 counters = 2;
2062 mipspmu.general_event_map = &loongson3_event_map1;
2063 mipspmu.cache_event_map = &loongson3_cache_map1;
2064 break;
2065 case LOONGSON_PMU_TYPE2:
2066 counters = 4;
2067 mipspmu.general_event_map = &loongson3_event_map2;
2068 mipspmu.cache_event_map = &loongson3_cache_map2;
2069 break;
2070 case LOONGSON_PMU_TYPE3:
2071 counters = 4;
2072 mipspmu.general_event_map = &loongson3_event_map3;
2073 mipspmu.cache_event_map = &loongson3_cache_map3;
2074 break;
2075 }
2076 break;
2077 case CPU_CAVIUM_OCTEON:
2078 case CPU_CAVIUM_OCTEON_PLUS:
2079 case CPU_CAVIUM_OCTEON2:
2080 mipspmu.name = "octeon";
2081 mipspmu.general_event_map = &octeon_event_map;
2082 mipspmu.cache_event_map = &octeon_cache_map;
2083 mipspmu.map_raw_event = octeon_pmu_map_raw_event;
2084 break;
2085 case CPU_BMIPS5000:
2086 mipspmu.name = "BMIPS5000";
2087 mipspmu.general_event_map = &bmips5000_event_map;
2088 mipspmu.cache_event_map = &bmips5000_cache_map;
2089 break;
2090 case CPU_XLP:
2091 mipspmu.name = "xlp";
2092 mipspmu.general_event_map = &xlp_event_map;
2093 mipspmu.cache_event_map = &xlp_cache_map;
2094 mipspmu.map_raw_event = xlp_pmu_map_raw_event;
2095 break;
2096 default:
2097 pr_cont("Either hardware does not support performance "
2098 "counters, or not yet implemented.\n");
2099 return -ENODEV;
2100 }
2101
2102 mipspmu.num_counters = counters;
2103 mipspmu.irq = irq;
2104
2105 if (read_c0_perfctrl0() & MIPS_PERFCTRL_W) {
2106 if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2) {
2107 counter_bits = 48;
2108 mipspmu.max_period = (1ULL << 47) - 1;
2109 mipspmu.valid_count = (1ULL << 47) - 1;
2110 mipspmu.overflow = 1ULL << 47;
2111 } else {
2112 counter_bits = 64;
2113 mipspmu.max_period = (1ULL << 63) - 1;
2114 mipspmu.valid_count = (1ULL << 63) - 1;
2115 mipspmu.overflow = 1ULL << 63;
2116 }
2117 mipspmu.read_counter = mipsxx_pmu_read_counter_64;
2118 mipspmu.write_counter = mipsxx_pmu_write_counter_64;
2119 } else {
2120 counter_bits = 32;
2121 mipspmu.max_period = (1ULL << 31) - 1;
2122 mipspmu.valid_count = (1ULL << 31) - 1;
2123 mipspmu.overflow = 1ULL << 31;
2124 mipspmu.read_counter = mipsxx_pmu_read_counter;
2125 mipspmu.write_counter = mipsxx_pmu_write_counter;
2126 }
2127
2128 on_each_cpu(reset_counters, (void *)(long)counters, 1);
2129
2130 pr_cont("%s PMU enabled, %d %d-bit counters available to each "
2131 "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq,
2132 irq < 0 ? " (share with timer interrupt)" : "");
2133
2134 perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
2135
2136 return 0;
2137}
2138early_initcall(init_hw_perf_events);