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1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra30-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra30-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7
8#include "skeleton.dtsi"
9
10/ {
11 compatible = "nvidia,tegra30";
12 interrupt-parent = <&lic>;
13
14 pcie@3000 {
15 compatible = "nvidia,tegra30-pcie";
16 device_type = "pci";
17 reg = <0x00003000 0x00000800 /* PADS registers */
18 0x00003800 0x00000200 /* AFI registers */
19 0x10000000 0x10000000>; /* configuration space */
20 reg-names = "pads", "afi", "cs";
21 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
22 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
23 interrupt-names = "intr", "msi";
24
25 #interrupt-cells = <1>;
26 interrupt-map-mask = <0 0 0 0>;
27 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
28
29 bus-range = <0x00 0xff>;
30 #address-cells = <3>;
31 #size-cells = <2>;
32
33 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
34 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
35 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
36 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
37 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
38 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
39
40 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
41 <&tegra_car TEGRA30_CLK_AFI>,
42 <&tegra_car TEGRA30_CLK_PLL_E>,
43 <&tegra_car TEGRA30_CLK_CML0>;
44 clock-names = "pex", "afi", "pll_e", "cml";
45 resets = <&tegra_car 70>,
46 <&tegra_car 72>,
47 <&tegra_car 74>;
48 reset-names = "pex", "afi", "pcie_x";
49 status = "disabled";
50
51 pci@1,0 {
52 device_type = "pci";
53 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
54 reg = <0x000800 0 0 0 0>;
55 bus-range = <0x00 0xff>;
56 status = "disabled";
57
58 #address-cells = <3>;
59 #size-cells = <2>;
60 ranges;
61
62 nvidia,num-lanes = <2>;
63 };
64
65 pci@2,0 {
66 device_type = "pci";
67 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
68 reg = <0x001000 0 0 0 0>;
69 bus-range = <0x00 0xff>;
70 status = "disabled";
71
72 #address-cells = <3>;
73 #size-cells = <2>;
74 ranges;
75
76 nvidia,num-lanes = <2>;
77 };
78
79 pci@3,0 {
80 device_type = "pci";
81 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
82 reg = <0x001800 0 0 0 0>;
83 bus-range = <0x00 0xff>;
84 status = "disabled";
85
86 #address-cells = <3>;
87 #size-cells = <2>;
88 ranges;
89
90 nvidia,num-lanes = <2>;
91 };
92 };
93
94 iram@40000000 {
95 compatible = "mmio-sram";
96 reg = <0x40000000 0x40000>;
97 #address-cells = <1>;
98 #size-cells = <1>;
99 ranges = <0 0x40000000 0x40000>;
100
101 vde_pool: vde@400 {
102 reg = <0x400 0x3fc00>;
103 pool;
104 };
105 };
106
107 host1x@50000000 {
108 compatible = "nvidia,tegra30-host1x", "simple-bus";
109 reg = <0x50000000 0x00024000>;
110 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
111 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
112 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
113 resets = <&tegra_car 28>;
114 reset-names = "host1x";
115
116 #address-cells = <1>;
117 #size-cells = <1>;
118
119 ranges = <0x54000000 0x54000000 0x04000000>;
120
121 mpe@54040000 {
122 compatible = "nvidia,tegra30-mpe";
123 reg = <0x54040000 0x00040000>;
124 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
125 clocks = <&tegra_car TEGRA30_CLK_MPE>;
126 resets = <&tegra_car 60>;
127 reset-names = "mpe";
128 };
129
130 vi@54080000 {
131 compatible = "nvidia,tegra30-vi";
132 reg = <0x54080000 0x00040000>;
133 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&tegra_car TEGRA30_CLK_VI>;
135 resets = <&tegra_car 20>;
136 reset-names = "vi";
137 };
138
139 epp@540c0000 {
140 compatible = "nvidia,tegra30-epp";
141 reg = <0x540c0000 0x00040000>;
142 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
143 clocks = <&tegra_car TEGRA30_CLK_EPP>;
144 resets = <&tegra_car 19>;
145 reset-names = "epp";
146 };
147
148 isp@54100000 {
149 compatible = "nvidia,tegra30-isp";
150 reg = <0x54100000 0x00040000>;
151 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
152 clocks = <&tegra_car TEGRA30_CLK_ISP>;
153 resets = <&tegra_car 23>;
154 reset-names = "isp";
155 };
156
157 gr2d@54140000 {
158 compatible = "nvidia,tegra30-gr2d";
159 reg = <0x54140000 0x00040000>;
160 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
162 resets = <&tegra_car 21>;
163 reset-names = "2d";
164 };
165
166 gr3d@54180000 {
167 compatible = "nvidia,tegra30-gr3d";
168 reg = <0x54180000 0x00040000>;
169 clocks = <&tegra_car TEGRA30_CLK_GR3D
170 &tegra_car TEGRA30_CLK_GR3D2>;
171 clock-names = "3d", "3d2";
172 resets = <&tegra_car 24>,
173 <&tegra_car 98>;
174 reset-names = "3d", "3d2";
175 };
176
177 dc@54200000 {
178 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
179 reg = <0x54200000 0x00040000>;
180 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
181 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
182 <&tegra_car TEGRA30_CLK_PLL_P>;
183 clock-names = "dc", "parent";
184 resets = <&tegra_car 27>;
185 reset-names = "dc";
186
187 iommus = <&mc TEGRA_SWGROUP_DC>;
188
189 nvidia,head = <0>;
190
191 rgb {
192 status = "disabled";
193 };
194 };
195
196 dc@54240000 {
197 compatible = "nvidia,tegra30-dc";
198 reg = <0x54240000 0x00040000>;
199 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
200 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
201 <&tegra_car TEGRA30_CLK_PLL_P>;
202 clock-names = "dc", "parent";
203 resets = <&tegra_car 26>;
204 reset-names = "dc";
205
206 iommus = <&mc TEGRA_SWGROUP_DCB>;
207
208 nvidia,head = <1>;
209
210 rgb {
211 status = "disabled";
212 };
213 };
214
215 hdmi@54280000 {
216 compatible = "nvidia,tegra30-hdmi";
217 reg = <0x54280000 0x00040000>;
218 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
219 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
220 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
221 clock-names = "hdmi", "parent";
222 resets = <&tegra_car 51>;
223 reset-names = "hdmi";
224 status = "disabled";
225 };
226
227 tvo@542c0000 {
228 compatible = "nvidia,tegra30-tvo";
229 reg = <0x542c0000 0x00040000>;
230 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
231 clocks = <&tegra_car TEGRA30_CLK_TVO>;
232 status = "disabled";
233 };
234
235 dsi@54300000 {
236 compatible = "nvidia,tegra30-dsi";
237 reg = <0x54300000 0x00040000>;
238 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
239 resets = <&tegra_car 48>;
240 reset-names = "dsi";
241 status = "disabled";
242 };
243 };
244
245 timer@50040600 {
246 compatible = "arm,cortex-a9-twd-timer";
247 reg = <0x50040600 0x20>;
248 interrupt-parent = <&intc>;
249 interrupts = <GIC_PPI 13
250 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
251 clocks = <&tegra_car TEGRA30_CLK_TWD>;
252 };
253
254 intc: interrupt-controller@50041000 {
255 compatible = "arm,cortex-a9-gic";
256 reg = <0x50041000 0x1000
257 0x50040100 0x0100>;
258 interrupt-controller;
259 #interrupt-cells = <3>;
260 interrupt-parent = <&intc>;
261 };
262
263 cache-controller@50043000 {
264 compatible = "arm,pl310-cache";
265 reg = <0x50043000 0x1000>;
266 arm,data-latency = <6 6 2>;
267 arm,tag-latency = <5 5 2>;
268 cache-unified;
269 cache-level = <2>;
270 };
271
272 lic: interrupt-controller@60004000 {
273 compatible = "nvidia,tegra30-ictlr";
274 reg = <0x60004000 0x100>,
275 <0x60004100 0x50>,
276 <0x60004200 0x50>,
277 <0x60004300 0x50>,
278 <0x60004400 0x50>;
279 interrupt-controller;
280 #interrupt-cells = <3>;
281 interrupt-parent = <&intc>;
282 };
283
284 timer@60005000 {
285 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
286 reg = <0x60005000 0x400>;
287 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
293 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
294 };
295
296 tegra_car: clock@60006000 {
297 compatible = "nvidia,tegra30-car";
298 reg = <0x60006000 0x1000>;
299 #clock-cells = <1>;
300 #reset-cells = <1>;
301 };
302
303 flow-controller@60007000 {
304 compatible = "nvidia,tegra30-flowctrl";
305 reg = <0x60007000 0x1000>;
306 };
307
308 apbdma: dma@6000a000 {
309 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
310 reg = <0x6000a000 0x1400>;
311 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
334 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
335 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
336 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
337 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
338 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
339 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
340 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
344 resets = <&tegra_car 34>;
345 reset-names = "dma";
346 #dma-cells = <1>;
347 };
348
349 ahb: ahb@6000c000 {
350 compatible = "nvidia,tegra30-ahb";
351 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
352 };
353
354 gpio: gpio@6000d000 {
355 compatible = "nvidia,tegra30-gpio";
356 reg = <0x6000d000 0x1000>;
357 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
365 #gpio-cells = <2>;
366 gpio-controller;
367 #interrupt-cells = <2>;
368 interrupt-controller;
369 /*
370 gpio-ranges = <&pinmux 0 0 248>;
371 */
372 };
373
374 vde@6001a000 {
375 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
376 reg = <0x6001a000 0x1000 /* Syntax Engine */
377 0x6001b000 0x1000 /* Video Bitstream Engine */
378 0x6001c000 0x100 /* Macroblock Engine */
379 0x6001c200 0x100 /* Post-processing Engine */
380 0x6001c400 0x100 /* Motion Compensation Engine */
381 0x6001c600 0x100 /* Transform Engine */
382 0x6001c800 0x100 /* Pixel prediction block */
383 0x6001ca00 0x100 /* Video DMA */
384 0x6001d800 0x400>; /* Video frame controls */
385 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
386 "tfe", "ppb", "vdma", "frameid";
387 iram = <&vde_pool>; /* IRAM region */
388 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
389 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
390 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
391 interrupt-names = "sync-token", "bsev", "sxe";
392 clocks = <&tegra_car TEGRA30_CLK_VDE>;
393 resets = <&tegra_car 61>;
394 };
395
396 apbmisc@70000800 {
397 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
398 reg = <0x70000800 0x64 /* Chip revision */
399 0x70000008 0x04>; /* Strapping options */
400 };
401
402 pinmux: pinmux@70000868 {
403 compatible = "nvidia,tegra30-pinmux";
404 reg = <0x70000868 0xd4 /* Pad control registers */
405 0x70003000 0x3e4>; /* Mux registers */
406 };
407
408 /*
409 * There are two serial driver i.e. 8250 based simple serial
410 * driver and APB DMA based serial driver for higher baudrate
411 * and performace. To enable the 8250 based driver, the compatible
412 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
413 * the APB DMA based serial driver, the compatible is
414 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
415 */
416 uarta: serial@70006000 {
417 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
418 reg = <0x70006000 0x40>;
419 reg-shift = <2>;
420 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
421 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
422 resets = <&tegra_car 6>;
423 reset-names = "serial";
424 dmas = <&apbdma 8>, <&apbdma 8>;
425 dma-names = "rx", "tx";
426 status = "disabled";
427 };
428
429 uartb: serial@70006040 {
430 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
431 reg = <0x70006040 0x40>;
432 reg-shift = <2>;
433 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
435 resets = <&tegra_car 7>;
436 reset-names = "serial";
437 dmas = <&apbdma 9>, <&apbdma 9>;
438 dma-names = "rx", "tx";
439 status = "disabled";
440 };
441
442 uartc: serial@70006200 {
443 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
444 reg = <0x70006200 0x100>;
445 reg-shift = <2>;
446 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
448 resets = <&tegra_car 55>;
449 reset-names = "serial";
450 dmas = <&apbdma 10>, <&apbdma 10>;
451 dma-names = "rx", "tx";
452 status = "disabled";
453 };
454
455 uartd: serial@70006300 {
456 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
457 reg = <0x70006300 0x100>;
458 reg-shift = <2>;
459 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
460 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
461 resets = <&tegra_car 65>;
462 reset-names = "serial";
463 dmas = <&apbdma 19>, <&apbdma 19>;
464 dma-names = "rx", "tx";
465 status = "disabled";
466 };
467
468 uarte: serial@70006400 {
469 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
470 reg = <0x70006400 0x100>;
471 reg-shift = <2>;
472 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
473 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
474 resets = <&tegra_car 66>;
475 reset-names = "serial";
476 dmas = <&apbdma 20>, <&apbdma 20>;
477 dma-names = "rx", "tx";
478 status = "disabled";
479 };
480
481 gmi@70009000 {
482 compatible = "nvidia,tegra30-gmi";
483 reg = <0x70009000 0x1000>;
484 #address-cells = <2>;
485 #size-cells = <1>;
486 ranges = <0 0 0x48000000 0x7ffffff>;
487 clocks = <&tegra_car TEGRA30_CLK_NOR>;
488 clock-names = "gmi";
489 resets = <&tegra_car 42>;
490 reset-names = "gmi";
491 status = "disabled";
492 };
493
494 pwm: pwm@7000a000 {
495 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
496 reg = <0x7000a000 0x100>;
497 #pwm-cells = <2>;
498 clocks = <&tegra_car TEGRA30_CLK_PWM>;
499 resets = <&tegra_car 17>;
500 reset-names = "pwm";
501 status = "disabled";
502 };
503
504 rtc@7000e000 {
505 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
506 reg = <0x7000e000 0x100>;
507 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&tegra_car TEGRA30_CLK_RTC>;
509 };
510
511 i2c@7000c000 {
512 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
513 reg = <0x7000c000 0x100>;
514 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
515 #address-cells = <1>;
516 #size-cells = <0>;
517 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
518 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
519 clock-names = "div-clk", "fast-clk";
520 resets = <&tegra_car 12>;
521 reset-names = "i2c";
522 dmas = <&apbdma 21>, <&apbdma 21>;
523 dma-names = "rx", "tx";
524 status = "disabled";
525 };
526
527 i2c@7000c400 {
528 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
529 reg = <0x7000c400 0x100>;
530 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
531 #address-cells = <1>;
532 #size-cells = <0>;
533 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
534 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
535 clock-names = "div-clk", "fast-clk";
536 resets = <&tegra_car 54>;
537 reset-names = "i2c";
538 dmas = <&apbdma 22>, <&apbdma 22>;
539 dma-names = "rx", "tx";
540 status = "disabled";
541 };
542
543 i2c@7000c500 {
544 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
545 reg = <0x7000c500 0x100>;
546 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
547 #address-cells = <1>;
548 #size-cells = <0>;
549 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
550 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
551 clock-names = "div-clk", "fast-clk";
552 resets = <&tegra_car 67>;
553 reset-names = "i2c";
554 dmas = <&apbdma 23>, <&apbdma 23>;
555 dma-names = "rx", "tx";
556 status = "disabled";
557 };
558
559 i2c@7000c700 {
560 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
561 reg = <0x7000c700 0x100>;
562 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
563 #address-cells = <1>;
564 #size-cells = <0>;
565 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
566 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
567 resets = <&tegra_car 103>;
568 reset-names = "i2c";
569 clock-names = "div-clk", "fast-clk";
570 dmas = <&apbdma 26>, <&apbdma 26>;
571 dma-names = "rx", "tx";
572 status = "disabled";
573 };
574
575 i2c@7000d000 {
576 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
577 reg = <0x7000d000 0x100>;
578 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
579 #address-cells = <1>;
580 #size-cells = <0>;
581 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
582 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
583 clock-names = "div-clk", "fast-clk";
584 resets = <&tegra_car 47>;
585 reset-names = "i2c";
586 dmas = <&apbdma 24>, <&apbdma 24>;
587 dma-names = "rx", "tx";
588 status = "disabled";
589 };
590
591 spi@7000d400 {
592 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
593 reg = <0x7000d400 0x200>;
594 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
595 #address-cells = <1>;
596 #size-cells = <0>;
597 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
598 resets = <&tegra_car 41>;
599 reset-names = "spi";
600 dmas = <&apbdma 15>, <&apbdma 15>;
601 dma-names = "rx", "tx";
602 status = "disabled";
603 };
604
605 spi@7000d600 {
606 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
607 reg = <0x7000d600 0x200>;
608 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
609 #address-cells = <1>;
610 #size-cells = <0>;
611 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
612 resets = <&tegra_car 44>;
613 reset-names = "spi";
614 dmas = <&apbdma 16>, <&apbdma 16>;
615 dma-names = "rx", "tx";
616 status = "disabled";
617 };
618
619 spi@7000d800 {
620 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
621 reg = <0x7000d800 0x200>;
622 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
623 #address-cells = <1>;
624 #size-cells = <0>;
625 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
626 resets = <&tegra_car 46>;
627 reset-names = "spi";
628 dmas = <&apbdma 17>, <&apbdma 17>;
629 dma-names = "rx", "tx";
630 status = "disabled";
631 };
632
633 spi@7000da00 {
634 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
635 reg = <0x7000da00 0x200>;
636 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
637 #address-cells = <1>;
638 #size-cells = <0>;
639 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
640 resets = <&tegra_car 68>;
641 reset-names = "spi";
642 dmas = <&apbdma 18>, <&apbdma 18>;
643 dma-names = "rx", "tx";
644 status = "disabled";
645 };
646
647 spi@7000dc00 {
648 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
649 reg = <0x7000dc00 0x200>;
650 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
651 #address-cells = <1>;
652 #size-cells = <0>;
653 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
654 resets = <&tegra_car 104>;
655 reset-names = "spi";
656 dmas = <&apbdma 27>, <&apbdma 27>;
657 dma-names = "rx", "tx";
658 status = "disabled";
659 };
660
661 spi@7000de00 {
662 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
663 reg = <0x7000de00 0x200>;
664 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
665 #address-cells = <1>;
666 #size-cells = <0>;
667 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
668 resets = <&tegra_car 106>;
669 reset-names = "spi";
670 dmas = <&apbdma 28>, <&apbdma 28>;
671 dma-names = "rx", "tx";
672 status = "disabled";
673 };
674
675 kbc@7000e200 {
676 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
677 reg = <0x7000e200 0x100>;
678 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
679 clocks = <&tegra_car TEGRA30_CLK_KBC>;
680 resets = <&tegra_car 36>;
681 reset-names = "kbc";
682 status = "disabled";
683 };
684
685 pmc@7000e400 {
686 compatible = "nvidia,tegra30-pmc";
687 reg = <0x7000e400 0x400>;
688 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
689 clock-names = "pclk", "clk32k_in";
690 };
691
692 mc: memory-controller@7000f000 {
693 compatible = "nvidia,tegra30-mc";
694 reg = <0x7000f000 0x400>;
695 clocks = <&tegra_car TEGRA30_CLK_MC>;
696 clock-names = "mc";
697
698 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
699
700 #iommu-cells = <1>;
701 };
702
703 fuse@7000f800 {
704 compatible = "nvidia,tegra30-efuse";
705 reg = <0x7000f800 0x400>;
706 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
707 clock-names = "fuse";
708 resets = <&tegra_car 39>;
709 reset-names = "fuse";
710 };
711
712 hda@70030000 {
713 compatible = "nvidia,tegra30-hda";
714 reg = <0x70030000 0x10000>;
715 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
716 clocks = <&tegra_car TEGRA30_CLK_HDA>,
717 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
718 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
719 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
720 resets = <&tegra_car 125>, /* hda */
721 <&tegra_car 128>, /* hda2hdmi */
722 <&tegra_car 111>; /* hda2codec_2x */
723 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
724 status = "disabled";
725 };
726
727 ahub@70080000 {
728 compatible = "nvidia,tegra30-ahub";
729 reg = <0x70080000 0x200
730 0x70080200 0x100>;
731 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
732 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
733 <&tegra_car TEGRA30_CLK_APBIF>;
734 clock-names = "d_audio", "apbif";
735 resets = <&tegra_car 106>, /* d_audio */
736 <&tegra_car 107>, /* apbif */
737 <&tegra_car 30>, /* i2s0 */
738 <&tegra_car 11>, /* i2s1 */
739 <&tegra_car 18>, /* i2s2 */
740 <&tegra_car 101>, /* i2s3 */
741 <&tegra_car 102>, /* i2s4 */
742 <&tegra_car 108>, /* dam0 */
743 <&tegra_car 109>, /* dam1 */
744 <&tegra_car 110>, /* dam2 */
745 <&tegra_car 10>; /* spdif */
746 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
747 "i2s3", "i2s4", "dam0", "dam1", "dam2",
748 "spdif";
749 dmas = <&apbdma 1>, <&apbdma 1>,
750 <&apbdma 2>, <&apbdma 2>,
751 <&apbdma 3>, <&apbdma 3>,
752 <&apbdma 4>, <&apbdma 4>;
753 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
754 "rx3", "tx3";
755 ranges;
756 #address-cells = <1>;
757 #size-cells = <1>;
758
759 tegra_i2s0: i2s@70080300 {
760 compatible = "nvidia,tegra30-i2s";
761 reg = <0x70080300 0x100>;
762 nvidia,ahub-cif-ids = <4 4>;
763 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
764 resets = <&tegra_car 30>;
765 reset-names = "i2s";
766 status = "disabled";
767 };
768
769 tegra_i2s1: i2s@70080400 {
770 compatible = "nvidia,tegra30-i2s";
771 reg = <0x70080400 0x100>;
772 nvidia,ahub-cif-ids = <5 5>;
773 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
774 resets = <&tegra_car 11>;
775 reset-names = "i2s";
776 status = "disabled";
777 };
778
779 tegra_i2s2: i2s@70080500 {
780 compatible = "nvidia,tegra30-i2s";
781 reg = <0x70080500 0x100>;
782 nvidia,ahub-cif-ids = <6 6>;
783 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
784 resets = <&tegra_car 18>;
785 reset-names = "i2s";
786 status = "disabled";
787 };
788
789 tegra_i2s3: i2s@70080600 {
790 compatible = "nvidia,tegra30-i2s";
791 reg = <0x70080600 0x100>;
792 nvidia,ahub-cif-ids = <7 7>;
793 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
794 resets = <&tegra_car 101>;
795 reset-names = "i2s";
796 status = "disabled";
797 };
798
799 tegra_i2s4: i2s@70080700 {
800 compatible = "nvidia,tegra30-i2s";
801 reg = <0x70080700 0x100>;
802 nvidia,ahub-cif-ids = <8 8>;
803 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
804 resets = <&tegra_car 102>;
805 reset-names = "i2s";
806 status = "disabled";
807 };
808 };
809
810 sdhci@78000000 {
811 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
812 reg = <0x78000000 0x200>;
813 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
815 resets = <&tegra_car 14>;
816 reset-names = "sdhci";
817 status = "disabled";
818 };
819
820 sdhci@78000200 {
821 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
822 reg = <0x78000200 0x200>;
823 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
824 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
825 resets = <&tegra_car 9>;
826 reset-names = "sdhci";
827 status = "disabled";
828 };
829
830 sdhci@78000400 {
831 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
832 reg = <0x78000400 0x200>;
833 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
834 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
835 resets = <&tegra_car 69>;
836 reset-names = "sdhci";
837 status = "disabled";
838 };
839
840 sdhci@78000600 {
841 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
842 reg = <0x78000600 0x200>;
843 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
844 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
845 resets = <&tegra_car 15>;
846 reset-names = "sdhci";
847 status = "disabled";
848 };
849
850 usb@7d000000 {
851 compatible = "nvidia,tegra30-ehci", "usb-ehci";
852 reg = <0x7d000000 0x4000>;
853 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
854 phy_type = "utmi";
855 clocks = <&tegra_car TEGRA30_CLK_USBD>;
856 resets = <&tegra_car 22>;
857 reset-names = "usb";
858 nvidia,needs-double-reset;
859 nvidia,phy = <&phy1>;
860 status = "disabled";
861 };
862
863 phy1: usb-phy@7d000000 {
864 compatible = "nvidia,tegra30-usb-phy";
865 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
866 phy_type = "utmi";
867 clocks = <&tegra_car TEGRA30_CLK_USBD>,
868 <&tegra_car TEGRA30_CLK_PLL_U>,
869 <&tegra_car TEGRA30_CLK_USBD>;
870 clock-names = "reg", "pll_u", "utmi-pads";
871 resets = <&tegra_car 22>, <&tegra_car 22>;
872 reset-names = "usb", "utmi-pads";
873 nvidia,hssync-start-delay = <9>;
874 nvidia,idle-wait-delay = <17>;
875 nvidia,elastic-limit = <16>;
876 nvidia,term-range-adj = <6>;
877 nvidia,xcvr-setup = <51>;
878 nvidia.xcvr-setup-use-fuses;
879 nvidia,xcvr-lsfslew = <1>;
880 nvidia,xcvr-lsrslew = <1>;
881 nvidia,xcvr-hsslew = <32>;
882 nvidia,hssquelch-level = <2>;
883 nvidia,hsdiscon-level = <5>;
884 nvidia,has-utmi-pad-registers;
885 status = "disabled";
886 };
887
888 usb@7d004000 {
889 compatible = "nvidia,tegra30-ehci", "usb-ehci";
890 reg = <0x7d004000 0x4000>;
891 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
892 phy_type = "utmi";
893 clocks = <&tegra_car TEGRA30_CLK_USB2>;
894 resets = <&tegra_car 58>;
895 reset-names = "usb";
896 nvidia,phy = <&phy2>;
897 status = "disabled";
898 };
899
900 phy2: usb-phy@7d004000 {
901 compatible = "nvidia,tegra30-usb-phy";
902 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
903 phy_type = "utmi";
904 clocks = <&tegra_car TEGRA30_CLK_USB2>,
905 <&tegra_car TEGRA30_CLK_PLL_U>,
906 <&tegra_car TEGRA30_CLK_USBD>;
907 clock-names = "reg", "pll_u", "utmi-pads";
908 resets = <&tegra_car 58>, <&tegra_car 22>;
909 reset-names = "usb", "utmi-pads";
910 nvidia,hssync-start-delay = <9>;
911 nvidia,idle-wait-delay = <17>;
912 nvidia,elastic-limit = <16>;
913 nvidia,term-range-adj = <6>;
914 nvidia,xcvr-setup = <51>;
915 nvidia.xcvr-setup-use-fuses;
916 nvidia,xcvr-lsfslew = <2>;
917 nvidia,xcvr-lsrslew = <2>;
918 nvidia,xcvr-hsslew = <32>;
919 nvidia,hssquelch-level = <2>;
920 nvidia,hsdiscon-level = <5>;
921 status = "disabled";
922 };
923
924 usb@7d008000 {
925 compatible = "nvidia,tegra30-ehci", "usb-ehci";
926 reg = <0x7d008000 0x4000>;
927 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
928 phy_type = "utmi";
929 clocks = <&tegra_car TEGRA30_CLK_USB3>;
930 resets = <&tegra_car 59>;
931 reset-names = "usb";
932 nvidia,phy = <&phy3>;
933 status = "disabled";
934 };
935
936 phy3: usb-phy@7d008000 {
937 compatible = "nvidia,tegra30-usb-phy";
938 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
939 phy_type = "utmi";
940 clocks = <&tegra_car TEGRA30_CLK_USB3>,
941 <&tegra_car TEGRA30_CLK_PLL_U>,
942 <&tegra_car TEGRA30_CLK_USBD>;
943 clock-names = "reg", "pll_u", "utmi-pads";
944 resets = <&tegra_car 59>, <&tegra_car 22>;
945 reset-names = "usb", "utmi-pads";
946 nvidia,hssync-start-delay = <0>;
947 nvidia,idle-wait-delay = <17>;
948 nvidia,elastic-limit = <16>;
949 nvidia,term-range-adj = <6>;
950 nvidia,xcvr-setup = <51>;
951 nvidia.xcvr-setup-use-fuses;
952 nvidia,xcvr-lsfslew = <2>;
953 nvidia,xcvr-lsrslew = <2>;
954 nvidia,xcvr-hsslew = <32>;
955 nvidia,hssquelch-level = <2>;
956 nvidia,hsdiscon-level = <5>;
957 status = "disabled";
958 };
959
960 cpus {
961 #address-cells = <1>;
962 #size-cells = <0>;
963
964 cpu@0 {
965 device_type = "cpu";
966 compatible = "arm,cortex-a9";
967 reg = <0>;
968 };
969
970 cpu@1 {
971 device_type = "cpu";
972 compatible = "arm,cortex-a9";
973 reg = <1>;
974 };
975
976 cpu@2 {
977 device_type = "cpu";
978 compatible = "arm,cortex-a9";
979 reg = <2>;
980 };
981
982 cpu@3 {
983 device_type = "cpu";
984 compatible = "arm,cortex-a9";
985 reg = <3>;
986 };
987 };
988
989 pmu {
990 compatible = "arm,cortex-a9-pmu";
991 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
992 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
993 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
994 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
995 };
996};
1// SPDX-License-Identifier: GPL-2.0
2#include <dt-bindings/clock/tegra30-car.h>
3#include <dt-bindings/gpio/tegra-gpio.h>
4#include <dt-bindings/memory/tegra30-mc.h>
5#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/soc/tegra-pmc.h>
8
9/ {
10 compatible = "nvidia,tegra30";
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
14
15 memory@80000000 {
16 device_type = "memory";
17 reg = <0x80000000 0x0>;
18 };
19
20 pcie@3000 {
21 compatible = "nvidia,tegra30-pcie";
22 device_type = "pci";
23 reg = <0x00003000 0x00000800>, /* PADS registers */
24 <0x00003800 0x00000200>, /* AFI registers */
25 <0x10000000 0x10000000>; /* configuration space */
26 reg-names = "pads", "afi", "cs";
27 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
28 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
29 interrupt-names = "intr", "msi";
30
31 #interrupt-cells = <1>;
32 interrupt-map-mask = <0 0 0 0>;
33 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
34
35 bus-range = <0x00 0xff>;
36 #address-cells = <3>;
37 #size-cells = <2>;
38
39 ranges = <0x02000000 0 0x00000000 0x00000000 0 0x00001000>, /* port 0 configuration space */
40 <0x02000000 0 0x00001000 0x00001000 0 0x00001000>, /* port 1 configuration space */
41 <0x02000000 0 0x00004000 0x00004000 0 0x00001000>, /* port 2 configuration space */
42 <0x01000000 0 0 0x02000000 0 0x00010000>, /* downstream I/O */
43 <0x02000000 0 0x20000000 0x20000000 0 0x08000000>, /* non-prefetchable memory */
44 <0x42000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
45
46 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
47 <&tegra_car TEGRA30_CLK_AFI>,
48 <&tegra_car TEGRA30_CLK_PLL_E>,
49 <&tegra_car TEGRA30_CLK_CML0>;
50 clock-names = "pex", "afi", "pll_e", "cml";
51 resets = <&tegra_car 70>,
52 <&tegra_car 72>,
53 <&tegra_car 74>;
54 reset-names = "pex", "afi", "pcie_x";
55 status = "disabled";
56
57 pci@1,0 {
58 device_type = "pci";
59 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
60 reg = <0x000800 0 0 0 0>;
61 bus-range = <0x00 0xff>;
62 status = "disabled";
63
64 #address-cells = <3>;
65 #size-cells = <2>;
66 ranges;
67
68 nvidia,num-lanes = <2>;
69 };
70
71 pci@2,0 {
72 device_type = "pci";
73 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
74 reg = <0x001000 0 0 0 0>;
75 bus-range = <0x00 0xff>;
76 status = "disabled";
77
78 #address-cells = <3>;
79 #size-cells = <2>;
80 ranges;
81
82 nvidia,num-lanes = <2>;
83 };
84
85 pci@3,0 {
86 device_type = "pci";
87 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
88 reg = <0x001800 0 0 0 0>;
89 bus-range = <0x00 0xff>;
90 status = "disabled";
91
92 #address-cells = <3>;
93 #size-cells = <2>;
94 ranges;
95
96 nvidia,num-lanes = <2>;
97 };
98 };
99
100 sram@40000000 {
101 compatible = "mmio-sram";
102 reg = <0x40000000 0x40000>;
103 #address-cells = <1>;
104 #size-cells = <1>;
105 ranges = <0 0x40000000 0x40000>;
106
107 vde_pool: sram@400 {
108 reg = <0x400 0x3fc00>;
109 pool;
110 };
111 };
112
113 host1x@50000000 {
114 compatible = "nvidia,tegra30-host1x";
115 reg = <0x50000000 0x00024000>;
116 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
117 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
118 interrupt-names = "syncpt", "host1x";
119 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
120 clock-names = "host1x";
121 resets = <&tegra_car 28>;
122 reset-names = "host1x";
123 iommus = <&mc TEGRA_SWGROUP_HC>;
124
125 #address-cells = <1>;
126 #size-cells = <1>;
127
128 ranges = <0x54000000 0x54000000 0x04000000>;
129
130 mpe@54040000 {
131 compatible = "nvidia,tegra30-mpe";
132 reg = <0x54040000 0x00040000>;
133 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
134 clocks = <&tegra_car TEGRA30_CLK_MPE>;
135 resets = <&tegra_car 60>;
136 reset-names = "mpe";
137
138 iommus = <&mc TEGRA_SWGROUP_MPE>;
139 };
140
141 vi@54080000 {
142 compatible = "nvidia,tegra30-vi";
143 reg = <0x54080000 0x00040000>;
144 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
145 clocks = <&tegra_car TEGRA30_CLK_VI>;
146 resets = <&tegra_car 20>;
147 reset-names = "vi";
148
149 iommus = <&mc TEGRA_SWGROUP_VI>;
150 };
151
152 epp@540c0000 {
153 compatible = "nvidia,tegra30-epp";
154 reg = <0x540c0000 0x00040000>;
155 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
156 clocks = <&tegra_car TEGRA30_CLK_EPP>;
157 resets = <&tegra_car 19>;
158 reset-names = "epp";
159
160 iommus = <&mc TEGRA_SWGROUP_EPP>;
161 };
162
163 isp@54100000 {
164 compatible = "nvidia,tegra30-isp";
165 reg = <0x54100000 0x00040000>;
166 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
167 clocks = <&tegra_car TEGRA30_CLK_ISP>;
168 resets = <&tegra_car 23>;
169 reset-names = "isp";
170
171 iommus = <&mc TEGRA_SWGROUP_ISP>;
172 };
173
174 gr2d@54140000 {
175 compatible = "nvidia,tegra30-gr2d";
176 reg = <0x54140000 0x00040000>;
177 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
178 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
179 resets = <&tegra_car 21>;
180 reset-names = "2d";
181
182 iommus = <&mc TEGRA_SWGROUP_G2>;
183 };
184
185 gr3d@54180000 {
186 compatible = "nvidia,tegra30-gr3d";
187 reg = <0x54180000 0x00040000>;
188 clocks = <&tegra_car TEGRA30_CLK_GR3D>,
189 <&tegra_car TEGRA30_CLK_GR3D2>;
190 clock-names = "3d", "3d2";
191 resets = <&tegra_car 24>,
192 <&tegra_car 98>;
193 reset-names = "3d", "3d2";
194
195 iommus = <&mc TEGRA_SWGROUP_NV>,
196 <&mc TEGRA_SWGROUP_NV2>;
197 };
198
199 dc@54200000 {
200 compatible = "nvidia,tegra30-dc";
201 reg = <0x54200000 0x00040000>;
202 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
203 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
204 <&tegra_car TEGRA30_CLK_PLL_P>;
205 clock-names = "dc", "parent";
206 resets = <&tegra_car 27>;
207 reset-names = "dc";
208
209 iommus = <&mc TEGRA_SWGROUP_DC>;
210
211 nvidia,head = <0>;
212
213 rgb {
214 status = "disabled";
215 };
216 };
217
218 dc@54240000 {
219 compatible = "nvidia,tegra30-dc";
220 reg = <0x54240000 0x00040000>;
221 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
223 <&tegra_car TEGRA30_CLK_PLL_P>;
224 clock-names = "dc", "parent";
225 resets = <&tegra_car 26>;
226 reset-names = "dc";
227
228 iommus = <&mc TEGRA_SWGROUP_DCB>;
229
230 nvidia,head = <1>;
231
232 rgb {
233 status = "disabled";
234 };
235 };
236
237 hdmi@54280000 {
238 compatible = "nvidia,tegra30-hdmi";
239 reg = <0x54280000 0x00040000>;
240 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
241 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
242 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
243 clock-names = "hdmi", "parent";
244 resets = <&tegra_car 51>;
245 reset-names = "hdmi";
246 status = "disabled";
247 };
248
249 tvo@542c0000 {
250 compatible = "nvidia,tegra30-tvo";
251 reg = <0x542c0000 0x00040000>;
252 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
253 clocks = <&tegra_car TEGRA30_CLK_TVO>;
254 status = "disabled";
255 };
256
257 dsi@54300000 {
258 compatible = "nvidia,tegra30-dsi";
259 reg = <0x54300000 0x00040000>;
260 clocks = <&tegra_car TEGRA30_CLK_DSIA>,
261 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
262 clock-names = "dsi", "parent";
263 resets = <&tegra_car 48>;
264 reset-names = "dsi";
265 status = "disabled";
266 };
267
268 dsi@54400000 {
269 compatible = "nvidia,tegra30-dsi";
270 reg = <0x54400000 0x00040000>;
271 clocks = <&tegra_car TEGRA30_CLK_DSIB>,
272 <&tegra_car TEGRA30_CLK_PLL_D_OUT0>;
273 clock-names = "dsi", "parent";
274 resets = <&tegra_car 84>;
275 reset-names = "dsi";
276 status = "disabled";
277 };
278 };
279
280 timer@50040600 {
281 compatible = "arm,cortex-a9-twd-timer";
282 reg = <0x50040600 0x20>;
283 interrupt-parent = <&intc>;
284 interrupts = <GIC_PPI 13
285 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
286 clocks = <&tegra_car TEGRA30_CLK_TWD>;
287 };
288
289 intc: interrupt-controller@50041000 {
290 compatible = "arm,cortex-a9-gic";
291 reg = <0x50041000 0x1000>,
292 <0x50040100 0x0100>;
293 interrupt-controller;
294 #interrupt-cells = <3>;
295 interrupt-parent = <&intc>;
296 };
297
298 cache-controller@50043000 {
299 compatible = "arm,pl310-cache";
300 reg = <0x50043000 0x1000>;
301 arm,data-latency = <6 6 2>;
302 arm,tag-latency = <5 5 2>;
303 cache-unified;
304 cache-level = <2>;
305 };
306
307 lic: interrupt-controller@60004000 {
308 compatible = "nvidia,tegra30-ictlr";
309 reg = <0x60004000 0x100>,
310 <0x60004100 0x50>,
311 <0x60004200 0x50>,
312 <0x60004300 0x50>,
313 <0x60004400 0x50>;
314 interrupt-controller;
315 #interrupt-cells = <3>;
316 interrupt-parent = <&intc>;
317 };
318
319 timer@60005000 {
320 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
321 reg = <0x60005000 0x400>;
322 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
326 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
328 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
329 };
330
331 tegra_car: clock@60006000 {
332 compatible = "nvidia,tegra30-car";
333 reg = <0x60006000 0x1000>;
334 #clock-cells = <1>;
335 #reset-cells = <1>;
336 };
337
338 flow-controller@60007000 {
339 compatible = "nvidia,tegra30-flowctrl";
340 reg = <0x60007000 0x1000>;
341 };
342
343 apbdma: dma@6000a000 {
344 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
345 reg = <0x6000a000 0x1400>;
346 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
348 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
349 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
350 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
351 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
352 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
353 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
354 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
355 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
356 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
357 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
358 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
359 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
360 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
361 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
362 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
363 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
364 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
365 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
366 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
367 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
368 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
369 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
370 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
371 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
372 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
373 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
374 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
375 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
376 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
377 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
378 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
379 resets = <&tegra_car 34>;
380 reset-names = "dma";
381 #dma-cells = <1>;
382 };
383
384 ahb: ahb@6000c000 {
385 compatible = "nvidia,tegra30-ahb";
386 reg = <0x6000c000 0x150>; /* AHB Arbitration + Gizmo Controller */
387 };
388
389 actmon@6000c800 {
390 compatible = "nvidia,tegra30-actmon";
391 reg = <0x6000c800 0x400>;
392 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
393 clocks = <&tegra_car TEGRA30_CLK_ACTMON>,
394 <&tegra_car TEGRA30_CLK_EMC>;
395 clock-names = "actmon", "emc";
396 resets = <&tegra_car TEGRA30_CLK_ACTMON>;
397 reset-names = "actmon";
398 };
399
400 gpio: gpio@6000d000 {
401 compatible = "nvidia,tegra30-gpio";
402 reg = <0x6000d000 0x1000>;
403 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
405 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
406 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
407 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
408 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
409 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
410 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
411 #gpio-cells = <2>;
412 gpio-controller;
413 #interrupt-cells = <2>;
414 interrupt-controller;
415 /*
416 gpio-ranges = <&pinmux 0 0 248>;
417 */
418 };
419
420 vde@6001a000 {
421 compatible = "nvidia,tegra30-vde", "nvidia,tegra20-vde";
422 reg = <0x6001a000 0x1000>, /* Syntax Engine */
423 <0x6001b000 0x1000>, /* Video Bitstream Engine */
424 <0x6001c000 0x100>, /* Macroblock Engine */
425 <0x6001c200 0x100>, /* Post-processing Engine */
426 <0x6001c400 0x100>, /* Motion Compensation Engine */
427 <0x6001c600 0x100>, /* Transform Engine */
428 <0x6001c800 0x100>, /* Pixel prediction block */
429 <0x6001ca00 0x100>, /* Video DMA */
430 <0x6001d800 0x400>; /* Video frame controls */
431 reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
432 "tfe", "ppb", "vdma", "frameid";
433 iram = <&vde_pool>; /* IRAM region */
434 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, /* Sync token interrupt */
435 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, /* BSE-V interrupt */
436 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; /* SXE interrupt */
437 interrupt-names = "sync-token", "bsev", "sxe";
438 clocks = <&tegra_car TEGRA30_CLK_VDE>;
439 reset-names = "vde", "mc";
440 resets = <&tegra_car 61>, <&mc TEGRA30_MC_RESET_VDE>;
441 iommus = <&mc TEGRA_SWGROUP_VDE>;
442 };
443
444 apbmisc@70000800 {
445 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
446 reg = <0x70000800 0x64>, /* Chip revision */
447 <0x70000008 0x04>; /* Strapping options */
448 };
449
450 pinmux: pinmux@70000868 {
451 compatible = "nvidia,tegra30-pinmux";
452 reg = <0x70000868 0x0d4>, /* Pad control registers */
453 <0x70003000 0x3e4>; /* Mux registers */
454 };
455
456 /*
457 * There are two serial driver i.e. 8250 based simple serial
458 * driver and APB DMA based serial driver for higher baudrate
459 * and performace. To enable the 8250 based driver, the compatible
460 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
461 * the APB DMA based serial driver, the compatible is
462 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
463 */
464 uarta: serial@70006000 {
465 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
466 reg = <0x70006000 0x40>;
467 reg-shift = <2>;
468 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
469 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
470 resets = <&tegra_car 6>;
471 reset-names = "serial";
472 dmas = <&apbdma 8>, <&apbdma 8>;
473 dma-names = "rx", "tx";
474 status = "disabled";
475 };
476
477 uartb: serial@70006040 {
478 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
479 reg = <0x70006040 0x40>;
480 reg-shift = <2>;
481 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
483 resets = <&tegra_car 7>;
484 reset-names = "serial";
485 dmas = <&apbdma 9>, <&apbdma 9>;
486 dma-names = "rx", "tx";
487 status = "disabled";
488 };
489
490 uartc: serial@70006200 {
491 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
492 reg = <0x70006200 0x100>;
493 reg-shift = <2>;
494 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
495 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
496 resets = <&tegra_car 55>;
497 reset-names = "serial";
498 dmas = <&apbdma 10>, <&apbdma 10>;
499 dma-names = "rx", "tx";
500 status = "disabled";
501 };
502
503 uartd: serial@70006300 {
504 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
505 reg = <0x70006300 0x100>;
506 reg-shift = <2>;
507 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
508 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
509 resets = <&tegra_car 65>;
510 reset-names = "serial";
511 dmas = <&apbdma 19>, <&apbdma 19>;
512 dma-names = "rx", "tx";
513 status = "disabled";
514 };
515
516 uarte: serial@70006400 {
517 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
518 reg = <0x70006400 0x100>;
519 reg-shift = <2>;
520 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
521 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
522 resets = <&tegra_car 66>;
523 reset-names = "serial";
524 dmas = <&apbdma 20>, <&apbdma 20>;
525 dma-names = "rx", "tx";
526 status = "disabled";
527 };
528
529 gmi@70009000 {
530 compatible = "nvidia,tegra30-gmi";
531 reg = <0x70009000 0x1000>;
532 #address-cells = <2>;
533 #size-cells = <1>;
534 ranges = <0 0 0x48000000 0x7ffffff>;
535 clocks = <&tegra_car TEGRA30_CLK_NOR>;
536 clock-names = "gmi";
537 resets = <&tegra_car 42>;
538 reset-names = "gmi";
539 status = "disabled";
540 };
541
542 pwm: pwm@7000a000 {
543 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
544 reg = <0x7000a000 0x100>;
545 #pwm-cells = <2>;
546 clocks = <&tegra_car TEGRA30_CLK_PWM>;
547 resets = <&tegra_car 17>;
548 reset-names = "pwm";
549 status = "disabled";
550 };
551
552 rtc@7000e000 {
553 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
554 reg = <0x7000e000 0x100>;
555 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
556 clocks = <&tegra_car TEGRA30_CLK_RTC>;
557 };
558
559 i2c@7000c000 {
560 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
561 reg = <0x7000c000 0x100>;
562 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
563 #address-cells = <1>;
564 #size-cells = <0>;
565 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
566 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
567 clock-names = "div-clk", "fast-clk";
568 resets = <&tegra_car 12>;
569 reset-names = "i2c";
570 dmas = <&apbdma 21>, <&apbdma 21>;
571 dma-names = "rx", "tx";
572 status = "disabled";
573 };
574
575 i2c@7000c400 {
576 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
577 reg = <0x7000c400 0x100>;
578 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
579 #address-cells = <1>;
580 #size-cells = <0>;
581 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
582 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
583 clock-names = "div-clk", "fast-clk";
584 resets = <&tegra_car 54>;
585 reset-names = "i2c";
586 dmas = <&apbdma 22>, <&apbdma 22>;
587 dma-names = "rx", "tx";
588 status = "disabled";
589 };
590
591 i2c@7000c500 {
592 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
593 reg = <0x7000c500 0x100>;
594 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
595 #address-cells = <1>;
596 #size-cells = <0>;
597 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
598 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
599 clock-names = "div-clk", "fast-clk";
600 resets = <&tegra_car 67>;
601 reset-names = "i2c";
602 dmas = <&apbdma 23>, <&apbdma 23>;
603 dma-names = "rx", "tx";
604 status = "disabled";
605 };
606
607 i2c@7000c700 {
608 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
609 reg = <0x7000c700 0x100>;
610 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
611 #address-cells = <1>;
612 #size-cells = <0>;
613 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
614 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
615 resets = <&tegra_car 103>;
616 reset-names = "i2c";
617 clock-names = "div-clk", "fast-clk";
618 dmas = <&apbdma 26>, <&apbdma 26>;
619 dma-names = "rx", "tx";
620 status = "disabled";
621 };
622
623 i2c@7000d000 {
624 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
625 reg = <0x7000d000 0x100>;
626 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
627 #address-cells = <1>;
628 #size-cells = <0>;
629 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
630 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
631 clock-names = "div-clk", "fast-clk";
632 resets = <&tegra_car 47>;
633 reset-names = "i2c";
634 dmas = <&apbdma 24>, <&apbdma 24>;
635 dma-names = "rx", "tx";
636 status = "disabled";
637 };
638
639 spi@7000d400 {
640 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
641 reg = <0x7000d400 0x200>;
642 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
643 #address-cells = <1>;
644 #size-cells = <0>;
645 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
646 resets = <&tegra_car 41>;
647 reset-names = "spi";
648 dmas = <&apbdma 15>, <&apbdma 15>;
649 dma-names = "rx", "tx";
650 status = "disabled";
651 };
652
653 spi@7000d600 {
654 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
655 reg = <0x7000d600 0x200>;
656 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
657 #address-cells = <1>;
658 #size-cells = <0>;
659 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
660 resets = <&tegra_car 44>;
661 reset-names = "spi";
662 dmas = <&apbdma 16>, <&apbdma 16>;
663 dma-names = "rx", "tx";
664 status = "disabled";
665 };
666
667 spi@7000d800 {
668 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
669 reg = <0x7000d800 0x200>;
670 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
671 #address-cells = <1>;
672 #size-cells = <0>;
673 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
674 resets = <&tegra_car 46>;
675 reset-names = "spi";
676 dmas = <&apbdma 17>, <&apbdma 17>;
677 dma-names = "rx", "tx";
678 status = "disabled";
679 };
680
681 spi@7000da00 {
682 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
683 reg = <0x7000da00 0x200>;
684 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
685 #address-cells = <1>;
686 #size-cells = <0>;
687 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
688 resets = <&tegra_car 68>;
689 reset-names = "spi";
690 dmas = <&apbdma 18>, <&apbdma 18>;
691 dma-names = "rx", "tx";
692 status = "disabled";
693 };
694
695 spi@7000dc00 {
696 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
697 reg = <0x7000dc00 0x200>;
698 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
699 #address-cells = <1>;
700 #size-cells = <0>;
701 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
702 resets = <&tegra_car 104>;
703 reset-names = "spi";
704 dmas = <&apbdma 27>, <&apbdma 27>;
705 dma-names = "rx", "tx";
706 status = "disabled";
707 };
708
709 spi@7000de00 {
710 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
711 reg = <0x7000de00 0x200>;
712 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
713 #address-cells = <1>;
714 #size-cells = <0>;
715 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
716 resets = <&tegra_car 106>;
717 reset-names = "spi";
718 dmas = <&apbdma 28>, <&apbdma 28>;
719 dma-names = "rx", "tx";
720 status = "disabled";
721 };
722
723 kbc@7000e200 {
724 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
725 reg = <0x7000e200 0x100>;
726 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&tegra_car TEGRA30_CLK_KBC>;
728 resets = <&tegra_car 36>;
729 reset-names = "kbc";
730 status = "disabled";
731 };
732
733 tegra_pmc: pmc@7000e400 {
734 compatible = "nvidia,tegra30-pmc";
735 reg = <0x7000e400 0x400>;
736 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
737 clock-names = "pclk", "clk32k_in";
738 #clock-cells = <1>;
739 };
740
741 mc: memory-controller@7000f000 {
742 compatible = "nvidia,tegra30-mc";
743 reg = <0x7000f000 0x400>;
744 clocks = <&tegra_car TEGRA30_CLK_MC>;
745 clock-names = "mc";
746
747 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
748
749 #iommu-cells = <1>;
750 #reset-cells = <1>;
751 };
752
753 memory-controller@7000f400 {
754 compatible = "nvidia,tegra30-emc";
755 reg = <0x7000f400 0x400>;
756 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&tegra_car TEGRA30_CLK_EMC>;
758
759 nvidia,memory-controller = <&mc>;
760 };
761
762 fuse@7000f800 {
763 compatible = "nvidia,tegra30-efuse";
764 reg = <0x7000f800 0x400>;
765 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
766 clock-names = "fuse";
767 resets = <&tegra_car 39>;
768 reset-names = "fuse";
769 };
770
771 hda@70030000 {
772 compatible = "nvidia,tegra30-hda";
773 reg = <0x70030000 0x10000>;
774 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
775 clocks = <&tegra_car TEGRA30_CLK_HDA>,
776 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
777 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
778 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
779 resets = <&tegra_car 125>, /* hda */
780 <&tegra_car 128>, /* hda2hdmi */
781 <&tegra_car 111>; /* hda2codec_2x */
782 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
783 status = "disabled";
784 };
785
786 ahub@70080000 {
787 compatible = "nvidia,tegra30-ahub";
788 reg = <0x70080000 0x200>,
789 <0x70080200 0x100>;
790 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
791 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
792 <&tegra_car TEGRA30_CLK_APBIF>;
793 clock-names = "d_audio", "apbif";
794 resets = <&tegra_car 106>, /* d_audio */
795 <&tegra_car 107>, /* apbif */
796 <&tegra_car 30>, /* i2s0 */
797 <&tegra_car 11>, /* i2s1 */
798 <&tegra_car 18>, /* i2s2 */
799 <&tegra_car 101>, /* i2s3 */
800 <&tegra_car 102>, /* i2s4 */
801 <&tegra_car 108>, /* dam0 */
802 <&tegra_car 109>, /* dam1 */
803 <&tegra_car 110>, /* dam2 */
804 <&tegra_car 10>; /* spdif */
805 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
806 "i2s3", "i2s4", "dam0", "dam1", "dam2",
807 "spdif";
808 dmas = <&apbdma 1>, <&apbdma 1>,
809 <&apbdma 2>, <&apbdma 2>,
810 <&apbdma 3>, <&apbdma 3>,
811 <&apbdma 4>, <&apbdma 4>;
812 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
813 "rx3", "tx3";
814 ranges;
815 #address-cells = <1>;
816 #size-cells = <1>;
817
818 tegra_i2s0: i2s@70080300 {
819 compatible = "nvidia,tegra30-i2s";
820 reg = <0x70080300 0x100>;
821 nvidia,ahub-cif-ids = <4 4>;
822 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
823 resets = <&tegra_car 30>;
824 reset-names = "i2s";
825 status = "disabled";
826 };
827
828 tegra_i2s1: i2s@70080400 {
829 compatible = "nvidia,tegra30-i2s";
830 reg = <0x70080400 0x100>;
831 nvidia,ahub-cif-ids = <5 5>;
832 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
833 resets = <&tegra_car 11>;
834 reset-names = "i2s";
835 status = "disabled";
836 };
837
838 tegra_i2s2: i2s@70080500 {
839 compatible = "nvidia,tegra30-i2s";
840 reg = <0x70080500 0x100>;
841 nvidia,ahub-cif-ids = <6 6>;
842 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
843 resets = <&tegra_car 18>;
844 reset-names = "i2s";
845 status = "disabled";
846 };
847
848 tegra_i2s3: i2s@70080600 {
849 compatible = "nvidia,tegra30-i2s";
850 reg = <0x70080600 0x100>;
851 nvidia,ahub-cif-ids = <7 7>;
852 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
853 resets = <&tegra_car 101>;
854 reset-names = "i2s";
855 status = "disabled";
856 };
857
858 tegra_i2s4: i2s@70080700 {
859 compatible = "nvidia,tegra30-i2s";
860 reg = <0x70080700 0x100>;
861 nvidia,ahub-cif-ids = <8 8>;
862 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
863 resets = <&tegra_car 102>;
864 reset-names = "i2s";
865 status = "disabled";
866 };
867 };
868
869 mmc@78000000 {
870 compatible = "nvidia,tegra30-sdhci";
871 reg = <0x78000000 0x200>;
872 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
874 clock-names = "sdhci";
875 resets = <&tegra_car 14>;
876 reset-names = "sdhci";
877 status = "disabled";
878 };
879
880 mmc@78000200 {
881 compatible = "nvidia,tegra30-sdhci";
882 reg = <0x78000200 0x200>;
883 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
884 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
885 clock-names = "sdhci";
886 resets = <&tegra_car 9>;
887 reset-names = "sdhci";
888 status = "disabled";
889 };
890
891 mmc@78000400 {
892 compatible = "nvidia,tegra30-sdhci";
893 reg = <0x78000400 0x200>;
894 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
895 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
896 clock-names = "sdhci";
897 resets = <&tegra_car 69>;
898 reset-names = "sdhci";
899 status = "disabled";
900 };
901
902 mmc@78000600 {
903 compatible = "nvidia,tegra30-sdhci";
904 reg = <0x78000600 0x200>;
905 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
906 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
907 clock-names = "sdhci";
908 resets = <&tegra_car 15>;
909 reset-names = "sdhci";
910 status = "disabled";
911 };
912
913 usb@7d000000 {
914 compatible = "nvidia,tegra30-ehci", "usb-ehci";
915 reg = <0x7d000000 0x4000>;
916 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
917 phy_type = "utmi";
918 clocks = <&tegra_car TEGRA30_CLK_USBD>;
919 resets = <&tegra_car 22>;
920 reset-names = "usb";
921 nvidia,needs-double-reset;
922 nvidia,phy = <&phy1>;
923 status = "disabled";
924 };
925
926 phy1: usb-phy@7d000000 {
927 compatible = "nvidia,tegra30-usb-phy";
928 reg = <0x7d000000 0x4000>,
929 <0x7d000000 0x4000>;
930 phy_type = "utmi";
931 clocks = <&tegra_car TEGRA30_CLK_USBD>,
932 <&tegra_car TEGRA30_CLK_PLL_U>,
933 <&tegra_car TEGRA30_CLK_USBD>;
934 clock-names = "reg", "pll_u", "utmi-pads";
935 resets = <&tegra_car 22>, <&tegra_car 22>;
936 reset-names = "usb", "utmi-pads";
937 #phy-cells = <0>;
938 nvidia,hssync-start-delay = <9>;
939 nvidia,idle-wait-delay = <17>;
940 nvidia,elastic-limit = <16>;
941 nvidia,term-range-adj = <6>;
942 nvidia,xcvr-setup = <51>;
943 nvidia,xcvr-setup-use-fuses;
944 nvidia,xcvr-lsfslew = <1>;
945 nvidia,xcvr-lsrslew = <1>;
946 nvidia,xcvr-hsslew = <32>;
947 nvidia,hssquelch-level = <2>;
948 nvidia,hsdiscon-level = <5>;
949 nvidia,has-utmi-pad-registers;
950 status = "disabled";
951 };
952
953 usb@7d004000 {
954 compatible = "nvidia,tegra30-ehci", "usb-ehci";
955 reg = <0x7d004000 0x4000>;
956 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
957 phy_type = "utmi";
958 clocks = <&tegra_car TEGRA30_CLK_USB2>;
959 resets = <&tegra_car 58>;
960 reset-names = "usb";
961 nvidia,phy = <&phy2>;
962 status = "disabled";
963 };
964
965 phy2: usb-phy@7d004000 {
966 compatible = "nvidia,tegra30-usb-phy";
967 reg = <0x7d004000 0x4000>,
968 <0x7d000000 0x4000>;
969 phy_type = "utmi";
970 clocks = <&tegra_car TEGRA30_CLK_USB2>,
971 <&tegra_car TEGRA30_CLK_PLL_U>,
972 <&tegra_car TEGRA30_CLK_USBD>;
973 clock-names = "reg", "pll_u", "utmi-pads";
974 resets = <&tegra_car 58>, <&tegra_car 22>;
975 reset-names = "usb", "utmi-pads";
976 #phy-cells = <0>;
977 nvidia,hssync-start-delay = <9>;
978 nvidia,idle-wait-delay = <17>;
979 nvidia,elastic-limit = <16>;
980 nvidia,term-range-adj = <6>;
981 nvidia,xcvr-setup = <51>;
982 nvidia,xcvr-setup-use-fuses;
983 nvidia,xcvr-lsfslew = <2>;
984 nvidia,xcvr-lsrslew = <2>;
985 nvidia,xcvr-hsslew = <32>;
986 nvidia,hssquelch-level = <2>;
987 nvidia,hsdiscon-level = <5>;
988 status = "disabled";
989 };
990
991 usb@7d008000 {
992 compatible = "nvidia,tegra30-ehci", "usb-ehci";
993 reg = <0x7d008000 0x4000>;
994 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
995 phy_type = "utmi";
996 clocks = <&tegra_car TEGRA30_CLK_USB3>;
997 resets = <&tegra_car 59>;
998 reset-names = "usb";
999 nvidia,phy = <&phy3>;
1000 status = "disabled";
1001 };
1002
1003 phy3: usb-phy@7d008000 {
1004 compatible = "nvidia,tegra30-usb-phy";
1005 reg = <0x7d008000 0x4000>,
1006 <0x7d000000 0x4000>;
1007 phy_type = "utmi";
1008 clocks = <&tegra_car TEGRA30_CLK_USB3>,
1009 <&tegra_car TEGRA30_CLK_PLL_U>,
1010 <&tegra_car TEGRA30_CLK_USBD>;
1011 clock-names = "reg", "pll_u", "utmi-pads";
1012 resets = <&tegra_car 59>, <&tegra_car 22>;
1013 reset-names = "usb", "utmi-pads";
1014 #phy-cells = <0>;
1015 nvidia,hssync-start-delay = <0>;
1016 nvidia,idle-wait-delay = <17>;
1017 nvidia,elastic-limit = <16>;
1018 nvidia,term-range-adj = <6>;
1019 nvidia,xcvr-setup = <51>;
1020 nvidia,xcvr-setup-use-fuses;
1021 nvidia,xcvr-lsfslew = <2>;
1022 nvidia,xcvr-lsrslew = <2>;
1023 nvidia,xcvr-hsslew = <32>;
1024 nvidia,hssquelch-level = <2>;
1025 nvidia,hsdiscon-level = <5>;
1026 status = "disabled";
1027 };
1028
1029 cpus {
1030 #address-cells = <1>;
1031 #size-cells = <0>;
1032
1033 cpu@0 {
1034 device_type = "cpu";
1035 compatible = "arm,cortex-a9";
1036 reg = <0>;
1037 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1038 };
1039
1040 cpu@1 {
1041 device_type = "cpu";
1042 compatible = "arm,cortex-a9";
1043 reg = <1>;
1044 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1045 };
1046
1047 cpu@2 {
1048 device_type = "cpu";
1049 compatible = "arm,cortex-a9";
1050 reg = <2>;
1051 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1052 };
1053
1054 cpu@3 {
1055 device_type = "cpu";
1056 compatible = "arm,cortex-a9";
1057 reg = <3>;
1058 clocks = <&tegra_car TEGRA30_CLK_CCLK_G>;
1059 };
1060 };
1061
1062 pmu {
1063 compatible = "arm,cortex-a9-pmu";
1064 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
1065 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
1066 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
1067 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1068 interrupt-affinity = <&{/cpus/cpu@0}>,
1069 <&{/cpus/cpu@1}>,
1070 <&{/cpus/cpu@2}>,
1071 <&{/cpus/cpu@3}>;
1072 };
1073};