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1/*
2 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
3 *
4 * Copyright (C) 2015 Atmel,
5 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
6 *
7 * This file is dual-licensed: you can use it either under the terms
8 * of the GPL or the X11 license, at your option. Note that this dual
9 * licensing only applies to this file, and not this project as a
10 * whole.
11 *
12 * a) This file is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of the
15 * License, or (at your option) any later version.
16 *
17 * This file is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * Or, alternatively,
23 *
24 * b) Permission is hereby granted, free of charge, to any person
25 * obtaining a copy of this software and associated documentation
26 * files (the "Software"), to deal in the Software without
27 * restriction, including without limitation the rights to use,
28 * copy, modify, merge, publish, distribute, sublicense, and/or
29 * sell copies of the Software, and to permit persons to whom the
30 * Software is furnished to do so, subject to the following
31 * conditions:
32 *
33 * The above copyright notice and this permission notice shall be
34 * included in all copies or substantial portions of the Software.
35 *
36 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
37 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
38 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
39 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
40 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
41 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
42 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
43 * OTHER DEALINGS IN THE SOFTWARE.
44 */
45
46#include "skeleton.dtsi"
47#include <dt-bindings/dma/at91.h>
48#include <dt-bindings/interrupt-controller/irq.h>
49#include <dt-bindings/clock/at91.h>
50
51/ {
52 model = "Atmel SAMA5D2 family SoC";
53 compatible = "atmel,sama5d2";
54 interrupt-parent = <&aic>;
55
56 aliases {
57 serial0 = &uart1;
58 serial1 = &uart3;
59 tcb0 = &tcb0;
60 tcb1 = &tcb1;
61 };
62
63 cpus {
64 #address-cells = <1>;
65 #size-cells = <0>;
66
67 cpu@0 {
68 device_type = "cpu";
69 compatible = "arm,cortex-a5";
70 reg = <0>;
71 next-level-cache = <&L2>;
72 };
73 };
74
75 pmu {
76 compatible = "arm,cortex-a5-pmu";
77 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
78 };
79
80 etb {
81 compatible = "arm,coresight-etb10", "arm,primecell";
82 reg = <0x740000 0x1000>;
83
84 clocks = <&mck>;
85 clock-names = "apb_pclk";
86
87 port {
88 etb_in: endpoint {
89 slave-mode;
90 remote-endpoint = <&etm_out>;
91 };
92 };
93 };
94
95 etm {
96 compatible = "arm,coresight-etm3x", "arm,primecell";
97 reg = <0x73C000 0x1000>;
98
99 clocks = <&mck>;
100 clock-names = "apb_pclk";
101
102 port {
103 etm_out: endpoint {
104 remote-endpoint = <&etb_in>;
105 };
106 };
107 };
108
109 memory {
110 reg = <0x20000000 0x20000000>;
111 };
112
113 clocks {
114 slow_xtal: slow_xtal {
115 compatible = "fixed-clock";
116 #clock-cells = <0>;
117 clock-frequency = <0>;
118 };
119
120 main_xtal: main_xtal {
121 compatible = "fixed-clock";
122 #clock-cells = <0>;
123 clock-frequency = <0>;
124 };
125 };
126
127 ns_sram: sram@200000 {
128 compatible = "mmio-sram";
129 reg = <0x00200000 0x20000>;
130 };
131
132 ahb {
133 compatible = "simple-bus";
134 #address-cells = <1>;
135 #size-cells = <1>;
136 ranges;
137
138 nfc_sram: sram@100000 {
139 compatible = "mmio-sram";
140 no-memory-wc;
141 reg = <0x00100000 0x2400>;
142 };
143
144 usb0: gadget@300000 {
145 #address-cells = <1>;
146 #size-cells = <0>;
147 compatible = "atmel,sama5d3-udc";
148 reg = <0x00300000 0x100000
149 0xfc02c000 0x400>;
150 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
151 clocks = <&udphs_clk>, <&utmi>;
152 clock-names = "pclk", "hclk";
153 status = "disabled";
154
155 ep@0 {
156 reg = <0>;
157 atmel,fifo-size = <64>;
158 atmel,nb-banks = <1>;
159 };
160
161 ep@1 {
162 reg = <1>;
163 atmel,fifo-size = <1024>;
164 atmel,nb-banks = <3>;
165 atmel,can-dma;
166 atmel,can-isoc;
167 };
168
169 ep@2 {
170 reg = <2>;
171 atmel,fifo-size = <1024>;
172 atmel,nb-banks = <3>;
173 atmel,can-dma;
174 atmel,can-isoc;
175 };
176
177 ep@3 {
178 reg = <3>;
179 atmel,fifo-size = <1024>;
180 atmel,nb-banks = <2>;
181 atmel,can-dma;
182 atmel,can-isoc;
183 };
184
185 ep@4 {
186 reg = <4>;
187 atmel,fifo-size = <1024>;
188 atmel,nb-banks = <2>;
189 atmel,can-dma;
190 atmel,can-isoc;
191 };
192
193 ep@5 {
194 reg = <5>;
195 atmel,fifo-size = <1024>;
196 atmel,nb-banks = <2>;
197 atmel,can-dma;
198 atmel,can-isoc;
199 };
200
201 ep@6 {
202 reg = <6>;
203 atmel,fifo-size = <1024>;
204 atmel,nb-banks = <2>;
205 atmel,can-dma;
206 atmel,can-isoc;
207 };
208
209 ep@7 {
210 reg = <7>;
211 atmel,fifo-size = <1024>;
212 atmel,nb-banks = <2>;
213 atmel,can-dma;
214 atmel,can-isoc;
215 };
216
217 ep@8 {
218 reg = <8>;
219 atmel,fifo-size = <1024>;
220 atmel,nb-banks = <2>;
221 atmel,can-isoc;
222 };
223
224 ep@9 {
225 reg = <9>;
226 atmel,fifo-size = <1024>;
227 atmel,nb-banks = <2>;
228 atmel,can-isoc;
229 };
230
231 ep@10 {
232 reg = <10>;
233 atmel,fifo-size = <1024>;
234 atmel,nb-banks = <2>;
235 atmel,can-isoc;
236 };
237
238 ep@11 {
239 reg = <11>;
240 atmel,fifo-size = <1024>;
241 atmel,nb-banks = <2>;
242 atmel,can-isoc;
243 };
244
245 ep@12 {
246 reg = <12>;
247 atmel,fifo-size = <1024>;
248 atmel,nb-banks = <2>;
249 atmel,can-isoc;
250 };
251
252 ep@13 {
253 reg = <13>;
254 atmel,fifo-size = <1024>;
255 atmel,nb-banks = <2>;
256 atmel,can-isoc;
257 };
258
259 ep@14 {
260 reg = <14>;
261 atmel,fifo-size = <1024>;
262 atmel,nb-banks = <2>;
263 atmel,can-isoc;
264 };
265
266 ep@15 {
267 reg = <15>;
268 atmel,fifo-size = <1024>;
269 atmel,nb-banks = <2>;
270 atmel,can-isoc;
271 };
272 };
273
274 usb1: ohci@400000 {
275 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
276 reg = <0x00400000 0x100000>;
277 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
278 clocks = <&uhphs_clk>, <&uhphs_clk>, <&uhpck>;
279 clock-names = "ohci_clk", "hclk", "uhpck";
280 status = "disabled";
281 };
282
283 usb2: ehci@500000 {
284 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
285 reg = <0x00500000 0x100000>;
286 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
287 clocks = <&utmi>, <&uhphs_clk>;
288 clock-names = "usb_clk", "ehci_clk";
289 status = "disabled";
290 };
291
292 L2: cache-controller@a00000 {
293 compatible = "arm,pl310-cache";
294 reg = <0x00a00000 0x1000>;
295 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
296 cache-unified;
297 cache-level = <2>;
298 };
299
300 ebi: ebi@10000000 {
301 compatible = "atmel,sama5d3-ebi";
302 #address-cells = <2>;
303 #size-cells = <1>;
304 atmel,smc = <&hsmc>;
305 reg = <0x10000000 0x10000000
306 0x60000000 0x30000000>;
307 ranges = <0x0 0x0 0x10000000 0x10000000
308 0x1 0x0 0x60000000 0x10000000
309 0x2 0x0 0x70000000 0x10000000
310 0x3 0x0 0x80000000 0x10000000>;
311 clocks = <&mck>;
312 status = "disabled";
313
314 nand_controller: nand-controller {
315 compatible = "atmel,sama5d3-nand-controller";
316 atmel,nfc-sram = <&nfc_sram>;
317 atmel,nfc-io = <&nfc_io>;
318 ecc-engine = <&pmecc>;
319 #address-cells = <2>;
320 #size-cells = <1>;
321 ranges;
322 status = "disabled";
323 };
324 };
325
326 nand0: nand@80000000 {
327 compatible = "atmel,sama5d2-nand";
328 #address-cells = <1>;
329 #size-cells = <1>;
330 ranges;
331 reg = < /* EBI CS3 */
332 0x80000000 0x08000000
333 /* SMC PMECC regs */
334 0xf8014070 0x00000490
335 /* SMC PMECC Error Location regs */
336 0xf8014500 0x00000200
337 /* ROM Galois tables */
338 0x00040000 0x00018000
339 >;
340 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
341 atmel,nand-addr-offset = <21>;
342 atmel,nand-cmd-offset = <22>;
343 atmel,nand-has-dma;
344 atmel,has-pmecc;
345 atmel,pmecc-lookup-table-offset = <0x0 0x8000>;
346 status = "disabled";
347
348 nfc@c0000000 {
349 compatible = "atmel,sama5d3-nfc";
350 #address-cells = <1>;
351 #size-cells = <1>;
352 reg = < /* NFC Command Registers */
353 0xc0000000 0x08000000
354 /* NFC HSMC regs */
355 0xf8014000 0x00000070
356 /* NFC SRAM banks */
357 0x00100000 0x00100000
358 >;
359 clocks = <&hsmc_clk>;
360 atmel,write-by-sram;
361 };
362 };
363
364 sdmmc0: sdio-host@a0000000 {
365 compatible = "atmel,sama5d2-sdhci";
366 reg = <0xa0000000 0x300>;
367 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
368 clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
369 clock-names = "hclock", "multclk", "baseclk";
370 status = "disabled";
371 };
372
373 sdmmc1: sdio-host@b0000000 {
374 compatible = "atmel,sama5d2-sdhci";
375 reg = <0xb0000000 0x300>;
376 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
377 clocks = <&sdmmc1_hclk>, <&sdmmc1_gclk>, <&main>;
378 clock-names = "hclock", "multclk", "baseclk";
379 status = "disabled";
380 };
381
382 nfc_io: nfc-io@c0000000 {
383 compatible = "atmel,sama5d3-nfc-io", "syscon";
384 reg = <0xc0000000 0x8000000>;
385 };
386
387 apb {
388 compatible = "simple-bus";
389 #address-cells = <1>;
390 #size-cells = <1>;
391 ranges;
392
393 hlcdc: hlcdc@f0000000 {
394 compatible = "atmel,sama5d2-hlcdc";
395 reg = <0xf0000000 0x2000>;
396 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
397 clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
398 clock-names = "periph_clk","sys_clk", "slow_clk";
399 status = "disabled";
400
401 hlcdc-display-controller {
402 compatible = "atmel,hlcdc-display-controller";
403 #address-cells = <1>;
404 #size-cells = <0>;
405
406 port@0 {
407 #address-cells = <1>;
408 #size-cells = <0>;
409 reg = <0>;
410 };
411 };
412
413 hlcdc_pwm: hlcdc-pwm {
414 compatible = "atmel,hlcdc-pwm";
415 #pwm-cells = <3>;
416 };
417 };
418
419 isc: isc@f0008000 {
420 compatible = "atmel,sama5d2-isc";
421 reg = <0xf0008000 0x4000>;
422 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
423 clocks = <&isc_clk>, <&iscck>, <&isc_gclk>;
424 clock-names = "hclock", "iscck", "gck";
425 #clock-cells = <0>;
426 clock-output-names = "isc-mck";
427 status = "disabled";
428 };
429
430 ramc0: ramc@f000c000 {
431 compatible = "atmel,sama5d3-ddramc";
432 reg = <0xf000c000 0x200>;
433 clocks = <&ddrck>, <&mpddr_clk>;
434 clock-names = "ddrck", "mpddr";
435 };
436
437 dma0: dma-controller@f0010000 {
438 compatible = "atmel,sama5d4-dma";
439 reg = <0xf0010000 0x1000>;
440 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
441 #dma-cells = <1>;
442 clocks = <&dma0_clk>;
443 clock-names = "dma_clk";
444 };
445
446 /* Place dma1 here despite its address */
447 dma1: dma-controller@f0004000 {
448 compatible = "atmel,sama5d4-dma";
449 reg = <0xf0004000 0x1000>;
450 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
451 #dma-cells = <1>;
452 clocks = <&dma1_clk>;
453 clock-names = "dma_clk";
454 };
455
456 pmc: pmc@f0014000 {
457 compatible = "atmel,sama5d2-pmc", "syscon";
458 reg = <0xf0014000 0x160>;
459 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
460 interrupt-controller;
461 #address-cells = <1>;
462 #size-cells = <0>;
463 #interrupt-cells = <1>;
464
465 main_rc_osc: main_rc_osc {
466 compatible = "atmel,at91sam9x5-clk-main-rc-osc";
467 #clock-cells = <0>;
468 interrupt-parent = <&pmc>;
469 interrupts = <AT91_PMC_MOSCRCS>;
470 clock-frequency = <12000000>;
471 clock-accuracy = <100000000>;
472 };
473
474 main_osc: main_osc {
475 compatible = "atmel,at91rm9200-clk-main-osc";
476 #clock-cells = <0>;
477 interrupt-parent = <&pmc>;
478 interrupts = <AT91_PMC_MOSCS>;
479 clocks = <&main_xtal>;
480 };
481
482 main: mainck {
483 compatible = "atmel,at91sam9x5-clk-main";
484 #clock-cells = <0>;
485 interrupt-parent = <&pmc>;
486 interrupts = <AT91_PMC_MOSCSELS>;
487 clocks = <&main_rc_osc &main_osc>;
488 };
489
490 plla: pllack {
491 compatible = "atmel,sama5d3-clk-pll";
492 #clock-cells = <0>;
493 interrupt-parent = <&pmc>;
494 interrupts = <AT91_PMC_LOCKA>;
495 clocks = <&main>;
496 reg = <0>;
497 atmel,clk-input-range = <12000000 12000000>;
498 #atmel,pll-clk-output-range-cells = <4>;
499 atmel,pll-clk-output-ranges = <600000000 1200000000 0 0>;
500 };
501
502 plladiv: plladivck {
503 compatible = "atmel,at91sam9x5-clk-plldiv";
504 #clock-cells = <0>;
505 clocks = <&plla>;
506 };
507
508 audio_pll_frac: audiopll_fracck {
509 compatible = "atmel,sama5d2-clk-audio-pll-frac";
510 #clock-cells = <0>;
511 clocks = <&main>;
512 };
513
514 audio_pll_pad: audiopll_padck {
515 compatible = "atmel,sama5d2-clk-audio-pll-pad";
516 #clock-cells = <0>;
517 clocks = <&audio_pll_frac>;
518 };
519
520 audio_pll_pmc: audiopll_pmcck {
521 compatible = "atmel,sama5d2-clk-audio-pll-pmc";
522 #clock-cells = <0>;
523 clocks = <&audio_pll_frac>;
524 };
525
526 utmi: utmick {
527 compatible = "atmel,at91sam9x5-clk-utmi";
528 #clock-cells = <0>;
529 interrupt-parent = <&pmc>;
530 interrupts = <AT91_PMC_LOCKU>;
531 clocks = <&main>;
532 };
533
534 mck: masterck {
535 compatible = "atmel,at91sam9x5-clk-master";
536 #clock-cells = <0>;
537 interrupt-parent = <&pmc>;
538 interrupts = <AT91_PMC_MCKRDY>;
539 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>;
540 atmel,clk-output-range = <124000000 166000000>;
541 atmel,clk-divisors = <1 2 4 3>;
542 };
543
544 h32ck: h32mxck {
545 #clock-cells = <0>;
546 compatible = "atmel,sama5d4-clk-h32mx";
547 clocks = <&mck>;
548 };
549
550 usb: usbck {
551 compatible = "atmel,at91sam9x5-clk-usb";
552 #clock-cells = <0>;
553 clocks = <&plladiv>, <&utmi>;
554 };
555
556 prog: progck {
557 compatible = "atmel,at91sam9x5-clk-programmable";
558 #address-cells = <1>;
559 #size-cells = <0>;
560 interrupt-parent = <&pmc>;
561 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>;
562
563 prog0: prog0 {
564 #clock-cells = <0>;
565 reg = <0>;
566 interrupts = <AT91_PMC_PCKRDY(0)>;
567 };
568
569 prog1: prog1 {
570 #clock-cells = <0>;
571 reg = <1>;
572 interrupts = <AT91_PMC_PCKRDY(1)>;
573 };
574
575 prog2: prog2 {
576 #clock-cells = <0>;
577 reg = <2>;
578 interrupts = <AT91_PMC_PCKRDY(2)>;
579 };
580 };
581
582 systemck {
583 compatible = "atmel,at91rm9200-clk-system";
584 #address-cells = <1>;
585 #size-cells = <0>;
586
587 ddrck: ddrck {
588 #clock-cells = <0>;
589 reg = <2>;
590 clocks = <&mck>;
591 };
592
593 lcdck: lcdck {
594 #clock-cells = <0>;
595 reg = <3>;
596 clocks = <&mck>;
597 };
598
599 uhpck: uhpck {
600 #clock-cells = <0>;
601 reg = <6>;
602 clocks = <&usb>;
603 };
604
605 udpck: udpck {
606 #clock-cells = <0>;
607 reg = <7>;
608 clocks = <&usb>;
609 };
610
611 pck0: pck0 {
612 #clock-cells = <0>;
613 reg = <8>;
614 clocks = <&prog0>;
615 };
616
617 pck1: pck1 {
618 #clock-cells = <0>;
619 reg = <9>;
620 clocks = <&prog1>;
621 };
622
623 pck2: pck2 {
624 #clock-cells = <0>;
625 reg = <10>;
626 clocks = <&prog2>;
627 };
628
629 iscck: iscck {
630 #clock-cells = <0>;
631 reg = <18>;
632 clocks = <&mck>;
633 };
634 };
635
636 periph32ck {
637 compatible = "atmel,at91sam9x5-clk-peripheral";
638 #address-cells = <1>;
639 #size-cells = <0>;
640 clocks = <&h32ck>;
641
642 macb0_clk: macb0_clk {
643 #clock-cells = <0>;
644 reg = <5>;
645 atmel,clk-output-range = <0 83000000>;
646 };
647
648 tdes_clk: tdes_clk {
649 #clock-cells = <0>;
650 reg = <11>;
651 atmel,clk-output-range = <0 83000000>;
652 };
653
654 matrix1_clk: matrix1_clk {
655 #clock-cells = <0>;
656 reg = <14>;
657 };
658
659 hsmc_clk: hsmc_clk {
660 #clock-cells = <0>;
661 reg = <17>;
662 };
663
664 pioA_clk: pioA_clk {
665 #clock-cells = <0>;
666 reg = <18>;
667 atmel,clk-output-range = <0 83000000>;
668 };
669
670 flx0_clk: flx0_clk {
671 #clock-cells = <0>;
672 reg = <19>;
673 atmel,clk-output-range = <0 83000000>;
674 };
675
676 flx1_clk: flx1_clk {
677 #clock-cells = <0>;
678 reg = <20>;
679 atmel,clk-output-range = <0 83000000>;
680 };
681
682 flx2_clk: flx2_clk {
683 #clock-cells = <0>;
684 reg = <21>;
685 atmel,clk-output-range = <0 83000000>;
686 };
687
688 flx3_clk: flx3_clk {
689 #clock-cells = <0>;
690 reg = <22>;
691 atmel,clk-output-range = <0 83000000>;
692 };
693
694 flx4_clk: flx4_clk {
695 #clock-cells = <0>;
696 reg = <23>;
697 atmel,clk-output-range = <0 83000000>;
698 };
699
700 uart0_clk: uart0_clk {
701 #clock-cells = <0>;
702 reg = <24>;
703 atmel,clk-output-range = <0 83000000>;
704 };
705
706 uart1_clk: uart1_clk {
707 #clock-cells = <0>;
708 reg = <25>;
709 atmel,clk-output-range = <0 83000000>;
710 };
711
712 uart2_clk: uart2_clk {
713 #clock-cells = <0>;
714 reg = <26>;
715 atmel,clk-output-range = <0 83000000>;
716 };
717
718 uart3_clk: uart3_clk {
719 #clock-cells = <0>;
720 reg = <27>;
721 atmel,clk-output-range = <0 83000000>;
722 };
723
724 uart4_clk: uart4_clk {
725 #clock-cells = <0>;
726 reg = <28>;
727 atmel,clk-output-range = <0 83000000>;
728 };
729
730 twi0_clk: twi0_clk {
731 reg = <29>;
732 #clock-cells = <0>;
733 atmel,clk-output-range = <0 83000000>;
734 };
735
736 twi1_clk: twi1_clk {
737 #clock-cells = <0>;
738 reg = <30>;
739 atmel,clk-output-range = <0 83000000>;
740 };
741
742 spi0_clk: spi0_clk {
743 #clock-cells = <0>;
744 reg = <33>;
745 atmel,clk-output-range = <0 83000000>;
746 };
747
748 spi1_clk: spi1_clk {
749 #clock-cells = <0>;
750 reg = <34>;
751 atmel,clk-output-range = <0 83000000>;
752 };
753
754 tcb0_clk: tcb0_clk {
755 #clock-cells = <0>;
756 reg = <35>;
757 atmel,clk-output-range = <0 83000000>;
758 };
759
760 tcb1_clk: tcb1_clk {
761 #clock-cells = <0>;
762 reg = <36>;
763 atmel,clk-output-range = <0 83000000>;
764 };
765
766 pwm_clk: pwm_clk {
767 #clock-cells = <0>;
768 reg = <38>;
769 atmel,clk-output-range = <0 83000000>;
770 };
771
772 adc_clk: adc_clk {
773 #clock-cells = <0>;
774 reg = <40>;
775 atmel,clk-output-range = <0 83000000>;
776 };
777
778 uhphs_clk: uhphs_clk {
779 #clock-cells = <0>;
780 reg = <41>;
781 atmel,clk-output-range = <0 83000000>;
782 };
783
784 udphs_clk: udphs_clk {
785 #clock-cells = <0>;
786 reg = <42>;
787 atmel,clk-output-range = <0 83000000>;
788 };
789
790 ssc0_clk: ssc0_clk {
791 #clock-cells = <0>;
792 reg = <43>;
793 atmel,clk-output-range = <0 83000000>;
794 };
795
796 ssc1_clk: ssc1_clk {
797 #clock-cells = <0>;
798 reg = <44>;
799 atmel,clk-output-range = <0 83000000>;
800 };
801
802 trng_clk: trng_clk {
803 #clock-cells = <0>;
804 reg = <47>;
805 atmel,clk-output-range = <0 83000000>;
806 };
807
808 pdmic_clk: pdmic_clk {
809 #clock-cells = <0>;
810 reg = <48>;
811 atmel,clk-output-range = <0 83000000>;
812 };
813
814 securam_clk: securam_clk {
815 #clock-cells = <0>;
816 reg = <51>;
817 };
818
819 i2s0_clk: i2s0_clk {
820 #clock-cells = <0>;
821 reg = <54>;
822 atmel,clk-output-range = <0 83000000>;
823 };
824
825 i2s1_clk: i2s1_clk {
826 #clock-cells = <0>;
827 reg = <55>;
828 atmel,clk-output-range = <0 83000000>;
829 };
830
831 can0_clk: can0_clk {
832 #clock-cells = <0>;
833 reg = <56>;
834 atmel,clk-output-range = <0 83000000>;
835 };
836
837 can1_clk: can1_clk {
838 #clock-cells = <0>;
839 reg = <57>;
840 atmel,clk-output-range = <0 83000000>;
841 };
842
843 classd_clk: classd_clk {
844 #clock-cells = <0>;
845 reg = <59>;
846 atmel,clk-output-range = <0 83000000>;
847 };
848 };
849
850 periph64ck {
851 compatible = "atmel,at91sam9x5-clk-peripheral";
852 #address-cells = <1>;
853 #size-cells = <0>;
854 clocks = <&mck>;
855
856 dma0_clk: dma0_clk {
857 #clock-cells = <0>;
858 reg = <6>;
859 };
860
861 dma1_clk: dma1_clk {
862 #clock-cells = <0>;
863 reg = <7>;
864 };
865
866 aes_clk: aes_clk {
867 #clock-cells = <0>;
868 reg = <9>;
869 };
870
871 aesb_clk: aesb_clk {
872 #clock-cells = <0>;
873 reg = <10>;
874 };
875
876 sha_clk: sha_clk {
877 #clock-cells = <0>;
878 reg = <12>;
879 };
880
881 mpddr_clk: mpddr_clk {
882 #clock-cells = <0>;
883 reg = <13>;
884 };
885
886 matrix0_clk: matrix0_clk {
887 #clock-cells = <0>;
888 reg = <15>;
889 };
890
891 sdmmc0_hclk: sdmmc0_hclk {
892 #clock-cells = <0>;
893 reg = <31>;
894 };
895
896 sdmmc1_hclk: sdmmc1_hclk {
897 #clock-cells = <0>;
898 reg = <32>;
899 };
900
901 lcdc_clk: lcdc_clk {
902 #clock-cells = <0>;
903 reg = <45>;
904 };
905
906 isc_clk: isc_clk {
907 #clock-cells = <0>;
908 reg = <46>;
909 };
910
911 qspi0_clk: qspi0_clk {
912 #clock-cells = <0>;
913 reg = <52>;
914 };
915
916 qspi1_clk: qspi1_clk {
917 #clock-cells = <0>;
918 reg = <53>;
919 };
920 };
921
922 gck {
923 compatible = "atmel,sama5d2-clk-generated";
924 #address-cells = <1>;
925 #size-cells = <0>;
926 interrupt-parent = <&pmc>;
927 clocks = <&clk32k>, <&main>, <&plladiv>, <&utmi>, <&mck>, <&audio_pll_pmc>;
928
929 sdmmc0_gclk: sdmmc0_gclk {
930 #clock-cells = <0>;
931 reg = <31>;
932 };
933
934 sdmmc1_gclk: sdmmc1_gclk {
935 #clock-cells = <0>;
936 reg = <32>;
937 };
938
939 tcb0_gclk: tcb0_gclk {
940 #clock-cells = <0>;
941 reg = <35>;
942 atmel,clk-output-range = <0 83000000>;
943 };
944
945 tcb1_gclk: tcb1_gclk {
946 #clock-cells = <0>;
947 reg = <36>;
948 atmel,clk-output-range = <0 83000000>;
949 };
950
951 pwm_gclk: pwm_gclk {
952 #clock-cells = <0>;
953 reg = <38>;
954 atmel,clk-output-range = <0 83000000>;
955 };
956
957 isc_gclk: isc_gclk {
958 #clock-cells = <0>;
959 reg = <46>;
960 };
961
962 pdmic_gclk: pdmic_gclk {
963 #clock-cells = <0>;
964 reg = <48>;
965 };
966
967 i2s0_gclk: i2s0_gclk {
968 #clock-cells = <0>;
969 reg = <54>;
970 };
971
972 i2s1_gclk: i2s1_gclk {
973 #clock-cells = <0>;
974 reg = <55>;
975 };
976
977 can0_gclk: can0_gclk {
978 #clock-cells = <0>;
979 reg = <56>;
980 atmel,clk-output-range = <0 80000000>;
981 };
982
983 can1_gclk: can1_gclk {
984 #clock-cells = <0>;
985 reg = <57>;
986 atmel,clk-output-range = <0 80000000>;
987 };
988
989 classd_gclk: classd_gclk {
990 #clock-cells = <0>;
991 reg = <59>;
992 atmel,clk-output-range = <0 100000000>;
993 };
994 };
995 };
996
997 qspi0: spi@f0020000 {
998 compatible = "atmel,sama5d2-qspi";
999 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
1000 reg-names = "qspi_base", "qspi_mmap";
1001 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
1002 clocks = <&qspi0_clk>;
1003 #address-cells = <1>;
1004 #size-cells = <0>;
1005 status = "disabled";
1006 };
1007
1008 qspi1: spi@f0024000 {
1009 compatible = "atmel,sama5d2-qspi";
1010 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
1011 reg-names = "qspi_base", "qspi_mmap";
1012 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
1013 clocks = <&qspi1_clk>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1016 status = "disabled";
1017 };
1018
1019 sha@f0028000 {
1020 compatible = "atmel,at91sam9g46-sha";
1021 reg = <0xf0028000 0x100>;
1022 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
1023 dmas = <&dma0
1024 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1025 AT91_XDMAC_DT_PERID(30))>;
1026 dma-names = "tx";
1027 clocks = <&sha_clk>;
1028 clock-names = "sha_clk";
1029 status = "okay";
1030 };
1031
1032 aes@f002c000 {
1033 compatible = "atmel,at91sam9g46-aes";
1034 reg = <0xf002c000 0x100>;
1035 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
1036 dmas = <&dma0
1037 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1038 AT91_XDMAC_DT_PERID(26))>,
1039 <&dma0
1040 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1041 AT91_XDMAC_DT_PERID(27))>;
1042 dma-names = "tx", "rx";
1043 clocks = <&aes_clk>;
1044 clock-names = "aes_clk";
1045 status = "okay";
1046 };
1047
1048 spi0: spi@f8000000 {
1049 compatible = "atmel,at91rm9200-spi";
1050 reg = <0xf8000000 0x100>;
1051 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
1052 dmas = <&dma0
1053 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1054 AT91_XDMAC_DT_PERID(6))>,
1055 <&dma0
1056 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1057 AT91_XDMAC_DT_PERID(7))>;
1058 dma-names = "tx", "rx";
1059 clocks = <&spi0_clk>;
1060 clock-names = "spi_clk";
1061 atmel,fifo-size = <16>;
1062 #address-cells = <1>;
1063 #size-cells = <0>;
1064 status = "disabled";
1065 };
1066
1067 ssc0: ssc@f8004000 {
1068 compatible = "atmel,at91sam9g45-ssc";
1069 reg = <0xf8004000 0x4000>;
1070 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
1071 dmas = <&dma0
1072 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1073 AT91_XDMAC_DT_PERID(21))>,
1074 <&dma0
1075 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1076 AT91_XDMAC_DT_PERID(22))>;
1077 dma-names = "tx", "rx";
1078 clocks = <&ssc0_clk>;
1079 clock-names = "pclk";
1080 status = "disabled";
1081 };
1082
1083 macb0: ethernet@f8008000 {
1084 compatible = "atmel,sama5d2-gem";
1085 reg = <0xf8008000 0x1000>;
1086 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
1087 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
1088 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
1089 #address-cells = <1>;
1090 #size-cells = <0>;
1091 clocks = <&macb0_clk>, <&macb0_clk>;
1092 clock-names = "hclk", "pclk";
1093 status = "disabled";
1094 };
1095
1096 tcb0: timer@f800c000 {
1097 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
1098 #address-cells = <1>;
1099 #size-cells = <0>;
1100 reg = <0xf800c000 0x100>;
1101 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
1102 clocks = <&tcb0_clk>, <&clk32k>;
1103 clock-names = "t0_clk", "slow_clk";
1104 };
1105
1106 tcb1: timer@f8010000 {
1107 compatible = "atmel,at91sam9x5-tcb", "simple-mfd", "syscon";
1108 #address-cells = <1>;
1109 #size-cells = <0>;
1110 reg = <0xf8010000 0x100>;
1111 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
1112 clocks = <&tcb1_clk>, <&clk32k>;
1113 clock-names = "t0_clk", "slow_clk";
1114 };
1115
1116 hsmc: hsmc@f8014000 {
1117 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
1118 reg = <0xf8014000 0x1000>;
1119 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
1120 clocks = <&hsmc_clk>;
1121 #address-cells = <1>;
1122 #size-cells = <1>;
1123 ranges;
1124
1125 pmecc: ecc-engine@f8014070 {
1126 compatible = "atmel,sama5d2-pmecc";
1127 reg = <0xf8014070 0x490>,
1128 <0xf8014500 0x100>;
1129 };
1130 };
1131
1132 pdmic: pdmic@f8018000 {
1133 compatible = "atmel,sama5d2-pdmic";
1134 reg = <0xf8018000 0x124>;
1135 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
1136 dmas = <&dma0
1137 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
1138 | AT91_XDMAC_DT_PERID(50))>;
1139 dma-names = "rx";
1140 clocks = <&pdmic_clk>, <&pdmic_gclk>;
1141 clock-names = "pclk", "gclk";
1142 status = "disabled";
1143 };
1144
1145 uart0: serial@f801c000 {
1146 compatible = "atmel,at91sam9260-usart";
1147 reg = <0xf801c000 0x100>;
1148 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
1149 dmas = <&dma0
1150 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1151 AT91_XDMAC_DT_PERID(35))>,
1152 <&dma0
1153 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1154 AT91_XDMAC_DT_PERID(36))>;
1155 dma-names = "tx", "rx";
1156 clocks = <&uart0_clk>;
1157 clock-names = "usart";
1158 status = "disabled";
1159 };
1160
1161 uart1: serial@f8020000 {
1162 compatible = "atmel,at91sam9260-usart";
1163 reg = <0xf8020000 0x100>;
1164 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
1165 dmas = <&dma0
1166 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1167 AT91_XDMAC_DT_PERID(37))>,
1168 <&dma0
1169 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1170 AT91_XDMAC_DT_PERID(38))>;
1171 dma-names = "tx", "rx";
1172 clocks = <&uart1_clk>;
1173 clock-names = "usart";
1174 status = "disabled";
1175 };
1176
1177 uart2: serial@f8024000 {
1178 compatible = "atmel,at91sam9260-usart";
1179 reg = <0xf8024000 0x100>;
1180 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
1181 dmas = <&dma0
1182 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1183 AT91_XDMAC_DT_PERID(39))>,
1184 <&dma0
1185 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1186 AT91_XDMAC_DT_PERID(40))>;
1187 dma-names = "tx", "rx";
1188 clocks = <&uart2_clk>;
1189 clock-names = "usart";
1190 status = "disabled";
1191 };
1192
1193 i2c0: i2c@f8028000 {
1194 compatible = "atmel,sama5d2-i2c";
1195 reg = <0xf8028000 0x100>;
1196 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
1197 dmas = <&dma0
1198 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1199 AT91_XDMAC_DT_PERID(0))>,
1200 <&dma0
1201 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1202 AT91_XDMAC_DT_PERID(1))>;
1203 dma-names = "tx", "rx";
1204 #address-cells = <1>;
1205 #size-cells = <0>;
1206 clocks = <&twi0_clk>;
1207 atmel,fifo-size = <16>;
1208 status = "disabled";
1209 };
1210
1211 pwm0: pwm@f802c000 {
1212 compatible = "atmel,sama5d2-pwm";
1213 reg = <0xf802c000 0x4000>;
1214 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
1215 #pwm-cells = <3>;
1216 clocks = <&pwm_clk>;
1217 };
1218
1219 sfr: sfr@f8030000 {
1220 compatible = "atmel,sama5d2-sfr", "syscon";
1221 reg = <0xf8030000 0x98>;
1222 };
1223
1224 flx0: flexcom@f8034000 {
1225 compatible = "atmel,sama5d2-flexcom";
1226 reg = <0xf8034000 0x200>;
1227 clocks = <&flx0_clk>;
1228 #address-cells = <1>;
1229 #size-cells = <1>;
1230 ranges = <0x0 0xf8034000 0x800>;
1231 status = "disabled";
1232 };
1233
1234 flx1: flexcom@f8038000 {
1235 compatible = "atmel,sama5d2-flexcom";
1236 reg = <0xf8038000 0x200>;
1237 clocks = <&flx1_clk>;
1238 #address-cells = <1>;
1239 #size-cells = <1>;
1240 ranges = <0x0 0xf8038000 0x800>;
1241 status = "disabled";
1242 };
1243
1244 securam: sram@f8044000 {
1245 compatible = "atmel,sama5d2-securam", "mmio-sram";
1246 reg = <0xf8044000 0x1420>;
1247 clocks = <&securam_clk>;
1248 #address-cells = <1>;
1249 #size-cells = <1>;
1250 ranges = <0 0xf8044000 0x1420>;
1251 };
1252
1253 rstc@f8048000 {
1254 compatible = "atmel,sama5d3-rstc";
1255 reg = <0xf8048000 0x10>;
1256 clocks = <&clk32k>;
1257 };
1258
1259 shdwc@f8048010 {
1260 compatible = "atmel,sama5d2-shdwc";
1261 reg = <0xf8048010 0x10>;
1262 clocks = <&clk32k>;
1263 #address-cells = <1>;
1264 #size-cells = <0>;
1265 atmel,wakeup-rtc-timer;
1266 };
1267
1268 pit: timer@f8048030 {
1269 compatible = "atmel,at91sam9260-pit";
1270 reg = <0xf8048030 0x10>;
1271 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
1272 clocks = <&h32ck>;
1273 };
1274
1275 watchdog@f8048040 {
1276 compatible = "atmel,sama5d4-wdt";
1277 reg = <0xf8048040 0x10>;
1278 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
1279 clocks = <&clk32k>;
1280 status = "disabled";
1281 };
1282
1283 clk32k: sckc@f8048050 {
1284 compatible = "atmel,sama5d4-sckc";
1285 reg = <0xf8048050 0x4>;
1286
1287 clocks = <&slow_xtal>;
1288 #clock-cells = <0>;
1289 };
1290
1291 rtc@f80480b0 {
1292 compatible = "atmel,at91rm9200-rtc";
1293 reg = <0xf80480b0 0x30>;
1294 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
1295 clocks = <&clk32k>;
1296 };
1297
1298 can0: can@f8054000 {
1299 compatible = "bosch,m_can";
1300 reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
1301 reg-names = "m_can", "message_ram";
1302 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
1303 <64 IRQ_TYPE_LEVEL_HIGH 7>;
1304 interrupt-names = "int0", "int1";
1305 clocks = <&can0_clk>, <&can0_gclk>;
1306 clock-names = "hclk", "cclk";
1307 assigned-clocks = <&can0_gclk>;
1308 assigned-clock-parents = <&utmi>;
1309 assigned-clock-rates = <40000000>;
1310 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
1311 status = "disabled";
1312 };
1313
1314 spi1: spi@fc000000 {
1315 compatible = "atmel,at91rm9200-spi";
1316 reg = <0xfc000000 0x100>;
1317 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
1318 dmas = <&dma0
1319 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1320 AT91_XDMAC_DT_PERID(8))>,
1321 <&dma0
1322 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1323 AT91_XDMAC_DT_PERID(9))>;
1324 dma-names = "tx", "rx";
1325 clocks = <&spi1_clk>;
1326 clock-names = "spi_clk";
1327 atmel,fifo-size = <16>;
1328 #address-cells = <1>;
1329 #size-cells = <0>;
1330 status = "disabled";
1331 };
1332
1333 uart3: serial@fc008000 {
1334 compatible = "atmel,at91sam9260-usart";
1335 reg = <0xfc008000 0x100>;
1336 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
1337 dmas = <&dma1
1338 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1339 AT91_XDMAC_DT_PERID(41))>,
1340 <&dma1
1341 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1342 AT91_XDMAC_DT_PERID(42))>;
1343 dma-names = "tx", "rx";
1344 clocks = <&uart3_clk>;
1345 clock-names = "usart";
1346 status = "disabled";
1347 };
1348
1349 uart4: serial@fc00c000 {
1350 compatible = "atmel,at91sam9260-usart";
1351 reg = <0xfc00c000 0x100>;
1352 dmas = <&dma0
1353 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1354 AT91_XDMAC_DT_PERID(43))>,
1355 <&dma0
1356 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1357 AT91_XDMAC_DT_PERID(44))>;
1358 dma-names = "tx", "rx";
1359 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
1360 clocks = <&uart4_clk>;
1361 clock-names = "usart";
1362 status = "disabled";
1363 };
1364
1365 flx2: flexcom@fc010000 {
1366 compatible = "atmel,sama5d2-flexcom";
1367 reg = <0xfc010000 0x200>;
1368 clocks = <&flx2_clk>;
1369 #address-cells = <1>;
1370 #size-cells = <1>;
1371 ranges = <0x0 0xfc010000 0x800>;
1372 status = "disabled";
1373 };
1374
1375 flx3: flexcom@fc014000 {
1376 compatible = "atmel,sama5d2-flexcom";
1377 reg = <0xfc014000 0x200>;
1378 clocks = <&flx3_clk>;
1379 #address-cells = <1>;
1380 #size-cells = <1>;
1381 ranges = <0x0 0xfc014000 0x800>;
1382 status = "disabled";
1383 };
1384
1385 flx4: flexcom@fc018000 {
1386 compatible = "atmel,sama5d2-flexcom";
1387 reg = <0xfc018000 0x200>;
1388 clocks = <&flx4_clk>;
1389 #address-cells = <1>;
1390 #size-cells = <1>;
1391 ranges = <0x0 0xfc018000 0x800>;
1392 status = "disabled";
1393 };
1394
1395 trng@fc01c000 {
1396 compatible = "atmel,at91sam9g45-trng";
1397 reg = <0xfc01c000 0x100>;
1398 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
1399 clocks = <&trng_clk>;
1400 };
1401
1402 aic: interrupt-controller@fc020000 {
1403 #interrupt-cells = <3>;
1404 compatible = "atmel,sama5d2-aic";
1405 interrupt-controller;
1406 reg = <0xfc020000 0x200>;
1407 atmel,external-irqs = <49>;
1408 };
1409
1410 i2c1: i2c@fc028000 {
1411 compatible = "atmel,sama5d2-i2c";
1412 reg = <0xfc028000 0x100>;
1413 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1414 dmas = <&dma0
1415 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1416 AT91_XDMAC_DT_PERID(2))>,
1417 <&dma0
1418 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1419 AT91_XDMAC_DT_PERID(3))>;
1420 dma-names = "tx", "rx";
1421 #address-cells = <1>;
1422 #size-cells = <0>;
1423 clocks = <&twi1_clk>;
1424 atmel,fifo-size = <16>;
1425 status = "disabled";
1426 };
1427
1428 adc: adc@fc030000 {
1429 compatible = "atmel,sama5d2-adc";
1430 reg = <0xfc030000 0x100>;
1431 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1432 clocks = <&adc_clk>;
1433 clock-names = "adc_clk";
1434 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1435 dma-names = "rx";
1436 atmel,min-sample-rate-hz = <200000>;
1437 atmel,max-sample-rate-hz = <20000000>;
1438 atmel,startup-time-ms = <4>;
1439 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1440 status = "disabled";
1441 };
1442
1443 pioA: pinctrl@fc038000 {
1444 compatible = "atmel,sama5d2-pinctrl";
1445 reg = <0xfc038000 0x600>;
1446 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1447 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1448 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1449 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1450 interrupt-controller;
1451 #interrupt-cells = <2>;
1452 gpio-controller;
1453 #gpio-cells = <2>;
1454 clocks = <&pioA_clk>;
1455 };
1456
1457 secumod@fc040000 {
1458 compatible = "atmel,sama5d2-secumod", "syscon";
1459 reg = <0xfc040000 0x100>;
1460 };
1461
1462 tdes@fc044000 {
1463 compatible = "atmel,at91sam9g46-tdes";
1464 reg = <0xfc044000 0x100>;
1465 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1466 dmas = <&dma0
1467 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1468 AT91_XDMAC_DT_PERID(28))>,
1469 <&dma0
1470 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1471 AT91_XDMAC_DT_PERID(29))>;
1472 dma-names = "tx", "rx";
1473 clocks = <&tdes_clk>;
1474 clock-names = "tdes_clk";
1475 status = "okay";
1476 };
1477
1478 classd: classd@fc048000 {
1479 compatible = "atmel,sama5d2-classd";
1480 reg = <0xfc048000 0x100>;
1481 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
1482 dmas = <&dma0
1483 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1484 AT91_XDMAC_DT_PERID(47))>;
1485 dma-names = "tx";
1486 clocks = <&classd_clk>, <&classd_gclk>;
1487 clock-names = "pclk", "gclk";
1488 status = "disabled";
1489 };
1490
1491 can1: can@fc050000 {
1492 compatible = "bosch,m_can";
1493 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
1494 reg-names = "m_can", "message_ram";
1495 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
1496 <65 IRQ_TYPE_LEVEL_HIGH 7>;
1497 interrupt-names = "int0", "int1";
1498 clocks = <&can1_clk>, <&can1_gclk>;
1499 clock-names = "hclk", "cclk";
1500 assigned-clocks = <&can1_gclk>;
1501 assigned-clock-parents = <&utmi>;
1502 assigned-clock-rates = <40000000>;
1503 bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
1504 status = "disabled";
1505 };
1506
1507 sfrbu: sfr@fc05c000 {
1508 compatible = "atmel,sama5d2-sfrbu", "syscon";
1509 reg = <0xfc05c000 0x20>;
1510 };
1511
1512 chipid@fc069000 {
1513 compatible = "atmel,sama5d2-chipid";
1514 reg = <0xfc069000 0x8>;
1515 };
1516 };
1517 };
1518};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * sama5d2.dtsi - Device Tree Include file for SAMA5D2 family SoC
4 *
5 * Copyright (C) 2015 Atmel,
6 * 2015 Ludovic Desroches <ludovic.desroches@atmel.com>
7 */
8
9#include <dt-bindings/dma/at91.h>
10#include <dt-bindings/interrupt-controller/irq.h>
11#include <dt-bindings/clock/at91.h>
12#include <dt-bindings/iio/adc/at91-sama5d2_adc.h>
13
14/ {
15 #address-cells = <1>;
16 #size-cells = <1>;
17 model = "Atmel SAMA5D2 family SoC";
18 compatible = "atmel,sama5d2";
19 interrupt-parent = <&aic>;
20
21 aliases {
22 serial0 = &uart1;
23 serial1 = &uart3;
24 };
25
26 cpus {
27 #address-cells = <1>;
28 #size-cells = <0>;
29
30 cpu@0 {
31 device_type = "cpu";
32 compatible = "arm,cortex-a5";
33 reg = <0>;
34 next-level-cache = <&L2>;
35 };
36 };
37
38 pmu {
39 compatible = "arm,cortex-a5-pmu";
40 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 0>;
41 };
42
43 etb {
44 compatible = "arm,coresight-etb10", "arm,primecell";
45 reg = <0x740000 0x1000>;
46
47 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
48 clock-names = "apb_pclk";
49
50 in-ports {
51 port {
52 etb_in: endpoint {
53 remote-endpoint = <&etm_out>;
54 };
55 };
56 };
57 };
58
59 etm {
60 compatible = "arm,coresight-etm3x", "arm,primecell";
61 reg = <0x73C000 0x1000>;
62
63 clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
64 clock-names = "apb_pclk";
65
66 out-ports {
67 port {
68 etm_out: endpoint {
69 remote-endpoint = <&etb_in>;
70 };
71 };
72 };
73 };
74
75 memory {
76 device_type = "memory";
77 reg = <0x20000000 0x20000000>;
78 };
79
80 clocks {
81 slow_xtal: slow_xtal {
82 compatible = "fixed-clock";
83 #clock-cells = <0>;
84 clock-frequency = <0>;
85 };
86
87 main_xtal: main_xtal {
88 compatible = "fixed-clock";
89 #clock-cells = <0>;
90 clock-frequency = <0>;
91 };
92 };
93
94 ns_sram: sram@200000 {
95 compatible = "mmio-sram";
96 reg = <0x00200000 0x20000>;
97 };
98
99 ahb {
100 compatible = "simple-bus";
101 #address-cells = <1>;
102 #size-cells = <1>;
103 ranges;
104
105 nfc_sram: sram@100000 {
106 compatible = "mmio-sram";
107 no-memory-wc;
108 reg = <0x00100000 0x2400>;
109 };
110
111 usb0: gadget@300000 {
112 compatible = "atmel,sama5d3-udc";
113 reg = <0x00300000 0x100000
114 0xfc02c000 0x400>;
115 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 2>;
116 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_CORE PMC_UTMI>;
117 clock-names = "pclk", "hclk";
118 status = "disabled";
119 };
120
121 usb1: ohci@400000 {
122 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
123 reg = <0x00400000 0x100000>;
124 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
125 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_PERIPHERAL 41>, <&pmc PMC_TYPE_SYSTEM 6>;
126 clock-names = "ohci_clk", "hclk", "uhpck";
127 status = "disabled";
128 };
129
130 usb2: ehci@500000 {
131 compatible = "atmel,at91sam9g45-ehci", "usb-ehci";
132 reg = <0x00500000 0x100000>;
133 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 2>;
134 clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_PERIPHERAL 41>;
135 clock-names = "usb_clk", "ehci_clk";
136 status = "disabled";
137 };
138
139 L2: cache-controller@a00000 {
140 compatible = "arm,pl310-cache";
141 reg = <0x00a00000 0x1000>;
142 interrupts = <63 IRQ_TYPE_LEVEL_HIGH 4>;
143 cache-unified;
144 cache-level = <2>;
145 };
146
147 ebi: ebi@10000000 {
148 compatible = "atmel,sama5d3-ebi";
149 #address-cells = <2>;
150 #size-cells = <1>;
151 atmel,smc = <&hsmc>;
152 reg = <0x10000000 0x10000000
153 0x60000000 0x30000000>;
154 ranges = <0x0 0x0 0x10000000 0x10000000
155 0x1 0x0 0x60000000 0x10000000
156 0x2 0x0 0x70000000 0x10000000
157 0x3 0x0 0x80000000 0x10000000>;
158 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
159 status = "disabled";
160
161 nand_controller: nand-controller {
162 compatible = "atmel,sama5d3-nand-controller";
163 atmel,nfc-sram = <&nfc_sram>;
164 atmel,nfc-io = <&nfc_io>;
165 ecc-engine = <&pmecc>;
166 #address-cells = <2>;
167 #size-cells = <1>;
168 ranges;
169 status = "disabled";
170 };
171 };
172
173 sdmmc0: sdio-host@a0000000 {
174 compatible = "atmel,sama5d2-sdhci";
175 reg = <0xa0000000 0x300>;
176 interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
177 clocks = <&pmc PMC_TYPE_PERIPHERAL 31>, <&pmc PMC_TYPE_GCK 31>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
178 clock-names = "hclock", "multclk", "baseclk";
179 assigned-clocks = <&pmc PMC_TYPE_GCK 31>;
180 assigned-clock-rates = <480000000>;
181 status = "disabled";
182 };
183
184 sdmmc1: sdio-host@b0000000 {
185 compatible = "atmel,sama5d2-sdhci";
186 reg = <0xb0000000 0x300>;
187 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 0>;
188 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>, <&pmc PMC_TYPE_GCK 32>, <&pmc PMC_TYPE_CORE PMC_MAIN>;
189 clock-names = "hclock", "multclk", "baseclk";
190 assigned-clocks = <&pmc PMC_TYPE_GCK 32>;
191 assigned-clock-rates = <480000000>;
192 status = "disabled";
193 };
194
195 nfc_io: nfc-io@c0000000 {
196 compatible = "atmel,sama5d3-nfc-io", "syscon";
197 reg = <0xc0000000 0x8000000>;
198 };
199
200 apb {
201 compatible = "simple-bus";
202 #address-cells = <1>;
203 #size-cells = <1>;
204 ranges;
205
206 hlcdc: hlcdc@f0000000 {
207 compatible = "atmel,sama5d2-hlcdc";
208 reg = <0xf0000000 0x2000>;
209 interrupts = <45 IRQ_TYPE_LEVEL_HIGH 0>;
210 clocks = <&pmc PMC_TYPE_PERIPHERAL 45>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
211 clock-names = "periph_clk","sys_clk", "slow_clk";
212 status = "disabled";
213
214 hlcdc-display-controller {
215 compatible = "atmel,hlcdc-display-controller";
216 #address-cells = <1>;
217 #size-cells = <0>;
218
219 port@0 {
220 #address-cells = <1>;
221 #size-cells = <0>;
222 reg = <0>;
223 };
224 };
225
226 hlcdc_pwm: hlcdc-pwm {
227 compatible = "atmel,hlcdc-pwm";
228 #pwm-cells = <3>;
229 };
230 };
231
232 isc: isc@f0008000 {
233 compatible = "atmel,sama5d2-isc";
234 reg = <0xf0008000 0x4000>;
235 interrupts = <46 IRQ_TYPE_LEVEL_HIGH 5>;
236 clocks = <&pmc PMC_TYPE_PERIPHERAL 46>, <&pmc PMC_TYPE_SYSTEM 18>, <&pmc PMC_TYPE_GCK 46>;
237 clock-names = "hclock", "iscck", "gck";
238 #clock-cells = <0>;
239 clock-output-names = "isc-mck";
240 status = "disabled";
241 };
242
243 ramc0: ramc@f000c000 {
244 compatible = "atmel,sama5d3-ddramc";
245 reg = <0xf000c000 0x200>;
246 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 13>;
247 clock-names = "ddrck", "mpddr";
248 };
249
250 dma0: dma-controller@f0010000 {
251 compatible = "atmel,sama5d4-dma";
252 reg = <0xf0010000 0x1000>;
253 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 0>;
254 #dma-cells = <1>;
255 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
256 clock-names = "dma_clk";
257 };
258
259 /* Place dma1 here despite its address */
260 dma1: dma-controller@f0004000 {
261 compatible = "atmel,sama5d4-dma";
262 reg = <0xf0004000 0x1000>;
263 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 0>;
264 #dma-cells = <1>;
265 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
266 clock-names = "dma_clk";
267 };
268
269 pmc: pmc@f0014000 {
270 compatible = "atmel,sama5d2-pmc", "syscon";
271 reg = <0xf0014000 0x160>;
272 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
273 #clock-cells = <2>;
274 clocks = <&clk32k>, <&main_xtal>;
275 clock-names = "slow_clk", "main_xtal";
276 };
277
278 qspi0: spi@f0020000 {
279 compatible = "atmel,sama5d2-qspi";
280 reg = <0xf0020000 0x100>, <0xd0000000 0x08000000>;
281 reg-names = "qspi_base", "qspi_mmap";
282 interrupts = <52 IRQ_TYPE_LEVEL_HIGH 7>;
283 clocks = <&pmc PMC_TYPE_PERIPHERAL 52>;
284 #address-cells = <1>;
285 #size-cells = <0>;
286 status = "disabled";
287 };
288
289 qspi1: spi@f0024000 {
290 compatible = "atmel,sama5d2-qspi";
291 reg = <0xf0024000 0x100>, <0xd8000000 0x08000000>;
292 reg-names = "qspi_base", "qspi_mmap";
293 interrupts = <53 IRQ_TYPE_LEVEL_HIGH 7>;
294 clocks = <&pmc PMC_TYPE_PERIPHERAL 53>;
295 #address-cells = <1>;
296 #size-cells = <0>;
297 status = "disabled";
298 };
299
300 sha@f0028000 {
301 compatible = "atmel,at91sam9g46-sha";
302 reg = <0xf0028000 0x100>;
303 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
304 dmas = <&dma0
305 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
306 AT91_XDMAC_DT_PERID(30))>;
307 dma-names = "tx";
308 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
309 clock-names = "sha_clk";
310 status = "okay";
311 };
312
313 aes@f002c000 {
314 compatible = "atmel,at91sam9g46-aes";
315 reg = <0xf002c000 0x100>;
316 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 0>;
317 dmas = <&dma0
318 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
319 AT91_XDMAC_DT_PERID(26))>,
320 <&dma0
321 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
322 AT91_XDMAC_DT_PERID(27))>;
323 dma-names = "tx", "rx";
324 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
325 clock-names = "aes_clk";
326 status = "okay";
327 };
328
329 spi0: spi@f8000000 {
330 compatible = "atmel,at91rm9200-spi";
331 reg = <0xf8000000 0x100>;
332 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>;
333 dmas = <&dma0
334 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
335 AT91_XDMAC_DT_PERID(6))>,
336 <&dma0
337 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
338 AT91_XDMAC_DT_PERID(7))>;
339 dma-names = "tx", "rx";
340 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>;
341 clock-names = "spi_clk";
342 atmel,fifo-size = <16>;
343 #address-cells = <1>;
344 #size-cells = <0>;
345 status = "disabled";
346 };
347
348 ssc0: ssc@f8004000 {
349 compatible = "atmel,at91sam9g45-ssc";
350 reg = <0xf8004000 0x4000>;
351 interrupts = <43 IRQ_TYPE_LEVEL_HIGH 4>;
352 dmas = <&dma0
353 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
354 AT91_XDMAC_DT_PERID(21))>,
355 <&dma0
356 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
357 AT91_XDMAC_DT_PERID(22))>;
358 dma-names = "tx", "rx";
359 clocks = <&pmc PMC_TYPE_PERIPHERAL 43>;
360 clock-names = "pclk";
361 status = "disabled";
362 };
363
364 macb0: ethernet@f8008000 {
365 compatible = "atmel,sama5d2-gem";
366 reg = <0xf8008000 0x1000>;
367 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 0 */
368 66 IRQ_TYPE_LEVEL_HIGH 3 /* Queue 1 */
369 67 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 2 */
370 #address-cells = <1>;
371 #size-cells = <0>;
372 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&pmc PMC_TYPE_PERIPHERAL 5>;
373 clock-names = "hclk", "pclk";
374 status = "disabled";
375 };
376
377 tcb0: timer@f800c000 {
378 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
379 #address-cells = <1>;
380 #size-cells = <0>;
381 reg = <0xf800c000 0x100>;
382 interrupts = <35 IRQ_TYPE_LEVEL_HIGH 0>;
383 clocks = <&pmc PMC_TYPE_PERIPHERAL 35>, <&pmc PMC_TYPE_GCK 35>, <&clk32k>;
384 clock-names = "t0_clk", "gclk", "slow_clk";
385 };
386
387 tcb1: timer@f8010000 {
388 compatible = "atmel,sama5d2-tcb", "simple-mfd", "syscon";
389 #address-cells = <1>;
390 #size-cells = <0>;
391 reg = <0xf8010000 0x100>;
392 interrupts = <36 IRQ_TYPE_LEVEL_HIGH 0>;
393 clocks = <&pmc PMC_TYPE_PERIPHERAL 36>, <&pmc PMC_TYPE_GCK 36>, <&clk32k>;
394 clock-names = "t0_clk", "gclk", "slow_clk";
395 };
396
397 hsmc: hsmc@f8014000 {
398 compatible = "atmel,sama5d2-smc", "syscon", "simple-mfd";
399 reg = <0xf8014000 0x1000>;
400 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 6>;
401 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>;
402 #address-cells = <1>;
403 #size-cells = <1>;
404 ranges;
405
406 pmecc: ecc-engine@f8014070 {
407 compatible = "atmel,sama5d2-pmecc";
408 reg = <0xf8014070 0x490>,
409 <0xf8014500 0x100>;
410 };
411 };
412
413 pdmic: pdmic@f8018000 {
414 compatible = "atmel,sama5d2-pdmic";
415 reg = <0xf8018000 0x124>;
416 interrupts = <48 IRQ_TYPE_LEVEL_HIGH 7>;
417 dmas = <&dma0
418 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1)
419 | AT91_XDMAC_DT_PERID(50))>;
420 dma-names = "rx";
421 clocks = <&pmc PMC_TYPE_PERIPHERAL 48>, <&pmc PMC_TYPE_GCK 48>;
422 clock-names = "pclk", "gclk";
423 status = "disabled";
424 };
425
426 uart0: serial@f801c000 {
427 compatible = "atmel,at91sam9260-usart";
428 reg = <0xf801c000 0x100>;
429 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 7>;
430 dmas = <&dma0
431 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
432 AT91_XDMAC_DT_PERID(35))>,
433 <&dma0
434 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
435 AT91_XDMAC_DT_PERID(36))>;
436 dma-names = "tx", "rx";
437 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
438 clock-names = "usart";
439 status = "disabled";
440 };
441
442 uart1: serial@f8020000 {
443 compatible = "atmel,at91sam9260-usart";
444 reg = <0xf8020000 0x100>;
445 interrupts = <25 IRQ_TYPE_LEVEL_HIGH 7>;
446 dmas = <&dma0
447 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
448 AT91_XDMAC_DT_PERID(37))>,
449 <&dma0
450 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
451 AT91_XDMAC_DT_PERID(38))>;
452 dma-names = "tx", "rx";
453 clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
454 clock-names = "usart";
455 status = "disabled";
456 };
457
458 uart2: serial@f8024000 {
459 compatible = "atmel,at91sam9260-usart";
460 reg = <0xf8024000 0x100>;
461 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 7>;
462 dmas = <&dma0
463 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
464 AT91_XDMAC_DT_PERID(39))>,
465 <&dma0
466 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
467 AT91_XDMAC_DT_PERID(40))>;
468 dma-names = "tx", "rx";
469 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>;
470 clock-names = "usart";
471 status = "disabled";
472 };
473
474 i2c0: i2c@f8028000 {
475 compatible = "atmel,sama5d2-i2c";
476 reg = <0xf8028000 0x100>;
477 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 7>;
478 dmas = <&dma0
479 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
480 AT91_XDMAC_DT_PERID(0))>,
481 <&dma0
482 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
483 AT91_XDMAC_DT_PERID(1))>;
484 dma-names = "tx", "rx";
485 #address-cells = <1>;
486 #size-cells = <0>;
487 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
488 atmel,fifo-size = <16>;
489 status = "disabled";
490 };
491
492 pwm0: pwm@f802c000 {
493 compatible = "atmel,sama5d2-pwm";
494 reg = <0xf802c000 0x4000>;
495 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 7>;
496 #pwm-cells = <3>;
497 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>;
498 status = "disabled";
499 };
500
501 sfr: sfr@f8030000 {
502 compatible = "atmel,sama5d2-sfr", "syscon";
503 reg = <0xf8030000 0x98>;
504 };
505
506 flx0: flexcom@f8034000 {
507 compatible = "atmel,sama5d2-flexcom";
508 reg = <0xf8034000 0x200>;
509 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
510 #address-cells = <1>;
511 #size-cells = <1>;
512 ranges = <0x0 0xf8034000 0x800>;
513 status = "disabled";
514
515 uart5: serial@200 {
516 compatible = "atmel,at91sam9260-usart";
517 reg = <0x200 0x200>;
518 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
519 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
520 clock-names = "usart";
521 dmas = <&dma0
522 (AT91_XDMAC_DT_MEM_IF(0) |
523 AT91_XDMAC_DT_PER_IF(1) |
524 AT91_XDMAC_DT_PERID(11))>,
525 <&dma0
526 (AT91_XDMAC_DT_MEM_IF(0) |
527 AT91_XDMAC_DT_PER_IF(1) |
528 AT91_XDMAC_DT_PERID(12))>;
529 dma-names = "tx", "rx";
530 atmel,fifo-size = <32>;
531 status = "disabled";
532 };
533
534 spi2: spi@400 {
535 compatible = "atmel,at91rm9200-spi";
536 reg = <0x400 0x200>;
537 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
538 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
539 clock-names = "spi_clk";
540 dmas = <&dma0
541 (AT91_XDMAC_DT_MEM_IF(0) |
542 AT91_XDMAC_DT_PER_IF(1) |
543 AT91_XDMAC_DT_PERID(11))>,
544 <&dma0
545 (AT91_XDMAC_DT_MEM_IF(0) |
546 AT91_XDMAC_DT_PER_IF(1) |
547 AT91_XDMAC_DT_PERID(12))>;
548 dma-names = "tx", "rx";
549 atmel,fifo-size = <16>;
550 status = "disabled";
551 };
552
553 i2c2: i2c@600 {
554 compatible = "atmel,sama5d2-i2c";
555 reg = <0x600 0x200>;
556 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 7>;
557 #address-cells = <1>;
558 #size-cells = <0>;
559 clocks = <&pmc PMC_TYPE_PERIPHERAL 19>;
560 dmas = <&dma0
561 (AT91_XDMAC_DT_MEM_IF(0) |
562 AT91_XDMAC_DT_PER_IF(1) |
563 AT91_XDMAC_DT_PERID(11))>,
564 <&dma0
565 (AT91_XDMAC_DT_MEM_IF(0) |
566 AT91_XDMAC_DT_PER_IF(1) |
567 AT91_XDMAC_DT_PERID(12))>;
568 dma-names = "tx", "rx";
569 atmel,fifo-size = <16>;
570 status = "disabled";
571 };
572 };
573
574 flx1: flexcom@f8038000 {
575 compatible = "atmel,sama5d2-flexcom";
576 reg = <0xf8038000 0x200>;
577 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
578 #address-cells = <1>;
579 #size-cells = <1>;
580 ranges = <0x0 0xf8038000 0x800>;
581 status = "disabled";
582
583 uart6: serial@200 {
584 compatible = "atmel,at91sam9260-usart";
585 reg = <0x200 0x200>;
586 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
587 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
588 clock-names = "usart";
589 dmas = <&dma0
590 (AT91_XDMAC_DT_MEM_IF(0) |
591 AT91_XDMAC_DT_PER_IF(1) |
592 AT91_XDMAC_DT_PERID(13))>,
593 <&dma0
594 (AT91_XDMAC_DT_MEM_IF(0) |
595 AT91_XDMAC_DT_PER_IF(1) |
596 AT91_XDMAC_DT_PERID(14))>;
597 dma-names = "tx", "rx";
598 atmel,fifo-size = <32>;
599 status = "disabled";
600 };
601
602 spi3: spi@400 {
603 compatible = "atmel,at91rm9200-spi";
604 reg = <0x400 0x200>;
605 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
606 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
607 clock-names = "spi_clk";
608 dmas = <&dma0
609 (AT91_XDMAC_DT_MEM_IF(0) |
610 AT91_XDMAC_DT_PER_IF(1) |
611 AT91_XDMAC_DT_PERID(13))>,
612 <&dma0
613 (AT91_XDMAC_DT_MEM_IF(0) |
614 AT91_XDMAC_DT_PER_IF(1) |
615 AT91_XDMAC_DT_PERID(14))>;
616 dma-names = "tx", "rx";
617 atmel,fifo-size = <16>;
618 status = "disabled";
619 };
620
621 i2c3: i2c@600 {
622 compatible = "atmel,sama5d2-i2c";
623 reg = <0x600 0x200>;
624 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 7>;
625 #address-cells = <1>;
626 #size-cells = <0>;
627 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>;
628 dmas = <&dma0
629 (AT91_XDMAC_DT_MEM_IF(0) |
630 AT91_XDMAC_DT_PER_IF(1) |
631 AT91_XDMAC_DT_PERID(13))>,
632 <&dma0
633 (AT91_XDMAC_DT_MEM_IF(0) |
634 AT91_XDMAC_DT_PER_IF(1) |
635 AT91_XDMAC_DT_PERID(14))>;
636 dma-names = "tx", "rx";
637 atmel,fifo-size = <16>;
638 status = "disabled";
639 };
640 };
641
642 securam: sram@f8044000 {
643 compatible = "atmel,sama5d2-securam", "mmio-sram";
644 reg = <0xf8044000 0x1420>;
645 clocks = <&pmc PMC_TYPE_PERIPHERAL 51>;
646 #address-cells = <1>;
647 #size-cells = <1>;
648 ranges = <0 0xf8044000 0x1420>;
649 };
650
651 reset_controller: rstc@f8048000 {
652 compatible = "atmel,sama5d3-rstc";
653 reg = <0xf8048000 0x10>;
654 clocks = <&clk32k>;
655 };
656
657 shutdown_controller: shdwc@f8048010 {
658 compatible = "atmel,sama5d2-shdwc";
659 reg = <0xf8048010 0x10>;
660 clocks = <&clk32k>;
661 #address-cells = <1>;
662 #size-cells = <0>;
663 atmel,wakeup-rtc-timer;
664 };
665
666 pit: timer@f8048030 {
667 compatible = "atmel,at91sam9260-pit";
668 reg = <0xf8048030 0x10>;
669 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 5>;
670 clocks = <&pmc PMC_TYPE_CORE PMC_MCK2>;
671 };
672
673 watchdog: watchdog@f8048040 {
674 compatible = "atmel,sama5d4-wdt";
675 reg = <0xf8048040 0x10>;
676 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 7>;
677 clocks = <&clk32k>;
678 status = "disabled";
679 };
680
681 clk32k: sckc@f8048050 {
682 compatible = "atmel,sama5d4-sckc";
683 reg = <0xf8048050 0x4>;
684
685 clocks = <&slow_xtal>;
686 #clock-cells = <0>;
687 };
688
689 rtc: rtc@f80480b0 {
690 compatible = "atmel,sama5d2-rtc";
691 reg = <0xf80480b0 0x30>;
692 interrupts = <74 IRQ_TYPE_LEVEL_HIGH 7>;
693 clocks = <&clk32k>;
694 };
695
696 i2s0: i2s@f8050000 {
697 compatible = "atmel,sama5d2-i2s";
698 reg = <0xf8050000 0x100>;
699 interrupts = <54 IRQ_TYPE_LEVEL_HIGH 7>;
700 dmas = <&dma0
701 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
702 AT91_XDMAC_DT_PERID(31))>,
703 <&dma0
704 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
705 AT91_XDMAC_DT_PERID(32))>;
706 dma-names = "tx", "rx";
707 clocks = <&pmc PMC_TYPE_PERIPHERAL 54>, <&pmc PMC_TYPE_GCK 54>;
708 clock-names = "pclk", "gclk";
709 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S0_MUX>;
710 assigned-clock-parents = <&pmc PMC_TYPE_GCK 54>;
711 status = "disabled";
712 };
713
714 can0: can@f8054000 {
715 compatible = "bosch,m_can";
716 reg = <0xf8054000 0x4000>, <0x210000 0x4000>;
717 reg-names = "m_can", "message_ram";
718 interrupts = <56 IRQ_TYPE_LEVEL_HIGH 7>,
719 <64 IRQ_TYPE_LEVEL_HIGH 7>;
720 interrupt-names = "int0", "int1";
721 clocks = <&pmc PMC_TYPE_PERIPHERAL 56>, <&pmc PMC_TYPE_GCK 56>;
722 clock-names = "hclk", "cclk";
723 assigned-clocks = <&pmc PMC_TYPE_GCK 56>;
724 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
725 assigned-clock-rates = <40000000>;
726 bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
727 status = "disabled";
728 };
729
730 spi1: spi@fc000000 {
731 compatible = "atmel,at91rm9200-spi";
732 reg = <0xfc000000 0x100>;
733 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>;
734 dmas = <&dma0
735 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
736 AT91_XDMAC_DT_PERID(8))>,
737 <&dma0
738 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
739 AT91_XDMAC_DT_PERID(9))>;
740 dma-names = "tx", "rx";
741 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>;
742 clock-names = "spi_clk";
743 atmel,fifo-size = <16>;
744 #address-cells = <1>;
745 #size-cells = <0>;
746 status = "disabled";
747 };
748
749 uart3: serial@fc008000 {
750 compatible = "atmel,at91sam9260-usart";
751 reg = <0xfc008000 0x100>;
752 interrupts = <27 IRQ_TYPE_LEVEL_HIGH 7>;
753 dmas = <&dma1
754 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
755 AT91_XDMAC_DT_PERID(41))>,
756 <&dma1
757 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
758 AT91_XDMAC_DT_PERID(42))>;
759 dma-names = "tx", "rx";
760 clocks = <&pmc PMC_TYPE_PERIPHERAL 27>;
761 clock-names = "usart";
762 status = "disabled";
763 };
764
765 uart4: serial@fc00c000 {
766 compatible = "atmel,at91sam9260-usart";
767 reg = <0xfc00c000 0x100>;
768 dmas = <&dma0
769 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
770 AT91_XDMAC_DT_PERID(43))>,
771 <&dma0
772 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
773 AT91_XDMAC_DT_PERID(44))>;
774 dma-names = "tx", "rx";
775 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 7>;
776 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>;
777 clock-names = "usart";
778 status = "disabled";
779 };
780
781 flx2: flexcom@fc010000 {
782 compatible = "atmel,sama5d2-flexcom";
783 reg = <0xfc010000 0x200>;
784 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
785 #address-cells = <1>;
786 #size-cells = <1>;
787 ranges = <0x0 0xfc010000 0x800>;
788 status = "disabled";
789
790 uart7: serial@200 {
791 compatible = "atmel,at91sam9260-usart";
792 reg = <0x200 0x200>;
793 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
794 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
795 clock-names = "usart";
796 dmas = <&dma0
797 (AT91_XDMAC_DT_MEM_IF(0) |
798 AT91_XDMAC_DT_PER_IF(1) |
799 AT91_XDMAC_DT_PERID(15))>,
800 <&dma0
801 (AT91_XDMAC_DT_MEM_IF(0) |
802 AT91_XDMAC_DT_PER_IF(1) |
803 AT91_XDMAC_DT_PERID(16))>;
804 dma-names = "tx", "rx";
805 atmel,fifo-size = <32>;
806 status = "disabled";
807 };
808
809 spi4: spi@400 {
810 compatible = "atmel,at91rm9200-spi";
811 reg = <0x400 0x200>;
812 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
813 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
814 clock-names = "spi_clk";
815 dmas = <&dma0
816 (AT91_XDMAC_DT_MEM_IF(0) |
817 AT91_XDMAC_DT_PER_IF(1) |
818 AT91_XDMAC_DT_PERID(15))>,
819 <&dma0
820 (AT91_XDMAC_DT_MEM_IF(0) |
821 AT91_XDMAC_DT_PER_IF(1) |
822 AT91_XDMAC_DT_PERID(16))>;
823 dma-names = "tx", "rx";
824 atmel,fifo-size = <16>;
825 status = "disabled";
826 };
827
828 i2c4: i2c@600 {
829 compatible = "atmel,sama5d2-i2c";
830 reg = <0x600 0x200>;
831 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 7>;
832 #address-cells = <1>;
833 #size-cells = <0>;
834 clocks = <&pmc PMC_TYPE_PERIPHERAL 21>;
835 dmas = <&dma0
836 (AT91_XDMAC_DT_MEM_IF(0) |
837 AT91_XDMAC_DT_PER_IF(1) |
838 AT91_XDMAC_DT_PERID(15))>,
839 <&dma0
840 (AT91_XDMAC_DT_MEM_IF(0) |
841 AT91_XDMAC_DT_PER_IF(1) |
842 AT91_XDMAC_DT_PERID(16))>;
843 dma-names = "tx", "rx";
844 atmel,fifo-size = <16>;
845 status = "disabled";
846 };
847 };
848
849 flx3: flexcom@fc014000 {
850 compatible = "atmel,sama5d2-flexcom";
851 reg = <0xfc014000 0x200>;
852 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
853 #address-cells = <1>;
854 #size-cells = <1>;
855 ranges = <0x0 0xfc014000 0x800>;
856 status = "disabled";
857
858 uart8: serial@200 {
859 compatible = "atmel,at91sam9260-usart";
860 reg = <0x200 0x200>;
861 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
862 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
863 clock-names = "usart";
864 dmas = <&dma0
865 (AT91_XDMAC_DT_MEM_IF(0) |
866 AT91_XDMAC_DT_PER_IF(1) |
867 AT91_XDMAC_DT_PERID(17))>,
868 <&dma0
869 (AT91_XDMAC_DT_MEM_IF(0) |
870 AT91_XDMAC_DT_PER_IF(1) |
871 AT91_XDMAC_DT_PERID(18))>;
872 dma-names = "tx", "rx";
873 atmel,fifo-size = <32>;
874 status = "disabled";
875 };
876
877 spi5: spi@400 {
878 compatible = "atmel,at91rm9200-spi";
879 reg = <0x400 0x200>;
880 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
881 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
882 clock-names = "spi_clk";
883 dmas = <&dma0
884 (AT91_XDMAC_DT_MEM_IF(0) |
885 AT91_XDMAC_DT_PER_IF(1) |
886 AT91_XDMAC_DT_PERID(17))>,
887 <&dma0
888 (AT91_XDMAC_DT_MEM_IF(0) |
889 AT91_XDMAC_DT_PER_IF(1) |
890 AT91_XDMAC_DT_PERID(18))>;
891 dma-names = "tx", "rx";
892 atmel,fifo-size = <16>;
893 status = "disabled";
894 };
895
896 i2c5: i2c@600 {
897 compatible = "atmel,sama5d2-i2c";
898 reg = <0x600 0x200>;
899 interrupts = <22 IRQ_TYPE_LEVEL_HIGH 7>;
900 #address-cells = <1>;
901 #size-cells = <0>;
902 clocks = <&pmc PMC_TYPE_PERIPHERAL 22>;
903 dmas = <&dma0
904 (AT91_XDMAC_DT_MEM_IF(0) |
905 AT91_XDMAC_DT_PER_IF(1) |
906 AT91_XDMAC_DT_PERID(17))>,
907 <&dma0
908 (AT91_XDMAC_DT_MEM_IF(0) |
909 AT91_XDMAC_DT_PER_IF(1) |
910 AT91_XDMAC_DT_PERID(18))>;
911 dma-names = "tx", "rx";
912 atmel,fifo-size = <16>;
913 status = "disabled";
914 };
915
916 };
917
918 flx4: flexcom@fc018000 {
919 compatible = "atmel,sama5d2-flexcom";
920 reg = <0xfc018000 0x200>;
921 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
922 #address-cells = <1>;
923 #size-cells = <1>;
924 ranges = <0x0 0xfc018000 0x800>;
925 status = "disabled";
926
927 uart9: serial@200 {
928 compatible = "atmel,at91sam9260-usart";
929 reg = <0x200 0x200>;
930 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
931 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
932 clock-names = "usart";
933 dmas = <&dma0
934 (AT91_XDMAC_DT_MEM_IF(0) |
935 AT91_XDMAC_DT_PER_IF(1) |
936 AT91_XDMAC_DT_PERID(19))>,
937 <&dma0
938 (AT91_XDMAC_DT_MEM_IF(0) |
939 AT91_XDMAC_DT_PER_IF(1) |
940 AT91_XDMAC_DT_PERID(20))>;
941 dma-names = "tx", "rx";
942 atmel,fifo-size = <32>;
943 status = "disabled";
944 };
945
946 spi6: spi@400 {
947 compatible = "atmel,at91rm9200-spi";
948 reg = <0x400 0x200>;
949 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
950 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
951 clock-names = "spi_clk";
952 dmas = <&dma0
953 (AT91_XDMAC_DT_MEM_IF(0) |
954 AT91_XDMAC_DT_PER_IF(1) |
955 AT91_XDMAC_DT_PERID(19))>,
956 <&dma0
957 (AT91_XDMAC_DT_MEM_IF(0) |
958 AT91_XDMAC_DT_PER_IF(1) |
959 AT91_XDMAC_DT_PERID(20))>;
960 dma-names = "tx", "rx";
961 atmel,fifo-size = <16>;
962 status = "disabled";
963 };
964
965 i2c6: i2c@600 {
966 compatible = "atmel,sama5d2-i2c";
967 reg = <0x600 0x200>;
968 interrupts = <23 IRQ_TYPE_LEVEL_HIGH 7>;
969 #address-cells = <1>;
970 #size-cells = <0>;
971 clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
972 dmas = <&dma0
973 (AT91_XDMAC_DT_MEM_IF(0) |
974 AT91_XDMAC_DT_PER_IF(1) |
975 AT91_XDMAC_DT_PERID(19))>,
976 <&dma0
977 (AT91_XDMAC_DT_MEM_IF(0) |
978 AT91_XDMAC_DT_PER_IF(1) |
979 AT91_XDMAC_DT_PERID(20))>;
980 dma-names = "tx", "rx";
981 atmel,fifo-size = <16>;
982 status = "disabled";
983 };
984 };
985
986 trng@fc01c000 {
987 compatible = "atmel,at91sam9g45-trng";
988 reg = <0xfc01c000 0x100>;
989 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 0>;
990 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>;
991 };
992
993 aic: interrupt-controller@fc020000 {
994 #interrupt-cells = <3>;
995 compatible = "atmel,sama5d2-aic";
996 interrupt-controller;
997 reg = <0xfc020000 0x200>;
998 atmel,external-irqs = <49>;
999 };
1000
1001 i2c1: i2c@fc028000 {
1002 compatible = "atmel,sama5d2-i2c";
1003 reg = <0xfc028000 0x100>;
1004 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 7>;
1005 dmas = <&dma0
1006 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1007 AT91_XDMAC_DT_PERID(2))>,
1008 <&dma0
1009 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1010 AT91_XDMAC_DT_PERID(3))>;
1011 dma-names = "tx", "rx";
1012 #address-cells = <1>;
1013 #size-cells = <0>;
1014 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
1015 atmel,fifo-size = <16>;
1016 status = "disabled";
1017 };
1018
1019 adc: adc@fc030000 {
1020 compatible = "atmel,sama5d2-adc";
1021 reg = <0xfc030000 0x100>;
1022 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 7>;
1023 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>;
1024 clock-names = "adc_clk";
1025 dmas = <&dma0 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | AT91_XDMAC_DT_PERID(25))>;
1026 dma-names = "rx";
1027 atmel,min-sample-rate-hz = <200000>;
1028 atmel,max-sample-rate-hz = <20000000>;
1029 atmel,startup-time-ms = <4>;
1030 atmel,trigger-edge-type = <IRQ_TYPE_EDGE_RISING>;
1031 #io-channel-cells = <1>;
1032 status = "disabled";
1033 };
1034
1035 resistive_touch: resistive-touch {
1036 compatible = "resistive-adc-touch";
1037 io-channels = <&adc AT91_SAMA5D2_ADC_X_CHANNEL>,
1038 <&adc AT91_SAMA5D2_ADC_Y_CHANNEL>,
1039 <&adc AT91_SAMA5D2_ADC_P_CHANNEL>;
1040 io-channel-names = "x", "y", "pressure";
1041 touchscreen-min-pressure = <50000>;
1042 status = "disabled";
1043 };
1044
1045 pioA: pinctrl@fc038000 {
1046 compatible = "atmel,sama5d2-pinctrl";
1047 reg = <0xfc038000 0x600>;
1048 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
1049 <68 IRQ_TYPE_LEVEL_HIGH 7>,
1050 <69 IRQ_TYPE_LEVEL_HIGH 7>,
1051 <70 IRQ_TYPE_LEVEL_HIGH 7>;
1052 interrupt-controller;
1053 #interrupt-cells = <2>;
1054 gpio-controller;
1055 #gpio-cells = <2>;
1056 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
1057 };
1058
1059 pioBU: secumod@fc040000 {
1060 compatible = "atmel,sama5d2-secumod", "syscon";
1061 reg = <0xfc040000 0x100>;
1062
1063 gpio-controller;
1064 #gpio-cells = <2>;
1065 };
1066
1067 tdes@fc044000 {
1068 compatible = "atmel,at91sam9g46-tdes";
1069 reg = <0xfc044000 0x100>;
1070 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
1071 dmas = <&dma0
1072 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1073 AT91_XDMAC_DT_PERID(28))>,
1074 <&dma0
1075 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1076 AT91_XDMAC_DT_PERID(29))>;
1077 dma-names = "tx", "rx";
1078 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
1079 clock-names = "tdes_clk";
1080 status = "okay";
1081 };
1082
1083 classd: classd@fc048000 {
1084 compatible = "atmel,sama5d2-classd";
1085 reg = <0xfc048000 0x100>;
1086 interrupts = <59 IRQ_TYPE_LEVEL_HIGH 7>;
1087 dmas = <&dma0
1088 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1089 AT91_XDMAC_DT_PERID(47))>;
1090 dma-names = "tx";
1091 clocks = <&pmc PMC_TYPE_PERIPHERAL 59>, <&pmc PMC_TYPE_GCK 59>;
1092 clock-names = "pclk", "gclk";
1093 status = "disabled";
1094 };
1095
1096 i2s1: i2s@fc04c000 {
1097 compatible = "atmel,sama5d2-i2s";
1098 reg = <0xfc04c000 0x100>;
1099 interrupts = <55 IRQ_TYPE_LEVEL_HIGH 7>;
1100 dmas = <&dma0
1101 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1102 AT91_XDMAC_DT_PERID(33))>,
1103 <&dma0
1104 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
1105 AT91_XDMAC_DT_PERID(34))>;
1106 dma-names = "tx", "rx";
1107 clocks = <&pmc PMC_TYPE_PERIPHERAL 55>, <&pmc PMC_TYPE_GCK 55>;
1108 clock-names = "pclk", "gclk";
1109 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_I2S1_MUX>;
1110 assigned-parrents = <&pmc PMC_TYPE_GCK 55>;
1111 status = "disabled";
1112 };
1113
1114 can1: can@fc050000 {
1115 compatible = "bosch,m_can";
1116 reg = <0xfc050000 0x4000>, <0x210000 0x4000>;
1117 reg-names = "m_can", "message_ram";
1118 interrupts = <57 IRQ_TYPE_LEVEL_HIGH 7>,
1119 <65 IRQ_TYPE_LEVEL_HIGH 7>;
1120 interrupt-names = "int0", "int1";
1121 clocks = <&pmc PMC_TYPE_PERIPHERAL 57>, <&pmc PMC_TYPE_GCK 57>;
1122 clock-names = "hclk", "cclk";
1123 assigned-clocks = <&pmc PMC_TYPE_GCK 57>;
1124 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>;
1125 assigned-clock-rates = <40000000>;
1126 bosch,mram-cfg = <0x1100 0 0 64 0 0 32 32>;
1127 status = "disabled";
1128 };
1129
1130 sfrbu: sfr@fc05c000 {
1131 compatible = "atmel,sama5d2-sfrbu", "syscon";
1132 reg = <0xfc05c000 0x20>;
1133 };
1134
1135 chipid@fc069000 {
1136 compatible = "atmel,sama5d2-chipid";
1137 reg = <0xfc069000 0x8>;
1138 };
1139 };
1140 };
1141};