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1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include "skeleton.dtsi"
5#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7#include <dt-bindings/soc/qcom,gsbi.h>
8
9/ {
10 model = "Qualcomm IPQ8064";
11 compatible = "qcom,ipq8064";
12 interrupt-parent = <&intc>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 compatible = "qcom,krait";
20 enable-method = "qcom,kpss-acc-v1";
21 device_type = "cpu";
22 reg = <0>;
23 next-level-cache = <&L2>;
24 qcom,acc = <&acc0>;
25 qcom,saw = <&saw0>;
26 };
27
28 cpu@1 {
29 compatible = "qcom,krait";
30 enable-method = "qcom,kpss-acc-v1";
31 device_type = "cpu";
32 reg = <1>;
33 next-level-cache = <&L2>;
34 qcom,acc = <&acc1>;
35 qcom,saw = <&saw1>;
36 };
37
38 L2: l2-cache {
39 compatible = "cache";
40 cache-level = <2>;
41 };
42 };
43
44 cpu-pmu {
45 compatible = "qcom,krait-pmu";
46 interrupts = <1 10 0x304>;
47 };
48
49 reserved-memory {
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges;
53
54 nss@40000000 {
55 reg = <0x40000000 0x1000000>;
56 no-map;
57 };
58
59 smem@41000000 {
60 reg = <0x41000000 0x200000>;
61 no-map;
62 };
63 };
64
65 clocks {
66 cxo_board {
67 compatible = "fixed-clock";
68 #clock-cells = <0>;
69 clock-frequency = <25000000>;
70 };
71
72 pxo_board {
73 compatible = "fixed-clock";
74 #clock-cells = <0>;
75 clock-frequency = <25000000>;
76 };
77
78 sleep_clk: sleep_clk {
79 compatible = "fixed-clock";
80 clock-frequency = <32768>;
81 #clock-cells = <0>;
82 };
83 };
84
85 soc: soc {
86 #address-cells = <1>;
87 #size-cells = <1>;
88 ranges;
89 compatible = "simple-bus";
90
91 lpass@28100000 {
92 compatible = "qcom,lpass-cpu";
93 status = "disabled";
94 clocks = <&lcc AHBIX_CLK>,
95 <&lcc MI2S_OSR_CLK>,
96 <&lcc MI2S_BIT_CLK>;
97 clock-names = "ahbix-clk",
98 "mi2s-osr-clk",
99 "mi2s-bit-clk";
100 interrupts = <0 85 1>;
101 interrupt-names = "lpass-irq-lpaif";
102 reg = <0x28100000 0x10000>;
103 reg-names = "lpass-lpaif";
104 };
105
106 qcom_pinmux: pinmux@800000 {
107 compatible = "qcom,ipq8064-pinctrl";
108 reg = <0x800000 0x4000>;
109
110 gpio-controller;
111 #gpio-cells = <2>;
112 interrupt-controller;
113 #interrupt-cells = <2>;
114 interrupts = <0 16 0x4>;
115 };
116
117 intc: interrupt-controller@2000000 {
118 compatible = "qcom,msm-qgic2";
119 interrupt-controller;
120 #interrupt-cells = <3>;
121 reg = <0x02000000 0x1000>,
122 <0x02002000 0x1000>;
123 };
124
125 timer@200a000 {
126 compatible = "qcom,kpss-timer",
127 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
128 interrupts = <1 1 0x301>,
129 <1 2 0x301>,
130 <1 3 0x301>,
131 <1 4 0x301>,
132 <1 5 0x301>;
133 reg = <0x0200a000 0x100>;
134 clock-frequency = <25000000>,
135 <32768>;
136 clocks = <&sleep_clk>;
137 clock-names = "sleep";
138 cpu-offset = <0x80000>;
139 };
140
141 acc0: clock-controller@2088000 {
142 compatible = "qcom,kpss-acc-v1";
143 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
144 };
145
146 acc1: clock-controller@2098000 {
147 compatible = "qcom,kpss-acc-v1";
148 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
149 };
150
151 saw0: regulator@2089000 {
152 compatible = "qcom,saw2";
153 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
154 regulator;
155 };
156
157 saw1: regulator@2099000 {
158 compatible = "qcom,saw2";
159 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
160 regulator;
161 };
162
163 gsbi2: gsbi@12480000 {
164 compatible = "qcom,gsbi-v1.0.0";
165 cell-index = <2>;
166 reg = <0x12480000 0x100>;
167 clocks = <&gcc GSBI2_H_CLK>;
168 clock-names = "iface";
169 #address-cells = <1>;
170 #size-cells = <1>;
171 ranges;
172 status = "disabled";
173
174 syscon-tcsr = <&tcsr>;
175
176 serial@12490000 {
177 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
178 reg = <0x12490000 0x1000>,
179 <0x12480000 0x1000>;
180 interrupts = <0 195 0x0>;
181 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
182 clock-names = "core", "iface";
183 status = "disabled";
184 };
185
186 i2c@124a0000 {
187 compatible = "qcom,i2c-qup-v1.1.1";
188 reg = <0x124a0000 0x1000>;
189 interrupts = <0 196 0>;
190
191 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
192 clock-names = "core", "iface";
193 status = "disabled";
194
195 #address-cells = <1>;
196 #size-cells = <0>;
197 };
198
199 };
200
201 gsbi4: gsbi@16300000 {
202 compatible = "qcom,gsbi-v1.0.0";
203 cell-index = <4>;
204 reg = <0x16300000 0x100>;
205 clocks = <&gcc GSBI4_H_CLK>;
206 clock-names = "iface";
207 #address-cells = <1>;
208 #size-cells = <1>;
209 ranges;
210 status = "disabled";
211
212 syscon-tcsr = <&tcsr>;
213
214 gsbi4_serial: serial@16340000 {
215 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
216 reg = <0x16340000 0x1000>,
217 <0x16300000 0x1000>;
218 interrupts = <0 152 0x0>;
219 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
220 clock-names = "core", "iface";
221 status = "disabled";
222 };
223
224 i2c@16380000 {
225 compatible = "qcom,i2c-qup-v1.1.1";
226 reg = <0x16380000 0x1000>;
227 interrupts = <0 153 0>;
228
229 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
230 clock-names = "core", "iface";
231 status = "disabled";
232
233 #address-cells = <1>;
234 #size-cells = <0>;
235 };
236 };
237
238 gsbi5: gsbi@1a200000 {
239 compatible = "qcom,gsbi-v1.0.0";
240 cell-index = <5>;
241 reg = <0x1a200000 0x100>;
242 clocks = <&gcc GSBI5_H_CLK>;
243 clock-names = "iface";
244 #address-cells = <1>;
245 #size-cells = <1>;
246 ranges;
247 status = "disabled";
248
249 syscon-tcsr = <&tcsr>;
250
251 serial@1a240000 {
252 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
253 reg = <0x1a240000 0x1000>,
254 <0x1a200000 0x1000>;
255 interrupts = <0 154 0x0>;
256 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
257 clock-names = "core", "iface";
258 status = "disabled";
259 };
260
261 i2c@1a280000 {
262 compatible = "qcom,i2c-qup-v1.1.1";
263 reg = <0x1a280000 0x1000>;
264 interrupts = <0 155 0>;
265
266 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
267 clock-names = "core", "iface";
268 status = "disabled";
269
270 #address-cells = <1>;
271 #size-cells = <0>;
272 };
273
274 spi@1a280000 {
275 compatible = "qcom,spi-qup-v1.1.1";
276 reg = <0x1a280000 0x1000>;
277 interrupts = <0 155 0>;
278
279 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
280 clock-names = "core", "iface";
281 status = "disabled";
282
283 #address-cells = <1>;
284 #size-cells = <0>;
285 };
286 };
287
288 gsbi7: gsbi@16600000 {
289 status = "disabled";
290 compatible = "qcom,gsbi-v1.0.0";
291 cell-index = <7>;
292 reg = <0x16600000 0x100>;
293 clocks = <&gcc GSBI7_H_CLK>;
294 clock-names = "iface";
295 #address-cells = <1>;
296 #size-cells = <1>;
297 ranges;
298 syscon-tcsr = <&tcsr>;
299
300 gsbi7_serial: serial@16640000 {
301 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
302 reg = <0x16640000 0x1000>,
303 <0x16600000 0x1000>;
304 interrupts = <0 158 0x0>;
305 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
306 clock-names = "core", "iface";
307 status = "disabled";
308 };
309 };
310
311 sata_phy: sata-phy@1b400000 {
312 compatible = "qcom,ipq806x-sata-phy";
313 reg = <0x1b400000 0x200>;
314
315 clocks = <&gcc SATA_PHY_CFG_CLK>;
316 clock-names = "cfg";
317
318 #phy-cells = <0>;
319 status = "disabled";
320 };
321
322 sata@29000000 {
323 compatible = "qcom,ipq806x-ahci", "generic-ahci";
324 reg = <0x29000000 0x180>;
325
326 interrupts = <0 209 0x0>;
327
328 clocks = <&gcc SFAB_SATA_S_H_CLK>,
329 <&gcc SATA_H_CLK>,
330 <&gcc SATA_A_CLK>,
331 <&gcc SATA_RXOOB_CLK>,
332 <&gcc SATA_PMALIVE_CLK>;
333 clock-names = "slave_face", "iface", "core",
334 "rxoob", "pmalive";
335
336 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
337 assigned-clock-rates = <100000000>, <100000000>;
338
339 phys = <&sata_phy>;
340 phy-names = "sata-phy";
341 status = "disabled";
342 };
343
344 qcom,ssbi@500000 {
345 compatible = "qcom,ssbi";
346 reg = <0x00500000 0x1000>;
347 qcom,controller-type = "pmic-arbiter";
348 };
349
350 gcc: clock-controller@900000 {
351 compatible = "qcom,gcc-ipq8064";
352 reg = <0x00900000 0x4000>;
353 #clock-cells = <1>;
354 #reset-cells = <1>;
355 };
356
357 tcsr: syscon@1a400000 {
358 compatible = "qcom,tcsr-ipq8064", "syscon";
359 reg = <0x1a400000 0x100>;
360 };
361
362 lcc: clock-controller@28000000 {
363 compatible = "qcom,lcc-ipq8064";
364 reg = <0x28000000 0x1000>;
365 #clock-cells = <1>;
366 #reset-cells = <1>;
367 };
368
369 };
370};
1// SPDX-License-Identifier: GPL-2.0
2/dts-v1/;
3
4#include <dt-bindings/interrupt-controller/arm-gic.h>
5#include <dt-bindings/clock/qcom,gcc-ipq806x.h>
6#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
9#include <dt-bindings/soc/qcom,gsbi.h>
10#include <dt-bindings/interrupt-controller/arm-gic.h>
11
12/ {
13 #address-cells = <1>;
14 #size-cells = <1>;
15 model = "Qualcomm IPQ8064";
16 compatible = "qcom,ipq8064";
17 interrupt-parent = <&intc>;
18
19 cpus {
20 #address-cells = <1>;
21 #size-cells = <0>;
22
23 cpu@0 {
24 compatible = "qcom,krait";
25 enable-method = "qcom,kpss-acc-v1";
26 device_type = "cpu";
27 reg = <0>;
28 next-level-cache = <&L2>;
29 qcom,acc = <&acc0>;
30 qcom,saw = <&saw0>;
31 };
32
33 cpu@1 {
34 compatible = "qcom,krait";
35 enable-method = "qcom,kpss-acc-v1";
36 device_type = "cpu";
37 reg = <1>;
38 next-level-cache = <&L2>;
39 qcom,acc = <&acc1>;
40 qcom,saw = <&saw1>;
41 };
42
43 L2: l2-cache {
44 compatible = "cache";
45 cache-level = <2>;
46 };
47 };
48
49 memory {
50 device_type = "memory";
51 reg = <0x0 0x0>;
52 };
53
54 cpu-pmu {
55 compatible = "qcom,krait-pmu";
56 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
57 IRQ_TYPE_LEVEL_HIGH)>;
58 };
59
60 reserved-memory {
61 #address-cells = <1>;
62 #size-cells = <1>;
63 ranges;
64
65 nss@40000000 {
66 reg = <0x40000000 0x1000000>;
67 no-map;
68 };
69
70 smem@41000000 {
71 reg = <0x41000000 0x200000>;
72 no-map;
73 };
74 };
75
76 clocks {
77 cxo_board {
78 compatible = "fixed-clock";
79 #clock-cells = <0>;
80 clock-frequency = <25000000>;
81 };
82
83 pxo_board {
84 compatible = "fixed-clock";
85 #clock-cells = <0>;
86 clock-frequency = <25000000>;
87 };
88
89 sleep_clk: sleep_clk {
90 compatible = "fixed-clock";
91 clock-frequency = <32768>;
92 #clock-cells = <0>;
93 };
94 };
95
96 firmware {
97 scm {
98 compatible = "qcom,scm-ipq806x", "qcom,scm";
99 };
100 };
101
102 soc: soc {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 ranges;
106 compatible = "simple-bus";
107
108 lpass@28100000 {
109 compatible = "qcom,lpass-cpu";
110 status = "disabled";
111 clocks = <&lcc AHBIX_CLK>,
112 <&lcc MI2S_OSR_CLK>,
113 <&lcc MI2S_BIT_CLK>;
114 clock-names = "ahbix-clk",
115 "mi2s-osr-clk",
116 "mi2s-bit-clk";
117 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
118 interrupt-names = "lpass-irq-lpaif";
119 reg = <0x28100000 0x10000>;
120 reg-names = "lpass-lpaif";
121 };
122
123 qcom_pinmux: pinmux@800000 {
124 compatible = "qcom,ipq8064-pinctrl";
125 reg = <0x800000 0x4000>;
126
127 gpio-controller;
128 gpio-ranges = <&qcom_pinmux 0 0 69>;
129 #gpio-cells = <2>;
130 interrupt-controller;
131 #interrupt-cells = <2>;
132 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
133
134 pcie0_pins: pcie0_pinmux {
135 mux {
136 pins = "gpio3";
137 function = "pcie1_rst";
138 drive-strength = <12>;
139 bias-disable;
140 };
141 };
142
143 pcie1_pins: pcie1_pinmux {
144 mux {
145 pins = "gpio48";
146 function = "pcie2_rst";
147 drive-strength = <12>;
148 bias-disable;
149 };
150 };
151
152 pcie2_pins: pcie2_pinmux {
153 mux {
154 pins = "gpio63";
155 function = "pcie3_rst";
156 drive-strength = <12>;
157 bias-disable;
158 };
159 };
160
161 spi_pins: spi_pins {
162 mux {
163 pins = "gpio18", "gpio19", "gpio21";
164 function = "gsbi5";
165 drive-strength = <10>;
166 bias-none;
167 };
168 };
169
170 leds_pins: leds_pins {
171 mux {
172 pins = "gpio7", "gpio8", "gpio9",
173 "gpio26", "gpio53";
174 function = "gpio";
175 drive-strength = <2>;
176 bias-pull-down;
177 output-low;
178 };
179 };
180
181 buttons_pins: buttons_pins {
182 mux {
183 pins = "gpio54";
184 drive-strength = <2>;
185 bias-pull-up;
186 };
187 };
188 };
189
190 intc: interrupt-controller@2000000 {
191 compatible = "qcom,msm-qgic2";
192 interrupt-controller;
193 #interrupt-cells = <3>;
194 reg = <0x02000000 0x1000>,
195 <0x02002000 0x1000>;
196 };
197
198 timer@200a000 {
199 compatible = "qcom,kpss-timer",
200 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
201 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
202 IRQ_TYPE_EDGE_RISING)>,
203 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
204 IRQ_TYPE_EDGE_RISING)>,
205 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
206 IRQ_TYPE_EDGE_RISING)>,
207 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
208 IRQ_TYPE_EDGE_RISING)>,
209 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
210 IRQ_TYPE_EDGE_RISING)>;
211 reg = <0x0200a000 0x100>;
212 clock-frequency = <25000000>,
213 <32768>;
214 clocks = <&sleep_clk>;
215 clock-names = "sleep";
216 cpu-offset = <0x80000>;
217 };
218
219 acc0: clock-controller@2088000 {
220 compatible = "qcom,kpss-acc-v1";
221 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
222 };
223
224 acc1: clock-controller@2098000 {
225 compatible = "qcom,kpss-acc-v1";
226 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
227 };
228
229 saw0: regulator@2089000 {
230 compatible = "qcom,saw2";
231 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
232 regulator;
233 };
234
235 saw1: regulator@2099000 {
236 compatible = "qcom,saw2";
237 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
238 regulator;
239 };
240
241 gsbi2: gsbi@12480000 {
242 compatible = "qcom,gsbi-v1.0.0";
243 cell-index = <2>;
244 reg = <0x12480000 0x100>;
245 clocks = <&gcc GSBI2_H_CLK>;
246 clock-names = "iface";
247 #address-cells = <1>;
248 #size-cells = <1>;
249 ranges;
250 status = "disabled";
251
252 syscon-tcsr = <&tcsr>;
253
254 serial@12490000 {
255 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
256 reg = <0x12490000 0x1000>,
257 <0x12480000 0x1000>;
258 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
259 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
260 clock-names = "core", "iface";
261 status = "disabled";
262 };
263
264 i2c@124a0000 {
265 compatible = "qcom,i2c-qup-v1.1.1";
266 reg = <0x124a0000 0x1000>;
267 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
268
269 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
270 clock-names = "core", "iface";
271 status = "disabled";
272
273 #address-cells = <1>;
274 #size-cells = <0>;
275 };
276
277 };
278
279 gsbi4: gsbi@16300000 {
280 compatible = "qcom,gsbi-v1.0.0";
281 cell-index = <4>;
282 reg = <0x16300000 0x100>;
283 clocks = <&gcc GSBI4_H_CLK>;
284 clock-names = "iface";
285 #address-cells = <1>;
286 #size-cells = <1>;
287 ranges;
288 status = "disabled";
289
290 syscon-tcsr = <&tcsr>;
291
292 gsbi4_serial: serial@16340000 {
293 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
294 reg = <0x16340000 0x1000>,
295 <0x16300000 0x1000>;
296 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
298 clock-names = "core", "iface";
299 status = "disabled";
300 };
301
302 i2c@16380000 {
303 compatible = "qcom,i2c-qup-v1.1.1";
304 reg = <0x16380000 0x1000>;
305 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
306
307 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
308 clock-names = "core", "iface";
309 status = "disabled";
310
311 #address-cells = <1>;
312 #size-cells = <0>;
313 };
314 };
315
316 gsbi5: gsbi@1a200000 {
317 compatible = "qcom,gsbi-v1.0.0";
318 cell-index = <5>;
319 reg = <0x1a200000 0x100>;
320 clocks = <&gcc GSBI5_H_CLK>;
321 clock-names = "iface";
322 #address-cells = <1>;
323 #size-cells = <1>;
324 ranges;
325 status = "disabled";
326
327 syscon-tcsr = <&tcsr>;
328
329 serial@1a240000 {
330 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
331 reg = <0x1a240000 0x1000>,
332 <0x1a200000 0x1000>;
333 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
335 clock-names = "core", "iface";
336 status = "disabled";
337 };
338
339 i2c@1a280000 {
340 compatible = "qcom,i2c-qup-v1.1.1";
341 reg = <0x1a280000 0x1000>;
342 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
343
344 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
345 clock-names = "core", "iface";
346 status = "disabled";
347
348 #address-cells = <1>;
349 #size-cells = <0>;
350 };
351
352 spi@1a280000 {
353 compatible = "qcom,spi-qup-v1.1.1";
354 reg = <0x1a280000 0x1000>;
355 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
356
357 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
358 clock-names = "core", "iface";
359 status = "disabled";
360
361 #address-cells = <1>;
362 #size-cells = <0>;
363 };
364 };
365
366 gsbi7: gsbi@16600000 {
367 status = "disabled";
368 compatible = "qcom,gsbi-v1.0.0";
369 cell-index = <7>;
370 reg = <0x16600000 0x100>;
371 clocks = <&gcc GSBI7_H_CLK>;
372 clock-names = "iface";
373 #address-cells = <1>;
374 #size-cells = <1>;
375 ranges;
376 syscon-tcsr = <&tcsr>;
377
378 gsbi7_serial: serial@16640000 {
379 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
380 reg = <0x16640000 0x1000>,
381 <0x16600000 0x1000>;
382 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
384 clock-names = "core", "iface";
385 status = "disabled";
386 };
387 };
388
389 sata_phy: sata-phy@1b400000 {
390 compatible = "qcom,ipq806x-sata-phy";
391 reg = <0x1b400000 0x200>;
392
393 clocks = <&gcc SATA_PHY_CFG_CLK>;
394 clock-names = "cfg";
395
396 #phy-cells = <0>;
397 status = "disabled";
398 };
399
400 sata@29000000 {
401 compatible = "qcom,ipq806x-ahci", "generic-ahci";
402 reg = <0x29000000 0x180>;
403
404 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
405
406 clocks = <&gcc SFAB_SATA_S_H_CLK>,
407 <&gcc SATA_H_CLK>,
408 <&gcc SATA_A_CLK>,
409 <&gcc SATA_RXOOB_CLK>,
410 <&gcc SATA_PMALIVE_CLK>;
411 clock-names = "slave_face", "iface", "core",
412 "rxoob", "pmalive";
413
414 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
415 assigned-clock-rates = <100000000>, <100000000>;
416
417 phys = <&sata_phy>;
418 phy-names = "sata-phy";
419 status = "disabled";
420 };
421
422 qcom,ssbi@500000 {
423 compatible = "qcom,ssbi";
424 reg = <0x00500000 0x1000>;
425 qcom,controller-type = "pmic-arbiter";
426 };
427
428 qfprom: qfprom@700000 {
429 compatible = "qcom,qfprom";
430 reg = <0x00700000 0x1000>;
431 #address-cells = <1>;
432 #size-cells = <1>;
433 };
434
435 gcc: clock-controller@900000 {
436 compatible = "qcom,gcc-ipq8064";
437 reg = <0x00900000 0x4000>;
438 #clock-cells = <1>;
439 #reset-cells = <1>;
440 };
441
442 tcsr: syscon@1a400000 {
443 compatible = "qcom,tcsr-ipq8064", "syscon";
444 reg = <0x1a400000 0x100>;
445 };
446
447 lcc: clock-controller@28000000 {
448 compatible = "qcom,lcc-ipq8064";
449 reg = <0x28000000 0x1000>;
450 #clock-cells = <1>;
451 #reset-cells = <1>;
452 };
453
454 pcie0: pci@1b500000 {
455 compatible = "qcom,pcie-ipq8064";
456 reg = <0x1b500000 0x1000
457 0x1b502000 0x80
458 0x1b600000 0x100
459 0x0ff00000 0x100000>;
460 reg-names = "dbi", "elbi", "parf", "config";
461 device_type = "pci";
462 linux,pci-domain = <0>;
463 bus-range = <0x00 0xff>;
464 num-lanes = <1>;
465 #address-cells = <3>;
466 #size-cells = <2>;
467
468 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
469 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
470
471 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
472 interrupt-names = "msi";
473 #interrupt-cells = <1>;
474 interrupt-map-mask = <0 0 0 0x7>;
475 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
476 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
477 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
478 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
479
480 clocks = <&gcc PCIE_A_CLK>,
481 <&gcc PCIE_H_CLK>,
482 <&gcc PCIE_PHY_CLK>,
483 <&gcc PCIE_AUX_CLK>,
484 <&gcc PCIE_ALT_REF_CLK>;
485 clock-names = "core", "iface", "phy", "aux", "ref";
486
487 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
488 assigned-clock-rates = <100000000>;
489
490 resets = <&gcc PCIE_ACLK_RESET>,
491 <&gcc PCIE_HCLK_RESET>,
492 <&gcc PCIE_POR_RESET>,
493 <&gcc PCIE_PCI_RESET>,
494 <&gcc PCIE_PHY_RESET>,
495 <&gcc PCIE_EXT_RESET>;
496 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
497
498 pinctrl-0 = <&pcie0_pins>;
499 pinctrl-names = "default";
500
501 status = "disabled";
502 perst-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
503 };
504
505 pcie1: pci@1b700000 {
506 compatible = "qcom,pcie-ipq8064";
507 reg = <0x1b700000 0x1000
508 0x1b702000 0x80
509 0x1b800000 0x100
510 0x31f00000 0x100000>;
511 reg-names = "dbi", "elbi", "parf", "config";
512 device_type = "pci";
513 linux,pci-domain = <1>;
514 bus-range = <0x00 0xff>;
515 num-lanes = <1>;
516 #address-cells = <3>;
517 #size-cells = <2>;
518
519 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
520 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
521
522 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
523 interrupt-names = "msi";
524 #interrupt-cells = <1>;
525 interrupt-map-mask = <0 0 0 0x7>;
526 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
527 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
528 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
529 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
530
531 clocks = <&gcc PCIE_1_A_CLK>,
532 <&gcc PCIE_1_H_CLK>,
533 <&gcc PCIE_1_PHY_CLK>,
534 <&gcc PCIE_1_AUX_CLK>,
535 <&gcc PCIE_1_ALT_REF_CLK>;
536 clock-names = "core", "iface", "phy", "aux", "ref";
537
538 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
539 assigned-clock-rates = <100000000>;
540
541 resets = <&gcc PCIE_1_ACLK_RESET>,
542 <&gcc PCIE_1_HCLK_RESET>,
543 <&gcc PCIE_1_POR_RESET>,
544 <&gcc PCIE_1_PCI_RESET>,
545 <&gcc PCIE_1_PHY_RESET>,
546 <&gcc PCIE_1_EXT_RESET>;
547 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
548
549 pinctrl-0 = <&pcie1_pins>;
550 pinctrl-names = "default";
551
552 status = "disabled";
553 perst-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
554 };
555
556 pcie2: pci@1b900000 {
557 compatible = "qcom,pcie-ipq8064";
558 reg = <0x1b900000 0x1000
559 0x1b902000 0x80
560 0x1ba00000 0x100
561 0x35f00000 0x100000>;
562 reg-names = "dbi", "elbi", "parf", "config";
563 device_type = "pci";
564 linux,pci-domain = <2>;
565 bus-range = <0x00 0xff>;
566 num-lanes = <1>;
567 #address-cells = <3>;
568 #size-cells = <2>;
569
570 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
571 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
572
573 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
574 interrupt-names = "msi";
575 #interrupt-cells = <1>;
576 interrupt-map-mask = <0 0 0 0x7>;
577 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
578 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
579 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
580 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
581
582 clocks = <&gcc PCIE_2_A_CLK>,
583 <&gcc PCIE_2_H_CLK>,
584 <&gcc PCIE_2_PHY_CLK>,
585 <&gcc PCIE_2_AUX_CLK>,
586 <&gcc PCIE_2_ALT_REF_CLK>;
587 clock-names = "core", "iface", "phy", "aux", "ref";
588
589 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
590 assigned-clock-rates = <100000000>;
591
592 resets = <&gcc PCIE_2_ACLK_RESET>,
593 <&gcc PCIE_2_HCLK_RESET>,
594 <&gcc PCIE_2_POR_RESET>,
595 <&gcc PCIE_2_PCI_RESET>,
596 <&gcc PCIE_2_PHY_RESET>,
597 <&gcc PCIE_2_EXT_RESET>;
598 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
599
600 pinctrl-0 = <&pcie2_pins>;
601 pinctrl-names = "default";
602
603 status = "disabled";
604 perst-gpio = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
605 };
606
607 nss_common: syscon@03000000 {
608 compatible = "syscon";
609 reg = <0x03000000 0x0000FFFF>;
610 };
611
612 qsgmii_csr: syscon@1bb00000 {
613 compatible = "syscon";
614 reg = <0x1bb00000 0x000001FF>;
615 };
616
617 stmmac_axi_setup: stmmac-axi-config {
618 snps,wr_osr_lmt = <7>;
619 snps,rd_osr_lmt = <7>;
620 snps,blen = <16 0 0 0 0 0 0>;
621 };
622
623 gmac0: ethernet@37000000 {
624 device_type = "network";
625 compatible = "qcom,ipq806x-gmac";
626 reg = <0x37000000 0x200000>;
627 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
628 interrupt-names = "macirq";
629
630 snps,axi-config = <&stmmac_axi_setup>;
631 snps,pbl = <32>;
632 snps,aal = <1>;
633
634 qcom,nss-common = <&nss_common>;
635 qcom,qsgmii-csr = <&qsgmii_csr>;
636
637 clocks = <&gcc GMAC_CORE1_CLK>;
638 clock-names = "stmmaceth";
639
640 resets = <&gcc GMAC_CORE1_RESET>;
641 reset-names = "stmmaceth";
642
643 status = "disabled";
644 };
645
646 gmac1: ethernet@37200000 {
647 device_type = "network";
648 compatible = "qcom,ipq806x-gmac";
649 reg = <0x37200000 0x200000>;
650 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
651 interrupt-names = "macirq";
652
653 snps,axi-config = <&stmmac_axi_setup>;
654 snps,pbl = <32>;
655 snps,aal = <1>;
656
657 qcom,nss-common = <&nss_common>;
658 qcom,qsgmii-csr = <&qsgmii_csr>;
659
660 clocks = <&gcc GMAC_CORE2_CLK>;
661 clock-names = "stmmaceth";
662
663 resets = <&gcc GMAC_CORE2_RESET>;
664 reset-names = "stmmaceth";
665
666 status = "disabled";
667 };
668
669 gmac2: ethernet@37400000 {
670 device_type = "network";
671 compatible = "qcom,ipq806x-gmac";
672 reg = <0x37400000 0x200000>;
673 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
674 interrupt-names = "macirq";
675
676 snps,axi-config = <&stmmac_axi_setup>;
677 snps,pbl = <32>;
678 snps,aal = <1>;
679
680 qcom,nss-common = <&nss_common>;
681 qcom,qsgmii-csr = <&qsgmii_csr>;
682
683 clocks = <&gcc GMAC_CORE3_CLK>;
684 clock-names = "stmmaceth";
685
686 resets = <&gcc GMAC_CORE3_RESET>;
687 reset-names = "stmmaceth";
688
689 status = "disabled";
690 };
691
692 gmac3: ethernet@37600000 {
693 device_type = "network";
694 compatible = "qcom,ipq806x-gmac";
695 reg = <0x37600000 0x200000>;
696 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
697 interrupt-names = "macirq";
698
699 snps,axi-config = <&stmmac_axi_setup>;
700 snps,pbl = <32>;
701 snps,aal = <1>;
702
703 qcom,nss-common = <&nss_common>;
704 qcom,qsgmii-csr = <&qsgmii_csr>;
705
706 clocks = <&gcc GMAC_CORE4_CLK>;
707 clock-names = "stmmaceth";
708
709 resets = <&gcc GMAC_CORE4_RESET>;
710 reset-names = "stmmaceth";
711
712 status = "disabled";
713 };
714
715 vsdcc_fixed: vsdcc-regulator {
716 compatible = "regulator-fixed";
717 regulator-name = "SDCC Power";
718 regulator-min-microvolt = <3300000>;
719 regulator-max-microvolt = <3300000>;
720 regulator-always-on;
721 };
722
723 sdcc1bam:dma@12402000 {
724 compatible = "qcom,bam-v1.3.0";
725 reg = <0x12402000 0x8000>;
726 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
727 clocks = <&gcc SDC1_H_CLK>;
728 clock-names = "bam_clk";
729 #dma-cells = <1>;
730 qcom,ee = <0>;
731 };
732
733 sdcc3bam:dma@12182000 {
734 compatible = "qcom,bam-v1.3.0";
735 reg = <0x12182000 0x8000>;
736 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
737 clocks = <&gcc SDC3_H_CLK>;
738 clock-names = "bam_clk";
739 #dma-cells = <1>;
740 qcom,ee = <0>;
741 };
742
743 amba {
744 compatible = "simple-bus";
745 #address-cells = <1>;
746 #size-cells = <1>;
747 ranges;
748
749 sdcc@12400000 {
750 status = "disabled";
751 compatible = "arm,pl18x", "arm,primecell";
752 arm,primecell-periphid = <0x00051180>;
753 reg = <0x12400000 0x2000>;
754 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
755 interrupt-names = "cmd_irq";
756 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
757 clock-names = "mclk", "apb_pclk";
758 bus-width = <8>;
759 max-frequency = <96000000>;
760 non-removable;
761 cap-sd-highspeed;
762 cap-mmc-highspeed;
763 mmc-ddr-1_8v;
764 vmmc-supply = <&vsdcc_fixed>;
765 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
766 dma-names = "tx", "rx";
767 };
768
769 sdcc@12180000 {
770 compatible = "arm,pl18x", "arm,primecell";
771 arm,primecell-periphid = <0x00051180>;
772 status = "disabled";
773 reg = <0x12180000 0x2000>;
774 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
775 interrupt-names = "cmd_irq";
776 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
777 clock-names = "mclk", "apb_pclk";
778 bus-width = <8>;
779 cap-sd-highspeed;
780 cap-mmc-highspeed;
781 max-frequency = <192000000>;
782 #mmc-ddr-1_8v;
783 sd-uhs-sdr104;
784 sd-uhs-ddr50;
785 vqmmc-supply = <&vsdcc_fixed>;
786 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
787 dma-names = "tx", "rx";
788 };
789 };
790 };
791};