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1/*
2 * Atmel MACB Ethernet Controller driver
3 *
4 * Copyright (C) 2004-2006 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _MACB_H
11#define _MACB_H
12
13#include <linux/phy.h>
14#include <linux/ptp_clock_kernel.h>
15#include <linux/net_tstamp.h>
16#include <linux/interrupt.h>
17
18#if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
19#define MACB_EXT_DESC
20#endif
21
22#define MACB_GREGS_NBR 16
23#define MACB_GREGS_VERSION 2
24#define MACB_MAX_QUEUES 8
25
26/* MACB register offsets */
27#define MACB_NCR 0x0000 /* Network Control */
28#define MACB_NCFGR 0x0004 /* Network Config */
29#define MACB_NSR 0x0008 /* Network Status */
30#define MACB_TAR 0x000c /* AT91RM9200 only */
31#define MACB_TCR 0x0010 /* AT91RM9200 only */
32#define MACB_TSR 0x0014 /* Transmit Status */
33#define MACB_RBQP 0x0018 /* RX Q Base Address */
34#define MACB_TBQP 0x001c /* TX Q Base Address */
35#define MACB_RSR 0x0020 /* Receive Status */
36#define MACB_ISR 0x0024 /* Interrupt Status */
37#define MACB_IER 0x0028 /* Interrupt Enable */
38#define MACB_IDR 0x002c /* Interrupt Disable */
39#define MACB_IMR 0x0030 /* Interrupt Mask */
40#define MACB_MAN 0x0034 /* PHY Maintenance */
41#define MACB_PTR 0x0038
42#define MACB_PFR 0x003c
43#define MACB_FTO 0x0040
44#define MACB_SCF 0x0044
45#define MACB_MCF 0x0048
46#define MACB_FRO 0x004c
47#define MACB_FCSE 0x0050
48#define MACB_ALE 0x0054
49#define MACB_DTF 0x0058
50#define MACB_LCOL 0x005c
51#define MACB_EXCOL 0x0060
52#define MACB_TUND 0x0064
53#define MACB_CSE 0x0068
54#define MACB_RRE 0x006c
55#define MACB_ROVR 0x0070
56#define MACB_RSE 0x0074
57#define MACB_ELE 0x0078
58#define MACB_RJA 0x007c
59#define MACB_USF 0x0080
60#define MACB_STE 0x0084
61#define MACB_RLE 0x0088
62#define MACB_TPF 0x008c
63#define MACB_HRB 0x0090
64#define MACB_HRT 0x0094
65#define MACB_SA1B 0x0098
66#define MACB_SA1T 0x009c
67#define MACB_SA2B 0x00a0
68#define MACB_SA2T 0x00a4
69#define MACB_SA3B 0x00a8
70#define MACB_SA3T 0x00ac
71#define MACB_SA4B 0x00b0
72#define MACB_SA4T 0x00b4
73#define MACB_TID 0x00b8
74#define MACB_TPQ 0x00bc
75#define MACB_USRIO 0x00c0
76#define MACB_WOL 0x00c4
77#define MACB_MID 0x00fc
78#define MACB_TBQPH 0x04C8
79#define MACB_RBQPH 0x04D4
80
81/* GEM register offsets. */
82#define GEM_NCFGR 0x0004 /* Network Config */
83#define GEM_USRIO 0x000c /* User IO */
84#define GEM_DMACFG 0x0010 /* DMA Configuration */
85#define GEM_JML 0x0048 /* Jumbo Max Length */
86#define GEM_HRB 0x0080 /* Hash Bottom */
87#define GEM_HRT 0x0084 /* Hash Top */
88#define GEM_SA1B 0x0088 /* Specific1 Bottom */
89#define GEM_SA1T 0x008C /* Specific1 Top */
90#define GEM_SA2B 0x0090 /* Specific2 Bottom */
91#define GEM_SA2T 0x0094 /* Specific2 Top */
92#define GEM_SA3B 0x0098 /* Specific3 Bottom */
93#define GEM_SA3T 0x009C /* Specific3 Top */
94#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
95#define GEM_SA4T 0x00A4 /* Specific4 Top */
96#define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
97#define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
98#define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
99#define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
100#define GEM_OTX 0x0100 /* Octets transmitted */
101#define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
102#define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
103#define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
104#define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
105#define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
106#define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
107#define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
108#define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
109#define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
110#define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
111#define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
112#define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
113#define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
114#define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
115#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
116#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
117#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
118#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
119#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
120#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
121#define GEM_ORX 0x0150 /* Octets received */
122#define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
123#define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
124#define GEM_RXCNT 0x0158 /* Frames Received Counter */
125#define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
126#define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
127#define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
128#define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
129#define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
130#define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
131#define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
132#define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
133#define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
134#define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
135#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
136#define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
137#define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
138#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
139#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
140#define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
141#define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
142#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
143#define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
144#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
145#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
146#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
147#define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
148#define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
149#define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
150#define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
151#define GEM_TA 0x01d8 /* 1588 Timer Adjust */
152#define GEM_TI 0x01dc /* 1588 Timer Increment */
153#define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
154#define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
155#define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
156#define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
157#define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
158#define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
159#define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
160#define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
161#define GEM_DCFG1 0x0280 /* Design Config 1 */
162#define GEM_DCFG2 0x0284 /* Design Config 2 */
163#define GEM_DCFG3 0x0288 /* Design Config 3 */
164#define GEM_DCFG4 0x028c /* Design Config 4 */
165#define GEM_DCFG5 0x0290 /* Design Config 5 */
166#define GEM_DCFG6 0x0294 /* Design Config 6 */
167#define GEM_DCFG7 0x0298 /* Design Config 7 */
168#define GEM_DCFG8 0x029C /* Design Config 8 */
169
170#define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
171#define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
172
173/* Screener Type 2 match registers */
174#define GEM_SCRT2 0x540
175
176/* EtherType registers */
177#define GEM_ETHT 0x06E0
178
179/* Type 2 compare registers */
180#define GEM_T2CMPW0 0x0700
181#define GEM_T2CMPW1 0x0704
182#define T2CMP_OFST(t2idx) (t2idx * 2)
183
184/* type 2 compare registers
185 * each location requires 3 compare regs
186 */
187#define GEM_IP4SRC_CMP(idx) (idx * 3)
188#define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
189#define GEM_PORT_CMP(idx) (idx * 3 + 2)
190
191/* Which screening type 2 EtherType register will be used (0 - 7) */
192#define SCRT2_ETHT 0
193
194#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
195#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
196#define GEM_TBQPH(hw_q) (0x04C8)
197#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
198#define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
199#define GEM_RBQPH(hw_q) (0x04D4)
200#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
201#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
202#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
203
204/* Bitfields in NCR */
205#define MACB_LB_OFFSET 0 /* reserved */
206#define MACB_LB_SIZE 1
207#define MACB_LLB_OFFSET 1 /* Loop back local */
208#define MACB_LLB_SIZE 1
209#define MACB_RE_OFFSET 2 /* Receive enable */
210#define MACB_RE_SIZE 1
211#define MACB_TE_OFFSET 3 /* Transmit enable */
212#define MACB_TE_SIZE 1
213#define MACB_MPE_OFFSET 4 /* Management port enable */
214#define MACB_MPE_SIZE 1
215#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
216#define MACB_CLRSTAT_SIZE 1
217#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
218#define MACB_INCSTAT_SIZE 1
219#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
220#define MACB_WESTAT_SIZE 1
221#define MACB_BP_OFFSET 8 /* Back pressure */
222#define MACB_BP_SIZE 1
223#define MACB_TSTART_OFFSET 9 /* Start transmission */
224#define MACB_TSTART_SIZE 1
225#define MACB_THALT_OFFSET 10 /* Transmit halt */
226#define MACB_THALT_SIZE 1
227#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
228#define MACB_NCR_TPF_SIZE 1
229#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
230#define MACB_TZQ_SIZE 1
231#define MACB_SRTSM_OFFSET 15
232#define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
233#define MACB_OSSMODE_SIZE 1
234
235/* Bitfields in NCFGR */
236#define MACB_SPD_OFFSET 0 /* Speed */
237#define MACB_SPD_SIZE 1
238#define MACB_FD_OFFSET 1 /* Full duplex */
239#define MACB_FD_SIZE 1
240#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
241#define MACB_BIT_RATE_SIZE 1
242#define MACB_JFRAME_OFFSET 3 /* reserved */
243#define MACB_JFRAME_SIZE 1
244#define MACB_CAF_OFFSET 4 /* Copy all frames */
245#define MACB_CAF_SIZE 1
246#define MACB_NBC_OFFSET 5 /* No broadcast */
247#define MACB_NBC_SIZE 1
248#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
249#define MACB_NCFGR_MTI_SIZE 1
250#define MACB_UNI_OFFSET 7 /* Unicast hash enable */
251#define MACB_UNI_SIZE 1
252#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
253#define MACB_BIG_SIZE 1
254#define MACB_EAE_OFFSET 9 /* External address match enable */
255#define MACB_EAE_SIZE 1
256#define MACB_CLK_OFFSET 10
257#define MACB_CLK_SIZE 2
258#define MACB_RTY_OFFSET 12 /* Retry test */
259#define MACB_RTY_SIZE 1
260#define MACB_PAE_OFFSET 13 /* Pause enable */
261#define MACB_PAE_SIZE 1
262#define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
263#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
264#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
265#define MACB_RBOF_SIZE 2
266#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
267#define MACB_RLCE_SIZE 1
268#define MACB_DRFCS_OFFSET 17 /* FCS remove */
269#define MACB_DRFCS_SIZE 1
270#define MACB_EFRHD_OFFSET 18
271#define MACB_EFRHD_SIZE 1
272#define MACB_IRXFCS_OFFSET 19
273#define MACB_IRXFCS_SIZE 1
274
275/* GEM specific NCFGR bitfields. */
276#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
277#define GEM_GBE_SIZE 1
278#define GEM_PCSSEL_OFFSET 11
279#define GEM_PCSSEL_SIZE 1
280#define GEM_CLK_OFFSET 18 /* MDC clock division */
281#define GEM_CLK_SIZE 3
282#define GEM_DBW_OFFSET 21 /* Data bus width */
283#define GEM_DBW_SIZE 2
284#define GEM_RXCOEN_OFFSET 24
285#define GEM_RXCOEN_SIZE 1
286#define GEM_SGMIIEN_OFFSET 27
287#define GEM_SGMIIEN_SIZE 1
288
289
290/* Constants for data bus width. */
291#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
292#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
293#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
294
295/* Bitfields in DMACFG. */
296#define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
297#define GEM_FBLDO_SIZE 5
298#define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
299#define GEM_ENDIA_DESC_SIZE 1
300#define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
301#define GEM_ENDIA_PKT_SIZE 1
302#define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
303#define GEM_RXBMS_SIZE 2
304#define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
305#define GEM_TXPBMS_SIZE 1
306#define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
307#define GEM_TXCOEN_SIZE 1
308#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
309#define GEM_RXBS_SIZE 8
310#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
311#define GEM_DDRP_SIZE 1
312#define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
313#define GEM_RXEXT_SIZE 1
314#define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
315#define GEM_TXEXT_SIZE 1
316#define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
317#define GEM_ADDR64_SIZE 1
318
319
320/* Bitfields in NSR */
321#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
322#define MACB_NSR_LINK_SIZE 1
323#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
324#define MACB_MDIO_SIZE 1
325#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
326#define MACB_IDLE_SIZE 1
327
328/* Bitfields in TSR */
329#define MACB_UBR_OFFSET 0 /* Used bit read */
330#define MACB_UBR_SIZE 1
331#define MACB_COL_OFFSET 1 /* Collision occurred */
332#define MACB_COL_SIZE 1
333#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
334#define MACB_TSR_RLE_SIZE 1
335#define MACB_TGO_OFFSET 3 /* Transmit go */
336#define MACB_TGO_SIZE 1
337#define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
338#define MACB_BEX_SIZE 1
339#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
340#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
341#define MACB_COMP_OFFSET 5 /* Trnasmit complete */
342#define MACB_COMP_SIZE 1
343#define MACB_UND_OFFSET 6 /* Trnasmit under run */
344#define MACB_UND_SIZE 1
345
346/* Bitfields in RSR */
347#define MACB_BNA_OFFSET 0 /* Buffer not available */
348#define MACB_BNA_SIZE 1
349#define MACB_REC_OFFSET 1 /* Frame received */
350#define MACB_REC_SIZE 1
351#define MACB_OVR_OFFSET 2 /* Receive overrun */
352#define MACB_OVR_SIZE 1
353
354/* Bitfields in ISR/IER/IDR/IMR */
355#define MACB_MFD_OFFSET 0 /* Management frame sent */
356#define MACB_MFD_SIZE 1
357#define MACB_RCOMP_OFFSET 1 /* Receive complete */
358#define MACB_RCOMP_SIZE 1
359#define MACB_RXUBR_OFFSET 2 /* RX used bit read */
360#define MACB_RXUBR_SIZE 1
361#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
362#define MACB_TXUBR_SIZE 1
363#define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
364#define MACB_ISR_TUND_SIZE 1
365#define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
366#define MACB_ISR_RLE_SIZE 1
367#define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
368#define MACB_TXERR_SIZE 1
369#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
370#define MACB_TCOMP_SIZE 1
371#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
372#define MACB_ISR_LINK_SIZE 1
373#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
374#define MACB_ISR_ROVR_SIZE 1
375#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
376#define MACB_HRESP_SIZE 1
377#define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
378#define MACB_PFR_SIZE 1
379#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
380#define MACB_PTZ_SIZE 1
381#define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
382#define MACB_WOL_SIZE 1
383#define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
384#define MACB_DRQFR_SIZE 1
385#define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
386#define MACB_SFR_SIZE 1
387#define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
388#define MACB_DRQFT_SIZE 1
389#define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
390#define MACB_SFT_SIZE 1
391#define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
392#define MACB_PDRQFR_SIZE 1
393#define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
394#define MACB_PDRSFR_SIZE 1
395#define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
396#define MACB_PDRQFT_SIZE 1
397#define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
398#define MACB_PDRSFT_SIZE 1
399#define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
400#define MACB_SRI_SIZE 1
401
402/* Timer increment fields */
403#define MACB_TI_CNS_OFFSET 0
404#define MACB_TI_CNS_SIZE 8
405#define MACB_TI_ACNS_OFFSET 8
406#define MACB_TI_ACNS_SIZE 8
407#define MACB_TI_NIT_OFFSET 16
408#define MACB_TI_NIT_SIZE 8
409
410/* Bitfields in MAN */
411#define MACB_DATA_OFFSET 0 /* data */
412#define MACB_DATA_SIZE 16
413#define MACB_CODE_OFFSET 16 /* Must be written to 10 */
414#define MACB_CODE_SIZE 2
415#define MACB_REGA_OFFSET 18 /* Register address */
416#define MACB_REGA_SIZE 5
417#define MACB_PHYA_OFFSET 23 /* PHY address */
418#define MACB_PHYA_SIZE 5
419#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
420#define MACB_RW_SIZE 2
421#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
422#define MACB_SOF_SIZE 2
423
424/* Bitfields in USRIO (AVR32) */
425#define MACB_MII_OFFSET 0
426#define MACB_MII_SIZE 1
427#define MACB_EAM_OFFSET 1
428#define MACB_EAM_SIZE 1
429#define MACB_TX_PAUSE_OFFSET 2
430#define MACB_TX_PAUSE_SIZE 1
431#define MACB_TX_PAUSE_ZERO_OFFSET 3
432#define MACB_TX_PAUSE_ZERO_SIZE 1
433
434/* Bitfields in USRIO (AT91) */
435#define MACB_RMII_OFFSET 0
436#define MACB_RMII_SIZE 1
437#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
438#define GEM_RGMII_SIZE 1
439#define MACB_CLKEN_OFFSET 1
440#define MACB_CLKEN_SIZE 1
441
442/* Bitfields in WOL */
443#define MACB_IP_OFFSET 0
444#define MACB_IP_SIZE 16
445#define MACB_MAG_OFFSET 16
446#define MACB_MAG_SIZE 1
447#define MACB_ARP_OFFSET 17
448#define MACB_ARP_SIZE 1
449#define MACB_SA1_OFFSET 18
450#define MACB_SA1_SIZE 1
451#define MACB_WOL_MTI_OFFSET 19
452#define MACB_WOL_MTI_SIZE 1
453
454/* Bitfields in MID */
455#define MACB_IDNUM_OFFSET 16
456#define MACB_IDNUM_SIZE 12
457#define MACB_REV_OFFSET 0
458#define MACB_REV_SIZE 16
459
460/* Bitfields in DCFG1. */
461#define GEM_IRQCOR_OFFSET 23
462#define GEM_IRQCOR_SIZE 1
463#define GEM_DBWDEF_OFFSET 25
464#define GEM_DBWDEF_SIZE 3
465
466/* Bitfields in DCFG2. */
467#define GEM_RX_PKT_BUFF_OFFSET 20
468#define GEM_RX_PKT_BUFF_SIZE 1
469#define GEM_TX_PKT_BUFF_OFFSET 21
470#define GEM_TX_PKT_BUFF_SIZE 1
471
472
473/* Bitfields in DCFG5. */
474#define GEM_TSU_OFFSET 8
475#define GEM_TSU_SIZE 1
476
477/* Bitfields in DCFG6. */
478#define GEM_PBUF_LSO_OFFSET 27
479#define GEM_PBUF_LSO_SIZE 1
480#define GEM_DAW64_OFFSET 23
481#define GEM_DAW64_SIZE 1
482
483/* Bitfields in DCFG8. */
484#define GEM_T1SCR_OFFSET 24
485#define GEM_T1SCR_SIZE 8
486#define GEM_T2SCR_OFFSET 16
487#define GEM_T2SCR_SIZE 8
488#define GEM_SCR2ETH_OFFSET 8
489#define GEM_SCR2ETH_SIZE 8
490#define GEM_SCR2CMP_OFFSET 0
491#define GEM_SCR2CMP_SIZE 8
492
493/* Bitfields in TISUBN */
494#define GEM_SUBNSINCR_OFFSET 0
495#define GEM_SUBNSINCR_SIZE 16
496
497/* Bitfields in TI */
498#define GEM_NSINCR_OFFSET 0
499#define GEM_NSINCR_SIZE 8
500
501/* Bitfields in TSH */
502#define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
503#define GEM_TSH_SIZE 16
504
505/* Bitfields in TSL */
506#define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
507#define GEM_TSL_SIZE 32
508
509/* Bitfields in TN */
510#define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
511#define GEM_TN_SIZE 30
512
513/* Bitfields in TXBDCTRL */
514#define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
515#define GEM_TXTSMODE_SIZE 2
516
517/* Bitfields in RXBDCTRL */
518#define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
519#define GEM_RXTSMODE_SIZE 2
520
521/* Bitfields in SCRT2 */
522#define GEM_QUEUE_OFFSET 0 /* Queue Number */
523#define GEM_QUEUE_SIZE 4
524#define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
525#define GEM_VLANPR_SIZE 3
526#define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
527#define GEM_VLANEN_SIZE 1
528#define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
529#define GEM_ETHT2IDX_SIZE 3
530#define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
531#define GEM_ETHTEN_SIZE 1
532#define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
533#define GEM_CMPA_SIZE 5
534#define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
535#define GEM_CMPAEN_SIZE 1
536#define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
537#define GEM_CMPB_SIZE 5
538#define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
539#define GEM_CMPBEN_SIZE 1
540#define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
541#define GEM_CMPC_SIZE 5
542#define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
543#define GEM_CMPCEN_SIZE 1
544
545/* Bitfields in ETHT */
546#define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
547#define GEM_ETHTCMP_SIZE 16
548
549/* Bitfields in T2CMPW0 */
550#define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
551#define GEM_T2CMP_SIZE 16
552#define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
553#define GEM_T2MASK_SIZE 16
554
555/* Bitfields in T2CMPW1 */
556#define GEM_T2DISMSK_OFFSET 9 /* disable mask */
557#define GEM_T2DISMSK_SIZE 1
558#define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
559#define GEM_T2CMPOFST_SIZE 2
560#define GEM_T2OFST_OFFSET 0 /* offset value */
561#define GEM_T2OFST_SIZE 7
562
563/* Offset for screener type 2 compare values (T2CMPOFST).
564 * Note the offset is applied after the specified point,
565 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
566 * of 12 bytes from this would be the source IP address in an IP header
567 */
568#define GEM_T2COMPOFST_SOF 0
569#define GEM_T2COMPOFST_ETYPE 1
570#define GEM_T2COMPOFST_IPHDR 2
571#define GEM_T2COMPOFST_TCPUDP 3
572
573/* offset from EtherType to IP address */
574#define ETYPE_SRCIP_OFFSET 12
575#define ETYPE_DSTIP_OFFSET 16
576
577/* offset from IP header to port */
578#define IPHDR_SRCPORT_OFFSET 0
579#define IPHDR_DSTPORT_OFFSET 2
580
581/* Transmit DMA buffer descriptor Word 1 */
582#define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
583#define GEM_DMA_TXVALID_SIZE 1
584
585/* Receive DMA buffer descriptor Word 0 */
586#define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
587#define GEM_DMA_RXVALID_SIZE 1
588
589/* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
590#define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
591#define GEM_DMA_SECL_SIZE 2
592#define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
593#define GEM_DMA_NSEC_SIZE 30
594
595/* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
596
597/* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
598 * Old hardware supports only 6 bit precision but it is enough for PTP.
599 * Less accuracy is used always instead of checking hardware version.
600 */
601#define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
602#define GEM_DMA_SECH_SIZE 4
603#define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
604#define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
605#define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
606
607/* Bitfields in ADJ */
608#define GEM_ADDSUB_OFFSET 31
609#define GEM_ADDSUB_SIZE 1
610/* Constants for CLK */
611#define MACB_CLK_DIV8 0
612#define MACB_CLK_DIV16 1
613#define MACB_CLK_DIV32 2
614#define MACB_CLK_DIV64 3
615
616/* GEM specific constants for CLK. */
617#define GEM_CLK_DIV8 0
618#define GEM_CLK_DIV16 1
619#define GEM_CLK_DIV32 2
620#define GEM_CLK_DIV48 3
621#define GEM_CLK_DIV64 4
622#define GEM_CLK_DIV96 5
623
624/* Constants for MAN register */
625#define MACB_MAN_SOF 1
626#define MACB_MAN_WRITE 1
627#define MACB_MAN_READ 2
628#define MACB_MAN_CODE 2
629
630/* Capability mask bits */
631#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
632#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
633#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
634#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
635#define MACB_CAPS_USRIO_DISABLED 0x00000010
636#define MACB_CAPS_JUMBO 0x00000020
637#define MACB_CAPS_GEM_HAS_PTP 0x00000040
638#define MACB_CAPS_FIFO_MODE 0x10000000
639#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
640#define MACB_CAPS_SG_DISABLED 0x40000000
641#define MACB_CAPS_MACB_IS_GEM 0x80000000
642
643/* LSO settings */
644#define MACB_LSO_UFO_ENABLE 0x01
645#define MACB_LSO_TSO_ENABLE 0x02
646
647/* Bit manipulation macros */
648#define MACB_BIT(name) \
649 (1 << MACB_##name##_OFFSET)
650#define MACB_BF(name,value) \
651 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
652 << MACB_##name##_OFFSET)
653#define MACB_BFEXT(name,value)\
654 (((value) >> MACB_##name##_OFFSET) \
655 & ((1 << MACB_##name##_SIZE) - 1))
656#define MACB_BFINS(name,value,old) \
657 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
658 << MACB_##name##_OFFSET)) \
659 | MACB_BF(name,value))
660
661#define GEM_BIT(name) \
662 (1 << GEM_##name##_OFFSET)
663#define GEM_BF(name, value) \
664 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
665 << GEM_##name##_OFFSET)
666#define GEM_BFEXT(name, value)\
667 (((value) >> GEM_##name##_OFFSET) \
668 & ((1 << GEM_##name##_SIZE) - 1))
669#define GEM_BFINS(name, value, old) \
670 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
671 << GEM_##name##_OFFSET)) \
672 | GEM_BF(name, value))
673
674/* Register access macros */
675#define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
676#define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
677#define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
678#define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
679#define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
680#define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
681#define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
682#define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
683
684#define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */
685
686/* Conditional GEM/MACB macros. These perform the operation to the correct
687 * register dependent on whether the device is a GEM or a MACB. For registers
688 * and bitfields that are common across both devices, use macb_{read,write}l
689 * to avoid the cost of the conditional.
690 */
691#define macb_or_gem_writel(__bp, __reg, __value) \
692 ({ \
693 if (macb_is_gem((__bp))) \
694 gem_writel((__bp), __reg, __value); \
695 else \
696 macb_writel((__bp), __reg, __value); \
697 })
698
699#define macb_or_gem_readl(__bp, __reg) \
700 ({ \
701 u32 __v; \
702 if (macb_is_gem((__bp))) \
703 __v = gem_readl((__bp), __reg); \
704 else \
705 __v = macb_readl((__bp), __reg); \
706 __v; \
707 })
708
709/* struct macb_dma_desc - Hardware DMA descriptor
710 * @addr: DMA address of data buffer
711 * @ctrl: Control and status bits
712 */
713struct macb_dma_desc {
714 u32 addr;
715 u32 ctrl;
716};
717
718#ifdef MACB_EXT_DESC
719#define HW_DMA_CAP_32B 0
720#define HW_DMA_CAP_64B (1 << 0)
721#define HW_DMA_CAP_PTP (1 << 1)
722#define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
723
724struct macb_dma_desc_64 {
725 u32 addrh;
726 u32 resvd;
727};
728
729struct macb_dma_desc_ptp {
730 u32 ts_1;
731 u32 ts_2;
732};
733
734struct gem_tx_ts {
735 struct sk_buff *skb;
736 struct macb_dma_desc_ptp desc_ptp;
737};
738#endif
739
740/* DMA descriptor bitfields */
741#define MACB_RX_USED_OFFSET 0
742#define MACB_RX_USED_SIZE 1
743#define MACB_RX_WRAP_OFFSET 1
744#define MACB_RX_WRAP_SIZE 1
745#define MACB_RX_WADDR_OFFSET 2
746#define MACB_RX_WADDR_SIZE 30
747
748#define MACB_RX_FRMLEN_OFFSET 0
749#define MACB_RX_FRMLEN_SIZE 12
750#define MACB_RX_OFFSET_OFFSET 12
751#define MACB_RX_OFFSET_SIZE 2
752#define MACB_RX_SOF_OFFSET 14
753#define MACB_RX_SOF_SIZE 1
754#define MACB_RX_EOF_OFFSET 15
755#define MACB_RX_EOF_SIZE 1
756#define MACB_RX_CFI_OFFSET 16
757#define MACB_RX_CFI_SIZE 1
758#define MACB_RX_VLAN_PRI_OFFSET 17
759#define MACB_RX_VLAN_PRI_SIZE 3
760#define MACB_RX_PRI_TAG_OFFSET 20
761#define MACB_RX_PRI_TAG_SIZE 1
762#define MACB_RX_VLAN_TAG_OFFSET 21
763#define MACB_RX_VLAN_TAG_SIZE 1
764#define MACB_RX_TYPEID_MATCH_OFFSET 22
765#define MACB_RX_TYPEID_MATCH_SIZE 1
766#define MACB_RX_SA4_MATCH_OFFSET 23
767#define MACB_RX_SA4_MATCH_SIZE 1
768#define MACB_RX_SA3_MATCH_OFFSET 24
769#define MACB_RX_SA3_MATCH_SIZE 1
770#define MACB_RX_SA2_MATCH_OFFSET 25
771#define MACB_RX_SA2_MATCH_SIZE 1
772#define MACB_RX_SA1_MATCH_OFFSET 26
773#define MACB_RX_SA1_MATCH_SIZE 1
774#define MACB_RX_EXT_MATCH_OFFSET 28
775#define MACB_RX_EXT_MATCH_SIZE 1
776#define MACB_RX_UHASH_MATCH_OFFSET 29
777#define MACB_RX_UHASH_MATCH_SIZE 1
778#define MACB_RX_MHASH_MATCH_OFFSET 30
779#define MACB_RX_MHASH_MATCH_SIZE 1
780#define MACB_RX_BROADCAST_OFFSET 31
781#define MACB_RX_BROADCAST_SIZE 1
782
783#define MACB_RX_FRMLEN_MASK 0xFFF
784#define MACB_RX_JFRMLEN_MASK 0x3FFF
785
786/* RX checksum offload disabled: bit 24 clear in NCFGR */
787#define GEM_RX_TYPEID_MATCH_OFFSET 22
788#define GEM_RX_TYPEID_MATCH_SIZE 2
789
790/* RX checksum offload enabled: bit 24 set in NCFGR */
791#define GEM_RX_CSUM_OFFSET 22
792#define GEM_RX_CSUM_SIZE 2
793
794#define MACB_TX_FRMLEN_OFFSET 0
795#define MACB_TX_FRMLEN_SIZE 11
796#define MACB_TX_LAST_OFFSET 15
797#define MACB_TX_LAST_SIZE 1
798#define MACB_TX_NOCRC_OFFSET 16
799#define MACB_TX_NOCRC_SIZE 1
800#define MACB_MSS_MFS_OFFSET 16
801#define MACB_MSS_MFS_SIZE 14
802#define MACB_TX_LSO_OFFSET 17
803#define MACB_TX_LSO_SIZE 2
804#define MACB_TX_TCP_SEQ_SRC_OFFSET 19
805#define MACB_TX_TCP_SEQ_SRC_SIZE 1
806#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
807#define MACB_TX_BUF_EXHAUSTED_SIZE 1
808#define MACB_TX_UNDERRUN_OFFSET 28
809#define MACB_TX_UNDERRUN_SIZE 1
810#define MACB_TX_ERROR_OFFSET 29
811#define MACB_TX_ERROR_SIZE 1
812#define MACB_TX_WRAP_OFFSET 30
813#define MACB_TX_WRAP_SIZE 1
814#define MACB_TX_USED_OFFSET 31
815#define MACB_TX_USED_SIZE 1
816
817#define GEM_TX_FRMLEN_OFFSET 0
818#define GEM_TX_FRMLEN_SIZE 14
819
820/* Buffer descriptor constants */
821#define GEM_RX_CSUM_NONE 0
822#define GEM_RX_CSUM_IP_ONLY 1
823#define GEM_RX_CSUM_IP_TCP 2
824#define GEM_RX_CSUM_IP_UDP 3
825
826/* limit RX checksum offload to TCP and UDP packets */
827#define GEM_RX_CSUM_CHECKED_MASK 2
828
829/* struct macb_tx_skb - data about an skb which is being transmitted
830 * @skb: skb currently being transmitted, only set for the last buffer
831 * of the frame
832 * @mapping: DMA address of the skb's fragment buffer
833 * @size: size of the DMA mapped buffer
834 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
835 * false when buffer was mapped with dma_map_single()
836 */
837struct macb_tx_skb {
838 struct sk_buff *skb;
839 dma_addr_t mapping;
840 size_t size;
841 bool mapped_as_page;
842};
843
844/* Hardware-collected statistics. Used when updating the network
845 * device stats by a periodic timer.
846 */
847struct macb_stats {
848 u32 rx_pause_frames;
849 u32 tx_ok;
850 u32 tx_single_cols;
851 u32 tx_multiple_cols;
852 u32 rx_ok;
853 u32 rx_fcs_errors;
854 u32 rx_align_errors;
855 u32 tx_deferred;
856 u32 tx_late_cols;
857 u32 tx_excessive_cols;
858 u32 tx_underruns;
859 u32 tx_carrier_errors;
860 u32 rx_resource_errors;
861 u32 rx_overruns;
862 u32 rx_symbol_errors;
863 u32 rx_oversize_pkts;
864 u32 rx_jabbers;
865 u32 rx_undersize_pkts;
866 u32 sqe_test_errors;
867 u32 rx_length_mismatch;
868 u32 tx_pause_frames;
869};
870
871struct gem_stats {
872 u32 tx_octets_31_0;
873 u32 tx_octets_47_32;
874 u32 tx_frames;
875 u32 tx_broadcast_frames;
876 u32 tx_multicast_frames;
877 u32 tx_pause_frames;
878 u32 tx_64_byte_frames;
879 u32 tx_65_127_byte_frames;
880 u32 tx_128_255_byte_frames;
881 u32 tx_256_511_byte_frames;
882 u32 tx_512_1023_byte_frames;
883 u32 tx_1024_1518_byte_frames;
884 u32 tx_greater_than_1518_byte_frames;
885 u32 tx_underrun;
886 u32 tx_single_collision_frames;
887 u32 tx_multiple_collision_frames;
888 u32 tx_excessive_collisions;
889 u32 tx_late_collisions;
890 u32 tx_deferred_frames;
891 u32 tx_carrier_sense_errors;
892 u32 rx_octets_31_0;
893 u32 rx_octets_47_32;
894 u32 rx_frames;
895 u32 rx_broadcast_frames;
896 u32 rx_multicast_frames;
897 u32 rx_pause_frames;
898 u32 rx_64_byte_frames;
899 u32 rx_65_127_byte_frames;
900 u32 rx_128_255_byte_frames;
901 u32 rx_256_511_byte_frames;
902 u32 rx_512_1023_byte_frames;
903 u32 rx_1024_1518_byte_frames;
904 u32 rx_greater_than_1518_byte_frames;
905 u32 rx_undersized_frames;
906 u32 rx_oversize_frames;
907 u32 rx_jabbers;
908 u32 rx_frame_check_sequence_errors;
909 u32 rx_length_field_frame_errors;
910 u32 rx_symbol_errors;
911 u32 rx_alignment_errors;
912 u32 rx_resource_errors;
913 u32 rx_overruns;
914 u32 rx_ip_header_checksum_errors;
915 u32 rx_tcp_checksum_errors;
916 u32 rx_udp_checksum_errors;
917};
918
919/* Describes the name and offset of an individual statistic register, as
920 * returned by `ethtool -S`. Also describes which net_device_stats statistics
921 * this register should contribute to.
922 */
923struct gem_statistic {
924 char stat_string[ETH_GSTRING_LEN];
925 int offset;
926 u32 stat_bits;
927};
928
929/* Bitfield defs for net_device_stat statistics */
930#define GEM_NDS_RXERR_OFFSET 0
931#define GEM_NDS_RXLENERR_OFFSET 1
932#define GEM_NDS_RXOVERERR_OFFSET 2
933#define GEM_NDS_RXCRCERR_OFFSET 3
934#define GEM_NDS_RXFRAMEERR_OFFSET 4
935#define GEM_NDS_RXFIFOERR_OFFSET 5
936#define GEM_NDS_TXERR_OFFSET 6
937#define GEM_NDS_TXABORTEDERR_OFFSET 7
938#define GEM_NDS_TXCARRIERERR_OFFSET 8
939#define GEM_NDS_TXFIFOERR_OFFSET 9
940#define GEM_NDS_COLLISIONS_OFFSET 10
941
942#define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
943#define GEM_STAT_TITLE_BITS(name, title, bits) { \
944 .stat_string = title, \
945 .offset = GEM_##name, \
946 .stat_bits = bits \
947}
948
949/* list of gem statistic registers. The names MUST match the
950 * corresponding GEM_* definitions.
951 */
952static const struct gem_statistic gem_statistics[] = {
953 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
954 GEM_STAT_TITLE(TXCNT, "tx_frames"),
955 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
956 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
957 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
958 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
959 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
960 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
961 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
962 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
963 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
964 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
965 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
966 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
967 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
968 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
969 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
970 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
971 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
972 GEM_BIT(NDS_TXERR)|
973 GEM_BIT(NDS_TXABORTEDERR)|
974 GEM_BIT(NDS_COLLISIONS)),
975 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
976 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
977 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
978 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
979 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
980 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
981 GEM_STAT_TITLE(RXCNT, "rx_frames"),
982 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
983 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
984 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
985 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
986 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
987 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
988 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
989 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
990 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
991 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
992 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
993 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
994 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
995 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
996 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
997 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
998 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
999 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
1000 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
1001 GEM_BIT(NDS_RXERR)),
1002 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
1003 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
1004 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
1005 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1006 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
1007 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1008 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
1009 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
1010 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
1011 GEM_BIT(NDS_RXERR)),
1012 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
1013 GEM_BIT(NDS_RXERR)),
1014 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
1015 GEM_BIT(NDS_RXERR)),
1016};
1017
1018#define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
1019
1020#define QUEUE_STAT_TITLE(title) { \
1021 .stat_string = title, \
1022}
1023
1024/* per queue statistics, each should be unsigned long type */
1025struct queue_stats {
1026 union {
1027 unsigned long first;
1028 unsigned long rx_packets;
1029 };
1030 unsigned long rx_bytes;
1031 unsigned long rx_dropped;
1032 unsigned long tx_packets;
1033 unsigned long tx_bytes;
1034 unsigned long tx_dropped;
1035};
1036
1037static const struct gem_statistic queue_statistics[] = {
1038 QUEUE_STAT_TITLE("rx_packets"),
1039 QUEUE_STAT_TITLE("rx_bytes"),
1040 QUEUE_STAT_TITLE("rx_dropped"),
1041 QUEUE_STAT_TITLE("tx_packets"),
1042 QUEUE_STAT_TITLE("tx_bytes"),
1043 QUEUE_STAT_TITLE("tx_dropped"),
1044};
1045
1046#define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
1047
1048struct macb;
1049struct macb_queue;
1050
1051struct macb_or_gem_ops {
1052 int (*mog_alloc_rx_buffers)(struct macb *bp);
1053 void (*mog_free_rx_buffers)(struct macb *bp);
1054 void (*mog_init_rings)(struct macb *bp);
1055 int (*mog_rx)(struct macb_queue *queue, int budget);
1056};
1057
1058/* MACB-PTP interface: adapt to platform needs. */
1059struct macb_ptp_info {
1060 void (*ptp_init)(struct net_device *ndev);
1061 void (*ptp_remove)(struct net_device *ndev);
1062 s32 (*get_ptp_max_adj)(void);
1063 unsigned int (*get_tsu_rate)(struct macb *bp);
1064 int (*get_ts_info)(struct net_device *dev,
1065 struct ethtool_ts_info *info);
1066 int (*get_hwtst)(struct net_device *netdev,
1067 struct ifreq *ifr);
1068 int (*set_hwtst)(struct net_device *netdev,
1069 struct ifreq *ifr, int cmd);
1070};
1071
1072struct macb_config {
1073 u32 caps;
1074 unsigned int dma_burst_length;
1075 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
1076 struct clk **hclk, struct clk **tx_clk,
1077 struct clk **rx_clk);
1078 int (*init)(struct platform_device *pdev);
1079 int jumbo_max_len;
1080};
1081
1082struct tsu_incr {
1083 u32 sub_ns;
1084 u32 ns;
1085};
1086
1087struct macb_queue {
1088 struct macb *bp;
1089 int irq;
1090
1091 unsigned int ISR;
1092 unsigned int IER;
1093 unsigned int IDR;
1094 unsigned int IMR;
1095 unsigned int TBQP;
1096 unsigned int TBQPH;
1097 unsigned int RBQS;
1098 unsigned int RBQP;
1099 unsigned int RBQPH;
1100
1101 unsigned int tx_head, tx_tail;
1102 struct macb_dma_desc *tx_ring;
1103 struct macb_tx_skb *tx_skb;
1104 dma_addr_t tx_ring_dma;
1105 struct work_struct tx_error_task;
1106
1107 dma_addr_t rx_ring_dma;
1108 dma_addr_t rx_buffers_dma;
1109 unsigned int rx_tail;
1110 unsigned int rx_prepared_head;
1111 struct macb_dma_desc *rx_ring;
1112 struct sk_buff **rx_skbuff;
1113 void *rx_buffers;
1114 struct napi_struct napi;
1115 struct queue_stats stats;
1116
1117#ifdef CONFIG_MACB_USE_HWSTAMP
1118 struct work_struct tx_ts_task;
1119 unsigned int tx_ts_head, tx_ts_tail;
1120 struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE];
1121#endif
1122};
1123
1124struct ethtool_rx_fs_item {
1125 struct ethtool_rx_flow_spec fs;
1126 struct list_head list;
1127};
1128
1129struct ethtool_rx_fs_list {
1130 struct list_head list;
1131 unsigned int count;
1132};
1133
1134struct macb {
1135 void __iomem *regs;
1136 bool native_io;
1137
1138 /* hardware IO accessors */
1139 u32 (*macb_reg_readl)(struct macb *bp, int offset);
1140 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
1141
1142 size_t rx_buffer_size;
1143
1144 unsigned int rx_ring_size;
1145 unsigned int tx_ring_size;
1146
1147 unsigned int num_queues;
1148 unsigned int queue_mask;
1149 struct macb_queue queues[MACB_MAX_QUEUES];
1150
1151 spinlock_t lock;
1152 struct platform_device *pdev;
1153 struct clk *pclk;
1154 struct clk *hclk;
1155 struct clk *tx_clk;
1156 struct clk *rx_clk;
1157 struct net_device *dev;
1158 union {
1159 struct macb_stats macb;
1160 struct gem_stats gem;
1161 } hw_stats;
1162
1163 struct macb_or_gem_ops macbgem_ops;
1164
1165 struct mii_bus *mii_bus;
1166 struct device_node *phy_node;
1167 int link;
1168 int speed;
1169 int duplex;
1170
1171 u32 caps;
1172 unsigned int dma_burst_length;
1173
1174 phy_interface_t phy_interface;
1175
1176 /* AT91RM9200 transmit */
1177 struct sk_buff *skb; /* holds skb until xmit interrupt completes */
1178 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
1179 int skb_length; /* saved skb length for pci_unmap_single */
1180 unsigned int max_tx_length;
1181
1182 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
1183
1184 unsigned int rx_frm_len_mask;
1185 unsigned int jumbo_max_len;
1186
1187 u32 wol;
1188
1189 struct macb_ptp_info *ptp_info; /* macb-ptp interface */
1190#ifdef MACB_EXT_DESC
1191 uint8_t hw_dma_cap;
1192#endif
1193 spinlock_t tsu_clk_lock; /* gem tsu clock locking */
1194 unsigned int tsu_rate;
1195 struct ptp_clock *ptp_clock;
1196 struct ptp_clock_info ptp_clock_info;
1197 struct tsu_incr tsu_incr;
1198 struct hwtstamp_config tstamp_config;
1199
1200 /* RX queue filer rule set*/
1201 struct ethtool_rx_fs_list rx_fs_list;
1202 spinlock_t rx_fs_lock;
1203 unsigned int max_tuples;
1204
1205 struct tasklet_struct hresp_err_tasklet;
1206};
1207
1208#ifdef CONFIG_MACB_USE_HWSTAMP
1209#define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
1210#define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1211#define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1212
1213enum macb_bd_control {
1214 TSTAMP_DISABLED,
1215 TSTAMP_FRAME_PTP_EVENT_ONLY,
1216 TSTAMP_ALL_PTP_FRAMES,
1217 TSTAMP_ALL_FRAMES,
1218};
1219
1220void gem_ptp_init(struct net_device *ndev);
1221void gem_ptp_remove(struct net_device *ndev);
1222int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des);
1223void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
1224static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1225{
1226 if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED)
1227 return -ENOTSUPP;
1228
1229 return gem_ptp_txstamp(queue, skb, desc);
1230}
1231
1232static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1233{
1234 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1235 return;
1236
1237 gem_ptp_rxstamp(bp, skb, desc);
1238}
1239int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);
1240int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);
1241#else
1242static inline void gem_ptp_init(struct net_device *ndev) { }
1243static inline void gem_ptp_remove(struct net_device *ndev) { }
1244
1245static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1246{
1247 return -1;
1248}
1249
1250static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1251#endif
1252
1253static inline bool macb_is_gem(struct macb *bp)
1254{
1255 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1256}
1257
1258static inline bool gem_has_ptp(struct macb *bp)
1259{
1260 return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
1261}
1262
1263#endif /* _MACB_H */
1/* SPDX-License-Identifier: GPL-2.0-only */
2/*
3 * Atmel MACB Ethernet Controller driver
4 *
5 * Copyright (C) 2004-2006 Atmel Corporation
6 */
7#ifndef _MACB_H
8#define _MACB_H
9
10#include <linux/phylink.h>
11#include <linux/ptp_clock_kernel.h>
12#include <linux/net_tstamp.h>
13#include <linux/interrupt.h>
14
15#if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
16#define MACB_EXT_DESC
17#endif
18
19#define MACB_GREGS_NBR 16
20#define MACB_GREGS_VERSION 2
21#define MACB_MAX_QUEUES 8
22
23/* MACB register offsets */
24#define MACB_NCR 0x0000 /* Network Control */
25#define MACB_NCFGR 0x0004 /* Network Config */
26#define MACB_NSR 0x0008 /* Network Status */
27#define MACB_TAR 0x000c /* AT91RM9200 only */
28#define MACB_TCR 0x0010 /* AT91RM9200 only */
29#define MACB_TSR 0x0014 /* Transmit Status */
30#define MACB_RBQP 0x0018 /* RX Q Base Address */
31#define MACB_TBQP 0x001c /* TX Q Base Address */
32#define MACB_RSR 0x0020 /* Receive Status */
33#define MACB_ISR 0x0024 /* Interrupt Status */
34#define MACB_IER 0x0028 /* Interrupt Enable */
35#define MACB_IDR 0x002c /* Interrupt Disable */
36#define MACB_IMR 0x0030 /* Interrupt Mask */
37#define MACB_MAN 0x0034 /* PHY Maintenance */
38#define MACB_PTR 0x0038
39#define MACB_PFR 0x003c
40#define MACB_FTO 0x0040
41#define MACB_SCF 0x0044
42#define MACB_MCF 0x0048
43#define MACB_FRO 0x004c
44#define MACB_FCSE 0x0050
45#define MACB_ALE 0x0054
46#define MACB_DTF 0x0058
47#define MACB_LCOL 0x005c
48#define MACB_EXCOL 0x0060
49#define MACB_TUND 0x0064
50#define MACB_CSE 0x0068
51#define MACB_RRE 0x006c
52#define MACB_ROVR 0x0070
53#define MACB_RSE 0x0074
54#define MACB_ELE 0x0078
55#define MACB_RJA 0x007c
56#define MACB_USF 0x0080
57#define MACB_STE 0x0084
58#define MACB_RLE 0x0088
59#define MACB_TPF 0x008c
60#define MACB_HRB 0x0090
61#define MACB_HRT 0x0094
62#define MACB_SA1B 0x0098
63#define MACB_SA1T 0x009c
64#define MACB_SA2B 0x00a0
65#define MACB_SA2T 0x00a4
66#define MACB_SA3B 0x00a8
67#define MACB_SA3T 0x00ac
68#define MACB_SA4B 0x00b0
69#define MACB_SA4T 0x00b4
70#define MACB_TID 0x00b8
71#define MACB_TPQ 0x00bc
72#define MACB_USRIO 0x00c0
73#define MACB_WOL 0x00c4
74#define MACB_MID 0x00fc
75#define MACB_TBQPH 0x04C8
76#define MACB_RBQPH 0x04D4
77
78/* GEM register offsets. */
79#define GEM_NCFGR 0x0004 /* Network Config */
80#define GEM_USRIO 0x000c /* User IO */
81#define GEM_DMACFG 0x0010 /* DMA Configuration */
82#define GEM_JML 0x0048 /* Jumbo Max Length */
83#define GEM_HRB 0x0080 /* Hash Bottom */
84#define GEM_HRT 0x0084 /* Hash Top */
85#define GEM_SA1B 0x0088 /* Specific1 Bottom */
86#define GEM_SA1T 0x008C /* Specific1 Top */
87#define GEM_SA2B 0x0090 /* Specific2 Bottom */
88#define GEM_SA2T 0x0094 /* Specific2 Top */
89#define GEM_SA3B 0x0098 /* Specific3 Bottom */
90#define GEM_SA3T 0x009C /* Specific3 Top */
91#define GEM_SA4B 0x00A0 /* Specific4 Bottom */
92#define GEM_SA4T 0x00A4 /* Specific4 Top */
93#define GEM_WOL 0x00b8 /* Wake on LAN */
94#define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
95#define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
96#define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
97#define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
98#define GEM_OTX 0x0100 /* Octets transmitted */
99#define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
100#define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
101#define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
102#define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
103#define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
104#define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
105#define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
106#define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
107#define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
108#define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
109#define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
110#define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
111#define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
112#define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
113#define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
114#define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
115#define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
116#define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
117#define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
118#define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
119#define GEM_ORX 0x0150 /* Octets received */
120#define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
121#define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
122#define GEM_RXCNT 0x0158 /* Frames Received Counter */
123#define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
124#define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
125#define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
126#define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
127#define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
128#define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
129#define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
130#define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
131#define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
132#define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
133#define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
134#define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
135#define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
136#define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
137#define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
138#define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
139#define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
140#define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
141#define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
142#define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
143#define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
144#define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
145#define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
146#define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
147#define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
148#define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
149#define GEM_TA 0x01d8 /* 1588 Timer Adjust */
150#define GEM_TI 0x01dc /* 1588 Timer Increment */
151#define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
152#define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
153#define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
154#define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
155#define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
156#define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
157#define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
158#define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
159#define GEM_DCFG1 0x0280 /* Design Config 1 */
160#define GEM_DCFG2 0x0284 /* Design Config 2 */
161#define GEM_DCFG3 0x0288 /* Design Config 3 */
162#define GEM_DCFG4 0x028c /* Design Config 4 */
163#define GEM_DCFG5 0x0290 /* Design Config 5 */
164#define GEM_DCFG6 0x0294 /* Design Config 6 */
165#define GEM_DCFG7 0x0298 /* Design Config 7 */
166#define GEM_DCFG8 0x029C /* Design Config 8 */
167#define GEM_DCFG10 0x02A4 /* Design Config 10 */
168
169#define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
170#define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
171
172/* Screener Type 2 match registers */
173#define GEM_SCRT2 0x540
174
175/* EtherType registers */
176#define GEM_ETHT 0x06E0
177
178/* Type 2 compare registers */
179#define GEM_T2CMPW0 0x0700
180#define GEM_T2CMPW1 0x0704
181#define T2CMP_OFST(t2idx) (t2idx * 2)
182
183/* type 2 compare registers
184 * each location requires 3 compare regs
185 */
186#define GEM_IP4SRC_CMP(idx) (idx * 3)
187#define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
188#define GEM_PORT_CMP(idx) (idx * 3 + 2)
189
190/* Which screening type 2 EtherType register will be used (0 - 7) */
191#define SCRT2_ETHT 0
192
193#define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
194#define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
195#define GEM_TBQPH(hw_q) (0x04C8)
196#define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
197#define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
198#define GEM_RBQPH(hw_q) (0x04D4)
199#define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
200#define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
201#define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
202
203/* Bitfields in NCR */
204#define MACB_LB_OFFSET 0 /* reserved */
205#define MACB_LB_SIZE 1
206#define MACB_LLB_OFFSET 1 /* Loop back local */
207#define MACB_LLB_SIZE 1
208#define MACB_RE_OFFSET 2 /* Receive enable */
209#define MACB_RE_SIZE 1
210#define MACB_TE_OFFSET 3 /* Transmit enable */
211#define MACB_TE_SIZE 1
212#define MACB_MPE_OFFSET 4 /* Management port enable */
213#define MACB_MPE_SIZE 1
214#define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
215#define MACB_CLRSTAT_SIZE 1
216#define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
217#define MACB_INCSTAT_SIZE 1
218#define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
219#define MACB_WESTAT_SIZE 1
220#define MACB_BP_OFFSET 8 /* Back pressure */
221#define MACB_BP_SIZE 1
222#define MACB_TSTART_OFFSET 9 /* Start transmission */
223#define MACB_TSTART_SIZE 1
224#define MACB_THALT_OFFSET 10 /* Transmit halt */
225#define MACB_THALT_SIZE 1
226#define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
227#define MACB_NCR_TPF_SIZE 1
228#define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
229#define MACB_TZQ_SIZE 1
230#define MACB_SRTSM_OFFSET 15
231#define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
232#define MACB_OSSMODE_SIZE 1
233
234/* Bitfields in NCFGR */
235#define MACB_SPD_OFFSET 0 /* Speed */
236#define MACB_SPD_SIZE 1
237#define MACB_FD_OFFSET 1 /* Full duplex */
238#define MACB_FD_SIZE 1
239#define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
240#define MACB_BIT_RATE_SIZE 1
241#define MACB_JFRAME_OFFSET 3 /* reserved */
242#define MACB_JFRAME_SIZE 1
243#define MACB_CAF_OFFSET 4 /* Copy all frames */
244#define MACB_CAF_SIZE 1
245#define MACB_NBC_OFFSET 5 /* No broadcast */
246#define MACB_NBC_SIZE 1
247#define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
248#define MACB_NCFGR_MTI_SIZE 1
249#define MACB_UNI_OFFSET 7 /* Unicast hash enable */
250#define MACB_UNI_SIZE 1
251#define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
252#define MACB_BIG_SIZE 1
253#define MACB_EAE_OFFSET 9 /* External address match enable */
254#define MACB_EAE_SIZE 1
255#define MACB_CLK_OFFSET 10
256#define MACB_CLK_SIZE 2
257#define MACB_RTY_OFFSET 12 /* Retry test */
258#define MACB_RTY_SIZE 1
259#define MACB_PAE_OFFSET 13 /* Pause enable */
260#define MACB_PAE_SIZE 1
261#define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
262#define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
263#define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
264#define MACB_RBOF_SIZE 2
265#define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
266#define MACB_RLCE_SIZE 1
267#define MACB_DRFCS_OFFSET 17 /* FCS remove */
268#define MACB_DRFCS_SIZE 1
269#define MACB_EFRHD_OFFSET 18
270#define MACB_EFRHD_SIZE 1
271#define MACB_IRXFCS_OFFSET 19
272#define MACB_IRXFCS_SIZE 1
273
274/* GEM specific NCFGR bitfields. */
275#define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
276#define GEM_GBE_SIZE 1
277#define GEM_PCSSEL_OFFSET 11
278#define GEM_PCSSEL_SIZE 1
279#define GEM_CLK_OFFSET 18 /* MDC clock division */
280#define GEM_CLK_SIZE 3
281#define GEM_DBW_OFFSET 21 /* Data bus width */
282#define GEM_DBW_SIZE 2
283#define GEM_RXCOEN_OFFSET 24
284#define GEM_RXCOEN_SIZE 1
285#define GEM_SGMIIEN_OFFSET 27
286#define GEM_SGMIIEN_SIZE 1
287
288
289/* Constants for data bus width. */
290#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
291#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
292#define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
293
294/* Bitfields in DMACFG. */
295#define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
296#define GEM_FBLDO_SIZE 5
297#define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
298#define GEM_ENDIA_DESC_SIZE 1
299#define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
300#define GEM_ENDIA_PKT_SIZE 1
301#define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
302#define GEM_RXBMS_SIZE 2
303#define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
304#define GEM_TXPBMS_SIZE 1
305#define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
306#define GEM_TXCOEN_SIZE 1
307#define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
308#define GEM_RXBS_SIZE 8
309#define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
310#define GEM_DDRP_SIZE 1
311#define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
312#define GEM_RXEXT_SIZE 1
313#define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
314#define GEM_TXEXT_SIZE 1
315#define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
316#define GEM_ADDR64_SIZE 1
317
318
319/* Bitfields in NSR */
320#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
321#define MACB_NSR_LINK_SIZE 1
322#define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
323#define MACB_MDIO_SIZE 1
324#define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
325#define MACB_IDLE_SIZE 1
326
327/* Bitfields in TSR */
328#define MACB_UBR_OFFSET 0 /* Used bit read */
329#define MACB_UBR_SIZE 1
330#define MACB_COL_OFFSET 1 /* Collision occurred */
331#define MACB_COL_SIZE 1
332#define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
333#define MACB_TSR_RLE_SIZE 1
334#define MACB_TGO_OFFSET 3 /* Transmit go */
335#define MACB_TGO_SIZE 1
336#define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
337#define MACB_BEX_SIZE 1
338#define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
339#define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
340#define MACB_COMP_OFFSET 5 /* Trnasmit complete */
341#define MACB_COMP_SIZE 1
342#define MACB_UND_OFFSET 6 /* Trnasmit under run */
343#define MACB_UND_SIZE 1
344
345/* Bitfields in RSR */
346#define MACB_BNA_OFFSET 0 /* Buffer not available */
347#define MACB_BNA_SIZE 1
348#define MACB_REC_OFFSET 1 /* Frame received */
349#define MACB_REC_SIZE 1
350#define MACB_OVR_OFFSET 2 /* Receive overrun */
351#define MACB_OVR_SIZE 1
352
353/* Bitfields in ISR/IER/IDR/IMR */
354#define MACB_MFD_OFFSET 0 /* Management frame sent */
355#define MACB_MFD_SIZE 1
356#define MACB_RCOMP_OFFSET 1 /* Receive complete */
357#define MACB_RCOMP_SIZE 1
358#define MACB_RXUBR_OFFSET 2 /* RX used bit read */
359#define MACB_RXUBR_SIZE 1
360#define MACB_TXUBR_OFFSET 3 /* TX used bit read */
361#define MACB_TXUBR_SIZE 1
362#define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
363#define MACB_ISR_TUND_SIZE 1
364#define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
365#define MACB_ISR_RLE_SIZE 1
366#define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
367#define MACB_TXERR_SIZE 1
368#define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
369#define MACB_TCOMP_SIZE 1
370#define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
371#define MACB_ISR_LINK_SIZE 1
372#define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
373#define MACB_ISR_ROVR_SIZE 1
374#define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
375#define MACB_HRESP_SIZE 1
376#define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
377#define MACB_PFR_SIZE 1
378#define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
379#define MACB_PTZ_SIZE 1
380#define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
381#define MACB_WOL_SIZE 1
382#define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
383#define MACB_DRQFR_SIZE 1
384#define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
385#define MACB_SFR_SIZE 1
386#define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
387#define MACB_DRQFT_SIZE 1
388#define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
389#define MACB_SFT_SIZE 1
390#define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
391#define MACB_PDRQFR_SIZE 1
392#define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
393#define MACB_PDRSFR_SIZE 1
394#define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
395#define MACB_PDRQFT_SIZE 1
396#define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
397#define MACB_PDRSFT_SIZE 1
398#define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
399#define MACB_SRI_SIZE 1
400#define GEM_WOL_OFFSET 28 /* Enable wake-on-lan interrupt */
401#define GEM_WOL_SIZE 1
402
403/* Timer increment fields */
404#define MACB_TI_CNS_OFFSET 0
405#define MACB_TI_CNS_SIZE 8
406#define MACB_TI_ACNS_OFFSET 8
407#define MACB_TI_ACNS_SIZE 8
408#define MACB_TI_NIT_OFFSET 16
409#define MACB_TI_NIT_SIZE 8
410
411/* Bitfields in MAN */
412#define MACB_DATA_OFFSET 0 /* data */
413#define MACB_DATA_SIZE 16
414#define MACB_CODE_OFFSET 16 /* Must be written to 10 */
415#define MACB_CODE_SIZE 2
416#define MACB_REGA_OFFSET 18 /* Register address */
417#define MACB_REGA_SIZE 5
418#define MACB_PHYA_OFFSET 23 /* PHY address */
419#define MACB_PHYA_SIZE 5
420#define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
421#define MACB_RW_SIZE 2
422#define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
423#define MACB_SOF_SIZE 2
424
425/* Bitfields in USRIO (AVR32) */
426#define MACB_MII_OFFSET 0
427#define MACB_MII_SIZE 1
428#define MACB_EAM_OFFSET 1
429#define MACB_EAM_SIZE 1
430#define MACB_TX_PAUSE_OFFSET 2
431#define MACB_TX_PAUSE_SIZE 1
432#define MACB_TX_PAUSE_ZERO_OFFSET 3
433#define MACB_TX_PAUSE_ZERO_SIZE 1
434
435/* Bitfields in USRIO (AT91) */
436#define MACB_RMII_OFFSET 0
437#define MACB_RMII_SIZE 1
438#define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
439#define GEM_RGMII_SIZE 1
440#define MACB_CLKEN_OFFSET 1
441#define MACB_CLKEN_SIZE 1
442
443/* Bitfields in WOL */
444#define MACB_IP_OFFSET 0
445#define MACB_IP_SIZE 16
446#define MACB_MAG_OFFSET 16
447#define MACB_MAG_SIZE 1
448#define MACB_ARP_OFFSET 17
449#define MACB_ARP_SIZE 1
450#define MACB_SA1_OFFSET 18
451#define MACB_SA1_SIZE 1
452#define MACB_WOL_MTI_OFFSET 19
453#define MACB_WOL_MTI_SIZE 1
454
455/* Bitfields in MID */
456#define MACB_IDNUM_OFFSET 16
457#define MACB_IDNUM_SIZE 12
458#define MACB_REV_OFFSET 0
459#define MACB_REV_SIZE 16
460
461/* Bitfields in DCFG1. */
462#define GEM_IRQCOR_OFFSET 23
463#define GEM_IRQCOR_SIZE 1
464#define GEM_DBWDEF_OFFSET 25
465#define GEM_DBWDEF_SIZE 3
466
467/* Bitfields in DCFG2. */
468#define GEM_RX_PKT_BUFF_OFFSET 20
469#define GEM_RX_PKT_BUFF_SIZE 1
470#define GEM_TX_PKT_BUFF_OFFSET 21
471#define GEM_TX_PKT_BUFF_SIZE 1
472
473
474/* Bitfields in DCFG5. */
475#define GEM_TSU_OFFSET 8
476#define GEM_TSU_SIZE 1
477
478/* Bitfields in DCFG6. */
479#define GEM_PBUF_LSO_OFFSET 27
480#define GEM_PBUF_LSO_SIZE 1
481#define GEM_DAW64_OFFSET 23
482#define GEM_DAW64_SIZE 1
483
484/* Bitfields in DCFG8. */
485#define GEM_T1SCR_OFFSET 24
486#define GEM_T1SCR_SIZE 8
487#define GEM_T2SCR_OFFSET 16
488#define GEM_T2SCR_SIZE 8
489#define GEM_SCR2ETH_OFFSET 8
490#define GEM_SCR2ETH_SIZE 8
491#define GEM_SCR2CMP_OFFSET 0
492#define GEM_SCR2CMP_SIZE 8
493
494/* Bitfields in DCFG10 */
495#define GEM_TXBD_RDBUFF_OFFSET 12
496#define GEM_TXBD_RDBUFF_SIZE 4
497#define GEM_RXBD_RDBUFF_OFFSET 8
498#define GEM_RXBD_RDBUFF_SIZE 4
499
500/* Bitfields in TISUBN */
501#define GEM_SUBNSINCR_OFFSET 0
502#define GEM_SUBNSINCRL_OFFSET 24
503#define GEM_SUBNSINCRL_SIZE 8
504#define GEM_SUBNSINCRH_OFFSET 0
505#define GEM_SUBNSINCRH_SIZE 16
506#define GEM_SUBNSINCR_SIZE 24
507
508/* Bitfields in TI */
509#define GEM_NSINCR_OFFSET 0
510#define GEM_NSINCR_SIZE 8
511
512/* Bitfields in TSH */
513#define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
514#define GEM_TSH_SIZE 16
515
516/* Bitfields in TSL */
517#define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
518#define GEM_TSL_SIZE 32
519
520/* Bitfields in TN */
521#define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
522#define GEM_TN_SIZE 30
523
524/* Bitfields in TXBDCTRL */
525#define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
526#define GEM_TXTSMODE_SIZE 2
527
528/* Bitfields in RXBDCTRL */
529#define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
530#define GEM_RXTSMODE_SIZE 2
531
532/* Bitfields in SCRT2 */
533#define GEM_QUEUE_OFFSET 0 /* Queue Number */
534#define GEM_QUEUE_SIZE 4
535#define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
536#define GEM_VLANPR_SIZE 3
537#define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
538#define GEM_VLANEN_SIZE 1
539#define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
540#define GEM_ETHT2IDX_SIZE 3
541#define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
542#define GEM_ETHTEN_SIZE 1
543#define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
544#define GEM_CMPA_SIZE 5
545#define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
546#define GEM_CMPAEN_SIZE 1
547#define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
548#define GEM_CMPB_SIZE 5
549#define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
550#define GEM_CMPBEN_SIZE 1
551#define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
552#define GEM_CMPC_SIZE 5
553#define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
554#define GEM_CMPCEN_SIZE 1
555
556/* Bitfields in ETHT */
557#define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
558#define GEM_ETHTCMP_SIZE 16
559
560/* Bitfields in T2CMPW0 */
561#define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
562#define GEM_T2CMP_SIZE 16
563#define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
564#define GEM_T2MASK_SIZE 16
565
566/* Bitfields in T2CMPW1 */
567#define GEM_T2DISMSK_OFFSET 9 /* disable mask */
568#define GEM_T2DISMSK_SIZE 1
569#define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
570#define GEM_T2CMPOFST_SIZE 2
571#define GEM_T2OFST_OFFSET 0 /* offset value */
572#define GEM_T2OFST_SIZE 7
573
574/* Offset for screener type 2 compare values (T2CMPOFST).
575 * Note the offset is applied after the specified point,
576 * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
577 * of 12 bytes from this would be the source IP address in an IP header
578 */
579#define GEM_T2COMPOFST_SOF 0
580#define GEM_T2COMPOFST_ETYPE 1
581#define GEM_T2COMPOFST_IPHDR 2
582#define GEM_T2COMPOFST_TCPUDP 3
583
584/* offset from EtherType to IP address */
585#define ETYPE_SRCIP_OFFSET 12
586#define ETYPE_DSTIP_OFFSET 16
587
588/* offset from IP header to port */
589#define IPHDR_SRCPORT_OFFSET 0
590#define IPHDR_DSTPORT_OFFSET 2
591
592/* Transmit DMA buffer descriptor Word 1 */
593#define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
594#define GEM_DMA_TXVALID_SIZE 1
595
596/* Receive DMA buffer descriptor Word 0 */
597#define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
598#define GEM_DMA_RXVALID_SIZE 1
599
600/* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
601#define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
602#define GEM_DMA_SECL_SIZE 2
603#define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
604#define GEM_DMA_NSEC_SIZE 30
605
606/* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
607
608/* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
609 * Old hardware supports only 6 bit precision but it is enough for PTP.
610 * Less accuracy is used always instead of checking hardware version.
611 */
612#define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
613#define GEM_DMA_SECH_SIZE 4
614#define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
615#define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
616#define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
617
618/* Bitfields in ADJ */
619#define GEM_ADDSUB_OFFSET 31
620#define GEM_ADDSUB_SIZE 1
621/* Constants for CLK */
622#define MACB_CLK_DIV8 0
623#define MACB_CLK_DIV16 1
624#define MACB_CLK_DIV32 2
625#define MACB_CLK_DIV64 3
626
627/* GEM specific constants for CLK. */
628#define GEM_CLK_DIV8 0
629#define GEM_CLK_DIV16 1
630#define GEM_CLK_DIV32 2
631#define GEM_CLK_DIV48 3
632#define GEM_CLK_DIV64 4
633#define GEM_CLK_DIV96 5
634
635/* Constants for MAN register */
636#define MACB_MAN_C22_SOF 1
637#define MACB_MAN_C22_WRITE 1
638#define MACB_MAN_C22_READ 2
639#define MACB_MAN_C22_CODE 2
640
641#define MACB_MAN_C45_SOF 0
642#define MACB_MAN_C45_ADDR 0
643#define MACB_MAN_C45_WRITE 1
644#define MACB_MAN_C45_POST_READ_INCR 2
645#define MACB_MAN_C45_READ 3
646#define MACB_MAN_C45_CODE 2
647
648/* Capability mask bits */
649#define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
650#define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
651#define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
652#define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
653#define MACB_CAPS_USRIO_DISABLED 0x00000010
654#define MACB_CAPS_JUMBO 0x00000020
655#define MACB_CAPS_GEM_HAS_PTP 0x00000040
656#define MACB_CAPS_BD_RD_PREFETCH 0x00000080
657#define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
658#define MACB_CAPS_MACB_IS_EMAC 0x08000000
659#define MACB_CAPS_FIFO_MODE 0x10000000
660#define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
661#define MACB_CAPS_SG_DISABLED 0x40000000
662#define MACB_CAPS_MACB_IS_GEM 0x80000000
663
664/* LSO settings */
665#define MACB_LSO_UFO_ENABLE 0x01
666#define MACB_LSO_TSO_ENABLE 0x02
667
668/* Bit manipulation macros */
669#define MACB_BIT(name) \
670 (1 << MACB_##name##_OFFSET)
671#define MACB_BF(name,value) \
672 (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
673 << MACB_##name##_OFFSET)
674#define MACB_BFEXT(name,value)\
675 (((value) >> MACB_##name##_OFFSET) \
676 & ((1 << MACB_##name##_SIZE) - 1))
677#define MACB_BFINS(name,value,old) \
678 (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
679 << MACB_##name##_OFFSET)) \
680 | MACB_BF(name,value))
681
682#define GEM_BIT(name) \
683 (1 << GEM_##name##_OFFSET)
684#define GEM_BF(name, value) \
685 (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
686 << GEM_##name##_OFFSET)
687#define GEM_BFEXT(name, value)\
688 (((value) >> GEM_##name##_OFFSET) \
689 & ((1 << GEM_##name##_SIZE) - 1))
690#define GEM_BFINS(name, value, old) \
691 (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
692 << GEM_##name##_OFFSET)) \
693 | GEM_BF(name, value))
694
695/* Register access macros */
696#define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
697#define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
698#define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
699#define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
700#define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
701#define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
702#define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
703#define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
704
705#define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */
706
707/* Conditional GEM/MACB macros. These perform the operation to the correct
708 * register dependent on whether the device is a GEM or a MACB. For registers
709 * and bitfields that are common across both devices, use macb_{read,write}l
710 * to avoid the cost of the conditional.
711 */
712#define macb_or_gem_writel(__bp, __reg, __value) \
713 ({ \
714 if (macb_is_gem((__bp))) \
715 gem_writel((__bp), __reg, __value); \
716 else \
717 macb_writel((__bp), __reg, __value); \
718 })
719
720#define macb_or_gem_readl(__bp, __reg) \
721 ({ \
722 u32 __v; \
723 if (macb_is_gem((__bp))) \
724 __v = gem_readl((__bp), __reg); \
725 else \
726 __v = macb_readl((__bp), __reg); \
727 __v; \
728 })
729
730#define MACB_READ_NSR(bp) macb_readl(bp, NSR)
731
732/* struct macb_dma_desc - Hardware DMA descriptor
733 * @addr: DMA address of data buffer
734 * @ctrl: Control and status bits
735 */
736struct macb_dma_desc {
737 u32 addr;
738 u32 ctrl;
739};
740
741#ifdef MACB_EXT_DESC
742#define HW_DMA_CAP_32B 0
743#define HW_DMA_CAP_64B (1 << 0)
744#define HW_DMA_CAP_PTP (1 << 1)
745#define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
746
747struct macb_dma_desc_64 {
748 u32 addrh;
749 u32 resvd;
750};
751
752struct macb_dma_desc_ptp {
753 u32 ts_1;
754 u32 ts_2;
755};
756
757struct gem_tx_ts {
758 struct sk_buff *skb;
759 struct macb_dma_desc_ptp desc_ptp;
760};
761#endif
762
763/* DMA descriptor bitfields */
764#define MACB_RX_USED_OFFSET 0
765#define MACB_RX_USED_SIZE 1
766#define MACB_RX_WRAP_OFFSET 1
767#define MACB_RX_WRAP_SIZE 1
768#define MACB_RX_WADDR_OFFSET 2
769#define MACB_RX_WADDR_SIZE 30
770
771#define MACB_RX_FRMLEN_OFFSET 0
772#define MACB_RX_FRMLEN_SIZE 12
773#define MACB_RX_OFFSET_OFFSET 12
774#define MACB_RX_OFFSET_SIZE 2
775#define MACB_RX_SOF_OFFSET 14
776#define MACB_RX_SOF_SIZE 1
777#define MACB_RX_EOF_OFFSET 15
778#define MACB_RX_EOF_SIZE 1
779#define MACB_RX_CFI_OFFSET 16
780#define MACB_RX_CFI_SIZE 1
781#define MACB_RX_VLAN_PRI_OFFSET 17
782#define MACB_RX_VLAN_PRI_SIZE 3
783#define MACB_RX_PRI_TAG_OFFSET 20
784#define MACB_RX_PRI_TAG_SIZE 1
785#define MACB_RX_VLAN_TAG_OFFSET 21
786#define MACB_RX_VLAN_TAG_SIZE 1
787#define MACB_RX_TYPEID_MATCH_OFFSET 22
788#define MACB_RX_TYPEID_MATCH_SIZE 1
789#define MACB_RX_SA4_MATCH_OFFSET 23
790#define MACB_RX_SA4_MATCH_SIZE 1
791#define MACB_RX_SA3_MATCH_OFFSET 24
792#define MACB_RX_SA3_MATCH_SIZE 1
793#define MACB_RX_SA2_MATCH_OFFSET 25
794#define MACB_RX_SA2_MATCH_SIZE 1
795#define MACB_RX_SA1_MATCH_OFFSET 26
796#define MACB_RX_SA1_MATCH_SIZE 1
797#define MACB_RX_EXT_MATCH_OFFSET 28
798#define MACB_RX_EXT_MATCH_SIZE 1
799#define MACB_RX_UHASH_MATCH_OFFSET 29
800#define MACB_RX_UHASH_MATCH_SIZE 1
801#define MACB_RX_MHASH_MATCH_OFFSET 30
802#define MACB_RX_MHASH_MATCH_SIZE 1
803#define MACB_RX_BROADCAST_OFFSET 31
804#define MACB_RX_BROADCAST_SIZE 1
805
806#define MACB_RX_FRMLEN_MASK 0xFFF
807#define MACB_RX_JFRMLEN_MASK 0x3FFF
808
809/* RX checksum offload disabled: bit 24 clear in NCFGR */
810#define GEM_RX_TYPEID_MATCH_OFFSET 22
811#define GEM_RX_TYPEID_MATCH_SIZE 2
812
813/* RX checksum offload enabled: bit 24 set in NCFGR */
814#define GEM_RX_CSUM_OFFSET 22
815#define GEM_RX_CSUM_SIZE 2
816
817#define MACB_TX_FRMLEN_OFFSET 0
818#define MACB_TX_FRMLEN_SIZE 11
819#define MACB_TX_LAST_OFFSET 15
820#define MACB_TX_LAST_SIZE 1
821#define MACB_TX_NOCRC_OFFSET 16
822#define MACB_TX_NOCRC_SIZE 1
823#define MACB_MSS_MFS_OFFSET 16
824#define MACB_MSS_MFS_SIZE 14
825#define MACB_TX_LSO_OFFSET 17
826#define MACB_TX_LSO_SIZE 2
827#define MACB_TX_TCP_SEQ_SRC_OFFSET 19
828#define MACB_TX_TCP_SEQ_SRC_SIZE 1
829#define MACB_TX_BUF_EXHAUSTED_OFFSET 27
830#define MACB_TX_BUF_EXHAUSTED_SIZE 1
831#define MACB_TX_UNDERRUN_OFFSET 28
832#define MACB_TX_UNDERRUN_SIZE 1
833#define MACB_TX_ERROR_OFFSET 29
834#define MACB_TX_ERROR_SIZE 1
835#define MACB_TX_WRAP_OFFSET 30
836#define MACB_TX_WRAP_SIZE 1
837#define MACB_TX_USED_OFFSET 31
838#define MACB_TX_USED_SIZE 1
839
840#define GEM_TX_FRMLEN_OFFSET 0
841#define GEM_TX_FRMLEN_SIZE 14
842
843/* Buffer descriptor constants */
844#define GEM_RX_CSUM_NONE 0
845#define GEM_RX_CSUM_IP_ONLY 1
846#define GEM_RX_CSUM_IP_TCP 2
847#define GEM_RX_CSUM_IP_UDP 3
848
849/* limit RX checksum offload to TCP and UDP packets */
850#define GEM_RX_CSUM_CHECKED_MASK 2
851
852/* Scaled PPM fraction */
853#define PPM_FRACTION 16
854
855/* struct macb_tx_skb - data about an skb which is being transmitted
856 * @skb: skb currently being transmitted, only set for the last buffer
857 * of the frame
858 * @mapping: DMA address of the skb's fragment buffer
859 * @size: size of the DMA mapped buffer
860 * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
861 * false when buffer was mapped with dma_map_single()
862 */
863struct macb_tx_skb {
864 struct sk_buff *skb;
865 dma_addr_t mapping;
866 size_t size;
867 bool mapped_as_page;
868};
869
870/* Hardware-collected statistics. Used when updating the network
871 * device stats by a periodic timer.
872 */
873struct macb_stats {
874 u32 rx_pause_frames;
875 u32 tx_ok;
876 u32 tx_single_cols;
877 u32 tx_multiple_cols;
878 u32 rx_ok;
879 u32 rx_fcs_errors;
880 u32 rx_align_errors;
881 u32 tx_deferred;
882 u32 tx_late_cols;
883 u32 tx_excessive_cols;
884 u32 tx_underruns;
885 u32 tx_carrier_errors;
886 u32 rx_resource_errors;
887 u32 rx_overruns;
888 u32 rx_symbol_errors;
889 u32 rx_oversize_pkts;
890 u32 rx_jabbers;
891 u32 rx_undersize_pkts;
892 u32 sqe_test_errors;
893 u32 rx_length_mismatch;
894 u32 tx_pause_frames;
895};
896
897struct gem_stats {
898 u32 tx_octets_31_0;
899 u32 tx_octets_47_32;
900 u32 tx_frames;
901 u32 tx_broadcast_frames;
902 u32 tx_multicast_frames;
903 u32 tx_pause_frames;
904 u32 tx_64_byte_frames;
905 u32 tx_65_127_byte_frames;
906 u32 tx_128_255_byte_frames;
907 u32 tx_256_511_byte_frames;
908 u32 tx_512_1023_byte_frames;
909 u32 tx_1024_1518_byte_frames;
910 u32 tx_greater_than_1518_byte_frames;
911 u32 tx_underrun;
912 u32 tx_single_collision_frames;
913 u32 tx_multiple_collision_frames;
914 u32 tx_excessive_collisions;
915 u32 tx_late_collisions;
916 u32 tx_deferred_frames;
917 u32 tx_carrier_sense_errors;
918 u32 rx_octets_31_0;
919 u32 rx_octets_47_32;
920 u32 rx_frames;
921 u32 rx_broadcast_frames;
922 u32 rx_multicast_frames;
923 u32 rx_pause_frames;
924 u32 rx_64_byte_frames;
925 u32 rx_65_127_byte_frames;
926 u32 rx_128_255_byte_frames;
927 u32 rx_256_511_byte_frames;
928 u32 rx_512_1023_byte_frames;
929 u32 rx_1024_1518_byte_frames;
930 u32 rx_greater_than_1518_byte_frames;
931 u32 rx_undersized_frames;
932 u32 rx_oversize_frames;
933 u32 rx_jabbers;
934 u32 rx_frame_check_sequence_errors;
935 u32 rx_length_field_frame_errors;
936 u32 rx_symbol_errors;
937 u32 rx_alignment_errors;
938 u32 rx_resource_errors;
939 u32 rx_overruns;
940 u32 rx_ip_header_checksum_errors;
941 u32 rx_tcp_checksum_errors;
942 u32 rx_udp_checksum_errors;
943};
944
945/* Describes the name and offset of an individual statistic register, as
946 * returned by `ethtool -S`. Also describes which net_device_stats statistics
947 * this register should contribute to.
948 */
949struct gem_statistic {
950 char stat_string[ETH_GSTRING_LEN];
951 int offset;
952 u32 stat_bits;
953};
954
955/* Bitfield defs for net_device_stat statistics */
956#define GEM_NDS_RXERR_OFFSET 0
957#define GEM_NDS_RXLENERR_OFFSET 1
958#define GEM_NDS_RXOVERERR_OFFSET 2
959#define GEM_NDS_RXCRCERR_OFFSET 3
960#define GEM_NDS_RXFRAMEERR_OFFSET 4
961#define GEM_NDS_RXFIFOERR_OFFSET 5
962#define GEM_NDS_TXERR_OFFSET 6
963#define GEM_NDS_TXABORTEDERR_OFFSET 7
964#define GEM_NDS_TXCARRIERERR_OFFSET 8
965#define GEM_NDS_TXFIFOERR_OFFSET 9
966#define GEM_NDS_COLLISIONS_OFFSET 10
967
968#define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
969#define GEM_STAT_TITLE_BITS(name, title, bits) { \
970 .stat_string = title, \
971 .offset = GEM_##name, \
972 .stat_bits = bits \
973}
974
975/* list of gem statistic registers. The names MUST match the
976 * corresponding GEM_* definitions.
977 */
978static const struct gem_statistic gem_statistics[] = {
979 GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
980 GEM_STAT_TITLE(TXCNT, "tx_frames"),
981 GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
982 GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
983 GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
984 GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
985 GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
986 GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
987 GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
988 GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
989 GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
990 GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
991 GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
992 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
993 GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
994 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
995 GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
996 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
997 GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
998 GEM_BIT(NDS_TXERR)|
999 GEM_BIT(NDS_TXABORTEDERR)|
1000 GEM_BIT(NDS_COLLISIONS)),
1001 GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
1002 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1003 GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
1004 GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
1005 GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
1006 GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
1007 GEM_STAT_TITLE(RXCNT, "rx_frames"),
1008 GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
1009 GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
1010 GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
1011 GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
1012 GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
1013 GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
1014 GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
1015 GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
1016 GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
1017 GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
1018 GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
1019 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1020 GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
1021 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1022 GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
1023 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
1024 GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
1025 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
1026 GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
1027 GEM_BIT(NDS_RXERR)),
1028 GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
1029 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
1030 GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
1031 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1032 GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
1033 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
1034 GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
1035 GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
1036 GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
1037 GEM_BIT(NDS_RXERR)),
1038 GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
1039 GEM_BIT(NDS_RXERR)),
1040 GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
1041 GEM_BIT(NDS_RXERR)),
1042};
1043
1044#define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
1045
1046#define QUEUE_STAT_TITLE(title) { \
1047 .stat_string = title, \
1048}
1049
1050/* per queue statistics, each should be unsigned long type */
1051struct queue_stats {
1052 union {
1053 unsigned long first;
1054 unsigned long rx_packets;
1055 };
1056 unsigned long rx_bytes;
1057 unsigned long rx_dropped;
1058 unsigned long tx_packets;
1059 unsigned long tx_bytes;
1060 unsigned long tx_dropped;
1061};
1062
1063static const struct gem_statistic queue_statistics[] = {
1064 QUEUE_STAT_TITLE("rx_packets"),
1065 QUEUE_STAT_TITLE("rx_bytes"),
1066 QUEUE_STAT_TITLE("rx_dropped"),
1067 QUEUE_STAT_TITLE("tx_packets"),
1068 QUEUE_STAT_TITLE("tx_bytes"),
1069 QUEUE_STAT_TITLE("tx_dropped"),
1070};
1071
1072#define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
1073
1074struct macb;
1075struct macb_queue;
1076
1077struct macb_or_gem_ops {
1078 int (*mog_alloc_rx_buffers)(struct macb *bp);
1079 void (*mog_free_rx_buffers)(struct macb *bp);
1080 void (*mog_init_rings)(struct macb *bp);
1081 int (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi,
1082 int budget);
1083};
1084
1085/* MACB-PTP interface: adapt to platform needs. */
1086struct macb_ptp_info {
1087 void (*ptp_init)(struct net_device *ndev);
1088 void (*ptp_remove)(struct net_device *ndev);
1089 s32 (*get_ptp_max_adj)(void);
1090 unsigned int (*get_tsu_rate)(struct macb *bp);
1091 int (*get_ts_info)(struct net_device *dev,
1092 struct ethtool_ts_info *info);
1093 int (*get_hwtst)(struct net_device *netdev,
1094 struct ifreq *ifr);
1095 int (*set_hwtst)(struct net_device *netdev,
1096 struct ifreq *ifr, int cmd);
1097};
1098
1099struct macb_pm_data {
1100 u32 scrt2;
1101 u32 usrio;
1102};
1103
1104struct macb_config {
1105 u32 caps;
1106 unsigned int dma_burst_length;
1107 int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
1108 struct clk **hclk, struct clk **tx_clk,
1109 struct clk **rx_clk, struct clk **tsu_clk);
1110 int (*init)(struct platform_device *pdev);
1111 int jumbo_max_len;
1112};
1113
1114struct tsu_incr {
1115 u32 sub_ns;
1116 u32 ns;
1117};
1118
1119struct macb_queue {
1120 struct macb *bp;
1121 int irq;
1122
1123 unsigned int ISR;
1124 unsigned int IER;
1125 unsigned int IDR;
1126 unsigned int IMR;
1127 unsigned int TBQP;
1128 unsigned int TBQPH;
1129 unsigned int RBQS;
1130 unsigned int RBQP;
1131 unsigned int RBQPH;
1132
1133 unsigned int tx_head, tx_tail;
1134 struct macb_dma_desc *tx_ring;
1135 struct macb_tx_skb *tx_skb;
1136 dma_addr_t tx_ring_dma;
1137 struct work_struct tx_error_task;
1138
1139 dma_addr_t rx_ring_dma;
1140 dma_addr_t rx_buffers_dma;
1141 unsigned int rx_tail;
1142 unsigned int rx_prepared_head;
1143 struct macb_dma_desc *rx_ring;
1144 struct sk_buff **rx_skbuff;
1145 void *rx_buffers;
1146 struct napi_struct napi;
1147 struct queue_stats stats;
1148
1149#ifdef CONFIG_MACB_USE_HWSTAMP
1150 struct work_struct tx_ts_task;
1151 unsigned int tx_ts_head, tx_ts_tail;
1152 struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE];
1153#endif
1154};
1155
1156struct ethtool_rx_fs_item {
1157 struct ethtool_rx_flow_spec fs;
1158 struct list_head list;
1159};
1160
1161struct ethtool_rx_fs_list {
1162 struct list_head list;
1163 unsigned int count;
1164};
1165
1166struct macb {
1167 void __iomem *regs;
1168 bool native_io;
1169
1170 /* hardware IO accessors */
1171 u32 (*macb_reg_readl)(struct macb *bp, int offset);
1172 void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
1173
1174 size_t rx_buffer_size;
1175
1176 unsigned int rx_ring_size;
1177 unsigned int tx_ring_size;
1178
1179 unsigned int num_queues;
1180 unsigned int queue_mask;
1181 struct macb_queue queues[MACB_MAX_QUEUES];
1182
1183 spinlock_t lock;
1184 struct platform_device *pdev;
1185 struct clk *pclk;
1186 struct clk *hclk;
1187 struct clk *tx_clk;
1188 struct clk *rx_clk;
1189 struct clk *tsu_clk;
1190 struct net_device *dev;
1191 union {
1192 struct macb_stats macb;
1193 struct gem_stats gem;
1194 } hw_stats;
1195
1196 struct macb_or_gem_ops macbgem_ops;
1197
1198 struct mii_bus *mii_bus;
1199 struct phylink *phylink;
1200 struct phylink_config phylink_config;
1201
1202 u32 caps;
1203 unsigned int dma_burst_length;
1204
1205 phy_interface_t phy_interface;
1206
1207 /* AT91RM9200 transmit */
1208 struct sk_buff *skb; /* holds skb until xmit interrupt completes */
1209 dma_addr_t skb_physaddr; /* phys addr from pci_map_single */
1210 int skb_length; /* saved skb length for pci_unmap_single */
1211 unsigned int max_tx_length;
1212
1213 u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
1214
1215 unsigned int rx_frm_len_mask;
1216 unsigned int jumbo_max_len;
1217
1218 u32 wol;
1219
1220 struct macb_ptp_info *ptp_info; /* macb-ptp interface */
1221#ifdef MACB_EXT_DESC
1222 uint8_t hw_dma_cap;
1223#endif
1224 spinlock_t tsu_clk_lock; /* gem tsu clock locking */
1225 unsigned int tsu_rate;
1226 struct ptp_clock *ptp_clock;
1227 struct ptp_clock_info ptp_clock_info;
1228 struct tsu_incr tsu_incr;
1229 struct hwtstamp_config tstamp_config;
1230
1231 /* RX queue filer rule set*/
1232 struct ethtool_rx_fs_list rx_fs_list;
1233 spinlock_t rx_fs_lock;
1234 unsigned int max_tuples;
1235
1236 struct tasklet_struct hresp_err_tasklet;
1237
1238 int rx_bd_rd_prefetch;
1239 int tx_bd_rd_prefetch;
1240
1241 u32 rx_intr_mask;
1242
1243 struct macb_pm_data pm_data;
1244};
1245
1246#ifdef CONFIG_MACB_USE_HWSTAMP
1247#define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
1248#define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
1249#define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
1250
1251enum macb_bd_control {
1252 TSTAMP_DISABLED,
1253 TSTAMP_FRAME_PTP_EVENT_ONLY,
1254 TSTAMP_ALL_PTP_FRAMES,
1255 TSTAMP_ALL_FRAMES,
1256};
1257
1258void gem_ptp_init(struct net_device *ndev);
1259void gem_ptp_remove(struct net_device *ndev);
1260int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des);
1261void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
1262static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1263{
1264 if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED)
1265 return -ENOTSUPP;
1266
1267 return gem_ptp_txstamp(queue, skb, desc);
1268}
1269
1270static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
1271{
1272 if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
1273 return;
1274
1275 gem_ptp_rxstamp(bp, skb, desc);
1276}
1277int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);
1278int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);
1279#else
1280static inline void gem_ptp_init(struct net_device *ndev) { }
1281static inline void gem_ptp_remove(struct net_device *ndev) { }
1282
1283static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
1284{
1285 return -1;
1286}
1287
1288static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
1289#endif
1290
1291static inline bool macb_is_gem(struct macb *bp)
1292{
1293 return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
1294}
1295
1296static inline bool gem_has_ptp(struct macb *bp)
1297{
1298 return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
1299}
1300
1301#endif /* _MACB_H */