1/*
   2 * B53 switch driver main logic
   3 *
   4 * Copyright (C) 2011-2013 Jonas Gorski <jogo@openwrt.org>
   5 * Copyright (C) 2016 Florian Fainelli <f.fainelli@gmail.com>
   6 *
   7 * Permission to use, copy, modify, and/or distribute this software for any
   8 * purpose with or without fee is hereby granted, provided that the above
   9 * copyright notice and this permission notice appear in all copies.
  10 *
  11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18 */
  19
  20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22#include <linux/delay.h>
  23#include <linux/export.h>
  24#include <linux/gpio.h>
  25#include <linux/kernel.h>
  26#include <linux/module.h>
  27#include <linux/platform_data/b53.h>
  28#include <linux/phy.h>
 
  29#include <linux/etherdevice.h>
  30#include <linux/if_bridge.h>
  31#include <net/dsa.h>
  32
  33#include "b53_regs.h"
  34#include "b53_priv.h"
  35
  36struct b53_mib_desc {
  37	u8 size;
  38	u8 offset;
  39	const char *name;
  40};
  41
  42/* BCM5365 MIB counters */
  43static const struct b53_mib_desc b53_mibs_65[] = {
  44	{ 8, 0x00, "TxOctets" },
  45	{ 4, 0x08, "TxDropPkts" },
  46	{ 4, 0x10, "TxBroadcastPkts" },
  47	{ 4, 0x14, "TxMulticastPkts" },
  48	{ 4, 0x18, "TxUnicastPkts" },
  49	{ 4, 0x1c, "TxCollisions" },
  50	{ 4, 0x20, "TxSingleCollision" },
  51	{ 4, 0x24, "TxMultipleCollision" },
  52	{ 4, 0x28, "TxDeferredTransmit" },
  53	{ 4, 0x2c, "TxLateCollision" },
  54	{ 4, 0x30, "TxExcessiveCollision" },
  55	{ 4, 0x38, "TxPausePkts" },
  56	{ 8, 0x44, "RxOctets" },
  57	{ 4, 0x4c, "RxUndersizePkts" },
  58	{ 4, 0x50, "RxPausePkts" },
  59	{ 4, 0x54, "Pkts64Octets" },
  60	{ 4, 0x58, "Pkts65to127Octets" },
  61	{ 4, 0x5c, "Pkts128to255Octets" },
  62	{ 4, 0x60, "Pkts256to511Octets" },
  63	{ 4, 0x64, "Pkts512to1023Octets" },
  64	{ 4, 0x68, "Pkts1024to1522Octets" },
  65	{ 4, 0x6c, "RxOversizePkts" },
  66	{ 4, 0x70, "RxJabbers" },
  67	{ 4, 0x74, "RxAlignmentErrors" },
  68	{ 4, 0x78, "RxFCSErrors" },
  69	{ 8, 0x7c, "RxGoodOctets" },
  70	{ 4, 0x84, "RxDropPkts" },
  71	{ 4, 0x88, "RxUnicastPkts" },
  72	{ 4, 0x8c, "RxMulticastPkts" },
  73	{ 4, 0x90, "RxBroadcastPkts" },
  74	{ 4, 0x94, "RxSAChanges" },
  75	{ 4, 0x98, "RxFragments" },
  76};
  77
  78#define B53_MIBS_65_SIZE	ARRAY_SIZE(b53_mibs_65)
  79
  80/* BCM63xx MIB counters */
  81static const struct b53_mib_desc b53_mibs_63xx[] = {
  82	{ 8, 0x00, "TxOctets" },
  83	{ 4, 0x08, "TxDropPkts" },
  84	{ 4, 0x0c, "TxQoSPkts" },
  85	{ 4, 0x10, "TxBroadcastPkts" },
  86	{ 4, 0x14, "TxMulticastPkts" },
  87	{ 4, 0x18, "TxUnicastPkts" },
  88	{ 4, 0x1c, "TxCollisions" },
  89	{ 4, 0x20, "TxSingleCollision" },
  90	{ 4, 0x24, "TxMultipleCollision" },
  91	{ 4, 0x28, "TxDeferredTransmit" },
  92	{ 4, 0x2c, "TxLateCollision" },
  93	{ 4, 0x30, "TxExcessiveCollision" },
  94	{ 4, 0x38, "TxPausePkts" },
  95	{ 8, 0x3c, "TxQoSOctets" },
  96	{ 8, 0x44, "RxOctets" },
  97	{ 4, 0x4c, "RxUndersizePkts" },
  98	{ 4, 0x50, "RxPausePkts" },
  99	{ 4, 0x54, "Pkts64Octets" },
 100	{ 4, 0x58, "Pkts65to127Octets" },
 101	{ 4, 0x5c, "Pkts128to255Octets" },
 102	{ 4, 0x60, "Pkts256to511Octets" },
 103	{ 4, 0x64, "Pkts512to1023Octets" },
 104	{ 4, 0x68, "Pkts1024to1522Octets" },
 105	{ 4, 0x6c, "RxOversizePkts" },
 106	{ 4, 0x70, "RxJabbers" },
 107	{ 4, 0x74, "RxAlignmentErrors" },
 108	{ 4, 0x78, "RxFCSErrors" },
 109	{ 8, 0x7c, "RxGoodOctets" },
 110	{ 4, 0x84, "RxDropPkts" },
 111	{ 4, 0x88, "RxUnicastPkts" },
 112	{ 4, 0x8c, "RxMulticastPkts" },
 113	{ 4, 0x90, "RxBroadcastPkts" },
 114	{ 4, 0x94, "RxSAChanges" },
 115	{ 4, 0x98, "RxFragments" },
 116	{ 4, 0xa0, "RxSymbolErrors" },
 117	{ 4, 0xa4, "RxQoSPkts" },
 118	{ 8, 0xa8, "RxQoSOctets" },
 119	{ 4, 0xb0, "Pkts1523to2047Octets" },
 120	{ 4, 0xb4, "Pkts2048to4095Octets" },
 121	{ 4, 0xb8, "Pkts4096to8191Octets" },
 122	{ 4, 0xbc, "Pkts8192to9728Octets" },
 123	{ 4, 0xc0, "RxDiscarded" },
 124};
 125
 126#define B53_MIBS_63XX_SIZE	ARRAY_SIZE(b53_mibs_63xx)
 127
 128/* MIB counters */
 129static const struct b53_mib_desc b53_mibs[] = {
 130	{ 8, 0x00, "TxOctets" },
 131	{ 4, 0x08, "TxDropPkts" },
 132	{ 4, 0x10, "TxBroadcastPkts" },
 133	{ 4, 0x14, "TxMulticastPkts" },
 134	{ 4, 0x18, "TxUnicastPkts" },
 135	{ 4, 0x1c, "TxCollisions" },
 136	{ 4, 0x20, "TxSingleCollision" },
 137	{ 4, 0x24, "TxMultipleCollision" },
 138	{ 4, 0x28, "TxDeferredTransmit" },
 139	{ 4, 0x2c, "TxLateCollision" },
 140	{ 4, 0x30, "TxExcessiveCollision" },
 141	{ 4, 0x38, "TxPausePkts" },
 142	{ 8, 0x50, "RxOctets" },
 143	{ 4, 0x58, "RxUndersizePkts" },
 144	{ 4, 0x5c, "RxPausePkts" },
 145	{ 4, 0x60, "Pkts64Octets" },
 146	{ 4, 0x64, "Pkts65to127Octets" },
 147	{ 4, 0x68, "Pkts128to255Octets" },
 148	{ 4, 0x6c, "Pkts256to511Octets" },
 149	{ 4, 0x70, "Pkts512to1023Octets" },
 150	{ 4, 0x74, "Pkts1024to1522Octets" },
 151	{ 4, 0x78, "RxOversizePkts" },
 152	{ 4, 0x7c, "RxJabbers" },
 153	{ 4, 0x80, "RxAlignmentErrors" },
 154	{ 4, 0x84, "RxFCSErrors" },
 155	{ 8, 0x88, "RxGoodOctets" },
 156	{ 4, 0x90, "RxDropPkts" },
 157	{ 4, 0x94, "RxUnicastPkts" },
 158	{ 4, 0x98, "RxMulticastPkts" },
 159	{ 4, 0x9c, "RxBroadcastPkts" },
 160	{ 4, 0xa0, "RxSAChanges" },
 161	{ 4, 0xa4, "RxFragments" },
 162	{ 4, 0xa8, "RxJumboPkts" },
 163	{ 4, 0xac, "RxSymbolErrors" },
 164	{ 4, 0xc0, "RxDiscarded" },
 165};
 166
 167#define B53_MIBS_SIZE	ARRAY_SIZE(b53_mibs)
 168
 169static const struct b53_mib_desc b53_mibs_58xx[] = {
 170	{ 8, 0x00, "TxOctets" },
 171	{ 4, 0x08, "TxDropPkts" },
 172	{ 4, 0x0c, "TxQPKTQ0" },
 173	{ 4, 0x10, "TxBroadcastPkts" },
 174	{ 4, 0x14, "TxMulticastPkts" },
 175	{ 4, 0x18, "TxUnicastPKts" },
 176	{ 4, 0x1c, "TxCollisions" },
 177	{ 4, 0x20, "TxSingleCollision" },
 178	{ 4, 0x24, "TxMultipleCollision" },
 179	{ 4, 0x28, "TxDeferredCollision" },
 180	{ 4, 0x2c, "TxLateCollision" },
 181	{ 4, 0x30, "TxExcessiveCollision" },
 182	{ 4, 0x34, "TxFrameInDisc" },
 183	{ 4, 0x38, "TxPausePkts" },
 184	{ 4, 0x3c, "TxQPKTQ1" },
 185	{ 4, 0x40, "TxQPKTQ2" },
 186	{ 4, 0x44, "TxQPKTQ3" },
 187	{ 4, 0x48, "TxQPKTQ4" },
 188	{ 4, 0x4c, "TxQPKTQ5" },
 189	{ 8, 0x50, "RxOctets" },
 190	{ 4, 0x58, "RxUndersizePkts" },
 191	{ 4, 0x5c, "RxPausePkts" },
 192	{ 4, 0x60, "RxPkts64Octets" },
 193	{ 4, 0x64, "RxPkts65to127Octets" },
 194	{ 4, 0x68, "RxPkts128to255Octets" },
 195	{ 4, 0x6c, "RxPkts256to511Octets" },
 196	{ 4, 0x70, "RxPkts512to1023Octets" },
 197	{ 4, 0x74, "RxPkts1024toMaxPktsOctets" },
 198	{ 4, 0x78, "RxOversizePkts" },
 199	{ 4, 0x7c, "RxJabbers" },
 200	{ 4, 0x80, "RxAlignmentErrors" },
 201	{ 4, 0x84, "RxFCSErrors" },
 202	{ 8, 0x88, "RxGoodOctets" },
 203	{ 4, 0x90, "RxDropPkts" },
 204	{ 4, 0x94, "RxUnicastPkts" },
 205	{ 4, 0x98, "RxMulticastPkts" },
 206	{ 4, 0x9c, "RxBroadcastPkts" },
 207	{ 4, 0xa0, "RxSAChanges" },
 208	{ 4, 0xa4, "RxFragments" },
 209	{ 4, 0xa8, "RxJumboPkt" },
 210	{ 4, 0xac, "RxSymblErr" },
 211	{ 4, 0xb0, "InRangeErrCount" },
 212	{ 4, 0xb4, "OutRangeErrCount" },
 213	{ 4, 0xb8, "EEELpiEvent" },
 214	{ 4, 0xbc, "EEELpiDuration" },
 215	{ 4, 0xc0, "RxDiscard" },
 216	{ 4, 0xc8, "TxQPKTQ6" },
 217	{ 4, 0xcc, "TxQPKTQ7" },
 218	{ 4, 0xd0, "TxPkts64Octets" },
 219	{ 4, 0xd4, "TxPkts65to127Octets" },
 220	{ 4, 0xd8, "TxPkts128to255Octets" },
 221	{ 4, 0xdc, "TxPkts256to511Ocets" },
 222	{ 4, 0xe0, "TxPkts512to1023Ocets" },
 223	{ 4, 0xe4, "TxPkts1024toMaxPktOcets" },
 224};
 225
 226#define B53_MIBS_58XX_SIZE	ARRAY_SIZE(b53_mibs_58xx)
 227
 228static int b53_do_vlan_op(struct b53_device *dev, u8 op)
 229{
 230	unsigned int i;
 231
 232	b53_write8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], VTA_START_CMD | op);
 233
 234	for (i = 0; i < 10; i++) {
 235		u8 vta;
 236
 237		b53_read8(dev, B53_ARLIO_PAGE, dev->vta_regs[0], &vta);
 238		if (!(vta & VTA_START_CMD))
 239			return 0;
 240
 241		usleep_range(100, 200);
 242	}
 243
 244	return -EIO;
 245}
 246
 247static void b53_set_vlan_entry(struct b53_device *dev, u16 vid,
 248			       struct b53_vlan *vlan)
 249{
 250	if (is5325(dev)) {
 251		u32 entry = 0;
 252
 253		if (vlan->members) {
 254			entry = ((vlan->untag & VA_UNTAG_MASK_25) <<
 255				 VA_UNTAG_S_25) | vlan->members;
 256			if (dev->core_rev >= 3)
 257				entry |= VA_VALID_25_R4 | vid << VA_VID_HIGH_S;
 258			else
 259				entry |= VA_VALID_25;
 260		}
 261
 262		b53_write32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, entry);
 263		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 264			    VTA_RW_STATE_WR | VTA_RW_OP_EN);
 265	} else if (is5365(dev)) {
 266		u16 entry = 0;
 267
 268		if (vlan->members)
 269			entry = ((vlan->untag & VA_UNTAG_MASK_65) <<
 270				 VA_UNTAG_S_65) | vlan->members | VA_VALID_65;
 271
 272		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, entry);
 273		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 274			    VTA_RW_STATE_WR | VTA_RW_OP_EN);
 275	} else {
 276		b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 277		b53_write32(dev, B53_ARLIO_PAGE, dev->vta_regs[2],
 278			    (vlan->untag << VTE_UNTAG_S) | vlan->members);
 279
 280		b53_do_vlan_op(dev, VTA_CMD_WRITE);
 281	}
 282
 283	dev_dbg(dev->ds->dev, "VID: %d, members: 0x%04x, untag: 0x%04x\n",
 284		vid, vlan->members, vlan->untag);
 285}
 286
 287static void b53_get_vlan_entry(struct b53_device *dev, u16 vid,
 288			       struct b53_vlan *vlan)
 289{
 290	if (is5325(dev)) {
 291		u32 entry = 0;
 292
 293		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, vid |
 294			    VTA_RW_STATE_RD | VTA_RW_OP_EN);
 295		b53_read32(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_25, &entry);
 296
 297		if (dev->core_rev >= 3)
 298			vlan->valid = !!(entry & VA_VALID_25_R4);
 299		else
 300			vlan->valid = !!(entry & VA_VALID_25);
 301		vlan->members = entry & VA_MEMBER_MASK;
 302		vlan->untag = (entry >> VA_UNTAG_S_25) & VA_UNTAG_MASK_25;
 303
 304	} else if (is5365(dev)) {
 305		u16 entry = 0;
 306
 307		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_65, vid |
 308			    VTA_RW_STATE_WR | VTA_RW_OP_EN);
 309		b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_WRITE_65, &entry);
 310
 311		vlan->valid = !!(entry & VA_VALID_65);
 312		vlan->members = entry & VA_MEMBER_MASK;
 313		vlan->untag = (entry >> VA_UNTAG_S_65) & VA_UNTAG_MASK_65;
 314	} else {
 315		u32 entry = 0;
 316
 317		b53_write16(dev, B53_ARLIO_PAGE, dev->vta_regs[1], vid);
 318		b53_do_vlan_op(dev, VTA_CMD_READ);
 319		b53_read32(dev, B53_ARLIO_PAGE, dev->vta_regs[2], &entry);
 320		vlan->members = entry & VTE_MEMBERS;
 321		vlan->untag = (entry >> VTE_UNTAG_S) & VTE_MEMBERS;
 322		vlan->valid = true;
 323	}
 324}
 325
 326static void b53_set_forwarding(struct b53_device *dev, int enable)
 327{
 328	u8 mgmt;
 329
 330	b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 331
 332	if (enable)
 333		mgmt |= SM_SW_FWD_EN;
 334	else
 335		mgmt &= ~SM_SW_FWD_EN;
 336
 337	b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 338
 339	/* Include IMP port in dumb forwarding mode
 340	 */
 341	b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, &mgmt);
 342	mgmt |= B53_MII_DUMB_FWDG_EN;
 343	b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_CTRL, mgmt);
 
 
 
 
 
 
 
 344}
 345
 346static void b53_enable_vlan(struct b53_device *dev, bool enable)
 
 347{
 348	u8 mgmt, vc0, vc1, vc4 = 0, vc5;
 349
 350	b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 351	b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, &vc0);
 352	b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, &vc1);
 353
 354	if (is5325(dev) || is5365(dev)) {
 355		b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
 356		b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, &vc5);
 357	} else if (is63xx(dev)) {
 358		b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, &vc4);
 359		b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, &vc5);
 360	} else {
 361		b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, &vc4);
 362		b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, &vc5);
 363	}
 364
 365	mgmt &= ~SM_SW_FWD_MODE;
 366
 367	if (enable) {
 368		vc0 |= VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID;
 369		vc1 |= VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN;
 370		vc4 &= ~VC4_ING_VID_CHECK_MASK;
 371		vc4 |= VC4_ING_VID_VIO_DROP << VC4_ING_VID_CHECK_S;
 372		vc5 |= VC5_DROP_VTABLE_MISS;
 
 
 
 
 
 373
 374		if (is5325(dev))
 375			vc0 &= ~VC0_RESERVED_1;
 376
 377		if (is5325(dev) || is5365(dev))
 378			vc1 |= VC1_RX_MCST_TAG_EN;
 379
 380	} else {
 381		vc0 &= ~(VC0_VLAN_EN | VC0_VID_CHK_EN | VC0_VID_HASH_VID);
 382		vc1 &= ~(VC1_RX_MCST_UNTAG_EN | VC1_RX_MCST_FWD_EN);
 383		vc4 &= ~VC4_ING_VID_CHECK_MASK;
 384		vc5 &= ~VC5_DROP_VTABLE_MISS;
 385
 386		if (is5325(dev) || is5365(dev))
 387			vc4 |= VC4_ING_VID_VIO_FWD << VC4_ING_VID_CHECK_S;
 388		else
 389			vc4 |= VC4_ING_VID_VIO_TO_IMP << VC4_ING_VID_CHECK_S;
 390
 391		if (is5325(dev) || is5365(dev))
 392			vc1 &= ~VC1_RX_MCST_TAG_EN;
 393	}
 394
 395	if (!is5325(dev) && !is5365(dev))
 396		vc5 &= ~VC5_VID_FFF_EN;
 397
 398	b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL0, vc0);
 399	b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL1, vc1);
 400
 401	if (is5325(dev) || is5365(dev)) {
 402		/* enable the high 8 bit vid check on 5325 */
 403		if (is5325(dev) && enable)
 404			b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3,
 405				   VC3_HIGH_8BIT_EN);
 406		else
 407			b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 408
 409		b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, vc4);
 410		b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_25, vc5);
 411	} else if (is63xx(dev)) {
 412		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3_63XX, 0);
 413		b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_63XX, vc4);
 414		b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5_63XX, vc5);
 415	} else {
 416		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_CTRL3, 0);
 417		b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4, vc4);
 418		b53_write8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL5, vc5);
 419	}
 420
 421	b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 
 
 422}
 423
 424static int b53_set_jumbo(struct b53_device *dev, bool enable, bool allow_10_100)
 425{
 426	u32 port_mask = 0;
 427	u16 max_size = JMS_MIN_SIZE;
 428
 429	if (is5325(dev) || is5365(dev))
 430		return -EINVAL;
 431
 432	if (enable) {
 433		port_mask = dev->enabled_ports;
 434		max_size = JMS_MAX_SIZE;
 435		if (allow_10_100)
 436			port_mask |= JPM_10_100_JUMBO_EN;
 437	}
 438
 439	b53_write32(dev, B53_JUMBO_PAGE, dev->jumbo_pm_reg, port_mask);
 440	return b53_write16(dev, B53_JUMBO_PAGE, dev->jumbo_size_reg, max_size);
 441}
 442
 443static int b53_flush_arl(struct b53_device *dev, u8 mask)
 444{
 445	unsigned int i;
 446
 447	b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 448		   FAST_AGE_DONE | FAST_AGE_DYNAMIC | mask);
 449
 450	for (i = 0; i < 10; i++) {
 451		u8 fast_age_ctrl;
 452
 453		b53_read8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL,
 454			  &fast_age_ctrl);
 455
 456		if (!(fast_age_ctrl & FAST_AGE_DONE))
 457			goto out;
 458
 459		msleep(1);
 460	}
 461
 462	return -ETIMEDOUT;
 463out:
 464	/* Only age dynamic entries (default behavior) */
 465	b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_CTRL, FAST_AGE_DYNAMIC);
 466	return 0;
 467}
 468
 469static int b53_fast_age_port(struct b53_device *dev, int port)
 470{
 471	b53_write8(dev, B53_CTRL_PAGE, B53_FAST_AGE_PORT_CTRL, port);
 472
 473	return b53_flush_arl(dev, FAST_AGE_PORT);
 474}
 475
 476static int b53_fast_age_vlan(struct b53_device *dev, u16 vid)
 477{
 478	b53_write16(dev, B53_CTRL_PAGE, B53_FAST_AGE_VID_CTRL, vid);
 479
 480	return b53_flush_arl(dev, FAST_AGE_VLAN);
 481}
 482
 483void b53_imp_vlan_setup(struct dsa_switch *ds, int cpu_port)
 484{
 485	struct b53_device *dev = ds->priv;
 486	unsigned int i;
 487	u16 pvlan;
 488
 489	/* Enable the IMP port to be in the same VLAN as the other ports
 490	 * on a per-port basis such that we only have Port i and IMP in
 491	 * the same VLAN.
 492	 */
 493	b53_for_each_port(dev, i) {
 494		b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &pvlan);
 495		pvlan |= BIT(cpu_port);
 496		b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), pvlan);
 497	}
 498}
 499EXPORT_SYMBOL(b53_imp_vlan_setup);
 500
 501int b53_enable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 502{
 503	struct b53_device *dev = ds->priv;
 504	unsigned int cpu_port = ds->ports[port].cpu_dp->index;
 
 505	u16 pvlan;
 506
 
 
 
 
 
 
 
 
 
 
 
 
 507	/* Clear the Rx and Tx disable bits and set to no spanning tree */
 508	b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), 0);
 509
 510	/* Set this port, and only this one to be in the default VLAN,
 511	 * if member of a bridge, restore its membership prior to
 512	 * bringing down this port.
 513	 */
 514	b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
 515	pvlan &= ~0x1ff;
 516	pvlan |= BIT(port);
 517	pvlan |= dev->ports[port].vlan_ctl_mask;
 518	b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
 519
 520	b53_imp_vlan_setup(ds, cpu_port);
 521
 522	/* If EEE was enabled, restore it */
 523	if (dev->ports[port].eee.eee_enabled)
 524		b53_eee_enable_set(ds, port, true);
 525
 526	return 0;
 527}
 528EXPORT_SYMBOL(b53_enable_port);
 529
 530void b53_disable_port(struct dsa_switch *ds, int port, struct phy_device *phy)
 531{
 532	struct b53_device *dev = ds->priv;
 533	u8 reg;
 534
 535	/* Disable Tx/Rx for the port */
 536	b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
 537	reg |= PORT_CTRL_RX_DISABLE | PORT_CTRL_TX_DISABLE;
 538	b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
 
 
 
 539}
 540EXPORT_SYMBOL(b53_disable_port);
 541
 542void b53_brcm_hdr_setup(struct dsa_switch *ds, int port)
 543{
 544	bool tag_en = !(ds->ops->get_tag_protocol(ds, port) ==
 545			 DSA_TAG_PROTO_NONE);
 546	struct b53_device *dev = ds->priv;
 
 547	u8 hdr_ctl, val;
 548	u16 reg;
 549
 550	/* Resolve which bit controls the Broadcom tag */
 551	switch (port) {
 552	case 8:
 553		val = BRCM_HDR_P8_EN;
 554		break;
 555	case 7:
 556		val = BRCM_HDR_P7_EN;
 557		break;
 558	case 5:
 559		val = BRCM_HDR_P5_EN;
 560		break;
 561	default:
 562		val = 0;
 563		break;
 564	}
 565
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 566	/* Enable Broadcom tags for IMP port */
 567	b53_read8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, &hdr_ctl);
 568	if (tag_en)
 569		hdr_ctl |= val;
 570	else
 571		hdr_ctl &= ~val;
 572	b53_write8(dev, B53_MGMT_PAGE, B53_BRCM_HDR, hdr_ctl);
 573
 574	/* Registers below are only accessible on newer devices */
 575	if (!is58xx(dev))
 576		return;
 577
 578	/* Enable reception Broadcom tag for CPU TX (switch RX) to
 579	 * allow us to tag outgoing frames
 580	 */
 581	b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, &reg);
 582	if (tag_en)
 583		reg &= ~BIT(port);
 584	else
 585		reg |= BIT(port);
 586	b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_RX_DIS, reg);
 587
 588	/* Enable transmission of Broadcom tags from the switch (CPU RX) to
 589	 * allow delivering frames to the per-port net_devices
 590	 */
 591	b53_read16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, &reg);
 592	if (tag_en)
 593		reg &= ~BIT(port);
 594	else
 595		reg |= BIT(port);
 596	b53_write16(dev, B53_MGMT_PAGE, B53_BRCM_HDR_TX_DIS, reg);
 597}
 598EXPORT_SYMBOL(b53_brcm_hdr_setup);
 599
 600static void b53_enable_cpu_port(struct b53_device *dev, int port)
 601{
 602	u8 port_ctrl;
 603
 604	/* BCM5325 CPU port is at 8 */
 605	if ((is5325(dev) || is5365(dev)) && port == B53_CPU_PORT_25)
 606		port = B53_CPU_PORT;
 607
 608	port_ctrl = PORT_CTRL_RX_BCST_EN |
 609		    PORT_CTRL_RX_MCST_EN |
 610		    PORT_CTRL_RX_UCST_EN;
 611	b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), port_ctrl);
 612
 613	b53_brcm_hdr_setup(dev->ds, port);
 
 
 614}
 615
 616static void b53_enable_mib(struct b53_device *dev)
 617{
 618	u8 gc;
 619
 620	b53_read8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 621	gc &= ~(GC_RESET_MIB | GC_MIB_AC_EN);
 622	b53_write8(dev, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc);
 623}
 624
 
 
 
 
 
 
 
 
 625int b53_configure_vlan(struct dsa_switch *ds)
 626{
 627	struct b53_device *dev = ds->priv;
 628	struct b53_vlan vl = { 0 };
 629	int i;
 
 
 
 
 630
 631	/* clear all vlan entries */
 632	if (is5325(dev) || is5365(dev)) {
 633		for (i = 1; i < dev->num_vlans; i++)
 634			b53_set_vlan_entry(dev, i, &vl);
 635	} else {
 636		b53_do_vlan_op(dev, VTA_CMD_CLEAR);
 637	}
 638
 639	b53_enable_vlan(dev, false);
 640
 641	b53_for_each_port(dev, i)
 642		b53_write16(dev, B53_VLAN_PAGE,
 643			    B53_VLAN_PORT_DEF_TAG(i), 1);
 644
 645	if (!is5325(dev) && !is5365(dev))
 646		b53_set_jumbo(dev, dev->enable_jumbo, false);
 
 
 
 
 
 
 
 
 
 
 647
 648	return 0;
 649}
 650EXPORT_SYMBOL(b53_configure_vlan);
 651
 652static void b53_switch_reset_gpio(struct b53_device *dev)
 653{
 654	int gpio = dev->reset_gpio;
 655
 656	if (gpio < 0)
 657		return;
 658
 659	/* Reset sequence: RESET low(50ms)->high(20ms)
 660	 */
 661	gpio_set_value(gpio, 0);
 662	mdelay(50);
 663
 664	gpio_set_value(gpio, 1);
 665	mdelay(20);
 666
 667	dev->current_page = 0xff;
 668}
 669
 670static int b53_switch_reset(struct b53_device *dev)
 671{
 672	unsigned int timeout = 1000;
 673	u8 mgmt, reg;
 674
 675	b53_switch_reset_gpio(dev);
 676
 677	if (is539x(dev)) {
 678		b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x83);
 679		b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, 0x00);
 680	}
 681
 682	/* This is specific to 58xx devices here, do not use is58xx() which
 683	 * covers the larger Starfigther 2 family, including 7445/7278 which
 684	 * still use this driver as a library and need to perform the reset
 685	 * earlier.
 686	 */
 687	if (dev->chip_id == BCM58XX_DEVICE_ID) {
 
 688		b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 689		reg |= SW_RST | EN_SW_RST | EN_CH_RST;
 690		b53_write8(dev, B53_CTRL_PAGE, B53_SOFTRESET, reg);
 691
 692		do {
 693			b53_read8(dev, B53_CTRL_PAGE, B53_SOFTRESET, &reg);
 694			if (!(reg & SW_RST))
 695				break;
 696
 697			usleep_range(1000, 2000);
 698		} while (timeout-- > 0);
 699
 700		if (timeout == 0)
 701			return -ETIMEDOUT;
 702	}
 703
 704	b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 705
 706	if (!(mgmt & SM_SW_FWD_EN)) {
 707		mgmt &= ~SM_SW_FWD_MODE;
 708		mgmt |= SM_SW_FWD_EN;
 709
 710		b53_write8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, mgmt);
 711		b53_read8(dev, B53_CTRL_PAGE, B53_SWITCH_MODE, &mgmt);
 712
 713		if (!(mgmt & SM_SW_FWD_EN)) {
 714			dev_err(dev->dev, "Failed to enable switch!\n");
 715			return -EINVAL;
 716		}
 717	}
 718
 719	b53_enable_mib(dev);
 720
 721	return b53_flush_arl(dev, FAST_AGE_STATIC);
 722}
 723
 724static int b53_phy_read16(struct dsa_switch *ds, int addr, int reg)
 725{
 726	struct b53_device *priv = ds->priv;
 727	u16 value = 0;
 728	int ret;
 729
 730	if (priv->ops->phy_read16)
 731		ret = priv->ops->phy_read16(priv, addr, reg, &value);
 732	else
 733		ret = b53_read16(priv, B53_PORT_MII_PAGE(addr),
 734				 reg * 2, &value);
 735
 736	return ret ? ret : value;
 737}
 738
 739static int b53_phy_write16(struct dsa_switch *ds, int addr, int reg, u16 val)
 740{
 741	struct b53_device *priv = ds->priv;
 742
 743	if (priv->ops->phy_write16)
 744		return priv->ops->phy_write16(priv, addr, reg, val);
 745
 746	return b53_write16(priv, B53_PORT_MII_PAGE(addr), reg * 2, val);
 747}
 748
 749static int b53_reset_switch(struct b53_device *priv)
 750{
 751	/* reset vlans */
 752	priv->enable_jumbo = false;
 753
 754	memset(priv->vlans, 0, sizeof(*priv->vlans) * priv->num_vlans);
 755	memset(priv->ports, 0, sizeof(*priv->ports) * priv->num_ports);
 756
 
 
 757	return b53_switch_reset(priv);
 758}
 759
 760static int b53_apply_config(struct b53_device *priv)
 761{
 762	/* disable switching */
 763	b53_set_forwarding(priv, 0);
 764
 765	b53_configure_vlan(priv->ds);
 766
 767	/* enable switching */
 768	b53_set_forwarding(priv, 1);
 769
 770	return 0;
 771}
 772
 773static void b53_reset_mib(struct b53_device *priv)
 774{
 775	u8 gc;
 776
 777	b53_read8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, &gc);
 778
 779	b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc | GC_RESET_MIB);
 780	msleep(1);
 781	b53_write8(priv, B53_MGMT_PAGE, B53_GLOBAL_CONFIG, gc & ~GC_RESET_MIB);
 782	msleep(1);
 783}
 784
 785static const struct b53_mib_desc *b53_get_mib(struct b53_device *dev)
 786{
 787	if (is5365(dev))
 788		return b53_mibs_65;
 789	else if (is63xx(dev))
 790		return b53_mibs_63xx;
 791	else if (is58xx(dev))
 792		return b53_mibs_58xx;
 793	else
 794		return b53_mibs;
 795}
 796
 797static unsigned int b53_get_mib_size(struct b53_device *dev)
 798{
 799	if (is5365(dev))
 800		return B53_MIBS_65_SIZE;
 801	else if (is63xx(dev))
 802		return B53_MIBS_63XX_SIZE;
 803	else if (is58xx(dev))
 804		return B53_MIBS_58XX_SIZE;
 805	else
 806		return B53_MIBS_SIZE;
 807}
 808
 809void b53_get_strings(struct dsa_switch *ds, int port, uint8_t *data)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 810{
 811	struct b53_device *dev = ds->priv;
 812	const struct b53_mib_desc *mibs = b53_get_mib(dev);
 813	unsigned int mib_size = b53_get_mib_size(dev);
 
 814	unsigned int i;
 815
 816	for (i = 0; i < mib_size; i++)
 817		strlcpy(data + i * ETH_GSTRING_LEN,
 818			mibs[i].name, ETH_GSTRING_LEN);
 
 
 
 
 
 
 
 
 819}
 820EXPORT_SYMBOL(b53_get_strings);
 821
 822void b53_get_ethtool_stats(struct dsa_switch *ds, int port, uint64_t *data)
 823{
 824	struct b53_device *dev = ds->priv;
 825	const struct b53_mib_desc *mibs = b53_get_mib(dev);
 826	unsigned int mib_size = b53_get_mib_size(dev);
 827	const struct b53_mib_desc *s;
 828	unsigned int i;
 829	u64 val = 0;
 830
 831	if (is5365(dev) && port == 5)
 832		port = 8;
 833
 834	mutex_lock(&dev->stats_mutex);
 835
 836	for (i = 0; i < mib_size; i++) {
 837		s = &mibs[i];
 838
 839		if (s->size == 8) {
 840			b53_read64(dev, B53_MIB_PAGE(port), s->offset, &val);
 841		} else {
 842			u32 val32;
 843
 844			b53_read32(dev, B53_MIB_PAGE(port), s->offset,
 845				   &val32);
 846			val = val32;
 847		}
 848		data[i] = (u64)val;
 849	}
 850
 851	mutex_unlock(&dev->stats_mutex);
 852}
 853EXPORT_SYMBOL(b53_get_ethtool_stats);
 854
 855int b53_get_sset_count(struct dsa_switch *ds, int port)
 
 
 
 
 
 
 
 
 
 
 
 
 856{
 857	struct b53_device *dev = ds->priv;
 
 
 
 
 
 
 
 
 
 
 
 858
 859	return b53_get_mib_size(dev);
 860}
 861EXPORT_SYMBOL(b53_get_sset_count);
 862
 863static int b53_setup(struct dsa_switch *ds)
 864{
 865	struct b53_device *dev = ds->priv;
 866	unsigned int port;
 867	int ret;
 868
 869	ret = b53_reset_switch(dev);
 870	if (ret) {
 871		dev_err(ds->dev, "failed to reset switch\n");
 872		return ret;
 873	}
 874
 875	b53_reset_mib(dev);
 876
 877	ret = b53_apply_config(dev);
 878	if (ret)
 879		dev_err(ds->dev, "failed to apply configuration\n");
 880
 881	/* Configure IMP/CPU port, disable unused ports. Enabled
 882	 * ports will be configured with .port_enable
 883	 */
 884	for (port = 0; port < dev->num_ports; port++) {
 885		if (dsa_is_cpu_port(ds, port))
 886			b53_enable_cpu_port(dev, port);
 887		else if (dsa_is_unused_port(ds, port))
 888			b53_disable_port(ds, port, NULL);
 889	}
 890
 
 
 
 
 
 
 
 891	return ret;
 892}
 893
 894static void b53_adjust_link(struct dsa_switch *ds, int port,
 895			    struct phy_device *phydev)
 896{
 897	struct b53_device *dev = ds->priv;
 898	struct ethtool_eee *p = &dev->ports[port].eee;
 899	u8 rgmii_ctrl = 0, reg = 0, off;
 900
 901	if (!phy_is_pseudo_fixed_link(phydev))
 902		return;
 903
 904	/* Override the port settings */
 905	if (port == dev->cpu_port) {
 906		off = B53_PORT_OVERRIDE_CTRL;
 907		reg = PORT_OVERRIDE_EN;
 908	} else {
 909		off = B53_GMII_PORT_OVERRIDE_CTRL(port);
 910		reg = GMII_PO_EN;
 911	}
 912
 913	/* Set the link UP */
 914	if (phydev->link)
 
 915		reg |= PORT_OVERRIDE_LINK;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 916
 917	if (phydev->duplex == DUPLEX_FULL)
 
 
 918		reg |= PORT_OVERRIDE_FULL_DUPLEX;
 
 
 919
 920	switch (phydev->speed) {
 921	case 2000:
 922		reg |= PORT_OVERRIDE_SPEED_2000M;
 923		/* fallthrough */
 924	case SPEED_1000:
 925		reg |= PORT_OVERRIDE_SPEED_1000M;
 926		break;
 927	case SPEED_100:
 928		reg |= PORT_OVERRIDE_SPEED_100M;
 929		break;
 930	case SPEED_10:
 931		reg |= PORT_OVERRIDE_SPEED_10M;
 932		break;
 933	default:
 934		dev_err(ds->dev, "unknown speed: %d\n", phydev->speed);
 935		return;
 936	}
 937
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 938	/* Enable flow control on BCM5301x's CPU port */
 939	if (is5301x(dev) && port == dev->cpu_port)
 940		reg |= PORT_OVERRIDE_RX_FLOW | PORT_OVERRIDE_TX_FLOW;
 941
 942	if (phydev->pause) {
 943		if (phydev->asym_pause)
 944			reg |= PORT_OVERRIDE_TX_FLOW;
 945		reg |= PORT_OVERRIDE_RX_FLOW;
 946	}
 947
 948	b53_write8(dev, B53_CTRL_PAGE, off, reg);
 
 
 949
 950	if (is531x5(dev) && phy_interface_is_rgmii(phydev)) {
 951		if (port == 8)
 952			off = B53_RGMII_CTRL_IMP;
 953		else
 954			off = B53_RGMII_CTRL_P(port);
 955
 956		/* Configure the port RGMII clock delay by DLL disabled and
 957		 * tx_clk aligned timing (restoring to reset defaults)
 958		 */
 959		b53_read8(dev, B53_CTRL_PAGE, off, &rgmii_ctrl);
 960		rgmii_ctrl &= ~(RGMII_CTRL_DLL_RXC | RGMII_CTRL_DLL_TXC |
 961				RGMII_CTRL_TIMING_SEL);
 962
 963		/* PHY_INTERFACE_MODE_RGMII_TXID means TX internal delay, make
 964		 * sure that we enable the port TX clock internal delay to
 965		 * account for this internal delay that is inserted, otherwise
 966		 * the switch won't be able to receive correctly.
 967		 *
 968		 * PHY_INTERFACE_MODE_RGMII means that we are not introducing
 969		 * any delay neither on transmission nor reception, so the
 970		 * BCM53125 must also be configured accordingly to account for
 971		 * the lack of delay and introduce
 972		 *
 973		 * The BCM53125 switch has its RX clock and TX clock control
 974		 * swapped, hence the reason why we modify the TX clock path in
 975		 * the "RGMII" case
 976		 */
 977		if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 978			rgmii_ctrl |= RGMII_CTRL_DLL_TXC;
 979		if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
 980			rgmii_ctrl |= RGMII_CTRL_DLL_TXC | RGMII_CTRL_DLL_RXC;
 981		rgmii_ctrl |= RGMII_CTRL_TIMING_SEL;
 982		b53_write8(dev, B53_CTRL_PAGE, off, rgmii_ctrl);
 983
 984		dev_info(ds->dev, "Configured port %d for %s\n", port,
 985			 phy_modes(phydev->interface));
 986	}
 987
 988	/* configure MII port if necessary */
 989	if (is5325(dev)) {
 990		b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
 991			  &reg);
 992
 993		/* reverse mii needs to be enabled */
 994		if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
 995			b53_write8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
 996				   reg | PORT_OVERRIDE_RV_MII_25);
 997			b53_read8(dev, B53_CTRL_PAGE, B53_PORT_OVERRIDE_CTRL,
 998				  &reg);
 999
1000			if (!(reg & PORT_OVERRIDE_RV_MII_25)) {
1001				dev_err(ds->dev,
1002					"Failed to enable reverse MII mode\n");
1003				return;
1004			}
1005		}
1006	} else if (is5301x(dev)) {
1007		if (port != dev->cpu_port) {
1008			u8 po_reg = B53_GMII_PORT_OVERRIDE_CTRL(dev->cpu_port);
1009			u8 gmii_po;
1010
1011			b53_read8(dev, B53_CTRL_PAGE, po_reg, &gmii_po);
1012			gmii_po |= GMII_PO_LINK |
1013				   GMII_PO_RX_FLOW |
1014				   GMII_PO_TX_FLOW |
1015				   GMII_PO_EN |
1016				   GMII_PO_SPEED_2000M;
1017			b53_write8(dev, B53_CTRL_PAGE, po_reg, gmii_po);
1018		}
1019	}
1020
1021	/* Re-negotiate EEE if it was enabled already */
1022	p->eee_enabled = b53_eee_init(ds, port, phydev);
1023}
1024
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1025int b53_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering)
1026{
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1027	return 0;
1028}
1029EXPORT_SYMBOL(b53_vlan_filtering);
1030
1031int b53_vlan_prepare(struct dsa_switch *ds, int port,
1032		     const struct switchdev_obj_port_vlan *vlan)
1033{
1034	struct b53_device *dev = ds->priv;
1035
1036	if ((is5325(dev) || is5365(dev)) && vlan->vid_begin == 0)
1037		return -EOPNOTSUPP;
1038
 
 
 
 
 
 
 
 
1039	if (vlan->vid_end > dev->num_vlans)
1040		return -ERANGE;
1041
1042	b53_enable_vlan(dev, true);
1043
1044	return 0;
1045}
1046EXPORT_SYMBOL(b53_vlan_prepare);
1047
1048void b53_vlan_add(struct dsa_switch *ds, int port,
1049		  const struct switchdev_obj_port_vlan *vlan)
1050{
1051	struct b53_device *dev = ds->priv;
1052	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1053	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1054	struct b53_vlan *vl;
1055	u16 vid;
1056
1057	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1058		vl = &dev->vlans[vid];
1059
1060		b53_get_vlan_entry(dev, vid, vl);
1061
 
 
 
1062		vl->members |= BIT(port);
1063		if (untagged)
1064			vl->untag |= BIT(port);
1065		else
1066			vl->untag &= ~BIT(port);
1067
1068		b53_set_vlan_entry(dev, vid, vl);
1069		b53_fast_age_vlan(dev, vid);
1070	}
1071
1072	if (pvid) {
1073		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port),
1074			    vlan->vid_end);
1075		b53_fast_age_vlan(dev, vid);
1076	}
1077}
1078EXPORT_SYMBOL(b53_vlan_add);
1079
1080int b53_vlan_del(struct dsa_switch *ds, int port,
1081		 const struct switchdev_obj_port_vlan *vlan)
1082{
1083	struct b53_device *dev = ds->priv;
1084	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1085	struct b53_vlan *vl;
1086	u16 vid;
1087	u16 pvid;
1088
1089	b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), &pvid);
1090
1091	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1092		vl = &dev->vlans[vid];
1093
1094		b53_get_vlan_entry(dev, vid, vl);
1095
1096		vl->members &= ~BIT(port);
1097
1098		if (pvid == vid) {
1099			if (is5325(dev) || is5365(dev))
1100				pvid = 1;
1101			else
1102				pvid = 0;
1103		}
1104
1105		if (untagged)
1106			vl->untag &= ~(BIT(port));
1107
1108		b53_set_vlan_entry(dev, vid, vl);
1109		b53_fast_age_vlan(dev, vid);
1110	}
1111
1112	b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_PORT_DEF_TAG(port), pvid);
1113	b53_fast_age_vlan(dev, pvid);
1114
1115	return 0;
1116}
1117EXPORT_SYMBOL(b53_vlan_del);
1118
1119/* Address Resolution Logic routines */
1120static int b53_arl_op_wait(struct b53_device *dev)
1121{
1122	unsigned int timeout = 10;
1123	u8 reg;
1124
1125	do {
1126		b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1127		if (!(reg & ARLTBL_START_DONE))
1128			return 0;
1129
1130		usleep_range(1000, 2000);
1131	} while (timeout--);
1132
1133	dev_warn(dev->dev, "timeout waiting for ARL to finish: 0x%02x\n", reg);
1134
1135	return -ETIMEDOUT;
1136}
1137
1138static int b53_arl_rw_op(struct b53_device *dev, unsigned int op)
1139{
1140	u8 reg;
1141
1142	if (op > ARLTBL_RW)
1143		return -EINVAL;
1144
1145	b53_read8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, &reg);
1146	reg |= ARLTBL_START_DONE;
1147	if (op)
1148		reg |= ARLTBL_RW;
1149	else
1150		reg &= ~ARLTBL_RW;
 
 
 
 
1151	b53_write8(dev, B53_ARLIO_PAGE, B53_ARLTBL_RW_CTRL, reg);
1152
1153	return b53_arl_op_wait(dev);
1154}
1155
1156static int b53_arl_read(struct b53_device *dev, u64 mac,
1157			u16 vid, struct b53_arl_entry *ent, u8 *idx,
1158			bool is_valid)
1159{
 
1160	unsigned int i;
1161	int ret;
1162
1163	ret = b53_arl_op_wait(dev);
1164	if (ret)
1165		return ret;
1166
 
 
1167	/* Read the bins */
1168	for (i = 0; i < dev->num_arl_entries; i++) {
1169		u64 mac_vid;
1170		u32 fwd_entry;
1171
1172		b53_read64(dev, B53_ARLIO_PAGE,
1173			   B53_ARLTBL_MAC_VID_ENTRY(i), &mac_vid);
1174		b53_read32(dev, B53_ARLIO_PAGE,
1175			   B53_ARLTBL_DATA_ENTRY(i), &fwd_entry);
1176		b53_arl_to_entry(ent, mac_vid, fwd_entry);
1177
1178		if (!(fwd_entry & ARLTBL_VALID))
 
1179			continue;
 
1180		if ((mac_vid & ARLTBL_MAC_MASK) != mac)
1181			continue;
 
 
 
1182		*idx = i;
 
1183	}
1184
 
 
 
 
 
1185	return -ENOENT;
1186}
1187
1188static int b53_arl_op(struct b53_device *dev, int op, int port,
1189		      const unsigned char *addr, u16 vid, bool is_valid)
1190{
1191	struct b53_arl_entry ent;
1192	u32 fwd_entry;
1193	u64 mac, mac_vid = 0;
1194	u8 idx = 0;
1195	int ret;
1196
1197	/* Convert the array into a 64-bit MAC */
1198	mac = ether_addr_to_u64(addr);
1199
1200	/* Perform a read for the given MAC and VID */
1201	b53_write48(dev, B53_ARLIO_PAGE, B53_MAC_ADDR_IDX, mac);
1202	b53_write16(dev, B53_ARLIO_PAGE, B53_VLAN_ID_IDX, vid);
1203
1204	/* Issue a read operation for this MAC */
1205	ret = b53_arl_rw_op(dev, 1);
1206	if (ret)
1207		return ret;
1208
1209	ret = b53_arl_read(dev, mac, vid, &ent, &idx, is_valid);
 
1210	/* If this is a read, just finish now */
1211	if (op)
1212		return ret;
1213
1214	/* We could not find a matching MAC, so reset to a new entry */
1215	if (ret) {
 
 
 
 
 
 
 
 
 
1216		fwd_entry = 0;
1217		idx = 1;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1218	}
1219
1220	memset(&ent, 0, sizeof(ent));
1221	ent.port = port;
1222	ent.is_valid = is_valid;
1223	ent.vid = vid;
1224	ent.is_static = true;
 
1225	memcpy(ent.mac, addr, ETH_ALEN);
1226	b53_arl_from_entry(&mac_vid, &fwd_entry, &ent);
1227
1228	b53_write64(dev, B53_ARLIO_PAGE,
1229		    B53_ARLTBL_MAC_VID_ENTRY(idx), mac_vid);
1230	b53_write32(dev, B53_ARLIO_PAGE,
1231		    B53_ARLTBL_DATA_ENTRY(idx), fwd_entry);
1232
1233	return b53_arl_rw_op(dev, 0);
1234}
1235
1236int b53_fdb_add(struct dsa_switch *ds, int port,
1237		const unsigned char *addr, u16 vid)
1238{
1239	struct b53_device *priv = ds->priv;
1240
1241	/* 5325 and 5365 require some more massaging, but could
1242	 * be supported eventually
1243	 */
1244	if (is5325(priv) || is5365(priv))
1245		return -EOPNOTSUPP;
1246
1247	return b53_arl_op(priv, 0, port, addr, vid, true);
1248}
1249EXPORT_SYMBOL(b53_fdb_add);
1250
1251int b53_fdb_del(struct dsa_switch *ds, int port,
1252		const unsigned char *addr, u16 vid)
1253{
1254	struct b53_device *priv = ds->priv;
1255
1256	return b53_arl_op(priv, 0, port, addr, vid, false);
1257}
1258EXPORT_SYMBOL(b53_fdb_del);
1259
1260static int b53_arl_search_wait(struct b53_device *dev)
1261{
1262	unsigned int timeout = 1000;
1263	u8 reg;
1264
1265	do {
1266		b53_read8(dev, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, &reg);
1267		if (!(reg & ARL_SRCH_STDN))
1268			return 0;
1269
1270		if (reg & ARL_SRCH_VLID)
1271			return 0;
1272
1273		usleep_range(1000, 2000);
1274	} while (timeout--);
1275
1276	return -ETIMEDOUT;
1277}
1278
1279static void b53_arl_search_rd(struct b53_device *dev, u8 idx,
1280			      struct b53_arl_entry *ent)
1281{
1282	u64 mac_vid;
1283	u32 fwd_entry;
1284
1285	b53_read64(dev, B53_ARLIO_PAGE,
1286		   B53_ARL_SRCH_RSTL_MACVID(idx), &mac_vid);
1287	b53_read32(dev, B53_ARLIO_PAGE,
1288		   B53_ARL_SRCH_RSTL(idx), &fwd_entry);
1289	b53_arl_to_entry(ent, mac_vid, fwd_entry);
1290}
1291
1292static int b53_fdb_copy(int port, const struct b53_arl_entry *ent,
1293			dsa_fdb_dump_cb_t *cb, void *data)
1294{
1295	if (!ent->is_valid)
1296		return 0;
1297
1298	if (port != ent->port)
1299		return 0;
1300
1301	return cb(ent->mac, ent->vid, ent->is_static, data);
1302}
1303
1304int b53_fdb_dump(struct dsa_switch *ds, int port,
1305		 dsa_fdb_dump_cb_t *cb, void *data)
1306{
1307	struct b53_device *priv = ds->priv;
1308	struct b53_arl_entry results[2];
1309	unsigned int count = 0;
1310	int ret;
1311	u8 reg;
1312
1313	/* Start search operation */
1314	reg = ARL_SRCH_STDN;
1315	b53_write8(priv, B53_ARLIO_PAGE, B53_ARL_SRCH_CTL, reg);
1316
1317	do {
1318		ret = b53_arl_search_wait(priv);
1319		if (ret)
1320			return ret;
1321
1322		b53_arl_search_rd(priv, 0, &results[0]);
1323		ret = b53_fdb_copy(port, &results[0], cb, data);
1324		if (ret)
1325			return ret;
1326
1327		if (priv->num_arl_entries > 2) {
1328			b53_arl_search_rd(priv, 1, &results[1]);
1329			ret = b53_fdb_copy(port, &results[1], cb, data);
1330			if (ret)
1331				return ret;
1332
1333			if (!results[0].is_valid && !results[1].is_valid)
1334				break;
1335		}
1336
1337	} while (count++ < 1024);
1338
1339	return 0;
1340}
1341EXPORT_SYMBOL(b53_fdb_dump);
1342
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1343int b53_br_join(struct dsa_switch *ds, int port, struct net_device *br)
1344{
1345	struct b53_device *dev = ds->priv;
1346	s8 cpu_port = ds->ports[port].cpu_dp->index;
1347	u16 pvlan, reg;
1348	unsigned int i;
1349
 
 
 
 
 
 
1350	/* Make this port leave the all VLANs join since we will have proper
1351	 * VLAN entries from now on
1352	 */
1353	if (is58xx(dev)) {
1354		b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1355		reg &= ~BIT(port);
1356		if ((reg & BIT(cpu_port)) == BIT(cpu_port))
1357			reg &= ~BIT(cpu_port);
1358		b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1359	}
1360
1361	b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1362
1363	b53_for_each_port(dev, i) {
1364		if (dsa_to_port(ds, i)->bridge_dev != br)
1365			continue;
1366
1367		/* Add this local port to the remote port VLAN control
1368		 * membership and update the remote port bitmask
1369		 */
1370		b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1371		reg |= BIT(port);
1372		b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1373		dev->ports[i].vlan_ctl_mask = reg;
1374
1375		pvlan |= BIT(i);
1376	}
1377
1378	/* Configure the local port VLAN control membership to include
1379	 * remote ports and update the local port bitmask
1380	 */
1381	b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1382	dev->ports[port].vlan_ctl_mask = pvlan;
1383
1384	return 0;
1385}
1386EXPORT_SYMBOL(b53_br_join);
1387
1388void b53_br_leave(struct dsa_switch *ds, int port, struct net_device *br)
1389{
1390	struct b53_device *dev = ds->priv;
1391	struct b53_vlan *vl = &dev->vlans[0];
1392	s8 cpu_port = ds->ports[port].cpu_dp->index;
1393	unsigned int i;
1394	u16 pvlan, reg, pvid;
1395
1396	b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), &pvlan);
1397
1398	b53_for_each_port(dev, i) {
1399		/* Don't touch the remaining ports */
1400		if (dsa_to_port(ds, i)->bridge_dev != br)
1401			continue;
1402
1403		b53_read16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), &reg);
1404		reg &= ~BIT(port);
1405		b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(i), reg);
1406		dev->ports[port].vlan_ctl_mask = reg;
1407
1408		/* Prevent self removal to preserve isolation */
1409		if (port != i)
1410			pvlan &= ~BIT(i);
1411	}
1412
1413	b53_write16(dev, B53_PVLAN_PAGE, B53_PVLAN_PORT_MASK(port), pvlan);
1414	dev->ports[port].vlan_ctl_mask = pvlan;
1415
1416	if (is5325(dev) || is5365(dev))
1417		pvid = 1;
1418	else
1419		pvid = 0;
1420
1421	/* Make this port join all VLANs without VLAN entries */
1422	if (is58xx(dev)) {
1423		b53_read16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, &reg);
1424		reg |= BIT(port);
1425		if (!(reg & BIT(cpu_port)))
1426			reg |= BIT(cpu_port);
1427		b53_write16(dev, B53_VLAN_PAGE, B53_JOIN_ALL_VLAN_EN, reg);
1428	} else {
1429		b53_get_vlan_entry(dev, pvid, vl);
1430		vl->members |= BIT(port) | BIT(cpu_port);
1431		vl->untag |= BIT(port) | BIT(cpu_port);
1432		b53_set_vlan_entry(dev, pvid, vl);
1433	}
1434}
1435EXPORT_SYMBOL(b53_br_leave);
1436
1437void b53_br_set_stp_state(struct dsa_switch *ds, int port, u8 state)
1438{
1439	struct b53_device *dev = ds->priv;
1440	u8 hw_state;
1441	u8 reg;
1442
1443	switch (state) {
1444	case BR_STATE_DISABLED:
1445		hw_state = PORT_CTRL_DIS_STATE;
1446		break;
1447	case BR_STATE_LISTENING:
1448		hw_state = PORT_CTRL_LISTEN_STATE;
1449		break;
1450	case BR_STATE_LEARNING:
1451		hw_state = PORT_CTRL_LEARN_STATE;
1452		break;
1453	case BR_STATE_FORWARDING:
1454		hw_state = PORT_CTRL_FWD_STATE;
1455		break;
1456	case BR_STATE_BLOCKING:
1457		hw_state = PORT_CTRL_BLOCK_STATE;
1458		break;
1459	default:
1460		dev_err(ds->dev, "invalid STP state: %d\n", state);
1461		return;
1462	}
1463
1464	b53_read8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), &reg);
1465	reg &= ~PORT_CTRL_STP_STATE_MASK;
1466	reg |= hw_state;
1467	b53_write8(dev, B53_CTRL_PAGE, B53_PORT_CTRL(port), reg);
1468}
1469EXPORT_SYMBOL(b53_br_set_stp_state);
1470
1471void b53_br_fast_age(struct dsa_switch *ds, int port)
1472{
1473	struct b53_device *dev = ds->priv;
1474
1475	if (b53_fast_age_port(dev, port))
1476		dev_err(ds->dev, "fast ageing failed\n");
1477}
1478EXPORT_SYMBOL(b53_br_fast_age);
1479
1480static bool b53_can_enable_brcm_tags(struct dsa_switch *ds, int port)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1481{
1482	/* Broadcom switches will accept enabling Broadcom tags on the
1483	 * following ports: 5, 7 and 8, any other port is not supported
1484	 */
1485	switch (port) {
1486	case B53_CPU_PORT_25:
1487	case 7:
1488	case B53_CPU_PORT:
1489		return true;
1490	}
1491
1492	dev_warn(ds->dev, "Port %d is not Broadcom tag capable\n", port);
1493	return false;
1494}
1495
1496enum dsa_tag_protocol b53_get_tag_protocol(struct dsa_switch *ds, int port)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1497{
1498	struct b53_device *dev = ds->priv;
1499
1500	/* Older models (5325, 5365) support a different tag format that we do
1501	 * not support in net/dsa/tag_brcm.c yet. 539x and 531x5 require managed
1502	 * mode to be turned on which means we need to specifically manage ARL
1503	 * misses on multicast addresses (TBD).
1504	 */
1505	if (is5325(dev) || is5365(dev) || is539x(dev) || is531x5(dev) ||
1506	    !b53_can_enable_brcm_tags(ds, port))
1507		return DSA_TAG_PROTO_NONE;
1508
1509	/* Broadcom BCM58xx chips have a flow accelerator on Port 8
1510	 * which requires us to use the prepended Broadcom tag type
1511	 */
1512	if (dev->chip_id == BCM58XX_DEVICE_ID && port == B53_CPU_PORT)
1513		return DSA_TAG_PROTO_BRCM_PREPEND;
 
 
1514
1515	return DSA_TAG_PROTO_BRCM;
 
 
1516}
1517EXPORT_SYMBOL(b53_get_tag_protocol);
1518
1519int b53_mirror_add(struct dsa_switch *ds, int port,
1520		   struct dsa_mall_mirror_tc_entry *mirror, bool ingress)
1521{
1522	struct b53_device *dev = ds->priv;
1523	u16 reg, loc;
1524
1525	if (ingress)
1526		loc = B53_IG_MIR_CTL;
1527	else
1528		loc = B53_EG_MIR_CTL;
1529
1530	b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1531	reg &= ~MIRROR_MASK;
1532	reg |= BIT(port);
1533	b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1534
1535	b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1536	reg &= ~CAP_PORT_MASK;
1537	reg |= mirror->to_local_port;
1538	reg |= MIRROR_EN;
1539	b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1540
1541	return 0;
1542}
1543EXPORT_SYMBOL(b53_mirror_add);
1544
1545void b53_mirror_del(struct dsa_switch *ds, int port,
1546		    struct dsa_mall_mirror_tc_entry *mirror)
1547{
1548	struct b53_device *dev = ds->priv;
1549	bool loc_disable = false, other_loc_disable = false;
1550	u16 reg, loc;
1551
1552	if (mirror->ingress)
1553		loc = B53_IG_MIR_CTL;
1554	else
1555		loc = B53_EG_MIR_CTL;
1556
1557	/* Update the desired ingress/egress register */
1558	b53_read16(dev, B53_MGMT_PAGE, loc, &reg);
1559	reg &= ~BIT(port);
1560	if (!(reg & MIRROR_MASK))
1561		loc_disable = true;
1562	b53_write16(dev, B53_MGMT_PAGE, loc, reg);
1563
1564	/* Now look at the other one to know if we can disable mirroring
1565	 * entirely
1566	 */
1567	if (mirror->ingress)
1568		b53_read16(dev, B53_MGMT_PAGE, B53_EG_MIR_CTL, &reg);
1569	else
1570		b53_read16(dev, B53_MGMT_PAGE, B53_IG_MIR_CTL, &reg);
1571	if (!(reg & MIRROR_MASK))
1572		other_loc_disable = true;
1573
1574	b53_read16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, &reg);
1575	/* Both no longer have ports, let's disable mirroring */
1576	if (loc_disable && other_loc_disable) {
1577		reg &= ~MIRROR_EN;
1578		reg &= ~mirror->to_local_port;
1579	}
1580	b53_write16(dev, B53_MGMT_PAGE, B53_MIR_CAP_CTL, reg);
1581}
1582EXPORT_SYMBOL(b53_mirror_del);
1583
1584void b53_eee_enable_set(struct dsa_switch *ds, int port, bool enable)
1585{
1586	struct b53_device *dev = ds->priv;
1587	u16 reg;
1588
1589	b53_read16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, &reg);
1590	if (enable)
1591		reg |= BIT(port);
1592	else
1593		reg &= ~BIT(port);
1594	b53_write16(dev, B53_EEE_PAGE, B53_EEE_EN_CTRL, reg);
1595}
1596EXPORT_SYMBOL(b53_eee_enable_set);
1597
1598
1599/* Returns 0 if EEE was not enabled, or 1 otherwise
1600 */
1601int b53_eee_init(struct dsa_switch *ds, int port, struct phy_device *phy)
1602{
1603	int ret;
1604
1605	ret = phy_init_eee(phy, 0);
1606	if (ret)
1607		return 0;
1608
1609	b53_eee_enable_set(ds, port, true);
1610
1611	return 1;
1612}
1613EXPORT_SYMBOL(b53_eee_init);
1614
1615int b53_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1616{
1617	struct b53_device *dev = ds->priv;
1618	struct ethtool_eee *p = &dev->ports[port].eee;
1619	u16 reg;
1620
1621	if (is5325(dev) || is5365(dev))
1622		return -EOPNOTSUPP;
1623
1624	b53_read16(dev, B53_EEE_PAGE, B53_EEE_LPI_INDICATE, &reg);
1625	e->eee_enabled = p->eee_enabled;
1626	e->eee_active = !!(reg & BIT(port));
1627
1628	return 0;
1629}
1630EXPORT_SYMBOL(b53_get_mac_eee);
1631
1632int b53_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
1633{
1634	struct b53_device *dev = ds->priv;
1635	struct ethtool_eee *p = &dev->ports[port].eee;
1636
1637	if (is5325(dev) || is5365(dev))
1638		return -EOPNOTSUPP;
1639
1640	p->eee_enabled = e->eee_enabled;
1641	b53_eee_enable_set(ds, port, e->eee_enabled);
1642
1643	return 0;
1644}
1645EXPORT_SYMBOL(b53_set_mac_eee);
1646
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1647static const struct dsa_switch_ops b53_switch_ops = {
1648	.get_tag_protocol	= b53_get_tag_protocol,
1649	.setup			= b53_setup,
1650	.get_strings		= b53_get_strings,
1651	.get_ethtool_stats	= b53_get_ethtool_stats,
1652	.get_sset_count		= b53_get_sset_count,
 
1653	.phy_read		= b53_phy_read16,
1654	.phy_write		= b53_phy_write16,
1655	.adjust_link		= b53_adjust_link,
 
 
 
 
 
 
1656	.port_enable		= b53_enable_port,
1657	.port_disable		= b53_disable_port,
1658	.get_mac_eee		= b53_get_mac_eee,
1659	.set_mac_eee		= b53_set_mac_eee,
1660	.port_bridge_join	= b53_br_join,
1661	.port_bridge_leave	= b53_br_leave,
1662	.port_stp_state_set	= b53_br_set_stp_state,
1663	.port_fast_age		= b53_br_fast_age,
 
1664	.port_vlan_filtering	= b53_vlan_filtering,
1665	.port_vlan_prepare	= b53_vlan_prepare,
1666	.port_vlan_add		= b53_vlan_add,
1667	.port_vlan_del		= b53_vlan_del,
1668	.port_fdb_dump		= b53_fdb_dump,
1669	.port_fdb_add		= b53_fdb_add,
1670	.port_fdb_del		= b53_fdb_del,
1671	.port_mirror_add	= b53_mirror_add,
1672	.port_mirror_del	= b53_mirror_del,
 
 
 
 
 
1673};
1674
1675struct b53_chip_data {
1676	u32 chip_id;
1677	const char *dev_name;
1678	u16 vlans;
1679	u16 enabled_ports;
1680	u8 cpu_port;
1681	u8 vta_regs[3];
1682	u8 arl_entries;
 
1683	u8 duplex_reg;
1684	u8 jumbo_pm_reg;
1685	u8 jumbo_size_reg;
1686};
1687
1688#define B53_VTA_REGS	\
1689	{ B53_VT_ACCESS, B53_VT_INDEX, B53_VT_ENTRY }
1690#define B53_VTA_REGS_9798 \
1691	{ B53_VT_ACCESS_9798, B53_VT_INDEX_9798, B53_VT_ENTRY_9798 }
1692#define B53_VTA_REGS_63XX \
1693	{ B53_VT_ACCESS_63XX, B53_VT_INDEX_63XX, B53_VT_ENTRY_63XX }
1694
1695static const struct b53_chip_data b53_switch_chips[] = {
1696	{
1697		.chip_id = BCM5325_DEVICE_ID,
1698		.dev_name = "BCM5325",
1699		.vlans = 16,
1700		.enabled_ports = 0x1f,
1701		.arl_entries = 2,
 
1702		.cpu_port = B53_CPU_PORT_25,
1703		.duplex_reg = B53_DUPLEX_STAT_FE,
1704	},
1705	{
1706		.chip_id = BCM5365_DEVICE_ID,
1707		.dev_name = "BCM5365",
1708		.vlans = 256,
1709		.enabled_ports = 0x1f,
1710		.arl_entries = 2,
 
1711		.cpu_port = B53_CPU_PORT_25,
1712		.duplex_reg = B53_DUPLEX_STAT_FE,
1713	},
1714	{
1715		.chip_id = BCM5389_DEVICE_ID,
1716		.dev_name = "BCM5389",
1717		.vlans = 4096,
1718		.enabled_ports = 0x1f,
1719		.arl_entries = 4,
 
1720		.cpu_port = B53_CPU_PORT,
1721		.vta_regs = B53_VTA_REGS,
1722		.duplex_reg = B53_DUPLEX_STAT_GE,
1723		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1724		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1725	},
1726	{
1727		.chip_id = BCM5395_DEVICE_ID,
1728		.dev_name = "BCM5395",
1729		.vlans = 4096,
1730		.enabled_ports = 0x1f,
1731		.arl_entries = 4,
 
1732		.cpu_port = B53_CPU_PORT,
1733		.vta_regs = B53_VTA_REGS,
1734		.duplex_reg = B53_DUPLEX_STAT_GE,
1735		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1736		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1737	},
1738	{
1739		.chip_id = BCM5397_DEVICE_ID,
1740		.dev_name = "BCM5397",
1741		.vlans = 4096,
1742		.enabled_ports = 0x1f,
1743		.arl_entries = 4,
 
1744		.cpu_port = B53_CPU_PORT,
1745		.vta_regs = B53_VTA_REGS_9798,
1746		.duplex_reg = B53_DUPLEX_STAT_GE,
1747		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1748		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1749	},
1750	{
1751		.chip_id = BCM5398_DEVICE_ID,
1752		.dev_name = "BCM5398",
1753		.vlans = 4096,
1754		.enabled_ports = 0x7f,
1755		.arl_entries = 4,
 
1756		.cpu_port = B53_CPU_PORT,
1757		.vta_regs = B53_VTA_REGS_9798,
1758		.duplex_reg = B53_DUPLEX_STAT_GE,
1759		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1760		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1761	},
1762	{
1763		.chip_id = BCM53115_DEVICE_ID,
1764		.dev_name = "BCM53115",
1765		.vlans = 4096,
1766		.enabled_ports = 0x1f,
1767		.arl_entries = 4,
 
1768		.vta_regs = B53_VTA_REGS,
1769		.cpu_port = B53_CPU_PORT,
1770		.duplex_reg = B53_DUPLEX_STAT_GE,
1771		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1772		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1773	},
1774	{
1775		.chip_id = BCM53125_DEVICE_ID,
1776		.dev_name = "BCM53125",
1777		.vlans = 4096,
1778		.enabled_ports = 0xff,
1779		.arl_entries = 4,
 
1780		.cpu_port = B53_CPU_PORT,
1781		.vta_regs = B53_VTA_REGS,
1782		.duplex_reg = B53_DUPLEX_STAT_GE,
1783		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1784		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1785	},
1786	{
1787		.chip_id = BCM53128_DEVICE_ID,
1788		.dev_name = "BCM53128",
1789		.vlans = 4096,
1790		.enabled_ports = 0x1ff,
1791		.arl_entries = 4,
 
1792		.cpu_port = B53_CPU_PORT,
1793		.vta_regs = B53_VTA_REGS,
1794		.duplex_reg = B53_DUPLEX_STAT_GE,
1795		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1796		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1797	},
1798	{
1799		.chip_id = BCM63XX_DEVICE_ID,
1800		.dev_name = "BCM63xx",
1801		.vlans = 4096,
1802		.enabled_ports = 0, /* pdata must provide them */
1803		.arl_entries = 4,
 
1804		.cpu_port = B53_CPU_PORT,
1805		.vta_regs = B53_VTA_REGS_63XX,
1806		.duplex_reg = B53_DUPLEX_STAT_63XX,
1807		.jumbo_pm_reg = B53_JUMBO_PORT_MASK_63XX,
1808		.jumbo_size_reg = B53_JUMBO_MAX_SIZE_63XX,
1809	},
1810	{
1811		.chip_id = BCM53010_DEVICE_ID,
1812		.dev_name = "BCM53010",
1813		.vlans = 4096,
1814		.enabled_ports = 0x1f,
1815		.arl_entries = 4,
 
1816		.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1817		.vta_regs = B53_VTA_REGS,
1818		.duplex_reg = B53_DUPLEX_STAT_GE,
1819		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1820		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1821	},
1822	{
1823		.chip_id = BCM53011_DEVICE_ID,
1824		.dev_name = "BCM53011",
1825		.vlans = 4096,
1826		.enabled_ports = 0x1bf,
1827		.arl_entries = 4,
 
1828		.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1829		.vta_regs = B53_VTA_REGS,
1830		.duplex_reg = B53_DUPLEX_STAT_GE,
1831		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1832		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1833	},
1834	{
1835		.chip_id = BCM53012_DEVICE_ID,
1836		.dev_name = "BCM53012",
1837		.vlans = 4096,
1838		.enabled_ports = 0x1bf,
1839		.arl_entries = 4,
 
1840		.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1841		.vta_regs = B53_VTA_REGS,
1842		.duplex_reg = B53_DUPLEX_STAT_GE,
1843		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1844		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1845	},
1846	{
1847		.chip_id = BCM53018_DEVICE_ID,
1848		.dev_name = "BCM53018",
1849		.vlans = 4096,
1850		.enabled_ports = 0x1f,
1851		.arl_entries = 4,
 
1852		.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1853		.vta_regs = B53_VTA_REGS,
1854		.duplex_reg = B53_DUPLEX_STAT_GE,
1855		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1856		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1857	},
1858	{
1859		.chip_id = BCM53019_DEVICE_ID,
1860		.dev_name = "BCM53019",
1861		.vlans = 4096,
1862		.enabled_ports = 0x1f,
1863		.arl_entries = 4,
 
1864		.cpu_port = B53_CPU_PORT_25, /* TODO: auto detect */
1865		.vta_regs = B53_VTA_REGS,
1866		.duplex_reg = B53_DUPLEX_STAT_GE,
1867		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1868		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1869	},
1870	{
1871		.chip_id = BCM58XX_DEVICE_ID,
1872		.dev_name = "BCM585xx/586xx/88312",
1873		.vlans	= 4096,
1874		.enabled_ports = 0x1ff,
1875		.arl_entries = 4,
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1876		.cpu_port = B53_CPU_PORT,
1877		.vta_regs = B53_VTA_REGS,
1878		.duplex_reg = B53_DUPLEX_STAT_GE,
1879		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1880		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1881	},
1882	{
1883		.chip_id = BCM7445_DEVICE_ID,
1884		.dev_name = "BCM7445",
1885		.vlans	= 4096,
1886		.enabled_ports = 0x1ff,
1887		.arl_entries = 4,
 
1888		.cpu_port = B53_CPU_PORT,
1889		.vta_regs = B53_VTA_REGS,
1890		.duplex_reg = B53_DUPLEX_STAT_GE,
1891		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1892		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1893	},
1894	{
1895		.chip_id = BCM7278_DEVICE_ID,
1896		.dev_name = "BCM7278",
1897		.vlans = 4096,
1898		.enabled_ports = 0x1ff,
1899		.arl_entries= 4,
 
1900		.cpu_port = B53_CPU_PORT,
1901		.vta_regs = B53_VTA_REGS,
1902		.duplex_reg = B53_DUPLEX_STAT_GE,
1903		.jumbo_pm_reg = B53_JUMBO_PORT_MASK,
1904		.jumbo_size_reg = B53_JUMBO_MAX_SIZE,
1905	},
1906};
1907
1908static int b53_switch_init(struct b53_device *dev)
1909{
1910	unsigned int i;
1911	int ret;
1912
1913	for (i = 0; i < ARRAY_SIZE(b53_switch_chips); i++) {
1914		const struct b53_chip_data *chip = &b53_switch_chips[i];
1915
1916		if (chip->chip_id == dev->chip_id) {
1917			if (!dev->enabled_ports)
1918				dev->enabled_ports = chip->enabled_ports;
1919			dev->name = chip->dev_name;
1920			dev->duplex_reg = chip->duplex_reg;
1921			dev->vta_regs[0] = chip->vta_regs[0];
1922			dev->vta_regs[1] = chip->vta_regs[1];
1923			dev->vta_regs[2] = chip->vta_regs[2];
1924			dev->jumbo_pm_reg = chip->jumbo_pm_reg;
1925			dev->cpu_port = chip->cpu_port;
1926			dev->num_vlans = chip->vlans;
1927			dev->num_arl_entries = chip->arl_entries;
 
1928			break;
1929		}
1930	}
1931
1932	/* check which BCM5325x version we have */
1933	if (is5325(dev)) {
1934		u8 vc4;
1935
1936		b53_read8(dev, B53_VLAN_PAGE, B53_VLAN_CTRL4_25, &vc4);
1937
1938		/* check reserved bits */
1939		switch (vc4 & 3) {
1940		case 1:
1941			/* BCM5325E */
1942			break;
1943		case 3:
1944			/* BCM5325F - do not use port 4 */
1945			dev->enabled_ports &= ~BIT(4);
1946			break;
1947		default:
1948/* On the BCM47XX SoCs this is the supported internal switch.*/
1949#ifndef CONFIG_BCM47XX
1950			/* BCM5325M */
1951			return -EINVAL;
1952#else
1953			break;
1954#endif
1955		}
1956	} else if (dev->chip_id == BCM53115_DEVICE_ID) {
1957		u64 strap_value;
1958
1959		b53_read48(dev, B53_STAT_PAGE, B53_STRAP_VALUE, &strap_value);
1960		/* use second IMP port if GMII is enabled */
1961		if (strap_value & SV_GMII_CTRL_115)
1962			dev->cpu_port = 5;
1963	}
1964
1965	/* cpu port is always last */
1966	dev->num_ports = dev->cpu_port + 1;
1967	dev->enabled_ports |= BIT(dev->cpu_port);
1968
1969	dev->ports = devm_kzalloc(dev->dev,
1970				  sizeof(struct b53_port) * dev->num_ports,
 
 
 
 
 
 
 
 
 
1971				  GFP_KERNEL);
1972	if (!dev->ports)
1973		return -ENOMEM;
1974
1975	dev->vlans = devm_kzalloc(dev->dev,
1976				  sizeof(struct b53_vlan) * dev->num_vlans,
1977				  GFP_KERNEL);
1978	if (!dev->vlans)
1979		return -ENOMEM;
1980
1981	dev->reset_gpio = b53_switch_get_reset_gpio(dev);
1982	if (dev->reset_gpio >= 0) {
1983		ret = devm_gpio_request_one(dev->dev, dev->reset_gpio,
1984					    GPIOF_OUT_INIT_HIGH, "robo_reset");
1985		if (ret)
1986			return ret;
1987	}
1988
1989	return 0;
1990}
1991
1992struct b53_device *b53_switch_alloc(struct device *base,
1993				    const struct b53_io_ops *ops,
1994				    void *priv)
1995{
1996	struct dsa_switch *ds;
1997	struct b53_device *dev;
1998
1999	ds = dsa_switch_alloc(base, DSA_MAX_PORTS);
2000	if (!ds)
2001		return NULL;
 
 
 
2002
2003	dev = devm_kzalloc(base, sizeof(*dev), GFP_KERNEL);
2004	if (!dev)
2005		return NULL;
2006
2007	ds->priv = dev;
2008	dev->dev = base;
2009
2010	dev->ds = ds;
2011	dev->priv = priv;
2012	dev->ops = ops;
2013	ds->ops = &b53_switch_ops;
2014	mutex_init(&dev->reg_mutex);
2015	mutex_init(&dev->stats_mutex);
2016
2017	return dev;
2018}
2019EXPORT_SYMBOL(b53_switch_alloc);
2020
2021int b53_switch_detect(struct b53_device *dev)
2022{
2023	u32 id32;
2024	u16 tmp;
2025	u8 id8;
2026	int ret;
2027
2028	ret = b53_read8(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id8);
2029	if (ret)
2030		return ret;
2031
2032	switch (id8) {
2033	case 0:
2034		/* BCM5325 and BCM5365 do not have this register so reads
2035		 * return 0. But the read operation did succeed, so assume this
2036		 * is one of them.
2037		 *
2038		 * Next check if we can write to the 5325's VTA register; for
2039		 * 5365 it is read only.
2040		 */
2041		b53_write16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, 0xf);
2042		b53_read16(dev, B53_VLAN_PAGE, B53_VLAN_TABLE_ACCESS_25, &tmp);
2043
2044		if (tmp == 0xf)
2045			dev->chip_id = BCM5325_DEVICE_ID;
2046		else
2047			dev->chip_id = BCM5365_DEVICE_ID;
2048		break;
2049	case BCM5389_DEVICE_ID:
2050	case BCM5395_DEVICE_ID:
2051	case BCM5397_DEVICE_ID:
2052	case BCM5398_DEVICE_ID:
2053		dev->chip_id = id8;
2054		break;
2055	default:
2056		ret = b53_read32(dev, B53_MGMT_PAGE, B53_DEVICE_ID, &id32);
2057		if (ret)
2058			return ret;
2059
2060		switch (id32) {
2061		case BCM53115_DEVICE_ID:
2062		case BCM53125_DEVICE_ID:
2063		case BCM53128_DEVICE_ID:
2064		case BCM53010_DEVICE_ID:
2065		case BCM53011_DEVICE_ID:
2066		case BCM53012_DEVICE_ID:
2067		case BCM53018_DEVICE_ID:
2068		case BCM53019_DEVICE_ID:
2069			dev->chip_id = id32;
2070			break;
2071		default:
2072			pr_err("unsupported switch detected (BCM53%02x/BCM%x)\n",
2073			       id8, id32);
2074			return -ENODEV;
2075		}
2076	}
2077
2078	if (dev->chip_id == BCM5325_DEVICE_ID)
2079		return b53_read8(dev, B53_STAT_PAGE, B53_REV_ID_25,
2080				 &dev->core_rev);
2081	else
2082		return b53_read8(dev, B53_MGMT_PAGE, B53_REV_ID,
2083				 &dev->core_rev);
2084}
2085EXPORT_SYMBOL(b53_switch_detect);
2086
2087int b53_switch_register(struct b53_device *dev)
2088{
2089	int ret;
2090
2091	if (dev->pdata) {
2092		dev->chip_id = dev->pdata->chip_id;
2093		dev->enabled_ports = dev->pdata->enabled_ports;
2094	}
2095
2096	if (!dev->chip_id && b53_switch_detect(dev))
2097		return -EINVAL;
2098
2099	ret = b53_switch_init(dev);
2100	if (ret)
2101		return ret;
2102
2103	pr_info("found switch: %s, rev %i\n", dev->name, dev->core_rev);
2104
2105	return dsa_register_switch(dev->ds);
2106}
2107EXPORT_SYMBOL(b53_switch_register);
2108
2109MODULE_AUTHOR("Jonas Gorski <jogo@openwrt.org>");
2110MODULE_DESCRIPTION("B53 switch library");
2111MODULE_LICENSE("Dual BSD/GPL");