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1/*
2 * Copyright (C) 1995 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
6 */
7
8/*
9 * This file handles the architecture-dependent parts of process handling..
10 */
11
12#include <linux/cpu.h>
13#include <linux/errno.h>
14#include <linux/sched.h>
15#include <linux/sched/task.h>
16#include <linux/sched/task_stack.h>
17#include <linux/fs.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/elfcore.h>
21#include <linux/smp.h>
22#include <linux/stddef.h>
23#include <linux/slab.h>
24#include <linux/vmalloc.h>
25#include <linux/user.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/reboot.h>
29#include <linux/mc146818rtc.h>
30#include <linux/export.h>
31#include <linux/kallsyms.h>
32#include <linux/ptrace.h>
33#include <linux/personality.h>
34#include <linux/percpu.h>
35#include <linux/prctl.h>
36#include <linux/ftrace.h>
37#include <linux/uaccess.h>
38#include <linux/io.h>
39#include <linux/kdebug.h>
40#include <linux/syscalls.h>
41
42#include <asm/pgtable.h>
43#include <asm/ldt.h>
44#include <asm/processor.h>
45#include <asm/fpu/internal.h>
46#include <asm/desc.h>
47#ifdef CONFIG_MATH_EMULATION
48#include <asm/math_emu.h>
49#endif
50
51#include <linux/err.h>
52
53#include <asm/tlbflush.h>
54#include <asm/cpu.h>
55#include <asm/syscalls.h>
56#include <asm/debugreg.h>
57#include <asm/switch_to.h>
58#include <asm/vm86.h>
59#include <asm/intel_rdt_sched.h>
60#include <asm/proto.h>
61
62void __show_regs(struct pt_regs *regs, int all)
63{
64 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
65 unsigned long d0, d1, d2, d3, d6, d7;
66 unsigned long sp;
67 unsigned short ss, gs;
68
69 if (user_mode(regs)) {
70 sp = regs->sp;
71 ss = regs->ss;
72 gs = get_user_gs(regs);
73 } else {
74 sp = kernel_stack_pointer(regs);
75 savesegment(ss, ss);
76 savesegment(gs, gs);
77 }
78
79 printk(KERN_DEFAULT "EIP: %pS\n", (void *)regs->ip);
80 printk(KERN_DEFAULT "EFLAGS: %08lx CPU: %d\n", regs->flags,
81 raw_smp_processor_id());
82
83 printk(KERN_DEFAULT "EAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
84 regs->ax, regs->bx, regs->cx, regs->dx);
85 printk(KERN_DEFAULT "ESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
86 regs->si, regs->di, regs->bp, sp);
87 printk(KERN_DEFAULT " DS: %04x ES: %04x FS: %04x GS: %04x SS: %04x\n",
88 (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, ss);
89
90 if (!all)
91 return;
92
93 cr0 = read_cr0();
94 cr2 = read_cr2();
95 cr3 = __read_cr3();
96 cr4 = __read_cr4();
97 printk(KERN_DEFAULT "CR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
98 cr0, cr2, cr3, cr4);
99
100 get_debugreg(d0, 0);
101 get_debugreg(d1, 1);
102 get_debugreg(d2, 2);
103 get_debugreg(d3, 3);
104 get_debugreg(d6, 6);
105 get_debugreg(d7, 7);
106
107 /* Only print out debug registers if they are in their non-default state. */
108 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
109 (d6 == DR6_RESERVED) && (d7 == 0x400))
110 return;
111
112 printk(KERN_DEFAULT "DR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
113 d0, d1, d2, d3);
114 printk(KERN_DEFAULT "DR6: %08lx DR7: %08lx\n",
115 d6, d7);
116}
117
118void release_thread(struct task_struct *dead_task)
119{
120 BUG_ON(dead_task->mm);
121 release_vm86_irqs(dead_task);
122}
123
124int copy_thread_tls(unsigned long clone_flags, unsigned long sp,
125 unsigned long arg, struct task_struct *p, unsigned long tls)
126{
127 struct pt_regs *childregs = task_pt_regs(p);
128 struct fork_frame *fork_frame = container_of(childregs, struct fork_frame, regs);
129 struct inactive_task_frame *frame = &fork_frame->frame;
130 struct task_struct *tsk;
131 int err;
132
133 frame->bp = 0;
134 frame->ret_addr = (unsigned long) ret_from_fork;
135 p->thread.sp = (unsigned long) fork_frame;
136 p->thread.sp0 = (unsigned long) (childregs+1);
137 memset(p->thread.ptrace_bps, 0, sizeof(p->thread.ptrace_bps));
138
139 if (unlikely(p->flags & PF_KTHREAD)) {
140 /* kernel thread */
141 memset(childregs, 0, sizeof(struct pt_regs));
142 frame->bx = sp; /* function */
143 frame->di = arg;
144 p->thread.io_bitmap_ptr = NULL;
145 return 0;
146 }
147 frame->bx = 0;
148 *childregs = *current_pt_regs();
149 childregs->ax = 0;
150 if (sp)
151 childregs->sp = sp;
152
153 task_user_gs(p) = get_user_gs(current_pt_regs());
154
155 p->thread.io_bitmap_ptr = NULL;
156 tsk = current;
157 err = -ENOMEM;
158
159 if (unlikely(test_tsk_thread_flag(tsk, TIF_IO_BITMAP))) {
160 p->thread.io_bitmap_ptr = kmemdup(tsk->thread.io_bitmap_ptr,
161 IO_BITMAP_BYTES, GFP_KERNEL);
162 if (!p->thread.io_bitmap_ptr) {
163 p->thread.io_bitmap_max = 0;
164 return -ENOMEM;
165 }
166 set_tsk_thread_flag(p, TIF_IO_BITMAP);
167 }
168
169 err = 0;
170
171 /*
172 * Set a new TLS for the child thread?
173 */
174 if (clone_flags & CLONE_SETTLS)
175 err = do_set_thread_area(p, -1,
176 (struct user_desc __user *)tls, 0);
177
178 if (err && p->thread.io_bitmap_ptr) {
179 kfree(p->thread.io_bitmap_ptr);
180 p->thread.io_bitmap_max = 0;
181 }
182 return err;
183}
184
185void
186start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
187{
188 set_user_gs(regs, 0);
189 regs->fs = 0;
190 regs->ds = __USER_DS;
191 regs->es = __USER_DS;
192 regs->ss = __USER_DS;
193 regs->cs = __USER_CS;
194 regs->ip = new_ip;
195 regs->sp = new_sp;
196 regs->flags = X86_EFLAGS_IF;
197 force_iret();
198}
199EXPORT_SYMBOL_GPL(start_thread);
200
201
202/*
203 * switch_to(x,y) should switch tasks from x to y.
204 *
205 * We fsave/fwait so that an exception goes off at the right time
206 * (as a call from the fsave or fwait in effect) rather than to
207 * the wrong process. Lazy FP saving no longer makes any sense
208 * with modern CPU's, and this simplifies a lot of things (SMP
209 * and UP become the same).
210 *
211 * NOTE! We used to use the x86 hardware context switching. The
212 * reason for not using it any more becomes apparent when you
213 * try to recover gracefully from saved state that is no longer
214 * valid (stale segment register values in particular). With the
215 * hardware task-switch, there is no way to fix up bad state in
216 * a reasonable manner.
217 *
218 * The fact that Intel documents the hardware task-switching to
219 * be slow is a fairly red herring - this code is not noticeably
220 * faster. However, there _is_ some room for improvement here,
221 * so the performance issues may eventually be a valid point.
222 * More important, however, is the fact that this allows us much
223 * more flexibility.
224 *
225 * The return value (in %ax) will be the "prev" task after
226 * the task-switch, and shows up in ret_from_fork in entry.S,
227 * for example.
228 */
229__visible __notrace_funcgraph struct task_struct *
230__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
231{
232 struct thread_struct *prev = &prev_p->thread,
233 *next = &next_p->thread;
234 struct fpu *prev_fpu = &prev->fpu;
235 struct fpu *next_fpu = &next->fpu;
236 int cpu = smp_processor_id();
237 struct tss_struct *tss = &per_cpu(cpu_tss_rw, cpu);
238
239 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
240
241 switch_fpu_prepare(prev_fpu, cpu);
242
243 /*
244 * Save away %gs. No need to save %fs, as it was saved on the
245 * stack on entry. No need to save %es and %ds, as those are
246 * always kernel segments while inside the kernel. Doing this
247 * before setting the new TLS descriptors avoids the situation
248 * where we temporarily have non-reloadable segments in %fs
249 * and %gs. This could be an issue if the NMI handler ever
250 * used %fs or %gs (it does not today), or if the kernel is
251 * running inside of a hypervisor layer.
252 */
253 lazy_save_gs(prev->gs);
254
255 /*
256 * Load the per-thread Thread-Local Storage descriptor.
257 */
258 load_TLS(next, cpu);
259
260 /*
261 * Restore IOPL if needed. In normal use, the flags restore
262 * in the switch assembly will handle this. But if the kernel
263 * is running virtualized at a non-zero CPL, the popf will
264 * not restore flags, so it must be done in a separate step.
265 */
266 if (get_kernel_rpl() && unlikely(prev->iopl != next->iopl))
267 set_iopl_mask(next->iopl);
268
269 /*
270 * Now maybe handle debug registers and/or IO bitmaps
271 */
272 if (unlikely(task_thread_info(prev_p)->flags & _TIF_WORK_CTXSW_PREV ||
273 task_thread_info(next_p)->flags & _TIF_WORK_CTXSW_NEXT))
274 __switch_to_xtra(prev_p, next_p, tss);
275
276 /*
277 * Leave lazy mode, flushing any hypercalls made here.
278 * This must be done before restoring TLS segments so
279 * the GDT and LDT are properly updated, and must be
280 * done before fpu__restore(), so the TS bit is up
281 * to date.
282 */
283 arch_end_context_switch(next_p);
284
285 /*
286 * Reload esp0 and cpu_current_top_of_stack. This changes
287 * current_thread_info(). Refresh the SYSENTER configuration in
288 * case prev or next is vm86.
289 */
290 update_sp0(next_p);
291 refresh_sysenter_cs(next);
292 this_cpu_write(cpu_current_top_of_stack,
293 (unsigned long)task_stack_page(next_p) +
294 THREAD_SIZE);
295
296 /*
297 * Restore %gs if needed (which is common)
298 */
299 if (prev->gs | next->gs)
300 lazy_load_gs(next->gs);
301
302 switch_fpu_finish(next_fpu, cpu);
303
304 this_cpu_write(current_task, next_p);
305
306 /* Load the Intel cache allocation PQR MSR. */
307 intel_rdt_sched_in();
308
309 return prev_p;
310}
311
312SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
313{
314 return do_arch_prctl_common(current, option, arg2);
315}
1/*
2 * Copyright (C) 1995 Linus Torvalds
3 *
4 * Pentium III FXSR, SSE support
5 * Gareth Hughes <gareth@valinux.com>, May 2000
6 */
7
8/*
9 * This file handles the architecture-dependent parts of process handling..
10 */
11
12#include <linux/cpu.h>
13#include <linux/errno.h>
14#include <linux/sched.h>
15#include <linux/sched/task.h>
16#include <linux/sched/task_stack.h>
17#include <linux/fs.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/elfcore.h>
21#include <linux/smp.h>
22#include <linux/stddef.h>
23#include <linux/slab.h>
24#include <linux/vmalloc.h>
25#include <linux/user.h>
26#include <linux/interrupt.h>
27#include <linux/delay.h>
28#include <linux/reboot.h>
29#include <linux/mc146818rtc.h>
30#include <linux/export.h>
31#include <linux/kallsyms.h>
32#include <linux/ptrace.h>
33#include <linux/personality.h>
34#include <linux/percpu.h>
35#include <linux/prctl.h>
36#include <linux/ftrace.h>
37#include <linux/uaccess.h>
38#include <linux/io.h>
39#include <linux/kdebug.h>
40#include <linux/syscalls.h>
41
42#include <asm/ldt.h>
43#include <asm/processor.h>
44#include <asm/fpu/internal.h>
45#include <asm/desc.h>
46
47#include <linux/err.h>
48
49#include <asm/tlbflush.h>
50#include <asm/cpu.h>
51#include <asm/debugreg.h>
52#include <asm/switch_to.h>
53#include <asm/vm86.h>
54#include <asm/resctrl.h>
55#include <asm/proto.h>
56
57#include "process.h"
58
59void __show_regs(struct pt_regs *regs, enum show_regs_mode mode,
60 const char *log_lvl)
61{
62 unsigned long cr0 = 0L, cr2 = 0L, cr3 = 0L, cr4 = 0L;
63 unsigned long d0, d1, d2, d3, d6, d7;
64 unsigned short gs;
65
66 if (user_mode(regs))
67 gs = get_user_gs(regs);
68 else
69 savesegment(gs, gs);
70
71 show_ip(regs, log_lvl);
72
73 printk("%sEAX: %08lx EBX: %08lx ECX: %08lx EDX: %08lx\n",
74 log_lvl, regs->ax, regs->bx, regs->cx, regs->dx);
75 printk("%sESI: %08lx EDI: %08lx EBP: %08lx ESP: %08lx\n",
76 log_lvl, regs->si, regs->di, regs->bp, regs->sp);
77 printk("%sDS: %04x ES: %04x FS: %04x GS: %04x SS: %04x EFLAGS: %08lx\n",
78 log_lvl, (u16)regs->ds, (u16)regs->es, (u16)regs->fs, gs, regs->ss, regs->flags);
79
80 if (mode != SHOW_REGS_ALL)
81 return;
82
83 cr0 = read_cr0();
84 cr2 = read_cr2();
85 cr3 = __read_cr3();
86 cr4 = __read_cr4();
87 printk("%sCR0: %08lx CR2: %08lx CR3: %08lx CR4: %08lx\n",
88 log_lvl, cr0, cr2, cr3, cr4);
89
90 get_debugreg(d0, 0);
91 get_debugreg(d1, 1);
92 get_debugreg(d2, 2);
93 get_debugreg(d3, 3);
94 get_debugreg(d6, 6);
95 get_debugreg(d7, 7);
96
97 /* Only print out debug registers if they are in their non-default state. */
98 if ((d0 == 0) && (d1 == 0) && (d2 == 0) && (d3 == 0) &&
99 (d6 == DR6_RESERVED) && (d7 == 0x400))
100 return;
101
102 printk("%sDR0: %08lx DR1: %08lx DR2: %08lx DR3: %08lx\n",
103 log_lvl, d0, d1, d2, d3);
104 printk("%sDR6: %08lx DR7: %08lx\n",
105 log_lvl, d6, d7);
106}
107
108void release_thread(struct task_struct *dead_task)
109{
110 BUG_ON(dead_task->mm);
111 release_vm86_irqs(dead_task);
112}
113
114void
115start_thread(struct pt_regs *regs, unsigned long new_ip, unsigned long new_sp)
116{
117 set_user_gs(regs, 0);
118 regs->fs = 0;
119 regs->ds = __USER_DS;
120 regs->es = __USER_DS;
121 regs->ss = __USER_DS;
122 regs->cs = __USER_CS;
123 regs->ip = new_ip;
124 regs->sp = new_sp;
125 regs->flags = X86_EFLAGS_IF;
126}
127EXPORT_SYMBOL_GPL(start_thread);
128
129
130/*
131 * switch_to(x,y) should switch tasks from x to y.
132 *
133 * We fsave/fwait so that an exception goes off at the right time
134 * (as a call from the fsave or fwait in effect) rather than to
135 * the wrong process. Lazy FP saving no longer makes any sense
136 * with modern CPU's, and this simplifies a lot of things (SMP
137 * and UP become the same).
138 *
139 * NOTE! We used to use the x86 hardware context switching. The
140 * reason for not using it any more becomes apparent when you
141 * try to recover gracefully from saved state that is no longer
142 * valid (stale segment register values in particular). With the
143 * hardware task-switch, there is no way to fix up bad state in
144 * a reasonable manner.
145 *
146 * The fact that Intel documents the hardware task-switching to
147 * be slow is a fairly red herring - this code is not noticeably
148 * faster. However, there _is_ some room for improvement here,
149 * so the performance issues may eventually be a valid point.
150 * More important, however, is the fact that this allows us much
151 * more flexibility.
152 *
153 * The return value (in %ax) will be the "prev" task after
154 * the task-switch, and shows up in ret_from_fork in entry.S,
155 * for example.
156 */
157__visible __notrace_funcgraph struct task_struct *
158__switch_to(struct task_struct *prev_p, struct task_struct *next_p)
159{
160 struct thread_struct *prev = &prev_p->thread,
161 *next = &next_p->thread;
162 struct fpu *prev_fpu = &prev->fpu;
163 struct fpu *next_fpu = &next->fpu;
164 int cpu = smp_processor_id();
165
166 /* never put a printk in __switch_to... printk() calls wake_up*() indirectly */
167
168 if (!test_thread_flag(TIF_NEED_FPU_LOAD))
169 switch_fpu_prepare(prev_fpu, cpu);
170
171 /*
172 * Save away %gs. No need to save %fs, as it was saved on the
173 * stack on entry. No need to save %es and %ds, as those are
174 * always kernel segments while inside the kernel. Doing this
175 * before setting the new TLS descriptors avoids the situation
176 * where we temporarily have non-reloadable segments in %fs
177 * and %gs. This could be an issue if the NMI handler ever
178 * used %fs or %gs (it does not today), or if the kernel is
179 * running inside of a hypervisor layer.
180 */
181 lazy_save_gs(prev->gs);
182
183 /*
184 * Load the per-thread Thread-Local Storage descriptor.
185 */
186 load_TLS(next, cpu);
187
188 switch_to_extra(prev_p, next_p);
189
190 /*
191 * Leave lazy mode, flushing any hypercalls made here.
192 * This must be done before restoring TLS segments so
193 * the GDT and LDT are properly updated.
194 */
195 arch_end_context_switch(next_p);
196
197 /*
198 * Reload esp0 and cpu_current_top_of_stack. This changes
199 * current_thread_info(). Refresh the SYSENTER configuration in
200 * case prev or next is vm86.
201 */
202 update_task_stack(next_p);
203 refresh_sysenter_cs(next);
204 this_cpu_write(cpu_current_top_of_stack,
205 (unsigned long)task_stack_page(next_p) +
206 THREAD_SIZE);
207
208 /*
209 * Restore %gs if needed (which is common)
210 */
211 if (prev->gs | next->gs)
212 lazy_load_gs(next->gs);
213
214 this_cpu_write(current_task, next_p);
215
216 switch_fpu_finish(next_fpu);
217
218 /* Load the Intel cache allocation PQR MSR. */
219 resctrl_sched_in();
220
221 return prev_p;
222}
223
224SYSCALL_DEFINE2(arch_prctl, int, option, unsigned long, arg2)
225{
226 return do_arch_prctl_common(current, option, arg2);
227}