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1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2
3/*
4 * Device tree file for ZII's SSMB SPU3 board
5 *
6 * SSMB - SPU3 Switch Management Board
7 * SPU - Seat Power Unit
8 *
9 * Copyright (C) 2015, 2016 Zodiac Inflight Innovations
10 *
11 * Based on an original 'vf610-twr.dts' which is Copyright 2015,
12 * Freescale Semiconductor, Inc.
13 */
14
15/dts-v1/;
16#include "vf610.dtsi"
17
18/ {
19 model = "ZII VF610 SSMB SPU3 Board";
20 compatible = "zii,vf610spu3", "zii,vf610dev", "fsl,vf610";
21
22 chosen {
23 stdout-path = &uart0;
24 };
25
26 memory@80000000 {
27 device_type = "memory";
28 reg = <0x80000000 0x20000000>;
29 };
30
31 gpio-leds {
32 compatible = "gpio-leds";
33 pinctrl-0 = <&pinctrl_leds_debug>;
34 pinctrl-names = "default";
35
36 led-debug {
37 label = "zii:green:debug1";
38 gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
39 linux,default-trigger = "heartbeat";
40 };
41 };
42
43 reg_vcc_3v3_mcu: regulator {
44 compatible = "regulator-fixed";
45 regulator-name = "vcc_3v3_mcu";
46 regulator-min-microvolt = <3300000>;
47 regulator-max-microvolt = <3300000>;
48 };
49
50 supply-voltage-monitor {
51 compatible = "iio-hwmon";
52 io-channels = <&adc0 8>, /* 12V_MAIN */
53 <&adc0 9>, /* +3.3V */
54 <&adc1 8>, /* VCC_1V5 */
55 <&adc1 9>; /* VCC_1V2 */
56 };
57};
58
59&adc0 {
60 vref-supply = <®_vcc_3v3_mcu>;
61 status = "okay";
62};
63
64&adc1 {
65 vref-supply = <®_vcc_3v3_mcu>;
66 status = "okay";
67};
68
69&dspi1 {
70 bus-num = <1>;
71 pinctrl-names = "default";
72 pinctrl-0 = <&pinctrl_dspi1>;
73 /*
74 * Some SPU3s come with SPI-NOR chip DNPed, so we leave this
75 * node disabled by default and rely on bootloader to enable
76 * it when appropriate.
77 */
78 status = "disabled";
79
80 flash@0 {
81 #address-cells = <1>;
82 #size-cells = <1>;
83 compatible = "m25p128", "jedec,spi-nor";
84 reg = <0>;
85 spi-max-frequency = <50000000>;
86
87 partition@0 {
88 label = "m25p128-0";
89 reg = <0x0 0x01000000>;
90 };
91 };
92};
93
94&edma0 {
95 status = "okay";
96};
97
98&edma1 {
99 status = "okay";
100};
101
102&esdhc0 {
103 pinctrl-names = "default";
104 pinctrl-0 = <&pinctrl_esdhc0>;
105 bus-width = <8>;
106 non-removable;
107 no-1-8-v;
108 keep-power-in-suspend;
109 no-sdio;
110 no-sd;
111 status = "okay";
112};
113
114&esdhc1 {
115 pinctrl-names = "default";
116 pinctrl-0 = <&pinctrl_esdhc1>;
117 bus-width = <4>;
118 no-sdio;
119 status = "okay";
120};
121
122&fec1 {
123 phy-mode = "rmii";
124 pinctrl-names = "default";
125 pinctrl-0 = <&pinctrl_fec1>;
126 status = "okay";
127
128 fixed-link {
129 speed = <100>;
130 full-duplex;
131 };
132
133 mdio1: mdio {
134 #address-cells = <1>;
135 #size-cells = <0>;
136 clock-frequency = <12500000>;
137 suppress-preamble;
138 status = "okay";
139
140 switch0: switch0@0 {
141 compatible = "marvell,mv88e6190";
142 pinctrl-0 = <&pinctrl_gpio_switch0>;
143 pinctrl-names = "default";
144 reg = <0>;
145 eeprom-length = <65536>;
146 reset-gpios = <&gpio3 11 GPIO_ACTIVE_LOW>;
147 interrupt-parent = <&gpio3>;
148 interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151
152 ports {
153 #address-cells = <1>;
154 #size-cells = <0>;
155
156 port@0 {
157 reg = <0>;
158 label = "cpu";
159 ethernet = <&fec1>;
160
161 fixed-link {
162 speed = <100>;
163 full-duplex;
164 };
165 };
166
167 port@1 {
168 reg = <1>;
169 label = "eth_cu_1000_1";
170 };
171
172 port@2 {
173 reg = <2>;
174 label = "eth_cu_1000_2";
175 };
176
177 port@3 {
178 reg = <3>;
179 label = "eth_cu_1000_3";
180 };
181
182 port@4 {
183 reg = <4>;
184 label = "eth_cu_1000_4";
185 };
186
187 port@5 {
188 reg = <5>;
189 label = "eth_cu_1000_5";
190 };
191
192 port@6 {
193 reg = <6>;
194 label = "eth_cu_1000_6";
195 };
196 };
197 };
198 };
199};
200
201&i2c0 {
202 clock-frequency = <100000>;
203 pinctrl-names = "default";
204 pinctrl-0 = <&pinctrl_i2c0>;
205 status = "okay";
206
207 gpio6: io-expander@22 {
208 compatible = "nxp,pca9554";
209 reg = <0x22>;
210 gpio-controller;
211 #gpio-cells = <2>;
212 };
213
214 lm75@48 {
215 compatible = "national,lm75";
216 reg = <0x48>;
217 };
218
219 eeprom@50 {
220 compatible = "atmel,24c04";
221 reg = <0x50>;
222 label = "nameplate";
223 };
224
225 eeprom@52 {
226 compatible = "atmel,24c04";
227 reg = <0x52>;
228 };
229};
230
231&i2c1 {
232 clock-frequency = <100000>;
233 pinctrl-names = "default";
234 pinctrl-0 = <&pinctrl_i2c1>;
235 status = "okay";
236
237 watchdog@38 {
238 compatible = "zii,rave-wdt";
239 reg = <0x38>;
240 };
241};
242
243&snvsrtc {
244 status = "disabled";
245};
246
247&uart0 {
248 pinctrl-names = "default";
249 pinctrl-0 = <&pinctrl_uart0>;
250 status = "okay";
251};
252
253&uart1 {
254 pinctrl-names = "default";
255 pinctrl-0 = <&pinctrl_uart1>;
256 status = "okay";
257
258 rave-sp {
259 compatible = "zii,rave-sp-rdu2";
260 current-speed = <1000000>;
261 #address-cells = <1>;
262 #size-cells = <1>;
263
264 watchdog {
265 compatible = "zii,rave-sp-watchdog";
266 };
267
268 eeprom@a3 {
269 compatible = "zii,rave-sp-eeprom";
270 reg = <0xa3 0x4000>;
271 #address-cells = <1>;
272 #size-cells = <1>;
273 zii,eeprom-name = "main-eeprom";
274 };
275 };
276};
277
278&wdoga5 {
279 status = "disabled";
280};
281
282&iomuxc {
283 pinctrl_dspi1: dspi1grp {
284 fsl,pins = <
285 VF610_PAD_PTD5__DSPI1_CS0 0x1182
286 VF610_PAD_PTD4__DSPI1_CS1 0x1182
287 VF610_PAD_PTC6__DSPI1_SIN 0x1181
288 VF610_PAD_PTC7__DSPI1_SOUT 0x1182
289 VF610_PAD_PTC8__DSPI1_SCK 0x1182
290 >;
291 };
292
293 pinctrl_esdhc0: esdhc0grp {
294 fsl,pins = <
295 VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
296 VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
297 VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
298 VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
299 VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
300 VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
301 VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
302 VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
303 VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
304 VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
305 >;
306 };
307
308 pinctrl_esdhc1: esdhc1grp {
309 fsl,pins = <
310 VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
311 VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
312 VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
313 VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
314 VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
315 VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
316 >;
317 };
318
319 pinctrl_fec1: fec1grp {
320 fsl,pins = <
321 VF610_PAD_PTA6__RMII_CLKIN 0x30d1
322 VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
323 VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
324 VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
325 VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
326 VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
327 VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
328 VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
329 VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
330 VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
331 >;
332 };
333
334 pinctrl_gpio_switch0: pinctrl-gpio-switch0 {
335 fsl,pins = <
336 VF610_PAD_PTE2__GPIO_107 0x31c2
337 VF610_PAD_PTB28__GPIO_98 0x219d
338 >;
339 };
340
341 pinctrl_i2c0: i2c0grp {
342 fsl,pins = <
343 VF610_PAD_PTB14__I2C0_SCL 0x37ff
344 VF610_PAD_PTB15__I2C0_SDA 0x37ff
345 >;
346 };
347
348 pinctrl_i2c1: i2c1grp {
349 fsl,pins = <
350 VF610_PAD_PTB16__I2C1_SCL 0x37ff
351 VF610_PAD_PTB17__I2C1_SDA 0x37ff
352 >;
353 };
354
355 pinctrl_leds_debug: pinctrl-leds-debug {
356 fsl,pins = <
357 VF610_PAD_PTD3__GPIO_82 0x31c2
358 >;
359 };
360
361 pinctrl_uart0: uart0grp {
362 fsl,pins = <
363 VF610_PAD_PTB10__UART0_TX 0x21a2
364 VF610_PAD_PTB11__UART0_RX 0x21a1
365 >;
366 };
367
368 pinctrl_uart1: uart1grp {
369 fsl,pins = <
370 VF610_PAD_PTB23__UART1_TX 0x21a2
371 VF610_PAD_PTB24__UART1_RX 0x21a1
372 >;
373 };
374};