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1// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
3 * Copyright (C) STMicroelectronics 2017 - All Rights Reserved
4 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
6#include <dt-bindings/interrupt-controller/arm-gic.h>
7#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu0: cpu@0 {
19 compatible = "arm,cortex-a7";
20 clock-frequency = <650000000>;
21 device_type = "cpu";
22 reg = <0>;
23 };
24 };
25
26 psci {
27 compatible = "arm,psci-1.0";
28 method = "smc";
29 };
30
31 intc: interrupt-controller@a0021000 {
32 compatible = "arm,cortex-a7-gic";
33 #interrupt-cells = <3>;
34 interrupt-controller;
35 reg = <0xa0021000 0x1000>,
36 <0xa0022000 0x2000>;
37 };
38
39 timer {
40 compatible = "arm,armv7-timer";
41 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
42 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
43 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
44 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
45 interrupt-parent = <&intc>;
46 };
47
48 clocks {
49 clk_hse: clk-hse {
50 #clock-cells = <0>;
51 compatible = "fixed-clock";
52 clock-frequency = <24000000>;
53 };
54
55 clk_hsi: clk-hsi {
56 #clock-cells = <0>;
57 compatible = "fixed-clock";
58 clock-frequency = <64000000>;
59 };
60
61 clk_lse: clk-lse {
62 #clock-cells = <0>;
63 compatible = "fixed-clock";
64 clock-frequency = <32768>;
65 };
66
67 clk_lsi: clk-lsi {
68 #clock-cells = <0>;
69 compatible = "fixed-clock";
70 clock-frequency = <32000>;
71 };
72
73 clk_csi: clk-csi {
74 #clock-cells = <0>;
75 compatible = "fixed-clock";
76 clock-frequency = <4000000>;
77 };
78 };
79
80 thermal-zones {
81 cpu_thermal: cpu-thermal {
82 polling-delay-passive = <0>;
83 polling-delay = <0>;
84 thermal-sensors = <&dts>;
85
86 trips {
87 cpu_alert1: cpu-alert1 {
88 temperature = <85000>;
89 hysteresis = <0>;
90 type = "passive";
91 };
92
93 cpu-crit {
94 temperature = <120000>;
95 hysteresis = <0>;
96 type = "critical";
97 };
98 };
99
100 cooling-maps {
101 };
102 };
103 };
104
105 booster: regulator-booster {
106 compatible = "st,stm32mp1-booster";
107 st,syscfg = <&syscfg>;
108 status = "disabled";
109 };
110
111 soc {
112 compatible = "simple-bus";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 interrupt-parent = <&intc>;
116 ranges;
117
118 timers2: timer@40000000 {
119 #address-cells = <1>;
120 #size-cells = <0>;
121 compatible = "st,stm32-timers";
122 reg = <0x40000000 0x400>;
123 clocks = <&rcc TIM2_K>;
124 clock-names = "int";
125 dmas = <&dmamux1 18 0x400 0x1>,
126 <&dmamux1 19 0x400 0x1>,
127 <&dmamux1 20 0x400 0x1>,
128 <&dmamux1 21 0x400 0x1>,
129 <&dmamux1 22 0x400 0x1>;
130 dma-names = "ch1", "ch2", "ch3", "ch4", "up";
131 status = "disabled";
132
133 pwm {
134 compatible = "st,stm32-pwm";
135 #pwm-cells = <3>;
136 status = "disabled";
137 };
138
139 timer@1 {
140 compatible = "st,stm32h7-timer-trigger";
141 reg = <1>;
142 status = "disabled";
143 };
144
145 counter {
146 compatible = "st,stm32-timer-counter";
147 status = "disabled";
148 };
149 };
150
151 timers3: timer@40001000 {
152 #address-cells = <1>;
153 #size-cells = <0>;
154 compatible = "st,stm32-timers";
155 reg = <0x40001000 0x400>;
156 clocks = <&rcc TIM3_K>;
157 clock-names = "int";
158 dmas = <&dmamux1 23 0x400 0x1>,
159 <&dmamux1 24 0x400 0x1>,
160 <&dmamux1 25 0x400 0x1>,
161 <&dmamux1 26 0x400 0x1>,
162 <&dmamux1 27 0x400 0x1>,
163 <&dmamux1 28 0x400 0x1>;
164 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
165 status = "disabled";
166
167 pwm {
168 compatible = "st,stm32-pwm";
169 #pwm-cells = <3>;
170 status = "disabled";
171 };
172
173 timer@2 {
174 compatible = "st,stm32h7-timer-trigger";
175 reg = <2>;
176 status = "disabled";
177 };
178
179 counter {
180 compatible = "st,stm32-timer-counter";
181 status = "disabled";
182 };
183 };
184
185 timers4: timer@40002000 {
186 #address-cells = <1>;
187 #size-cells = <0>;
188 compatible = "st,stm32-timers";
189 reg = <0x40002000 0x400>;
190 clocks = <&rcc TIM4_K>;
191 clock-names = "int";
192 dmas = <&dmamux1 29 0x400 0x1>,
193 <&dmamux1 30 0x400 0x1>,
194 <&dmamux1 31 0x400 0x1>,
195 <&dmamux1 32 0x400 0x1>;
196 dma-names = "ch1", "ch2", "ch3", "ch4";
197 status = "disabled";
198
199 pwm {
200 compatible = "st,stm32-pwm";
201 #pwm-cells = <3>;
202 status = "disabled";
203 };
204
205 timer@3 {
206 compatible = "st,stm32h7-timer-trigger";
207 reg = <3>;
208 status = "disabled";
209 };
210
211 counter {
212 compatible = "st,stm32-timer-counter";
213 status = "disabled";
214 };
215 };
216
217 timers5: timer@40003000 {
218 #address-cells = <1>;
219 #size-cells = <0>;
220 compatible = "st,stm32-timers";
221 reg = <0x40003000 0x400>;
222 clocks = <&rcc TIM5_K>;
223 clock-names = "int";
224 dmas = <&dmamux1 55 0x400 0x1>,
225 <&dmamux1 56 0x400 0x1>,
226 <&dmamux1 57 0x400 0x1>,
227 <&dmamux1 58 0x400 0x1>,
228 <&dmamux1 59 0x400 0x1>,
229 <&dmamux1 60 0x400 0x1>;
230 dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig";
231 status = "disabled";
232
233 pwm {
234 compatible = "st,stm32-pwm";
235 #pwm-cells = <3>;
236 status = "disabled";
237 };
238
239 timer@4 {
240 compatible = "st,stm32h7-timer-trigger";
241 reg = <4>;
242 status = "disabled";
243 };
244
245 counter {
246 compatible = "st,stm32-timer-counter";
247 status = "disabled";
248 };
249 };
250
251 timers6: timer@40004000 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "st,stm32-timers";
255 reg = <0x40004000 0x400>;
256 clocks = <&rcc TIM6_K>;
257 clock-names = "int";
258 dmas = <&dmamux1 69 0x400 0x1>;
259 dma-names = "up";
260 status = "disabled";
261
262 timer@5 {
263 compatible = "st,stm32h7-timer-trigger";
264 reg = <5>;
265 status = "disabled";
266 };
267 };
268
269 timers7: timer@40005000 {
270 #address-cells = <1>;
271 #size-cells = <0>;
272 compatible = "st,stm32-timers";
273 reg = <0x40005000 0x400>;
274 clocks = <&rcc TIM7_K>;
275 clock-names = "int";
276 dmas = <&dmamux1 70 0x400 0x1>;
277 dma-names = "up";
278 status = "disabled";
279
280 timer@6 {
281 compatible = "st,stm32h7-timer-trigger";
282 reg = <6>;
283 status = "disabled";
284 };
285 };
286
287 timers12: timer@40006000 {
288 #address-cells = <1>;
289 #size-cells = <0>;
290 compatible = "st,stm32-timers";
291 reg = <0x40006000 0x400>;
292 clocks = <&rcc TIM12_K>;
293 clock-names = "int";
294 status = "disabled";
295
296 pwm {
297 compatible = "st,stm32-pwm";
298 #pwm-cells = <3>;
299 status = "disabled";
300 };
301
302 timer@11 {
303 compatible = "st,stm32h7-timer-trigger";
304 reg = <11>;
305 status = "disabled";
306 };
307 };
308
309 timers13: timer@40007000 {
310 #address-cells = <1>;
311 #size-cells = <0>;
312 compatible = "st,stm32-timers";
313 reg = <0x40007000 0x400>;
314 clocks = <&rcc TIM13_K>;
315 clock-names = "int";
316 status = "disabled";
317
318 pwm {
319 compatible = "st,stm32-pwm";
320 #pwm-cells = <3>;
321 status = "disabled";
322 };
323
324 timer@12 {
325 compatible = "st,stm32h7-timer-trigger";
326 reg = <12>;
327 status = "disabled";
328 };
329 };
330
331 timers14: timer@40008000 {
332 #address-cells = <1>;
333 #size-cells = <0>;
334 compatible = "st,stm32-timers";
335 reg = <0x40008000 0x400>;
336 clocks = <&rcc TIM14_K>;
337 clock-names = "int";
338 status = "disabled";
339
340 pwm {
341 compatible = "st,stm32-pwm";
342 #pwm-cells = <3>;
343 status = "disabled";
344 };
345
346 timer@13 {
347 compatible = "st,stm32h7-timer-trigger";
348 reg = <13>;
349 status = "disabled";
350 };
351 };
352
353 lptimer1: timer@40009000 {
354 #address-cells = <1>;
355 #size-cells = <0>;
356 compatible = "st,stm32-lptimer";
357 reg = <0x40009000 0x400>;
358 clocks = <&rcc LPTIM1_K>;
359 clock-names = "mux";
360 status = "disabled";
361
362 pwm {
363 compatible = "st,stm32-pwm-lp";
364 #pwm-cells = <3>;
365 status = "disabled";
366 };
367
368 trigger@0 {
369 compatible = "st,stm32-lptimer-trigger";
370 reg = <0>;
371 status = "disabled";
372 };
373
374 counter {
375 compatible = "st,stm32-lptimer-counter";
376 status = "disabled";
377 };
378 };
379
380 spi2: spi@4000b000 {
381 #address-cells = <1>;
382 #size-cells = <0>;
383 compatible = "st,stm32h7-spi";
384 reg = <0x4000b000 0x400>;
385 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
386 clocks = <&rcc SPI2_K>;
387 resets = <&rcc SPI2_R>;
388 dmas = <&dmamux1 39 0x400 0x05>,
389 <&dmamux1 40 0x400 0x05>;
390 dma-names = "rx", "tx";
391 status = "disabled";
392 };
393
394 i2s2: audio-controller@4000b000 {
395 compatible = "st,stm32h7-i2s";
396 #sound-dai-cells = <0>;
397 reg = <0x4000b000 0x400>;
398 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
399 dmas = <&dmamux1 39 0x400 0x01>,
400 <&dmamux1 40 0x400 0x01>;
401 dma-names = "rx", "tx";
402 status = "disabled";
403 };
404
405 spi3: spi@4000c000 {
406 #address-cells = <1>;
407 #size-cells = <0>;
408 compatible = "st,stm32h7-spi";
409 reg = <0x4000c000 0x400>;
410 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
411 clocks = <&rcc SPI3_K>;
412 resets = <&rcc SPI3_R>;
413 dmas = <&dmamux1 61 0x400 0x05>,
414 <&dmamux1 62 0x400 0x05>;
415 dma-names = "rx", "tx";
416 status = "disabled";
417 };
418
419 i2s3: audio-controller@4000c000 {
420 compatible = "st,stm32h7-i2s";
421 #sound-dai-cells = <0>;
422 reg = <0x4000c000 0x400>;
423 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
424 dmas = <&dmamux1 61 0x400 0x01>,
425 <&dmamux1 62 0x400 0x01>;
426 dma-names = "rx", "tx";
427 status = "disabled";
428 };
429
430 spdifrx: audio-controller@4000d000 {
431 compatible = "st,stm32h7-spdifrx";
432 #sound-dai-cells = <0>;
433 reg = <0x4000d000 0x400>;
434 clocks = <&rcc SPDIF_K>;
435 clock-names = "kclk";
436 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
437 dmas = <&dmamux1 93 0x400 0x01>,
438 <&dmamux1 94 0x400 0x01>;
439 dma-names = "rx", "rx-ctrl";
440 status = "disabled";
441 };
442
443 usart2: serial@4000e000 {
444 compatible = "st,stm32h7-uart";
445 reg = <0x4000e000 0x400>;
446 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&rcc USART2_K>;
448 status = "disabled";
449 };
450
451 usart3: serial@4000f000 {
452 compatible = "st,stm32h7-uart";
453 reg = <0x4000f000 0x400>;
454 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
455 clocks = <&rcc USART3_K>;
456 status = "disabled";
457 };
458
459 uart4: serial@40010000 {
460 compatible = "st,stm32h7-uart";
461 reg = <0x40010000 0x400>;
462 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
463 clocks = <&rcc UART4_K>;
464 status = "disabled";
465 };
466
467 uart5: serial@40011000 {
468 compatible = "st,stm32h7-uart";
469 reg = <0x40011000 0x400>;
470 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
471 clocks = <&rcc UART5_K>;
472 status = "disabled";
473 };
474
475 i2c1: i2c@40012000 {
476 compatible = "st,stm32mp15-i2c";
477 reg = <0x40012000 0x400>;
478 interrupt-names = "event", "error";
479 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>,
480 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
481 clocks = <&rcc I2C1_K>;
482 resets = <&rcc I2C1_R>;
483 #address-cells = <1>;
484 #size-cells = <0>;
485 st,syscfg-fmp = <&syscfg 0x4 0x1>;
486 wakeup-source;
487 status = "disabled";
488 };
489
490 i2c2: i2c@40013000 {
491 compatible = "st,stm32mp15-i2c";
492 reg = <0x40013000 0x400>;
493 interrupt-names = "event", "error";
494 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
495 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
496 clocks = <&rcc I2C2_K>;
497 resets = <&rcc I2C2_R>;
498 #address-cells = <1>;
499 #size-cells = <0>;
500 st,syscfg-fmp = <&syscfg 0x4 0x2>;
501 wakeup-source;
502 status = "disabled";
503 };
504
505 i2c3: i2c@40014000 {
506 compatible = "st,stm32mp15-i2c";
507 reg = <0x40014000 0x400>;
508 interrupt-names = "event", "error";
509 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
510 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
511 clocks = <&rcc I2C3_K>;
512 resets = <&rcc I2C3_R>;
513 #address-cells = <1>;
514 #size-cells = <0>;
515 st,syscfg-fmp = <&syscfg 0x4 0x4>;
516 wakeup-source;
517 status = "disabled";
518 };
519
520 i2c5: i2c@40015000 {
521 compatible = "st,stm32mp15-i2c";
522 reg = <0x40015000 0x400>;
523 interrupt-names = "event", "error";
524 interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
525 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
526 clocks = <&rcc I2C5_K>;
527 resets = <&rcc I2C5_R>;
528 #address-cells = <1>;
529 #size-cells = <0>;
530 st,syscfg-fmp = <&syscfg 0x4 0x10>;
531 wakeup-source;
532 status = "disabled";
533 };
534
535 cec: cec@40016000 {
536 compatible = "st,stm32-cec";
537 reg = <0x40016000 0x400>;
538 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
539 clocks = <&rcc CEC_K>, <&clk_lse>;
540 clock-names = "cec", "hdmi-cec";
541 status = "disabled";
542 };
543
544 dac: dac@40017000 {
545 compatible = "st,stm32h7-dac-core";
546 reg = <0x40017000 0x400>;
547 clocks = <&rcc DAC12>;
548 clock-names = "pclk";
549 #address-cells = <1>;
550 #size-cells = <0>;
551 status = "disabled";
552
553 dac1: dac@1 {
554 compatible = "st,stm32-dac";
555 #io-channel-cells = <1>;
556 reg = <1>;
557 status = "disabled";
558 };
559
560 dac2: dac@2 {
561 compatible = "st,stm32-dac";
562 #io-channel-cells = <1>;
563 reg = <2>;
564 status = "disabled";
565 };
566 };
567
568 uart7: serial@40018000 {
569 compatible = "st,stm32h7-uart";
570 reg = <0x40018000 0x400>;
571 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
572 clocks = <&rcc UART7_K>;
573 status = "disabled";
574 };
575
576 uart8: serial@40019000 {
577 compatible = "st,stm32h7-uart";
578 reg = <0x40019000 0x400>;
579 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
580 clocks = <&rcc UART8_K>;
581 status = "disabled";
582 };
583
584 timers1: timer@44000000 {
585 #address-cells = <1>;
586 #size-cells = <0>;
587 compatible = "st,stm32-timers";
588 reg = <0x44000000 0x400>;
589 clocks = <&rcc TIM1_K>;
590 clock-names = "int";
591 dmas = <&dmamux1 11 0x400 0x1>,
592 <&dmamux1 12 0x400 0x1>,
593 <&dmamux1 13 0x400 0x1>,
594 <&dmamux1 14 0x400 0x1>,
595 <&dmamux1 15 0x400 0x1>,
596 <&dmamux1 16 0x400 0x1>,
597 <&dmamux1 17 0x400 0x1>;
598 dma-names = "ch1", "ch2", "ch3", "ch4",
599 "up", "trig", "com";
600 status = "disabled";
601
602 pwm {
603 compatible = "st,stm32-pwm";
604 #pwm-cells = <3>;
605 status = "disabled";
606 };
607
608 timer@0 {
609 compatible = "st,stm32h7-timer-trigger";
610 reg = <0>;
611 status = "disabled";
612 };
613
614 counter {
615 compatible = "st,stm32-timer-counter";
616 status = "disabled";
617 };
618 };
619
620 timers8: timer@44001000 {
621 #address-cells = <1>;
622 #size-cells = <0>;
623 compatible = "st,stm32-timers";
624 reg = <0x44001000 0x400>;
625 clocks = <&rcc TIM8_K>;
626 clock-names = "int";
627 dmas = <&dmamux1 47 0x400 0x1>,
628 <&dmamux1 48 0x400 0x1>,
629 <&dmamux1 49 0x400 0x1>,
630 <&dmamux1 50 0x400 0x1>,
631 <&dmamux1 51 0x400 0x1>,
632 <&dmamux1 52 0x400 0x1>,
633 <&dmamux1 53 0x400 0x1>;
634 dma-names = "ch1", "ch2", "ch3", "ch4",
635 "up", "trig", "com";
636 status = "disabled";
637
638 pwm {
639 compatible = "st,stm32-pwm";
640 #pwm-cells = <3>;
641 status = "disabled";
642 };
643
644 timer@7 {
645 compatible = "st,stm32h7-timer-trigger";
646 reg = <7>;
647 status = "disabled";
648 };
649
650 counter {
651 compatible = "st,stm32-timer-counter";
652 status = "disabled";
653 };
654 };
655
656 usart6: serial@44003000 {
657 compatible = "st,stm32h7-uart";
658 reg = <0x44003000 0x400>;
659 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
660 clocks = <&rcc USART6_K>;
661 status = "disabled";
662 };
663
664 spi1: spi@44004000 {
665 #address-cells = <1>;
666 #size-cells = <0>;
667 compatible = "st,stm32h7-spi";
668 reg = <0x44004000 0x400>;
669 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
670 clocks = <&rcc SPI1_K>;
671 resets = <&rcc SPI1_R>;
672 dmas = <&dmamux1 37 0x400 0x05>,
673 <&dmamux1 38 0x400 0x05>;
674 dma-names = "rx", "tx";
675 status = "disabled";
676 };
677
678 i2s1: audio-controller@44004000 {
679 compatible = "st,stm32h7-i2s";
680 #sound-dai-cells = <0>;
681 reg = <0x44004000 0x400>;
682 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
683 dmas = <&dmamux1 37 0x400 0x01>,
684 <&dmamux1 38 0x400 0x01>;
685 dma-names = "rx", "tx";
686 status = "disabled";
687 };
688
689 spi4: spi@44005000 {
690 #address-cells = <1>;
691 #size-cells = <0>;
692 compatible = "st,stm32h7-spi";
693 reg = <0x44005000 0x400>;
694 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
695 clocks = <&rcc SPI4_K>;
696 resets = <&rcc SPI4_R>;
697 dmas = <&dmamux1 83 0x400 0x05>,
698 <&dmamux1 84 0x400 0x05>;
699 dma-names = "rx", "tx";
700 status = "disabled";
701 };
702
703 timers15: timer@44006000 {
704 #address-cells = <1>;
705 #size-cells = <0>;
706 compatible = "st,stm32-timers";
707 reg = <0x44006000 0x400>;
708 clocks = <&rcc TIM15_K>;
709 clock-names = "int";
710 dmas = <&dmamux1 105 0x400 0x1>,
711 <&dmamux1 106 0x400 0x1>,
712 <&dmamux1 107 0x400 0x1>,
713 <&dmamux1 108 0x400 0x1>;
714 dma-names = "ch1", "up", "trig", "com";
715 status = "disabled";
716
717 pwm {
718 compatible = "st,stm32-pwm";
719 #pwm-cells = <3>;
720 status = "disabled";
721 };
722
723 timer@14 {
724 compatible = "st,stm32h7-timer-trigger";
725 reg = <14>;
726 status = "disabled";
727 };
728 };
729
730 timers16: timer@44007000 {
731 #address-cells = <1>;
732 #size-cells = <0>;
733 compatible = "st,stm32-timers";
734 reg = <0x44007000 0x400>;
735 clocks = <&rcc TIM16_K>;
736 clock-names = "int";
737 dmas = <&dmamux1 109 0x400 0x1>,
738 <&dmamux1 110 0x400 0x1>;
739 dma-names = "ch1", "up";
740 status = "disabled";
741
742 pwm {
743 compatible = "st,stm32-pwm";
744 #pwm-cells = <3>;
745 status = "disabled";
746 };
747 timer@15 {
748 compatible = "st,stm32h7-timer-trigger";
749 reg = <15>;
750 status = "disabled";
751 };
752 };
753
754 timers17: timer@44008000 {
755 #address-cells = <1>;
756 #size-cells = <0>;
757 compatible = "st,stm32-timers";
758 reg = <0x44008000 0x400>;
759 clocks = <&rcc TIM17_K>;
760 clock-names = "int";
761 dmas = <&dmamux1 111 0x400 0x1>,
762 <&dmamux1 112 0x400 0x1>;
763 dma-names = "ch1", "up";
764 status = "disabled";
765
766 pwm {
767 compatible = "st,stm32-pwm";
768 #pwm-cells = <3>;
769 status = "disabled";
770 };
771
772 timer@16 {
773 compatible = "st,stm32h7-timer-trigger";
774 reg = <16>;
775 status = "disabled";
776 };
777 };
778
779 spi5: spi@44009000 {
780 #address-cells = <1>;
781 #size-cells = <0>;
782 compatible = "st,stm32h7-spi";
783 reg = <0x44009000 0x400>;
784 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&rcc SPI5_K>;
786 resets = <&rcc SPI5_R>;
787 dmas = <&dmamux1 85 0x400 0x05>,
788 <&dmamux1 86 0x400 0x05>;
789 dma-names = "rx", "tx";
790 status = "disabled";
791 };
792
793 sai1: sai@4400a000 {
794 compatible = "st,stm32h7-sai";
795 #address-cells = <1>;
796 #size-cells = <1>;
797 ranges = <0 0x4400a000 0x400>;
798 reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>;
799 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
800 resets = <&rcc SAI1_R>;
801 status = "disabled";
802
803 sai1a: audio-controller@4400a004 {
804 #sound-dai-cells = <0>;
805
806 compatible = "st,stm32-sai-sub-a";
807 reg = <0x4 0x1c>;
808 clocks = <&rcc SAI1_K>;
809 clock-names = "sai_ck";
810 dmas = <&dmamux1 87 0x400 0x01>;
811 status = "disabled";
812 };
813
814 sai1b: audio-controller@4400a024 {
815 #sound-dai-cells = <0>;
816 compatible = "st,stm32-sai-sub-b";
817 reg = <0x24 0x1c>;
818 clocks = <&rcc SAI1_K>;
819 clock-names = "sai_ck";
820 dmas = <&dmamux1 88 0x400 0x01>;
821 status = "disabled";
822 };
823 };
824
825 sai2: sai@4400b000 {
826 compatible = "st,stm32h7-sai";
827 #address-cells = <1>;
828 #size-cells = <1>;
829 ranges = <0 0x4400b000 0x400>;
830 reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>;
831 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
832 resets = <&rcc SAI2_R>;
833 status = "disabled";
834
835 sai2a: audio-controller@4400b004 {
836 #sound-dai-cells = <0>;
837 compatible = "st,stm32-sai-sub-a";
838 reg = <0x4 0x1c>;
839 clocks = <&rcc SAI2_K>;
840 clock-names = "sai_ck";
841 dmas = <&dmamux1 89 0x400 0x01>;
842 status = "disabled";
843 };
844
845 sai2b: audio-controller@4400b024 {
846 #sound-dai-cells = <0>;
847 compatible = "st,stm32-sai-sub-b";
848 reg = <0x24 0x1c>;
849 clocks = <&rcc SAI2_K>;
850 clock-names = "sai_ck";
851 dmas = <&dmamux1 90 0x400 0x01>;
852 status = "disabled";
853 };
854 };
855
856 sai3: sai@4400c000 {
857 compatible = "st,stm32h7-sai";
858 #address-cells = <1>;
859 #size-cells = <1>;
860 ranges = <0 0x4400c000 0x400>;
861 reg = <0x4400c000 0x4>, <0x4400c3f0 0x10>;
862 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
863 resets = <&rcc SAI3_R>;
864 status = "disabled";
865
866 sai3a: audio-controller@4400c004 {
867 #sound-dai-cells = <0>;
868 compatible = "st,stm32-sai-sub-a";
869 reg = <0x04 0x1c>;
870 clocks = <&rcc SAI3_K>;
871 clock-names = "sai_ck";
872 dmas = <&dmamux1 113 0x400 0x01>;
873 status = "disabled";
874 };
875
876 sai3b: audio-controller@4400c024 {
877 #sound-dai-cells = <0>;
878 compatible = "st,stm32-sai-sub-b";
879 reg = <0x24 0x1c>;
880 clocks = <&rcc SAI3_K>;
881 clock-names = "sai_ck";
882 dmas = <&dmamux1 114 0x400 0x01>;
883 status = "disabled";
884 };
885 };
886
887 dfsdm: dfsdm@4400d000 {
888 compatible = "st,stm32mp1-dfsdm";
889 reg = <0x4400d000 0x800>;
890 clocks = <&rcc DFSDM_K>;
891 clock-names = "dfsdm";
892 #address-cells = <1>;
893 #size-cells = <0>;
894 status = "disabled";
895
896 dfsdm0: filter@0 {
897 compatible = "st,stm32-dfsdm-adc";
898 #io-channel-cells = <1>;
899 reg = <0>;
900 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
901 dmas = <&dmamux1 101 0x400 0x01>;
902 dma-names = "rx";
903 status = "disabled";
904 };
905
906 dfsdm1: filter@1 {
907 compatible = "st,stm32-dfsdm-adc";
908 #io-channel-cells = <1>;
909 reg = <1>;
910 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
911 dmas = <&dmamux1 102 0x400 0x01>;
912 dma-names = "rx";
913 status = "disabled";
914 };
915
916 dfsdm2: filter@2 {
917 compatible = "st,stm32-dfsdm-adc";
918 #io-channel-cells = <1>;
919 reg = <2>;
920 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
921 dmas = <&dmamux1 103 0x400 0x01>;
922 dma-names = "rx";
923 status = "disabled";
924 };
925
926 dfsdm3: filter@3 {
927 compatible = "st,stm32-dfsdm-adc";
928 #io-channel-cells = <1>;
929 reg = <3>;
930 interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>;
931 dmas = <&dmamux1 104 0x400 0x01>;
932 dma-names = "rx";
933 status = "disabled";
934 };
935
936 dfsdm4: filter@4 {
937 compatible = "st,stm32-dfsdm-adc";
938 #io-channel-cells = <1>;
939 reg = <4>;
940 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
941 dmas = <&dmamux1 91 0x400 0x01>;
942 dma-names = "rx";
943 status = "disabled";
944 };
945
946 dfsdm5: filter@5 {
947 compatible = "st,stm32-dfsdm-adc";
948 #io-channel-cells = <1>;
949 reg = <5>;
950 interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
951 dmas = <&dmamux1 92 0x400 0x01>;
952 dma-names = "rx";
953 status = "disabled";
954 };
955 };
956
957 dma1: dma-controller@48000000 {
958 compatible = "st,stm32-dma";
959 reg = <0x48000000 0x400>;
960 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
961 <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
962 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
963 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
964 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
965 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
966 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
967 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
968 clocks = <&rcc DMA1>;
969 resets = <&rcc DMA1_R>;
970 #dma-cells = <4>;
971 st,mem2mem;
972 dma-requests = <8>;
973 };
974
975 dma2: dma-controller@48001000 {
976 compatible = "st,stm32-dma";
977 reg = <0x48001000 0x400>;
978 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
979 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
980 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
981 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
982 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
983 <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
984 <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>,
985 <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
986 clocks = <&rcc DMA2>;
987 resets = <&rcc DMA2_R>;
988 #dma-cells = <4>;
989 st,mem2mem;
990 dma-requests = <8>;
991 };
992
993 dmamux1: dma-router@48002000 {
994 compatible = "st,stm32h7-dmamux";
995 reg = <0x48002000 0x1c>;
996 #dma-cells = <3>;
997 dma-requests = <128>;
998 dma-masters = <&dma1 &dma2>;
999 dma-channels = <16>;
1000 clocks = <&rcc DMAMUX>;
1001 resets = <&rcc DMAMUX_R>;
1002 };
1003
1004 adc: adc@48003000 {
1005 compatible = "st,stm32mp1-adc-core";
1006 reg = <0x48003000 0x400>;
1007 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
1008 <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
1009 clocks = <&rcc ADC12>, <&rcc ADC12_K>;
1010 clock-names = "bus", "adc";
1011 interrupt-controller;
1012 st,syscfg = <&syscfg>;
1013 #interrupt-cells = <1>;
1014 #address-cells = <1>;
1015 #size-cells = <0>;
1016 status = "disabled";
1017
1018 adc1: adc@0 {
1019 compatible = "st,stm32mp1-adc";
1020 #io-channel-cells = <1>;
1021 reg = <0x0>;
1022 interrupt-parent = <&adc>;
1023 interrupts = <0>;
1024 dmas = <&dmamux1 9 0x400 0x01>;
1025 dma-names = "rx";
1026 status = "disabled";
1027 };
1028
1029 adc2: adc@100 {
1030 compatible = "st,stm32mp1-adc";
1031 #io-channel-cells = <1>;
1032 reg = <0x100>;
1033 interrupt-parent = <&adc>;
1034 interrupts = <1>;
1035 dmas = <&dmamux1 10 0x400 0x01>;
1036 dma-names = "rx";
1037 status = "disabled";
1038 };
1039 };
1040
1041 sdmmc3: sdmmc@48004000 {
1042 compatible = "arm,pl18x", "arm,primecell";
1043 arm,primecell-periphid = <0x10153180>;
1044 reg = <0x48004000 0x400>;
1045 interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
1046 interrupt-names = "cmd_irq";
1047 clocks = <&rcc SDMMC3_K>;
1048 clock-names = "apb_pclk";
1049 resets = <&rcc SDMMC3_R>;
1050 cap-sd-highspeed;
1051 cap-mmc-highspeed;
1052 max-frequency = <120000000>;
1053 status = "disabled";
1054 };
1055
1056 usbotg_hs: usb-otg@49000000 {
1057 compatible = "st,stm32mp15-hsotg", "snps,dwc2";
1058 reg = <0x49000000 0x10000>;
1059 clocks = <&rcc USBO_K>;
1060 clock-names = "otg";
1061 resets = <&rcc USBO_R>;
1062 reset-names = "dwc2";
1063 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1064 g-rx-fifo-size = <256>;
1065 g-np-tx-fifo-size = <32>;
1066 g-tx-fifo-size = <128 128 64 64 64 64 32 32>;
1067 dr_mode = "otg";
1068 usb33d-supply = <&usb33>;
1069 status = "disabled";
1070 };
1071
1072 ipcc: mailbox@4c001000 {
1073 compatible = "st,stm32mp1-ipcc";
1074 #mbox-cells = <1>;
1075 reg = <0x4c001000 0x400>;
1076 st,proc-id = <0>;
1077 interrupts-extended =
1078 <&intc GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
1079 <&intc GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
1080 <&exti 61 1>;
1081 interrupt-names = "rx", "tx", "wakeup";
1082 clocks = <&rcc IPCC>;
1083 wakeup-source;
1084 status = "disabled";
1085 };
1086
1087 dcmi: dcmi@4c006000 {
1088 compatible = "st,stm32-dcmi";
1089 reg = <0x4c006000 0x400>;
1090 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
1091 resets = <&rcc CAMITF_R>;
1092 clocks = <&rcc DCMI>;
1093 clock-names = "mclk";
1094 dmas = <&dmamux1 75 0x400 0x0d>;
1095 dma-names = "tx";
1096 status = "disabled";
1097 };
1098
1099 rcc: rcc@50000000 {
1100 compatible = "st,stm32mp1-rcc", "syscon";
1101 reg = <0x50000000 0x1000>;
1102 #clock-cells = <1>;
1103 #reset-cells = <1>;
1104 };
1105
1106 pwr_regulators: pwr@50001000 {
1107 compatible = "st,stm32mp1,pwr-reg";
1108 reg = <0x50001000 0x10>;
1109
1110 reg11: reg11 {
1111 regulator-name = "reg11";
1112 regulator-min-microvolt = <1100000>;
1113 regulator-max-microvolt = <1100000>;
1114 };
1115
1116 reg18: reg18 {
1117 regulator-name = "reg18";
1118 regulator-min-microvolt = <1800000>;
1119 regulator-max-microvolt = <1800000>;
1120 };
1121
1122 usb33: usb33 {
1123 regulator-name = "usb33";
1124 regulator-min-microvolt = <3300000>;
1125 regulator-max-microvolt = <3300000>;
1126 };
1127 };
1128
1129 pwr_mcu: pwr_mcu@50001014 {
1130 compatible = "st,stm32mp151-pwr-mcu", "syscon";
1131 reg = <0x50001014 0x4>;
1132 };
1133
1134 exti: interrupt-controller@5000d000 {
1135 compatible = "st,stm32mp1-exti", "syscon";
1136 interrupt-controller;
1137 #interrupt-cells = <2>;
1138 reg = <0x5000d000 0x400>;
1139 };
1140
1141 syscfg: syscon@50020000 {
1142 compatible = "st,stm32mp157-syscfg", "syscon";
1143 reg = <0x50020000 0x400>;
1144 clocks = <&rcc SYSCFG>;
1145 };
1146
1147 lptimer2: timer@50021000 {
1148 #address-cells = <1>;
1149 #size-cells = <0>;
1150 compatible = "st,stm32-lptimer";
1151 reg = <0x50021000 0x400>;
1152 clocks = <&rcc LPTIM2_K>;
1153 clock-names = "mux";
1154 status = "disabled";
1155
1156 pwm {
1157 compatible = "st,stm32-pwm-lp";
1158 #pwm-cells = <3>;
1159 status = "disabled";
1160 };
1161
1162 trigger@1 {
1163 compatible = "st,stm32-lptimer-trigger";
1164 reg = <1>;
1165 status = "disabled";
1166 };
1167
1168 counter {
1169 compatible = "st,stm32-lptimer-counter";
1170 status = "disabled";
1171 };
1172 };
1173
1174 lptimer3: timer@50022000 {
1175 #address-cells = <1>;
1176 #size-cells = <0>;
1177 compatible = "st,stm32-lptimer";
1178 reg = <0x50022000 0x400>;
1179 clocks = <&rcc LPTIM3_K>;
1180 clock-names = "mux";
1181 status = "disabled";
1182
1183 pwm {
1184 compatible = "st,stm32-pwm-lp";
1185 #pwm-cells = <3>;
1186 status = "disabled";
1187 };
1188
1189 trigger@2 {
1190 compatible = "st,stm32-lptimer-trigger";
1191 reg = <2>;
1192 status = "disabled";
1193 };
1194 };
1195
1196 lptimer4: timer@50023000 {
1197 compatible = "st,stm32-lptimer";
1198 reg = <0x50023000 0x400>;
1199 clocks = <&rcc LPTIM4_K>;
1200 clock-names = "mux";
1201 status = "disabled";
1202
1203 pwm {
1204 compatible = "st,stm32-pwm-lp";
1205 #pwm-cells = <3>;
1206 status = "disabled";
1207 };
1208 };
1209
1210 lptimer5: timer@50024000 {
1211 compatible = "st,stm32-lptimer";
1212 reg = <0x50024000 0x400>;
1213 clocks = <&rcc LPTIM5_K>;
1214 clock-names = "mux";
1215 status = "disabled";
1216
1217 pwm {
1218 compatible = "st,stm32-pwm-lp";
1219 #pwm-cells = <3>;
1220 status = "disabled";
1221 };
1222 };
1223
1224 vrefbuf: vrefbuf@50025000 {
1225 compatible = "st,stm32-vrefbuf";
1226 reg = <0x50025000 0x8>;
1227 regulator-min-microvolt = <1500000>;
1228 regulator-max-microvolt = <2500000>;
1229 clocks = <&rcc VREF>;
1230 status = "disabled";
1231 };
1232
1233 sai4: sai@50027000 {
1234 compatible = "st,stm32h7-sai";
1235 #address-cells = <1>;
1236 #size-cells = <1>;
1237 ranges = <0 0x50027000 0x400>;
1238 reg = <0x50027000 0x4>, <0x500273f0 0x10>;
1239 interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
1240 resets = <&rcc SAI4_R>;
1241 status = "disabled";
1242
1243 sai4a: audio-controller@50027004 {
1244 #sound-dai-cells = <0>;
1245 compatible = "st,stm32-sai-sub-a";
1246 reg = <0x04 0x1c>;
1247 clocks = <&rcc SAI4_K>;
1248 clock-names = "sai_ck";
1249 dmas = <&dmamux1 99 0x400 0x01>;
1250 status = "disabled";
1251 };
1252
1253 sai4b: audio-controller@50027024 {
1254 #sound-dai-cells = <0>;
1255 compatible = "st,stm32-sai-sub-b";
1256 reg = <0x24 0x1c>;
1257 clocks = <&rcc SAI4_K>;
1258 clock-names = "sai_ck";
1259 dmas = <&dmamux1 100 0x400 0x01>;
1260 status = "disabled";
1261 };
1262 };
1263
1264 dts: thermal@50028000 {
1265 compatible = "st,stm32-thermal";
1266 reg = <0x50028000 0x100>;
1267 interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
1268 clocks = <&rcc TMPSENS>;
1269 clock-names = "pclk";
1270 #thermal-sensor-cells = <0>;
1271 status = "disabled";
1272 };
1273
1274 hash1: hash@54002000 {
1275 compatible = "st,stm32f756-hash";
1276 reg = <0x54002000 0x400>;
1277 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
1278 clocks = <&rcc HASH1>;
1279 resets = <&rcc HASH1_R>;
1280 dmas = <&mdma1 31 0x10 0x1000A02 0x0 0x0>;
1281 dma-names = "in";
1282 dma-maxburst = <2>;
1283 status = "disabled";
1284 };
1285
1286 rng1: rng@54003000 {
1287 compatible = "st,stm32-rng";
1288 reg = <0x54003000 0x400>;
1289 clocks = <&rcc RNG1_K>;
1290 resets = <&rcc RNG1_R>;
1291 status = "disabled";
1292 };
1293
1294 mdma1: dma-controller@58000000 {
1295 compatible = "st,stm32h7-mdma";
1296 reg = <0x58000000 0x1000>;
1297 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1298 clocks = <&rcc MDMA>;
1299 resets = <&rcc MDMA_R>;
1300 #dma-cells = <5>;
1301 dma-channels = <32>;
1302 dma-requests = <48>;
1303 };
1304
1305 fmc: nand-controller@58002000 {
1306 compatible = "st,stm32mp15-fmc2";
1307 reg = <0x58002000 0x1000>,
1308 <0x80000000 0x1000>,
1309 <0x88010000 0x1000>,
1310 <0x88020000 0x1000>,
1311 <0x81000000 0x1000>,
1312 <0x89010000 0x1000>,
1313 <0x89020000 0x1000>;
1314 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1315 dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
1316 <&mdma1 20 0x10 0x12000a08 0x0 0x0>,
1317 <&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
1318 dma-names = "tx", "rx", "ecc";
1319 clocks = <&rcc FMC_K>;
1320 resets = <&rcc FMC_R>;
1321 status = "disabled";
1322 };
1323
1324 qspi: spi@58003000 {
1325 compatible = "st,stm32f469-qspi";
1326 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
1327 reg-names = "qspi", "qspi_mm";
1328 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
1329 dmas = <&mdma1 22 0x10 0x100002 0x0 0x0>,
1330 <&mdma1 22 0x10 0x100008 0x0 0x0>;
1331 dma-names = "tx", "rx";
1332 clocks = <&rcc QSPI_K>;
1333 resets = <&rcc QSPI_R>;
1334 #address-cells = <1>;
1335 #size-cells = <0>;
1336 status = "disabled";
1337 };
1338
1339 sdmmc1: sdmmc@58005000 {
1340 compatible = "arm,pl18x", "arm,primecell";
1341 arm,primecell-periphid = <0x10153180>;
1342 reg = <0x58005000 0x1000>;
1343 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1344 interrupt-names = "cmd_irq";
1345 clocks = <&rcc SDMMC1_K>;
1346 clock-names = "apb_pclk";
1347 resets = <&rcc SDMMC1_R>;
1348 cap-sd-highspeed;
1349 cap-mmc-highspeed;
1350 max-frequency = <120000000>;
1351 status = "disabled";
1352 };
1353
1354 sdmmc2: sdmmc@58007000 {
1355 compatible = "arm,pl18x", "arm,primecell";
1356 arm,primecell-periphid = <0x10153180>;
1357 reg = <0x58007000 0x1000>;
1358 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1359 interrupt-names = "cmd_irq";
1360 clocks = <&rcc SDMMC2_K>;
1361 clock-names = "apb_pclk";
1362 resets = <&rcc SDMMC2_R>;
1363 cap-sd-highspeed;
1364 cap-mmc-highspeed;
1365 max-frequency = <120000000>;
1366 status = "disabled";
1367 };
1368
1369 crc1: crc@58009000 {
1370 compatible = "st,stm32f7-crc";
1371 reg = <0x58009000 0x400>;
1372 clocks = <&rcc CRC1>;
1373 status = "disabled";
1374 };
1375
1376 stmmac_axi_config_0: stmmac-axi-config {
1377 snps,wr_osr_lmt = <0x7>;
1378 snps,rd_osr_lmt = <0x7>;
1379 snps,blen = <0 0 0 0 16 8 4>;
1380 };
1381
1382 ethernet0: ethernet@5800a000 {
1383 compatible = "st,stm32mp1-dwmac", "snps,dwmac-4.20a";
1384 reg = <0x5800a000 0x2000>;
1385 reg-names = "stmmaceth";
1386 interrupts-extended = <&intc GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
1387 interrupt-names = "macirq";
1388 clock-names = "stmmaceth",
1389 "mac-clk-tx",
1390 "mac-clk-rx",
1391 "eth-ck",
1392 "ethstp";
1393 clocks = <&rcc ETHMAC>,
1394 <&rcc ETHTX>,
1395 <&rcc ETHRX>,
1396 <&rcc ETHCK_K>,
1397 <&rcc ETHSTP>;
1398 st,syscon = <&syscfg 0x4>;
1399 snps,mixed-burst;
1400 snps,pbl = <2>;
1401 snps,en-tx-lpi-clockgating;
1402 snps,axi-config = <&stmmac_axi_config_0>;
1403 snps,tso;
1404 status = "disabled";
1405 };
1406
1407 usbh_ohci: usbh-ohci@5800c000 {
1408 compatible = "generic-ohci";
1409 reg = <0x5800c000 0x1000>;
1410 clocks = <&rcc USBH>;
1411 resets = <&rcc USBH_R>;
1412 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
1413 status = "disabled";
1414 };
1415
1416 usbh_ehci: usbh-ehci@5800d000 {
1417 compatible = "generic-ehci";
1418 reg = <0x5800d000 0x1000>;
1419 clocks = <&rcc USBH>;
1420 resets = <&rcc USBH_R>;
1421 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
1422 companion = <&usbh_ohci>;
1423 status = "disabled";
1424 };
1425
1426 ltdc: display-controller@5a001000 {
1427 compatible = "st,stm32-ltdc";
1428 reg = <0x5a001000 0x400>;
1429 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
1430 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
1431 clocks = <&rcc LTDC_PX>;
1432 clock-names = "lcd";
1433 resets = <&rcc LTDC_R>;
1434 status = "disabled";
1435
1436 port {
1437 #address-cells = <1>;
1438 #size-cells = <0>;
1439 };
1440 };
1441
1442 iwdg2: watchdog@5a002000 {
1443 compatible = "st,stm32mp1-iwdg";
1444 reg = <0x5a002000 0x400>;
1445 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
1446 clock-names = "pclk", "lsi";
1447 status = "disabled";
1448 };
1449
1450 usbphyc: usbphyc@5a006000 {
1451 #address-cells = <1>;
1452 #size-cells = <0>;
1453 compatible = "st,stm32mp1-usbphyc";
1454 reg = <0x5a006000 0x1000>;
1455 clocks = <&rcc USBPHY_K>;
1456 resets = <&rcc USBPHY_R>;
1457 status = "disabled";
1458
1459 usbphyc_port0: usb-phy@0 {
1460 #phy-cells = <0>;
1461 reg = <0>;
1462 };
1463
1464 usbphyc_port1: usb-phy@1 {
1465 #phy-cells = <1>;
1466 reg = <1>;
1467 };
1468 };
1469
1470 usart1: serial@5c000000 {
1471 compatible = "st,stm32h7-uart";
1472 reg = <0x5c000000 0x400>;
1473 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1474 clocks = <&rcc USART1_K>;
1475 status = "disabled";
1476 };
1477
1478 spi6: spi@5c001000 {
1479 #address-cells = <1>;
1480 #size-cells = <0>;
1481 compatible = "st,stm32h7-spi";
1482 reg = <0x5c001000 0x400>;
1483 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
1484 clocks = <&rcc SPI6_K>;
1485 resets = <&rcc SPI6_R>;
1486 dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>,
1487 <&mdma1 35 0x0 0x40002 0x0 0x0>;
1488 dma-names = "rx", "tx";
1489 status = "disabled";
1490 };
1491
1492 i2c4: i2c@5c002000 {
1493 compatible = "st,stm32mp15-i2c";
1494 reg = <0x5c002000 0x400>;
1495 interrupt-names = "event", "error";
1496 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
1497 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1498 clocks = <&rcc I2C4_K>;
1499 resets = <&rcc I2C4_R>;
1500 #address-cells = <1>;
1501 #size-cells = <0>;
1502 st,syscfg-fmp = <&syscfg 0x4 0x8>;
1503 wakeup-source;
1504 status = "disabled";
1505 };
1506
1507 rtc: rtc@5c004000 {
1508 compatible = "st,stm32mp1-rtc";
1509 reg = <0x5c004000 0x400>;
1510 clocks = <&rcc RTCAPB>, <&rcc RTC>;
1511 clock-names = "pclk", "rtc_ck";
1512 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
1513 status = "disabled";
1514 };
1515
1516 bsec: efuse@5c005000 {
1517 compatible = "st,stm32mp15-bsec";
1518 reg = <0x5c005000 0x400>;
1519 #address-cells = <1>;
1520 #size-cells = <1>;
1521 ts_cal1: calib@5c {
1522 reg = <0x5c 0x2>;
1523 };
1524 ts_cal2: calib@5e {
1525 reg = <0x5e 0x2>;
1526 };
1527 };
1528
1529 i2c6: i2c@5c009000 {
1530 compatible = "st,stm32mp15-i2c";
1531 reg = <0x5c009000 0x400>;
1532 interrupt-names = "event", "error";
1533 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
1534 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1535 clocks = <&rcc I2C6_K>;
1536 resets = <&rcc I2C6_R>;
1537 #address-cells = <1>;
1538 #size-cells = <0>;
1539 st,syscfg-fmp = <&syscfg 0x4 0x20>;
1540 wakeup-source;
1541 status = "disabled";
1542 };
1543
1544 /*
1545 * Break node order to solve dependency probe issue between
1546 * pinctrl and exti.
1547 */
1548 pinctrl: pin-controller@50002000 {
1549 #address-cells = <1>;
1550 #size-cells = <1>;
1551 compatible = "st,stm32mp157-pinctrl";
1552 ranges = <0 0x50002000 0xa400>;
1553 interrupt-parent = <&exti>;
1554 st,syscfg = <&exti 0x60 0xff>;
1555 pins-are-numbered;
1556
1557 gpioa: gpio@50002000 {
1558 gpio-controller;
1559 #gpio-cells = <2>;
1560 interrupt-controller;
1561 #interrupt-cells = <2>;
1562 reg = <0x0 0x400>;
1563 clocks = <&rcc GPIOA>;
1564 st,bank-name = "GPIOA";
1565 status = "disabled";
1566 };
1567
1568 gpiob: gpio@50003000 {
1569 gpio-controller;
1570 #gpio-cells = <2>;
1571 interrupt-controller;
1572 #interrupt-cells = <2>;
1573 reg = <0x1000 0x400>;
1574 clocks = <&rcc GPIOB>;
1575 st,bank-name = "GPIOB";
1576 status = "disabled";
1577 };
1578
1579 gpioc: gpio@50004000 {
1580 gpio-controller;
1581 #gpio-cells = <2>;
1582 interrupt-controller;
1583 #interrupt-cells = <2>;
1584 reg = <0x2000 0x400>;
1585 clocks = <&rcc GPIOC>;
1586 st,bank-name = "GPIOC";
1587 status = "disabled";
1588 };
1589
1590 gpiod: gpio@50005000 {
1591 gpio-controller;
1592 #gpio-cells = <2>;
1593 interrupt-controller;
1594 #interrupt-cells = <2>;
1595 reg = <0x3000 0x400>;
1596 clocks = <&rcc GPIOD>;
1597 st,bank-name = "GPIOD";
1598 status = "disabled";
1599 };
1600
1601 gpioe: gpio@50006000 {
1602 gpio-controller;
1603 #gpio-cells = <2>;
1604 interrupt-controller;
1605 #interrupt-cells = <2>;
1606 reg = <0x4000 0x400>;
1607 clocks = <&rcc GPIOE>;
1608 st,bank-name = "GPIOE";
1609 status = "disabled";
1610 };
1611
1612 gpiof: gpio@50007000 {
1613 gpio-controller;
1614 #gpio-cells = <2>;
1615 interrupt-controller;
1616 #interrupt-cells = <2>;
1617 reg = <0x5000 0x400>;
1618 clocks = <&rcc GPIOF>;
1619 st,bank-name = "GPIOF";
1620 status = "disabled";
1621 };
1622
1623 gpiog: gpio@50008000 {
1624 gpio-controller;
1625 #gpio-cells = <2>;
1626 interrupt-controller;
1627 #interrupt-cells = <2>;
1628 reg = <0x6000 0x400>;
1629 clocks = <&rcc GPIOG>;
1630 st,bank-name = "GPIOG";
1631 status = "disabled";
1632 };
1633
1634 gpioh: gpio@50009000 {
1635 gpio-controller;
1636 #gpio-cells = <2>;
1637 interrupt-controller;
1638 #interrupt-cells = <2>;
1639 reg = <0x7000 0x400>;
1640 clocks = <&rcc GPIOH>;
1641 st,bank-name = "GPIOH";
1642 status = "disabled";
1643 };
1644
1645 gpioi: gpio@5000a000 {
1646 gpio-controller;
1647 #gpio-cells = <2>;
1648 interrupt-controller;
1649 #interrupt-cells = <2>;
1650 reg = <0x8000 0x400>;
1651 clocks = <&rcc GPIOI>;
1652 st,bank-name = "GPIOI";
1653 status = "disabled";
1654 };
1655
1656 gpioj: gpio@5000b000 {
1657 gpio-controller;
1658 #gpio-cells = <2>;
1659 interrupt-controller;
1660 #interrupt-cells = <2>;
1661 reg = <0x9000 0x400>;
1662 clocks = <&rcc GPIOJ>;
1663 st,bank-name = "GPIOJ";
1664 status = "disabled";
1665 };
1666
1667 gpiok: gpio@5000c000 {
1668 gpio-controller;
1669 #gpio-cells = <2>;
1670 interrupt-controller;
1671 #interrupt-cells = <2>;
1672 reg = <0xa000 0x400>;
1673 clocks = <&rcc GPIOK>;
1674 st,bank-name = "GPIOK";
1675 status = "disabled";
1676 };
1677 };
1678
1679 pinctrl_z: pin-controller-z@54004000 {
1680 #address-cells = <1>;
1681 #size-cells = <1>;
1682 compatible = "st,stm32mp157-z-pinctrl";
1683 ranges = <0 0x54004000 0x400>;
1684 pins-are-numbered;
1685 interrupt-parent = <&exti>;
1686 st,syscfg = <&exti 0x60 0xff>;
1687
1688 gpioz: gpio@54004000 {
1689 gpio-controller;
1690 #gpio-cells = <2>;
1691 interrupt-controller;
1692 #interrupt-cells = <2>;
1693 reg = <0 0x400>;
1694 clocks = <&rcc GPIOZ>;
1695 st,bank-name = "GPIOZ";
1696 st,bank-ioport = <11>;
1697 status = "disabled";
1698 };
1699 };
1700 };
1701
1702 mlahb: ahb {
1703 compatible = "st,mlahb", "simple-bus";
1704 #address-cells = <1>;
1705 #size-cells = <1>;
1706 ranges;
1707 dma-ranges = <0x00000000 0x38000000 0x10000>,
1708 <0x10000000 0x10000000 0x60000>,
1709 <0x30000000 0x30000000 0x60000>;
1710
1711 m4_rproc: m4@10000000 {
1712 compatible = "st,stm32mp1-m4";
1713 reg = <0x10000000 0x40000>,
1714 <0x30000000 0x40000>,
1715 <0x38000000 0x10000>;
1716 resets = <&rcc MCU_R>;
1717 st,syscfg-holdboot = <&rcc 0x10C 0x1>;
1718 st,syscfg-tz = <&rcc 0x000 0x1>;
1719 st,syscfg-pdds = <&pwr_mcu 0x0 0x1>;
1720 status = "disabled";
1721 };
1722 };
1723};