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1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
17 led0 = &led0;
18 led1 = &led1;
19 led2 = &led2;
20 nand = &gpmi;
21 ssi0 = &ssi1;
22 usb0 = &usbh1;
23 usb1 = &usbotg;
24 };
25
26 chosen {
27 bootargs = "console=ttymxc1,115200";
28 };
29
30 backlight {
31 compatible = "pwm-backlight";
32 pwms = <&pwm4 0 5000000>;
33 brightness-levels = <0 4 8 16 32 64 128 255>;
34 default-brightness-level = <7>;
35 };
36
37 leds {
38 compatible = "gpio-leds";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_gpio_leds>;
41
42 led0: user1 {
43 label = "user1";
44 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
45 default-state = "on";
46 linux,default-trigger = "heartbeat";
47 };
48
49 led1: user2 {
50 label = "user2";
51 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
52 default-state = "off";
53 };
54
55 led2: user3 {
56 label = "user3";
57 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
58 default-state = "off";
59 };
60 };
61
62 memory@10000000 {
63 reg = <0x10000000 0x40000000>;
64 };
65
66 pps {
67 compatible = "pps-gpio";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pps>;
70 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
71 status = "okay";
72 };
73
74 regulators {
75 compatible = "simple-bus";
76 #address-cells = <1>;
77 #size-cells = <0>;
78
79 reg_1p0v: regulator@0 {
80 compatible = "regulator-fixed";
81 reg = <0>;
82 regulator-name = "1P0V";
83 regulator-min-microvolt = <1000000>;
84 regulator-max-microvolt = <1000000>;
85 regulator-always-on;
86 };
87
88 reg_3p3v: regulator@1 {
89 compatible = "regulator-fixed";
90 reg = <1>;
91 regulator-name = "3P3V";
92 regulator-min-microvolt = <3300000>;
93 regulator-max-microvolt = <3300000>;
94 regulator-always-on;
95 };
96
97 reg_usb_h1_vbus: regulator@2 {
98 compatible = "regulator-fixed";
99 reg = <2>;
100 regulator-name = "usb_h1_vbus";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 regulator-always-on;
104 };
105
106 reg_usb_otg_vbus: regulator@3 {
107 compatible = "regulator-fixed";
108 reg = <3>;
109 regulator-name = "usb_otg_vbus";
110 regulator-min-microvolt = <5000000>;
111 regulator-max-microvolt = <5000000>;
112 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
113 enable-active-high;
114 };
115 };
116
117 sound {
118 compatible = "fsl,imx6q-ventana-sgtl5000",
119 "fsl,imx-audio-sgtl5000";
120 model = "sgtl5000-audio";
121 ssi-controller = <&ssi1>;
122 audio-codec = <&codec>;
123 audio-routing =
124 "MIC_IN", "Mic Jack",
125 "Mic Jack", "Mic Bias",
126 "Headphone Jack", "HP_OUT";
127 mux-int-port = <1>;
128 mux-ext-port = <4>;
129 };
130};
131
132&audmux {
133 pinctrl-names = "default";
134 pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
135 status = "okay";
136};
137
138&can1 {
139 pinctrl-names = "default";
140 pinctrl-0 = <&pinctrl_flexcan1>;
141 status = "okay";
142};
143
144&clks {
145 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
146 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
147 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
148 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
149};
150
151&ecspi2 {
152 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
153 pinctrl-names = "default";
154 pinctrl-0 = <&pinctrl_ecspi2>;
155 status = "okay";
156};
157
158&fec {
159 pinctrl-names = "default";
160 pinctrl-0 = <&pinctrl_enet>;
161 phy-mode = "rgmii-id";
162 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
163 status = "okay";
164};
165
166&gpmi {
167 pinctrl-names = "default";
168 pinctrl-0 = <&pinctrl_gpmi_nand>;
169 status = "okay";
170};
171
172&hdmi {
173 ddc-i2c-bus = <&i2c3>;
174 status = "okay";
175};
176
177&i2c1 {
178 clock-frequency = <100000>;
179 pinctrl-names = "default";
180 pinctrl-0 = <&pinctrl_i2c1>;
181 status = "okay";
182
183 eeprom1: eeprom@50 {
184 compatible = "atmel,24c02";
185 reg = <0x50>;
186 pagesize = <16>;
187 };
188
189 eeprom2: eeprom@51 {
190 compatible = "atmel,24c02";
191 reg = <0x51>;
192 pagesize = <16>;
193 };
194
195 eeprom3: eeprom@52 {
196 compatible = "atmel,24c02";
197 reg = <0x52>;
198 pagesize = <16>;
199 };
200
201 eeprom4: eeprom@53 {
202 compatible = "atmel,24c02";
203 reg = <0x53>;
204 pagesize = <16>;
205 };
206
207 gpio: pca9555@23 {
208 compatible = "nxp,pca9555";
209 reg = <0x23>;
210 gpio-controller;
211 #gpio-cells = <2>;
212 };
213
214 rtc: ds1672@68 {
215 compatible = "dallas,ds1672";
216 reg = <0x68>;
217 };
218};
219
220&i2c2 {
221 clock-frequency = <100000>;
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_i2c2>;
224 status = "okay";
225
226 pmic: pfuze100@8 {
227 compatible = "fsl,pfuze100";
228 reg = <0x08>;
229
230 regulators {
231 sw1a_reg: sw1ab {
232 regulator-min-microvolt = <300000>;
233 regulator-max-microvolt = <1875000>;
234 regulator-boot-on;
235 regulator-always-on;
236 regulator-ramp-delay = <6250>;
237 };
238
239 sw1c_reg: sw1c {
240 regulator-min-microvolt = <300000>;
241 regulator-max-microvolt = <1875000>;
242 regulator-boot-on;
243 regulator-always-on;
244 regulator-ramp-delay = <6250>;
245 };
246
247 sw2_reg: sw2 {
248 regulator-min-microvolt = <800000>;
249 regulator-max-microvolt = <3950000>;
250 regulator-boot-on;
251 regulator-always-on;
252 };
253
254 sw3a_reg: sw3a {
255 regulator-min-microvolt = <400000>;
256 regulator-max-microvolt = <1975000>;
257 regulator-boot-on;
258 regulator-always-on;
259 };
260
261 sw3b_reg: sw3b {
262 regulator-min-microvolt = <400000>;
263 regulator-max-microvolt = <1975000>;
264 regulator-boot-on;
265 regulator-always-on;
266 };
267
268 sw4_reg: sw4 {
269 regulator-min-microvolt = <800000>;
270 regulator-max-microvolt = <3300000>;
271 };
272
273 swbst_reg: swbst {
274 regulator-min-microvolt = <5000000>;
275 regulator-max-microvolt = <5150000>;
276 regulator-boot-on;
277 regulator-always-on;
278 };
279
280 snvs_reg: vsnvs {
281 regulator-min-microvolt = <1000000>;
282 regulator-max-microvolt = <3000000>;
283 regulator-boot-on;
284 regulator-always-on;
285 };
286
287 vref_reg: vrefddr {
288 regulator-boot-on;
289 regulator-always-on;
290 };
291
292 vgen1_reg: vgen1 {
293 regulator-min-microvolt = <800000>;
294 regulator-max-microvolt = <1550000>;
295 };
296
297 vgen2_reg: vgen2 {
298 regulator-min-microvolt = <800000>;
299 regulator-max-microvolt = <1550000>;
300 };
301
302 vgen3_reg: vgen3 {
303 regulator-min-microvolt = <1800000>;
304 regulator-max-microvolt = <3300000>;
305 };
306
307 vgen4_reg: vgen4 {
308 regulator-min-microvolt = <1800000>;
309 regulator-max-microvolt = <3300000>;
310 regulator-always-on;
311 };
312
313 vgen5_reg: vgen5 {
314 regulator-min-microvolt = <1800000>;
315 regulator-max-microvolt = <3300000>;
316 regulator-always-on;
317 };
318
319 vgen6_reg: vgen6 {
320 regulator-min-microvolt = <1800000>;
321 regulator-max-microvolt = <3300000>;
322 regulator-always-on;
323 };
324 };
325 };
326};
327
328&i2c3 {
329 clock-frequency = <100000>;
330 pinctrl-names = "default";
331 pinctrl-0 = <&pinctrl_i2c3>;
332 status = "okay";
333
334 codec: sgtl5000@a {
335 compatible = "fsl,sgtl5000";
336 reg = <0x0a>;
337 clocks = <&clks IMX6QDL_CLK_CKO>;
338 VDDA-supply = <&sw4_reg>;
339 VDDIO-supply = <®_3p3v>;
340 };
341
342 touchscreen: egalax_ts@4 {
343 compatible = "eeti,egalax_ts";
344 reg = <0x04>;
345 interrupt-parent = <&gpio7>;
346 interrupts = <12 2>;
347 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
348 };
349};
350
351&ldb {
352 status = "okay";
353
354 lvds-channel@0 {
355 fsl,data-mapping = "spwg";
356 fsl,data-width = <18>;
357 status = "okay";
358
359 display-timings {
360 native-mode = <&timing0>;
361 timing0: hsd100pxn1 {
362 clock-frequency = <65000000>;
363 hactive = <1024>;
364 vactive = <768>;
365 hback-porch = <220>;
366 hfront-porch = <40>;
367 vback-porch = <21>;
368 vfront-porch = <7>;
369 hsync-len = <60>;
370 vsync-len = <10>;
371 };
372 };
373 };
374};
375
376&pcie {
377 pinctrl-names = "default";
378 pinctrl-0 = <&pinctrl_pcie>;
379 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
380 status = "okay";
381};
382
383&pwm1 {
384 pinctrl-names = "default";
385 pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
386 status = "disabled";
387};
388
389&pwm2 {
390 pinctrl-names = "default";
391 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
392 status = "disabled";
393};
394
395&pwm3 {
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
398 status = "disabled";
399};
400
401&pwm4 {
402 pinctrl-names = "default", "state_dio";
403 pinctrl-0 = <&pinctrl_pwm4_backlight>;
404 pinctrl-1 = <&pinctrl_pwm4_dio>;
405 status = "okay";
406};
407
408&ssi1 {
409 status = "okay";
410};
411
412&ssi2 {
413 status = "okay";
414};
415
416&uart1 {
417 pinctrl-names = "default";
418 pinctrl-0 = <&pinctrl_uart1>;
419 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
420 status = "okay";
421};
422
423&uart2 {
424 pinctrl-names = "default";
425 pinctrl-0 = <&pinctrl_uart2>;
426 status = "okay";
427};
428
429&uart5 {
430 pinctrl-names = "default";
431 pinctrl-0 = <&pinctrl_uart5>;
432 status = "okay";
433};
434
435&usbotg {
436 vbus-supply = <®_usb_otg_vbus>;
437 pinctrl-names = "default";
438 pinctrl-0 = <&pinctrl_usbotg>;
439 disable-over-current;
440 status = "okay";
441};
442
443&usbh1 {
444 vbus-supply = <®_usb_h1_vbus>;
445 status = "okay";
446};
447
448&usdhc3 {
449 pinctrl-names = "default", "state_100mhz", "state_200mhz";
450 pinctrl-0 = <&pinctrl_usdhc3>;
451 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
452 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
453 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
454 vmmc-supply = <®_3p3v>;
455 no-1-8-v; /* firmware will remove if board revision supports */
456 status = "okay";
457};
458
459&wdog1 {
460 status = "disabled";
461};
462
463&wdog2 {
464 pinctrl-names = "default";
465 pinctrl-0 = <&pinctrl_wdog>;
466 fsl,ext-reset-output;
467 status = "okay";
468};
469
470&iomuxc {
471 pinctrl_audmux: audmuxgrp {
472 fsl,pins = <
473 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
474 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
475 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
476 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
477 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
478 >;
479 };
480
481 pinctrl_enet: enetgrp {
482 fsl,pins = <
483 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
484 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
485 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
486 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
487 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
488 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
489 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
490 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
491 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
492 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
493 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
494 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
495 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
496 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
497 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
498 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
499 >;
500 };
501
502 pinctrl_ecspi2: escpi2grp {
503 fsl,pins = <
504 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
505 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
506 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
507 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
508 >;
509 };
510
511 pinctrl_flexcan1: flexcan1grp {
512 fsl,pins = <
513 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
514 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
515 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
516 >;
517 };
518
519 pinctrl_gpio_leds: gpioledsgrp {
520 fsl,pins = <
521 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
522 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
523 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
524 >;
525 };
526
527 pinctrl_gpmi_nand: gpminandgrp {
528 fsl,pins = <
529 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
530 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
531 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
532 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
533 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
534 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
535 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
536 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
537 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
538 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
539 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
540 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
541 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
542 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
543 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
544 >;
545 };
546
547 pinctrl_i2c1: i2c1grp {
548 fsl,pins = <
549 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
550 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
551 >;
552 };
553
554 pinctrl_i2c2: i2c2grp {
555 fsl,pins = <
556 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
557 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
558 >;
559 };
560
561 pinctrl_i2c3: i2c3grp {
562 fsl,pins = <
563 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
564 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
565 >;
566 };
567
568 pinctrl_pcie: pciegrp {
569 fsl,pins = <
570 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
571 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
572 >;
573 };
574
575 pinctrl_pps: ppsgrp {
576 fsl,pins = <
577 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
578 >;
579 };
580
581 pinctrl_pwm1: pwm1grp {
582 fsl,pins = <
583 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
584 >;
585 };
586
587 pinctrl_pwm2: pwm2grp {
588 fsl,pins = <
589 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
590 >;
591 };
592
593 pinctrl_pwm3: pwm3grp {
594 fsl,pins = <
595 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
596 >;
597 };
598
599 pinctrl_pwm4_backlight: pwm4grpbacklight {
600 fsl,pins = <
601 /* LVDS_PWM J6.5 */
602 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
603 >;
604 };
605
606 pinctrl_pwm4_dio: pwm4grpdio {
607 fsl,pins = <
608 /* DIO3 J16.4 */
609 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
610 >;
611 };
612
613 pinctrl_uart1: uart1grp {
614 fsl,pins = <
615 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
616 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
617 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
618 >;
619 };
620
621 pinctrl_uart2: uart2grp {
622 fsl,pins = <
623 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
624 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
625 >;
626 };
627
628 pinctrl_uart5: uart5grp {
629 fsl,pins = <
630 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
631 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
632 >;
633 };
634
635 pinctrl_usbotg: usbotggrp {
636 fsl,pins = <
637 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
638 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
639 >;
640 };
641
642 pinctrl_usdhc3: usdhc3grp {
643 fsl,pins = <
644 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
645 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
646 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
647 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
648 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
649 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
650 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
651 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
652 >;
653 };
654
655 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
656 fsl,pins = <
657 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
658 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
659 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
660 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
661 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
662 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
663 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
664 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
665 >;
666 };
667
668 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
669 fsl,pins = <
670 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
671 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
672 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
673 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
674 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
675 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
676 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
677 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
678 >;
679 };
680
681 pinctrl_wdog: wdoggrp {
682 fsl,pins = <
683 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
684 >;
685 };
686};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8#include <dt-bindings/sound/fsl-imx-audmux.h>
9
10/ {
11 /* these are used by bootloader for disabling nodes */
12 aliases {
13 led0 = &led0;
14 led1 = &led1;
15 led2 = &led2;
16 nand = &gpmi;
17 ssi0 = &ssi1;
18 usb0 = &usbh1;
19 usb1 = &usbotg;
20 };
21
22 chosen {
23 bootargs = "console=ttymxc1,115200";
24 };
25
26 backlight {
27 compatible = "pwm-backlight";
28 pwms = <&pwm4 0 5000000>;
29 brightness-levels = <0 4 8 16 32 64 128 255>;
30 default-brightness-level = <7>;
31 };
32
33 gpio-keys {
34 compatible = "gpio-keys";
35 #address-cells = <1>;
36 #size-cells = <0>;
37
38 user-pb {
39 label = "user_pb";
40 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
41 linux,code = <BTN_0>;
42 };
43
44 user-pb1x {
45 label = "user_pb1x";
46 linux,code = <BTN_1>;
47 interrupt-parent = <&gsc>;
48 interrupts = <0>;
49 };
50
51 key-erased {
52 label = "key-erased";
53 linux,code = <BTN_2>;
54 interrupt-parent = <&gsc>;
55 interrupts = <1>;
56 };
57
58 eeprom-wp {
59 label = "eeprom_wp";
60 linux,code = <BTN_3>;
61 interrupt-parent = <&gsc>;
62 interrupts = <2>;
63 };
64
65 tamper {
66 label = "tamper";
67 linux,code = <BTN_4>;
68 interrupt-parent = <&gsc>;
69 interrupts = <5>;
70 };
71
72 switch-hold {
73 label = "switch_hold";
74 linux,code = <BTN_5>;
75 interrupt-parent = <&gsc>;
76 interrupts = <7>;
77 };
78 };
79
80 leds {
81 compatible = "gpio-leds";
82 pinctrl-names = "default";
83 pinctrl-0 = <&pinctrl_gpio_leds>;
84
85 led0: user1 {
86 label = "user1";
87 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
88 default-state = "on";
89 linux,default-trigger = "heartbeat";
90 };
91
92 led1: user2 {
93 label = "user2";
94 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
95 default-state = "off";
96 };
97
98 led2: user3 {
99 label = "user3";
100 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
101 default-state = "off";
102 };
103 };
104
105 memory@10000000 {
106 device_type = "memory";
107 reg = <0x10000000 0x40000000>;
108 };
109
110 pps {
111 compatible = "pps-gpio";
112 pinctrl-names = "default";
113 pinctrl-0 = <&pinctrl_pps>;
114 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
115 status = "okay";
116 };
117
118 regulators {
119 compatible = "simple-bus";
120 #address-cells = <1>;
121 #size-cells = <0>;
122
123 reg_1p0v: regulator@0 {
124 compatible = "regulator-fixed";
125 reg = <0>;
126 regulator-name = "1P0V";
127 regulator-min-microvolt = <1000000>;
128 regulator-max-microvolt = <1000000>;
129 regulator-always-on;
130 };
131
132 reg_3p3v: regulator@1 {
133 compatible = "regulator-fixed";
134 reg = <1>;
135 regulator-name = "3P3V";
136 regulator-min-microvolt = <3300000>;
137 regulator-max-microvolt = <3300000>;
138 regulator-always-on;
139 };
140
141 reg_usb_h1_vbus: regulator@2 {
142 compatible = "regulator-fixed";
143 reg = <2>;
144 regulator-name = "usb_h1_vbus";
145 regulator-min-microvolt = <5000000>;
146 regulator-max-microvolt = <5000000>;
147 regulator-always-on;
148 };
149
150 reg_usb_otg_vbus: regulator@3 {
151 compatible = "regulator-fixed";
152 reg = <3>;
153 regulator-name = "usb_otg_vbus";
154 regulator-min-microvolt = <5000000>;
155 regulator-max-microvolt = <5000000>;
156 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
157 enable-active-high;
158 };
159 };
160
161 sound-analog {
162 compatible = "fsl,imx6q-ventana-sgtl5000",
163 "fsl,imx-audio-sgtl5000";
164 model = "sgtl5000-audio";
165 ssi-controller = <&ssi1>;
166 audio-codec = <&sgtl5000>;
167 audio-routing =
168 "MIC_IN", "Mic Jack",
169 "Mic Jack", "Mic Bias",
170 "Headphone Jack", "HP_OUT";
171 mux-int-port = <1>;
172 mux-ext-port = <4>;
173 };
174};
175
176&audmux {
177 pinctrl-names = "default";
178 pinctrl-0 = <&pinctrl_audmux>; /* AUD4<->sgtl5000 */
179 status = "okay";
180
181 ssi2 {
182 fsl,audmux-port = <1>;
183 fsl,port-config = <
184 (IMX_AUDMUX_V2_PTCR_TFSDIR |
185 IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */
186 IMX_AUDMUX_V2_PTCR_TCLKDIR |
187 IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */
188 IMX_AUDMUX_V2_PTCR_SYN)
189 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
190 >;
191 };
192
193 aud5 {
194 fsl,audmux-port = <4>;
195 fsl,port-config = <
196 IMX_AUDMUX_V2_PTCR_SYN
197 IMX_AUDMUX_V2_PDCR_RXDSEL(1)>;
198 };
199};
200
201&can1 {
202 pinctrl-names = "default";
203 pinctrl-0 = <&pinctrl_flexcan1>;
204 status = "okay";
205};
206
207&clks {
208 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
209 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
210 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
211 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
212};
213
214&ecspi2 {
215 cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
216 pinctrl-names = "default";
217 pinctrl-0 = <&pinctrl_ecspi2>;
218 status = "okay";
219};
220
221&fec {
222 pinctrl-names = "default";
223 pinctrl-0 = <&pinctrl_enet>;
224 phy-mode = "rgmii-id";
225 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
226 status = "okay";
227};
228
229&gpmi {
230 pinctrl-names = "default";
231 pinctrl-0 = <&pinctrl_gpmi_nand>;
232 status = "okay";
233};
234
235&hdmi {
236 ddc-i2c-bus = <&i2c3>;
237 status = "okay";
238};
239
240&i2c1 {
241 clock-frequency = <100000>;
242 pinctrl-names = "default";
243 pinctrl-0 = <&pinctrl_i2c1>;
244 status = "okay";
245
246 gsc: gsc@20 {
247 compatible = "gw,gsc";
248 reg = <0x20>;
249 interrupt-parent = <&gpio1>;
250 interrupts = <4 GPIO_ACTIVE_LOW>;
251 interrupt-controller;
252 #interrupt-cells = <1>;
253 #address-cells = <1>;
254 #size-cells = <0>;
255
256 adc {
257 compatible = "gw,gsc-adc";
258 #address-cells = <1>;
259 #size-cells = <0>;
260
261 channel@0 {
262 gw,mode = <0>;
263 reg = <0x00>;
264 label = "temp";
265 };
266
267 channel@2 {
268 gw,mode = <1>;
269 reg = <0x02>;
270 label = "vdd_vin";
271 };
272
273 channel@5 {
274 gw,mode = <1>;
275 reg = <0x05>;
276 label = "vdd_3p3";
277 };
278
279 channel@8 {
280 gw,mode = <1>;
281 reg = <0x08>;
282 label = "vdd_bat";
283 };
284
285 channel@b {
286 gw,mode = <1>;
287 reg = <0x0b>;
288 label = "vdd_5p0";
289 };
290
291 channel@e {
292 gw,mode = <1>;
293 reg = <0xe>;
294 label = "vdd_arm";
295 };
296
297 channel@11 {
298 gw,mode = <1>;
299 reg = <0x11>;
300 label = "vdd_soc";
301 };
302
303 channel@14 {
304 gw,mode = <1>;
305 reg = <0x14>;
306 label = "vdd_3p0";
307 };
308
309 channel@17 {
310 gw,mode = <1>;
311 reg = <0x17>;
312 label = "vdd_1p5";
313 };
314
315 channel@1d {
316 gw,mode = <1>;
317 reg = <0x1d>;
318 label = "vdd_1p8";
319 };
320
321 channel@20 {
322 gw,mode = <1>;
323 reg = <0x20>;
324 label = "vdd_1p0";
325 };
326
327 channel@23 {
328 gw,mode = <1>;
329 reg = <0x23>;
330 label = "vdd_2p5";
331 };
332
333 channel@26 {
334 gw,mode = <1>;
335 reg = <0x26>;
336 label = "vdd_gps";
337 };
338 };
339
340 fan-controller@2c {
341 compatible = "gw,gsc-fan";
342 #address-cells = <1>;
343 #size-cells = <0>;
344 reg = <0x2c>;
345 };
346 };
347
348 gsc_gpio: gpio@23 {
349 compatible = "nxp,pca9555";
350 reg = <0x23>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-parent = <&gsc>;
354 interrupts = <4>;
355 };
356
357 eeprom1: eeprom@50 {
358 compatible = "atmel,24c02";
359 reg = <0x50>;
360 pagesize = <16>;
361 };
362
363 eeprom2: eeprom@51 {
364 compatible = "atmel,24c02";
365 reg = <0x51>;
366 pagesize = <16>;
367 };
368
369 eeprom3: eeprom@52 {
370 compatible = "atmel,24c02";
371 reg = <0x52>;
372 pagesize = <16>;
373 };
374
375 eeprom4: eeprom@53 {
376 compatible = "atmel,24c02";
377 reg = <0x53>;
378 pagesize = <16>;
379 };
380
381 rtc: ds1672@68 {
382 compatible = "dallas,ds1672";
383 reg = <0x68>;
384 };
385};
386
387&i2c2 {
388 clock-frequency = <100000>;
389 pinctrl-names = "default";
390 pinctrl-0 = <&pinctrl_i2c2>;
391 status = "okay";
392
393 pmic: pfuze100@8 {
394 compatible = "fsl,pfuze100";
395 reg = <0x08>;
396
397 regulators {
398 sw1a_reg: sw1ab {
399 regulator-min-microvolt = <300000>;
400 regulator-max-microvolt = <1875000>;
401 regulator-boot-on;
402 regulator-always-on;
403 regulator-ramp-delay = <6250>;
404 };
405
406 sw1c_reg: sw1c {
407 regulator-min-microvolt = <300000>;
408 regulator-max-microvolt = <1875000>;
409 regulator-boot-on;
410 regulator-always-on;
411 regulator-ramp-delay = <6250>;
412 };
413
414 sw2_reg: sw2 {
415 regulator-min-microvolt = <800000>;
416 regulator-max-microvolt = <3950000>;
417 regulator-boot-on;
418 regulator-always-on;
419 };
420
421 sw3a_reg: sw3a {
422 regulator-min-microvolt = <400000>;
423 regulator-max-microvolt = <1975000>;
424 regulator-boot-on;
425 regulator-always-on;
426 };
427
428 sw3b_reg: sw3b {
429 regulator-min-microvolt = <400000>;
430 regulator-max-microvolt = <1975000>;
431 regulator-boot-on;
432 regulator-always-on;
433 };
434
435 sw4_reg: sw4 {
436 regulator-min-microvolt = <800000>;
437 regulator-max-microvolt = <3300000>;
438 };
439
440 swbst_reg: swbst {
441 regulator-min-microvolt = <5000000>;
442 regulator-max-microvolt = <5150000>;
443 regulator-boot-on;
444 regulator-always-on;
445 };
446
447 snvs_reg: vsnvs {
448 regulator-min-microvolt = <1000000>;
449 regulator-max-microvolt = <3000000>;
450 regulator-boot-on;
451 regulator-always-on;
452 };
453
454 vref_reg: vrefddr {
455 regulator-boot-on;
456 regulator-always-on;
457 };
458
459 vgen1_reg: vgen1 {
460 regulator-min-microvolt = <800000>;
461 regulator-max-microvolt = <1550000>;
462 };
463
464 vgen2_reg: vgen2 {
465 regulator-min-microvolt = <800000>;
466 regulator-max-microvolt = <1550000>;
467 };
468
469 vgen3_reg: vgen3 {
470 regulator-min-microvolt = <1800000>;
471 regulator-max-microvolt = <3300000>;
472 };
473
474 vgen4_reg: vgen4 {
475 regulator-min-microvolt = <1800000>;
476 regulator-max-microvolt = <3300000>;
477 regulator-always-on;
478 };
479
480 vgen5_reg: vgen5 {
481 regulator-min-microvolt = <1800000>;
482 regulator-max-microvolt = <3300000>;
483 regulator-always-on;
484 };
485
486 vgen6_reg: vgen6 {
487 regulator-min-microvolt = <1800000>;
488 regulator-max-microvolt = <3300000>;
489 regulator-always-on;
490 };
491 };
492 };
493};
494
495&i2c3 {
496 clock-frequency = <100000>;
497 pinctrl-names = "default";
498 pinctrl-0 = <&pinctrl_i2c3>;
499 status = "okay";
500
501 sgtl5000: audio-codec@a {
502 compatible = "fsl,sgtl5000";
503 reg = <0x0a>;
504 clocks = <&clks IMX6QDL_CLK_CKO>;
505 VDDA-supply = <&sw4_reg>;
506 VDDIO-supply = <®_3p3v>;
507 };
508
509 touchscreen: egalax_ts@4 {
510 compatible = "eeti,egalax_ts";
511 reg = <0x04>;
512 interrupt-parent = <&gpio7>;
513 interrupts = <12 2>;
514 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
515 };
516
517 accel@1e {
518 compatible = "nxp,fxos8700";
519 reg = <0x1e>;
520 };
521};
522
523&ldb {
524 status = "okay";
525
526 lvds-channel@0 {
527 fsl,data-mapping = "spwg";
528 fsl,data-width = <18>;
529 status = "okay";
530
531 display-timings {
532 native-mode = <&timing0>;
533 timing0: hsd100pxn1 {
534 clock-frequency = <65000000>;
535 hactive = <1024>;
536 vactive = <768>;
537 hback-porch = <220>;
538 hfront-porch = <40>;
539 vback-porch = <21>;
540 vfront-porch = <7>;
541 hsync-len = <60>;
542 vsync-len = <10>;
543 };
544 };
545 };
546};
547
548&pcie {
549 pinctrl-names = "default";
550 pinctrl-0 = <&pinctrl_pcie>;
551 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
552 status = "okay";
553};
554
555&pwm1 {
556 pinctrl-names = "default";
557 pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
558 status = "disabled";
559};
560
561&pwm2 {
562 pinctrl-names = "default";
563 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
564 status = "disabled";
565};
566
567&pwm3 {
568 pinctrl-names = "default";
569 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
570 status = "disabled";
571};
572
573&pwm4 {
574 #pwm-cells = <2>;
575 pinctrl-names = "default", "state_dio";
576 pinctrl-0 = <&pinctrl_pwm4_backlight>;
577 pinctrl-1 = <&pinctrl_pwm4_dio>;
578 status = "okay";
579};
580
581&ssi1 {
582 status = "okay";
583};
584
585&ssi2 {
586 status = "okay";
587};
588
589&uart1 {
590 pinctrl-names = "default";
591 pinctrl-0 = <&pinctrl_uart1>;
592 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
593 status = "okay";
594};
595
596&uart2 {
597 pinctrl-names = "default";
598 pinctrl-0 = <&pinctrl_uart2>;
599 status = "okay";
600};
601
602&uart5 {
603 pinctrl-names = "default";
604 pinctrl-0 = <&pinctrl_uart5>;
605 status = "okay";
606};
607
608&usbotg {
609 vbus-supply = <®_usb_otg_vbus>;
610 pinctrl-names = "default";
611 pinctrl-0 = <&pinctrl_usbotg>;
612 disable-over-current;
613 status = "okay";
614};
615
616&usbh1 {
617 vbus-supply = <®_usb_h1_vbus>;
618 status = "okay";
619};
620
621&usdhc3 {
622 pinctrl-names = "default", "state_100mhz", "state_200mhz";
623 pinctrl-0 = <&pinctrl_usdhc3>;
624 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
625 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
626 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
627 vmmc-supply = <®_3p3v>;
628 no-1-8-v; /* firmware will remove if board revision supports */
629 status = "okay";
630};
631
632&wdog1 {
633 status = "disabled";
634};
635
636&wdog2 {
637 pinctrl-names = "default";
638 pinctrl-0 = <&pinctrl_wdog>;
639 fsl,ext-reset-output;
640 status = "okay";
641};
642
643&iomuxc {
644 pinctrl_audmux: audmuxgrp {
645 fsl,pins = <
646 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
647 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
648 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
649 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
650 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
651 MX6QDL_PAD_EIM_D25__AUD5_RXC 0x130b0
652 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
653 MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x130b0
654 >;
655 };
656
657 pinctrl_enet: enetgrp {
658 fsl,pins = <
659 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
660 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
661 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
662 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
663 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
664 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
665 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
666 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
667 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
668 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
669 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
670 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
671 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
672 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
673 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
674 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
675 >;
676 };
677
678 pinctrl_ecspi2: escpi2grp {
679 fsl,pins = <
680 MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
681 MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
682 MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
683 MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
684 >;
685 };
686
687 pinctrl_flexcan1: flexcan1grp {
688 fsl,pins = <
689 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
690 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
691 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0 /* CAN_STBY */
692 >;
693 };
694
695 pinctrl_gpio_leds: gpioledsgrp {
696 fsl,pins = <
697 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
698 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
699 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
700 >;
701 };
702
703 pinctrl_gpmi_nand: gpminandgrp {
704 fsl,pins = <
705 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
706 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
707 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
708 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
709 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
710 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
711 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
712 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
713 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
714 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
715 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
716 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
717 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
718 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
719 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
720 >;
721 };
722
723 pinctrl_i2c1: i2c1grp {
724 fsl,pins = <
725 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
726 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
727 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
728 >;
729 };
730
731 pinctrl_i2c2: i2c2grp {
732 fsl,pins = <
733 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
734 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
735 >;
736 };
737
738 pinctrl_i2c3: i2c3grp {
739 fsl,pins = <
740 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
741 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
742 >;
743 };
744
745 pinctrl_pcie: pciegrp {
746 fsl,pins = <
747 MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0 /* PCIE IRQ */
748 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE RST */
749 >;
750 };
751
752 pinctrl_pps: ppsgrp {
753 fsl,pins = <
754 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
755 >;
756 };
757
758 pinctrl_pwm1: pwm1grp {
759 fsl,pins = <
760 MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
761 >;
762 };
763
764 pinctrl_pwm2: pwm2grp {
765 fsl,pins = <
766 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
767 >;
768 };
769
770 pinctrl_pwm3: pwm3grp {
771 fsl,pins = <
772 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
773 >;
774 };
775
776 pinctrl_pwm4_backlight: pwm4grpbacklight {
777 fsl,pins = <
778 /* LVDS_PWM J6.5 */
779 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
780 >;
781 };
782
783 pinctrl_pwm4_dio: pwm4grpdio {
784 fsl,pins = <
785 /* DIO3 J16.4 */
786 MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
787 >;
788 };
789
790 pinctrl_uart1: uart1grp {
791 fsl,pins = <
792 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
793 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
794 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
795 >;
796 };
797
798 pinctrl_uart2: uart2grp {
799 fsl,pins = <
800 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
801 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
802 >;
803 };
804
805 pinctrl_uart5: uart5grp {
806 fsl,pins = <
807 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
808 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
809 >;
810 };
811
812 pinctrl_usbotg: usbotggrp {
813 fsl,pins = <
814 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
815 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* PWR_EN */
816 >;
817 };
818
819 pinctrl_usdhc3: usdhc3grp {
820 fsl,pins = <
821 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
822 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
823 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
824 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
825 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
826 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
827 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
828 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
829 >;
830 };
831
832 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
833 fsl,pins = <
834 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
835 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
836 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
837 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
838 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
839 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
840 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
841 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
842 >;
843 };
844
845 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
846 fsl,pins = <
847 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
848 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
849 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
850 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
851 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
852 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
853 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
854 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
855 >;
856 };
857
858 pinctrl_wdog: wdoggrp {
859 fsl,pins = <
860 MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
861 >;
862 };
863};