Loading...
1/*
2 * Copyright 2013 Gateworks Corporation
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13
14/ {
15 /* these are used by bootloader for disabling nodes */
16 aliases {
17 led0 = &led0;
18 led1 = &led1;
19 led2 = &led2;
20 nand = &gpmi;
21 ssi0 = &ssi1;
22 usb0 = &usbh1;
23 usb1 = &usbotg;
24 };
25
26 chosen {
27 bootargs = "console=ttymxc1,115200";
28 };
29
30 backlight {
31 compatible = "pwm-backlight";
32 pwms = <&pwm4 0 5000000>;
33 brightness-levels = <0 4 8 16 32 64 128 255>;
34 default-brightness-level = <7>;
35 };
36
37 leds {
38 compatible = "gpio-leds";
39 pinctrl-names = "default";
40 pinctrl-0 = <&pinctrl_gpio_leds>;
41
42 led0: user1 {
43 label = "user1";
44 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
45 default-state = "on";
46 linux,default-trigger = "heartbeat";
47 };
48
49 led1: user2 {
50 label = "user2";
51 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
52 default-state = "off";
53 };
54
55 led2: user3 {
56 label = "user3";
57 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
58 default-state = "off";
59 };
60 };
61
62 memory@10000000 {
63 reg = <0x10000000 0x20000000>;
64 };
65
66 pps {
67 compatible = "pps-gpio";
68 pinctrl-names = "default";
69 pinctrl-0 = <&pinctrl_pps>;
70 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
71 status = "okay";
72 };
73
74 reg_1p0v: regulator-1p0v {
75 compatible = "regulator-fixed";
76 regulator-name = "1P0V";
77 regulator-min-microvolt = <1000000>;
78 regulator-max-microvolt = <1000000>;
79 regulator-always-on;
80 };
81
82 reg_3p3v: regulator-3p3v {
83 compatible = "regulator-fixed";
84 regulator-name = "3P3V";
85 regulator-min-microvolt = <3300000>;
86 regulator-max-microvolt = <3300000>;
87 regulator-always-on;
88 };
89
90 reg_5p0v: regulator-5p0v {
91 compatible = "regulator-fixed";
92 regulator-name = "5P0V";
93 regulator-min-microvolt = <5000000>;
94 regulator-max-microvolt = <5000000>;
95 regulator-always-on;
96 };
97
98 reg_usb_otg_vbus: regulator-usb-otg-vbus {
99 compatible = "regulator-fixed";
100 regulator-name = "usb_otg_vbus";
101 regulator-min-microvolt = <5000000>;
102 regulator-max-microvolt = <5000000>;
103 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
104 enable-active-high;
105 };
106
107 sound {
108 compatible = "fsl,imx6q-ventana-sgtl5000",
109 "fsl,imx-audio-sgtl5000";
110 model = "sgtl5000-audio";
111 ssi-controller = <&ssi1>;
112 audio-codec = <&codec>;
113 audio-routing =
114 "MIC_IN", "Mic Jack",
115 "Mic Jack", "Mic Bias",
116 "Headphone Jack", "HP_OUT";
117 mux-int-port = <1>;
118 mux-ext-port = <4>;
119 };
120};
121
122&audmux {
123 pinctrl-names = "default";
124 pinctrl-0 = <&pinctrl_audmux>;
125 status = "okay";
126};
127
128&can1 {
129 pinctrl-names = "default";
130 pinctrl-0 = <&pinctrl_flexcan1>;
131 status = "okay";
132};
133
134&clks {
135 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
136 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
137 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
138 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
139};
140
141&ecspi3 {
142 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
143 pinctrl-names = "default";
144 pinctrl-0 = <&pinctrl_ecspi3>;
145 status = "okay";
146};
147
148&fec {
149 pinctrl-names = "default";
150 pinctrl-0 = <&pinctrl_enet>;
151 phy-mode = "rgmii-id";
152 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
153 status = "okay";
154};
155
156&gpmi {
157 pinctrl-names = "default";
158 pinctrl-0 = <&pinctrl_gpmi_nand>;
159 status = "okay";
160};
161
162&hdmi {
163 ddc-i2c-bus = <&i2c3>;
164 status = "okay";
165};
166
167&i2c1 {
168 clock-frequency = <100000>;
169 pinctrl-names = "default";
170 pinctrl-0 = <&pinctrl_i2c1>;
171 status = "okay";
172
173 eeprom1: eeprom@50 {
174 compatible = "atmel,24c02";
175 reg = <0x50>;
176 pagesize = <16>;
177 };
178
179 eeprom2: eeprom@51 {
180 compatible = "atmel,24c02";
181 reg = <0x51>;
182 pagesize = <16>;
183 };
184
185 eeprom3: eeprom@52 {
186 compatible = "atmel,24c02";
187 reg = <0x52>;
188 pagesize = <16>;
189 };
190
191 eeprom4: eeprom@53 {
192 compatible = "atmel,24c02";
193 reg = <0x53>;
194 pagesize = <16>;
195 };
196
197 gpio: pca9555@23 {
198 compatible = "nxp,pca9555";
199 reg = <0x23>;
200 gpio-controller;
201 #gpio-cells = <2>;
202 };
203
204 rtc: ds1672@68 {
205 compatible = "dallas,ds1672";
206 reg = <0x68>;
207 };
208};
209
210&i2c2 {
211 clock-frequency = <100000>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_i2c2>;
214 status = "okay";
215
216 ltc3676: pmic@3c {
217 compatible = "lltc,ltc3676";
218 reg = <0x3c>;
219 pinctrl-names = "default";
220 pinctrl-0 = <&pinctrl_pmic>;
221 interrupt-parent = <&gpio1>;
222 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
223
224 regulators {
225 /* VDD_SOC (1+R1/R2 = 1.635) */
226 reg_vdd_soc: sw1 {
227 regulator-name = "vddsoc";
228 regulator-min-microvolt = <674400>;
229 regulator-max-microvolt = <1308000>;
230 lltc,fb-voltage-divider = <127000 200000>;
231 regulator-ramp-delay = <7000>;
232 regulator-boot-on;
233 regulator-always-on;
234 };
235
236 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
237 reg_1p8v: sw2 {
238 regulator-name = "vdd1p8";
239 regulator-min-microvolt = <1033310>;
240 regulator-max-microvolt = <2004000>;
241 lltc,fb-voltage-divider = <301000 200000>;
242 regulator-ramp-delay = <7000>;
243 regulator-boot-on;
244 regulator-always-on;
245 };
246
247 /* VDD_ARM (1+R1/R2 = 1.635) */
248 reg_vdd_arm: sw3 {
249 regulator-name = "vddarm";
250 regulator-min-microvolt = <674400>;
251 regulator-max-microvolt = <1308000>;
252 lltc,fb-voltage-divider = <127000 200000>;
253 regulator-ramp-delay = <7000>;
254 regulator-boot-on;
255 regulator-always-on;
256 };
257
258 /* VDD_DDR (1+R1/R2 = 2.105) */
259 reg_vdd_ddr: sw4 {
260 regulator-name = "vddddr";
261 regulator-min-microvolt = <868310>;
262 regulator-max-microvolt = <1684000>;
263 lltc,fb-voltage-divider = <221000 200000>;
264 regulator-ramp-delay = <7000>;
265 regulator-boot-on;
266 regulator-always-on;
267 };
268
269 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
270 reg_2p5v: ldo2 {
271 regulator-name = "vdd2p5";
272 regulator-min-microvolt = <2490375>;
273 regulator-max-microvolt = <2490375>;
274 lltc,fb-voltage-divider = <487000 200000>;
275 regulator-boot-on;
276 regulator-always-on;
277 };
278
279 /* VDD_AUD_1P8: Audio codec */
280 reg_aud_1p8v: ldo3 {
281 regulator-name = "vdd1p8";
282 regulator-min-microvolt = <1800000>;
283 regulator-max-microvolt = <1800000>;
284 regulator-boot-on;
285 };
286
287 /* VDD_HIGH (1+R1/R2 = 4.17) */
288 reg_3p0v: ldo4 {
289 regulator-name = "vdd3p0";
290 regulator-min-microvolt = <3023250>;
291 regulator-max-microvolt = <3023250>;
292 lltc,fb-voltage-divider = <634000 200000>;
293 regulator-boot-on;
294 regulator-always-on;
295 };
296 };
297 };
298};
299
300&i2c3 {
301 clock-frequency = <100000>;
302 pinctrl-names = "default";
303 pinctrl-0 = <&pinctrl_i2c3>;
304 status = "okay";
305
306 codec: sgtl5000@a {
307 compatible = "fsl,sgtl5000";
308 reg = <0x0a>;
309 clocks = <&clks IMX6QDL_CLK_CKO>;
310 VDDA-supply = <®_1p8v>;
311 VDDIO-supply = <®_3p3v>;
312 };
313
314 touchscreen: egalax_ts@4 {
315 compatible = "eeti,egalax_ts";
316 reg = <0x04>;
317 interrupt-parent = <&gpio7>;
318 interrupts = <12 2>;
319 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
320 };
321};
322
323&ldb {
324 status = "okay";
325
326 lvds-channel@0 {
327 fsl,data-mapping = "spwg";
328 fsl,data-width = <18>;
329 status = "okay";
330
331 display-timings {
332 native-mode = <&timing0>;
333 timing0: hsd100pxn1 {
334 clock-frequency = <65000000>;
335 hactive = <1024>;
336 vactive = <768>;
337 hback-porch = <220>;
338 hfront-porch = <40>;
339 vback-porch = <21>;
340 vfront-porch = <7>;
341 hsync-len = <60>;
342 vsync-len = <10>;
343 };
344 };
345 };
346};
347
348&pcie {
349 pinctrl-names = "default";
350 pinctrl-0 = <&pinctrl_pcie>;
351 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
352 status = "okay";
353};
354
355&pwm2 {
356 pinctrl-names = "default";
357 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
358 status = "disabled";
359};
360
361&pwm3 {
362 pinctrl-names = "default";
363 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
364 status = "disabled";
365};
366
367&pwm4 {
368 pinctrl-names = "default";
369 pinctrl-0 = <&pinctrl_pwm4>;
370 status = "okay";
371};
372
373&ssi1 {
374 status = "okay";
375};
376
377&uart1 {
378 pinctrl-names = "default";
379 pinctrl-0 = <&pinctrl_uart1>;
380 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
381 status = "okay";
382};
383
384&uart2 {
385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_uart2>;
387 status = "okay";
388};
389
390&uart5 {
391 pinctrl-names = "default";
392 pinctrl-0 = <&pinctrl_uart5>;
393 status = "okay";
394};
395
396&usbotg {
397 vbus-supply = <®_usb_otg_vbus>;
398 pinctrl-names = "default";
399 pinctrl-0 = <&pinctrl_usbotg>;
400 disable-over-current;
401 status = "okay";
402};
403
404&usbh1 {
405 status = "okay";
406};
407
408&usdhc3 {
409 pinctrl-names = "default", "state_100mhz", "state_200mhz";
410 pinctrl-0 = <&pinctrl_usdhc3>;
411 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
412 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
413 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
414 vmmc-supply = <®_3p3v>;
415 no-1-8-v; /* firmware will remove if board revision supports */
416 status = "okay";
417};
418
419&wdog1 {
420 pinctrl-names = "default";
421 pinctrl-0 = <&pinctrl_wdog>;
422 fsl,ext-reset-output;
423};
424
425&iomuxc {
426 pinctrl_audmux: audmuxgrp {
427 fsl,pins = <
428 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
429 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
430 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
431 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
432 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
433 >;
434 };
435
436 pinctrl_ecspi3: escpi3grp {
437 fsl,pins = <
438 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
439 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
440 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
441 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
442 >;
443 };
444
445 pinctrl_enet: enetgrp {
446 fsl,pins = <
447 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
448 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
449 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
450 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
451 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
452 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
453 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
454 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
455 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
456 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
457 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
458 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
459 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
460 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
461 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
462 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
463 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
464 >;
465 };
466
467 pinctrl_flexcan1: flexcan1grp {
468 fsl,pins = <
469 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
470 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
471 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
472 >;
473 };
474
475 pinctrl_gpio_leds: gpioledsgrp {
476 fsl,pins = <
477 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
478 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
479 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
480 >;
481 };
482
483 pinctrl_gpmi_nand: gpminandgrp {
484 fsl,pins = <
485 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
486 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
487 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
488 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
489 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
490 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
491 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
492 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
493 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
494 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
495 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
496 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
497 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
498 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
499 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
500 >;
501 };
502
503 pinctrl_i2c1: i2c1grp {
504 fsl,pins = <
505 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
506 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
507 >;
508 };
509
510 pinctrl_i2c2: i2c2grp {
511 fsl,pins = <
512 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
513 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
514 >;
515 };
516
517 pinctrl_i2c3: i2c3grp {
518 fsl,pins = <
519 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
520 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
521 >;
522 };
523
524 pinctrl_pcie: pciegrp {
525 fsl,pins = <
526 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
527 >;
528 };
529
530 pinctrl_pmic: pmicgrp {
531 fsl,pins = <
532 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
533 >;
534 };
535
536 pinctrl_pps: ppsgrp {
537 fsl,pins = <
538 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
539 >;
540 };
541
542 pinctrl_pwm2: pwm2grp {
543 fsl,pins = <
544 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
545 >;
546 };
547
548 pinctrl_pwm3: pwm3grp {
549 fsl,pins = <
550 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
551 >;
552 };
553
554 pinctrl_pwm4: pwm4grp {
555 fsl,pins = <
556 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
557 >;
558 };
559
560 pinctrl_uart1: uart1grp {
561 fsl,pins = <
562 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
563 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
564 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
565 >;
566 };
567
568 pinctrl_uart2: uart2grp {
569 fsl,pins = <
570 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
571 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
572 >;
573 };
574
575 pinctrl_uart5: uart5grp {
576 fsl,pins = <
577 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
578 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
579 >;
580 };
581
582 pinctrl_usbotg: usbotggrp {
583 fsl,pins = <
584 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
585 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
586 >;
587 };
588
589 pinctrl_usdhc3: usdhc3grp {
590 fsl,pins = <
591 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
592 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
593 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
594 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
595 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
596 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
597 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
598 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
599 >;
600 };
601
602 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
603 fsl,pins = <
604 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
605 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
606 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
607 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
608 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
609 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
610 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
611 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
612 >;
613 };
614
615 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
616 fsl,pins = <
617 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
618 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
619 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
620 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
621 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
622 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
623 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
624 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
625 >;
626 };
627
628 pinctrl_wdog: wdoggrp {
629 fsl,pins = <
630 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
631 >;
632 };
633};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Copyright 2013 Gateworks Corporation
4 */
5
6#include <dt-bindings/gpio/gpio.h>
7#include <dt-bindings/input/linux-event-codes.h>
8
9/ {
10 /* these are used by bootloader for disabling nodes */
11 aliases {
12 led0 = &led0;
13 led1 = &led1;
14 led2 = &led2;
15 nand = &gpmi;
16 ssi0 = &ssi1;
17 usb0 = &usbh1;
18 usb1 = &usbotg;
19 };
20
21 chosen {
22 bootargs = "console=ttymxc1,115200";
23 };
24
25 backlight {
26 compatible = "pwm-backlight";
27 pwms = <&pwm4 0 5000000>;
28 brightness-levels = <0 4 8 16 32 64 128 255>;
29 default-brightness-level = <7>;
30 };
31
32 gpio-keys {
33 compatible = "gpio-keys";
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 user-pb {
38 label = "user_pb";
39 gpios = <&gsc_gpio 0 GPIO_ACTIVE_LOW>;
40 linux,code = <BTN_0>;
41 };
42
43 user-pb1x {
44 label = "user_pb1x";
45 linux,code = <BTN_1>;
46 interrupt-parent = <&gsc>;
47 interrupts = <0>;
48 };
49
50 key-erased {
51 label = "key-erased";
52 linux,code = <BTN_2>;
53 interrupt-parent = <&gsc>;
54 interrupts = <1>;
55 };
56
57 eeprom-wp {
58 label = "eeprom_wp";
59 linux,code = <BTN_3>;
60 interrupt-parent = <&gsc>;
61 interrupts = <2>;
62 };
63
64 tamper {
65 label = "tamper";
66 linux,code = <BTN_4>;
67 interrupt-parent = <&gsc>;
68 interrupts = <5>;
69 };
70
71 switch-hold {
72 label = "switch_hold";
73 linux,code = <BTN_5>;
74 interrupt-parent = <&gsc>;
75 interrupts = <7>;
76 };
77 };
78
79 leds {
80 compatible = "gpio-leds";
81 pinctrl-names = "default";
82 pinctrl-0 = <&pinctrl_gpio_leds>;
83
84 led0: user1 {
85 label = "user1";
86 gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
87 default-state = "on";
88 linux,default-trigger = "heartbeat";
89 };
90
91 led1: user2 {
92 label = "user2";
93 gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
94 default-state = "off";
95 };
96
97 led2: user3 {
98 label = "user3";
99 gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
100 default-state = "off";
101 };
102 };
103
104 memory@10000000 {
105 device_type = "memory";
106 reg = <0x10000000 0x20000000>;
107 };
108
109 pps {
110 compatible = "pps-gpio";
111 pinctrl-names = "default";
112 pinctrl-0 = <&pinctrl_pps>;
113 gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
114 status = "okay";
115 };
116
117 reg_1p0v: regulator-1p0v {
118 compatible = "regulator-fixed";
119 regulator-name = "1P0V";
120 regulator-min-microvolt = <1000000>;
121 regulator-max-microvolt = <1000000>;
122 regulator-always-on;
123 };
124
125 reg_3p3v: regulator-3p3v {
126 compatible = "regulator-fixed";
127 regulator-name = "3P3V";
128 regulator-min-microvolt = <3300000>;
129 regulator-max-microvolt = <3300000>;
130 regulator-always-on;
131 };
132
133 reg_5p0v: regulator-5p0v {
134 compatible = "regulator-fixed";
135 regulator-name = "5P0V";
136 regulator-min-microvolt = <5000000>;
137 regulator-max-microvolt = <5000000>;
138 regulator-always-on;
139 };
140
141 reg_usb_otg_vbus: regulator-usb-otg-vbus {
142 compatible = "regulator-fixed";
143 regulator-name = "usb_otg_vbus";
144 regulator-min-microvolt = <5000000>;
145 regulator-max-microvolt = <5000000>;
146 gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
147 enable-active-high;
148 };
149
150 sound {
151 compatible = "fsl,imx6q-ventana-sgtl5000",
152 "fsl,imx-audio-sgtl5000";
153 model = "sgtl5000-audio";
154 ssi-controller = <&ssi1>;
155 audio-codec = <&codec>;
156 audio-routing =
157 "MIC_IN", "Mic Jack",
158 "Mic Jack", "Mic Bias",
159 "Headphone Jack", "HP_OUT";
160 mux-int-port = <1>;
161 mux-ext-port = <4>;
162 };
163};
164
165&audmux {
166 pinctrl-names = "default";
167 pinctrl-0 = <&pinctrl_audmux>;
168 status = "okay";
169};
170
171&can1 {
172 pinctrl-names = "default";
173 pinctrl-0 = <&pinctrl_flexcan1>;
174 status = "okay";
175};
176
177&clks {
178 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
179 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
180 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
181 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
182};
183
184&ecspi3 {
185 cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
186 pinctrl-names = "default";
187 pinctrl-0 = <&pinctrl_ecspi3>;
188 status = "okay";
189};
190
191&fec {
192 pinctrl-names = "default";
193 pinctrl-0 = <&pinctrl_enet>;
194 phy-mode = "rgmii-id";
195 phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
196 status = "okay";
197};
198
199&gpmi {
200 pinctrl-names = "default";
201 pinctrl-0 = <&pinctrl_gpmi_nand>;
202 status = "okay";
203};
204
205&hdmi {
206 ddc-i2c-bus = <&i2c3>;
207 status = "okay";
208};
209
210&i2c1 {
211 clock-frequency = <100000>;
212 pinctrl-names = "default";
213 pinctrl-0 = <&pinctrl_i2c1>;
214 status = "okay";
215
216 gsc: gsc@20 {
217 compatible = "gw,gsc";
218 reg = <0x20>;
219 interrupt-parent = <&gpio1>;
220 interrupts = <4 GPIO_ACTIVE_LOW>;
221 interrupt-controller;
222 #interrupt-cells = <1>;
223 #size-cells = <0>;
224
225 adc {
226 compatible = "gw,gsc-adc";
227 #address-cells = <1>;
228 #size-cells = <0>;
229
230 channel@0 {
231 gw,mode = <0>;
232 reg = <0x00>;
233 label = "temp";
234 };
235
236 channel@2 {
237 gw,mode = <1>;
238 reg = <0x02>;
239 label = "vdd_vin";
240 };
241
242 channel@5 {
243 gw,mode = <1>;
244 reg = <0x05>;
245 label = "vdd_3p3";
246 };
247
248 channel@8 {
249 gw,mode = <1>;
250 reg = <0x08>;
251 label = "vdd_bat";
252 };
253
254 channel@b {
255 gw,mode = <1>;
256 reg = <0x0b>;
257 label = "vdd_5p0";
258 };
259
260 channel@e {
261 gw,mode = <1>;
262 reg = <0xe>;
263 label = "vdd_arm";
264 };
265
266 channel@11 {
267 gw,mode = <1>;
268 reg = <0x11>;
269 label = "vdd_soc";
270 };
271
272 channel@14 {
273 gw,mode = <1>;
274 reg = <0x14>;
275 label = "vdd_3p0";
276 };
277
278 channel@17 {
279 gw,mode = <1>;
280 reg = <0x17>;
281 label = "vdd_1p5";
282 };
283
284 channel@1d {
285 gw,mode = <1>;
286 reg = <0x1d>;
287 label = "vdd_1p8";
288 };
289
290 channel@20 {
291 gw,mode = <1>;
292 reg = <0x20>;
293 label = "vdd_1p0";
294 };
295
296 channel@23 {
297 gw,mode = <1>;
298 reg = <0x23>;
299 label = "vdd_2p5";
300 };
301
302 channel@29 {
303 gw,mode = <1>;
304 reg = <0x29>;
305 label = "vdd_an1";
306 };
307 };
308 };
309
310 gsc_gpio: gpio@23 {
311 compatible = "nxp,pca9555";
312 reg = <0x23>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-parent = <&gsc>;
316 interrupts = <4>;
317 };
318
319 eeprom1: eeprom@50 {
320 compatible = "atmel,24c02";
321 reg = <0x50>;
322 pagesize = <16>;
323 };
324
325 eeprom2: eeprom@51 {
326 compatible = "atmel,24c02";
327 reg = <0x51>;
328 pagesize = <16>;
329 };
330
331 eeprom3: eeprom@52 {
332 compatible = "atmel,24c02";
333 reg = <0x52>;
334 pagesize = <16>;
335 };
336
337 eeprom4: eeprom@53 {
338 compatible = "atmel,24c02";
339 reg = <0x53>;
340 pagesize = <16>;
341 };
342
343 rtc: ds1672@68 {
344 compatible = "dallas,ds1672";
345 reg = <0x68>;
346 };
347};
348
349&i2c2 {
350 clock-frequency = <100000>;
351 pinctrl-names = "default";
352 pinctrl-0 = <&pinctrl_i2c2>;
353 status = "okay";
354
355 ltc3676: pmic@3c {
356 compatible = "lltc,ltc3676";
357 reg = <0x3c>;
358 pinctrl-names = "default";
359 pinctrl-0 = <&pinctrl_pmic>;
360 interrupt-parent = <&gpio1>;
361 interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
362
363 regulators {
364 /* VDD_SOC (1+R1/R2 = 1.635) */
365 reg_vdd_soc: sw1 {
366 regulator-name = "vddsoc";
367 regulator-min-microvolt = <674400>;
368 regulator-max-microvolt = <1308000>;
369 lltc,fb-voltage-divider = <127000 200000>;
370 regulator-ramp-delay = <7000>;
371 regulator-boot-on;
372 regulator-always-on;
373 };
374
375 /* VDD_1P8 (1+R1/R2 = 2.505): GPS/VideoIn/ENET-PHY */
376 reg_1p8v: sw2 {
377 regulator-name = "vdd1p8";
378 regulator-min-microvolt = <1033310>;
379 regulator-max-microvolt = <2004000>;
380 lltc,fb-voltage-divider = <301000 200000>;
381 regulator-ramp-delay = <7000>;
382 regulator-boot-on;
383 regulator-always-on;
384 };
385
386 /* VDD_ARM (1+R1/R2 = 1.635) */
387 reg_vdd_arm: sw3 {
388 regulator-name = "vddarm";
389 regulator-min-microvolt = <674400>;
390 regulator-max-microvolt = <1308000>;
391 lltc,fb-voltage-divider = <127000 200000>;
392 regulator-ramp-delay = <7000>;
393 regulator-boot-on;
394 regulator-always-on;
395 };
396
397 /* VDD_DDR (1+R1/R2 = 2.105) */
398 reg_vdd_ddr: sw4 {
399 regulator-name = "vddddr";
400 regulator-min-microvolt = <868310>;
401 regulator-max-microvolt = <1684000>;
402 lltc,fb-voltage-divider = <221000 200000>;
403 regulator-ramp-delay = <7000>;
404 regulator-boot-on;
405 regulator-always-on;
406 };
407
408 /* VDD_2P5 (1+R1/R2 = 3.435): PCIe/ENET-PHY */
409 reg_2p5v: ldo2 {
410 regulator-name = "vdd2p5";
411 regulator-min-microvolt = <2490375>;
412 regulator-max-microvolt = <2490375>;
413 lltc,fb-voltage-divider = <487000 200000>;
414 regulator-boot-on;
415 regulator-always-on;
416 };
417
418 /* VDD_AUD_1P8: Audio codec */
419 reg_aud_1p8v: ldo3 {
420 regulator-name = "vdd1p8";
421 regulator-min-microvolt = <1800000>;
422 regulator-max-microvolt = <1800000>;
423 regulator-boot-on;
424 };
425
426 /* VDD_HIGH (1+R1/R2 = 4.17) */
427 reg_3p0v: ldo4 {
428 regulator-name = "vdd3p0";
429 regulator-min-microvolt = <3023250>;
430 regulator-max-microvolt = <3023250>;
431 lltc,fb-voltage-divider = <634000 200000>;
432 regulator-boot-on;
433 regulator-always-on;
434 };
435 };
436 };
437};
438
439&i2c3 {
440 clock-frequency = <100000>;
441 pinctrl-names = "default";
442 pinctrl-0 = <&pinctrl_i2c3>;
443 status = "okay";
444
445 codec: sgtl5000@a {
446 compatible = "fsl,sgtl5000";
447 reg = <0x0a>;
448 clocks = <&clks IMX6QDL_CLK_CKO>;
449 VDDA-supply = <®_1p8v>;
450 VDDIO-supply = <®_3p3v>;
451 };
452
453 touchscreen: egalax_ts@4 {
454 compatible = "eeti,egalax_ts";
455 reg = <0x04>;
456 interrupt-parent = <&gpio7>;
457 interrupts = <12 2>;
458 wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
459 };
460
461 accel@1e {
462 compatible = "nxp,fxos8700";
463 reg = <0x1e>;
464 };
465};
466
467&ldb {
468 status = "okay";
469
470 lvds-channel@0 {
471 fsl,data-mapping = "spwg";
472 fsl,data-width = <18>;
473 status = "okay";
474
475 display-timings {
476 native-mode = <&timing0>;
477 timing0: hsd100pxn1 {
478 clock-frequency = <65000000>;
479 hactive = <1024>;
480 vactive = <768>;
481 hback-porch = <220>;
482 hfront-porch = <40>;
483 vback-porch = <21>;
484 vfront-porch = <7>;
485 hsync-len = <60>;
486 vsync-len = <10>;
487 };
488 };
489 };
490};
491
492&pcie {
493 pinctrl-names = "default";
494 pinctrl-0 = <&pinctrl_pcie>;
495 reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
496 status = "okay";
497};
498
499&pwm2 {
500 pinctrl-names = "default";
501 pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
502 status = "disabled";
503};
504
505&pwm3 {
506 pinctrl-names = "default";
507 pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
508 status = "disabled";
509};
510
511&pwm4 {
512 #pwm-cells = <2>;
513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_pwm4>;
515 status = "okay";
516};
517
518&ssi1 {
519 status = "okay";
520};
521
522&uart1 {
523 pinctrl-names = "default";
524 pinctrl-0 = <&pinctrl_uart1>;
525 rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
526 status = "okay";
527};
528
529&uart2 {
530 pinctrl-names = "default";
531 pinctrl-0 = <&pinctrl_uart2>;
532 status = "okay";
533};
534
535&uart5 {
536 pinctrl-names = "default";
537 pinctrl-0 = <&pinctrl_uart5>;
538 status = "okay";
539};
540
541&usbotg {
542 vbus-supply = <®_usb_otg_vbus>;
543 pinctrl-names = "default";
544 pinctrl-0 = <&pinctrl_usbotg>;
545 disable-over-current;
546 status = "okay";
547};
548
549&usbh1 {
550 status = "okay";
551};
552
553&usdhc3 {
554 pinctrl-names = "default", "state_100mhz", "state_200mhz";
555 pinctrl-0 = <&pinctrl_usdhc3>;
556 pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
557 pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
558 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
559 vmmc-supply = <®_3p3v>;
560 no-1-8-v; /* firmware will remove if board revision supports */
561 status = "okay";
562};
563
564&wdog1 {
565 pinctrl-names = "default";
566 pinctrl-0 = <&pinctrl_wdog>;
567 fsl,ext-reset-output;
568};
569
570&iomuxc {
571 pinctrl_audmux: audmuxgrp {
572 fsl,pins = <
573 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
574 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
575 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
576 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
577 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x130b0 /* AUD4_MCK */
578 >;
579 };
580
581 pinctrl_ecspi3: escpi3grp {
582 fsl,pins = <
583 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
584 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
585 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
586 MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
587 >;
588 };
589
590 pinctrl_enet: enetgrp {
591 fsl,pins = <
592 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
593 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
594 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
595 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
596 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
597 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
598 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
599 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
600 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
601 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
602 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
603 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
604 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
605 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
606 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
607 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
608 MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0 /* PHY Reset */
609 >;
610 };
611
612 pinctrl_flexcan1: flexcan1grp {
613 fsl,pins = <
614 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
615 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
616 MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */
617 >;
618 };
619
620 pinctrl_gpio_leds: gpioledsgrp {
621 fsl,pins = <
622 MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
623 MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
624 MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
625 >;
626 };
627
628 pinctrl_gpmi_nand: gpminandgrp {
629 fsl,pins = <
630 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
631 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
632 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
633 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
634 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
635 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
636 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
637 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
638 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
639 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
640 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
641 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
642 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
643 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
644 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
645 >;
646 };
647
648 pinctrl_i2c1: i2c1grp {
649 fsl,pins = <
650 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
651 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
652 MX6QDL_PAD_GPIO_4__GPIO1_IO04 0xb0b1
653 >;
654 };
655
656 pinctrl_i2c2: i2c2grp {
657 fsl,pins = <
658 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
659 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
660 >;
661 };
662
663 pinctrl_i2c3: i2c3grp {
664 fsl,pins = <
665 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
666 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
667 >;
668 };
669
670 pinctrl_pcie: pciegrp {
671 fsl,pins = <
672 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0 /* PCIE_RST# */
673 >;
674 };
675
676 pinctrl_pmic: pmicgrp {
677 fsl,pins = <
678 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x0001b0b0 /* PMIC_IRQ# */
679 >;
680 };
681
682 pinctrl_pps: ppsgrp {
683 fsl,pins = <
684 MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
685 >;
686 };
687
688 pinctrl_pwm2: pwm2grp {
689 fsl,pins = <
690 MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
691 >;
692 };
693
694 pinctrl_pwm3: pwm3grp {
695 fsl,pins = <
696 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
697 >;
698 };
699
700 pinctrl_pwm4: pwm4grp {
701 fsl,pins = <
702 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
703 >;
704 };
705
706 pinctrl_uart1: uart1grp {
707 fsl,pins = <
708 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
709 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
710 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x4001b0b1 /* TEN */
711 >;
712 };
713
714 pinctrl_uart2: uart2grp {
715 fsl,pins = <
716 MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
717 MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
718 >;
719 };
720
721 pinctrl_uart5: uart5grp {
722 fsl,pins = <
723 MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
724 MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
725 >;
726 };
727
728 pinctrl_usbotg: usbotggrp {
729 fsl,pins = <
730 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
731 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0 /* OTG_PWR_EN */
732 >;
733 };
734
735 pinctrl_usdhc3: usdhc3grp {
736 fsl,pins = <
737 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
738 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
739 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
740 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
741 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
742 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
743 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
744 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
745 >;
746 };
747
748 pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
749 fsl,pins = <
750 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
751 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
752 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
753 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
754 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
755 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
756 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
757 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
758 >;
759 };
760
761 pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
762 fsl,pins = <
763 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
764 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
765 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
766 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
767 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
768 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
769 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
770 MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
771 >;
772 };
773
774 pinctrl_wdog: wdoggrp {
775 fsl,pins = <
776 MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
777 >;
778 };
779};