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1/*
2 * max98927.c -- MAX98927 ALSA Soc Audio driver
3 *
4 * Copyright (C) 2016-2017 Maxim Integrated Products
5 * Author: Ryan Lee <ryans.lee@maximintegrated.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
11 */
12
13#include <linux/acpi.h>
14#include <linux/i2c.h>
15#include <linux/module.h>
16#include <linux/regmap.h>
17#include <linux/slab.h>
18#include <linux/cdev.h>
19#include <sound/pcm.h>
20#include <sound/pcm_params.h>
21#include <sound/soc.h>
22#include <linux/gpio.h>
23#include <linux/of_gpio.h>
24#include <sound/tlv.h>
25#include "max98927.h"
26
27static struct reg_default max98927_reg[] = {
28 {MAX98927_R0001_INT_RAW1, 0x00},
29 {MAX98927_R0002_INT_RAW2, 0x00},
30 {MAX98927_R0003_INT_RAW3, 0x00},
31 {MAX98927_R0004_INT_STATE1, 0x00},
32 {MAX98927_R0005_INT_STATE2, 0x00},
33 {MAX98927_R0006_INT_STATE3, 0x00},
34 {MAX98927_R0007_INT_FLAG1, 0x00},
35 {MAX98927_R0008_INT_FLAG2, 0x00},
36 {MAX98927_R0009_INT_FLAG3, 0x00},
37 {MAX98927_R000A_INT_EN1, 0x00},
38 {MAX98927_R000B_INT_EN2, 0x00},
39 {MAX98927_R000C_INT_EN3, 0x00},
40 {MAX98927_R000D_INT_FLAG_CLR1, 0x00},
41 {MAX98927_R000E_INT_FLAG_CLR2, 0x00},
42 {MAX98927_R000F_INT_FLAG_CLR3, 0x00},
43 {MAX98927_R0010_IRQ_CTRL, 0x00},
44 {MAX98927_R0011_CLK_MON, 0x00},
45 {MAX98927_R0012_WDOG_CTRL, 0x00},
46 {MAX98927_R0013_WDOG_RST, 0x00},
47 {MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH, 0x75},
48 {MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH, 0x8c},
49 {MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS, 0x08},
50 {MAX98927_R0017_PIN_CFG, 0x55},
51 {MAX98927_R0018_PCM_RX_EN_A, 0x00},
52 {MAX98927_R0019_PCM_RX_EN_B, 0x00},
53 {MAX98927_R001A_PCM_TX_EN_A, 0x00},
54 {MAX98927_R001B_PCM_TX_EN_B, 0x00},
55 {MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0x00},
56 {MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0x00},
57 {MAX98927_R001E_PCM_TX_CH_SRC_A, 0x00},
58 {MAX98927_R001F_PCM_TX_CH_SRC_B, 0x00},
59 {MAX98927_R0020_PCM_MODE_CFG, 0x40},
60 {MAX98927_R0021_PCM_MASTER_MODE, 0x00},
61 {MAX98927_R0022_PCM_CLK_SETUP, 0x22},
62 {MAX98927_R0023_PCM_SR_SETUP1, 0x00},
63 {MAX98927_R0024_PCM_SR_SETUP2, 0x00},
64 {MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 0x00},
65 {MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 0x00},
66 {MAX98927_R0027_ICC_RX_EN_A, 0x00},
67 {MAX98927_R0028_ICC_RX_EN_B, 0x00},
68 {MAX98927_R002B_ICC_TX_EN_A, 0x00},
69 {MAX98927_R002C_ICC_TX_EN_B, 0x00},
70 {MAX98927_R002E_ICC_HIZ_MANUAL_MODE, 0x00},
71 {MAX98927_R002F_ICC_TX_HIZ_EN_A, 0x00},
72 {MAX98927_R0030_ICC_TX_HIZ_EN_B, 0x00},
73 {MAX98927_R0031_ICC_LNK_EN, 0x00},
74 {MAX98927_R0032_PDM_TX_EN, 0x00},
75 {MAX98927_R0033_PDM_TX_HIZ_CTRL, 0x00},
76 {MAX98927_R0034_PDM_TX_CTRL, 0x00},
77 {MAX98927_R0035_PDM_RX_CTRL, 0x00},
78 {MAX98927_R0036_AMP_VOL_CTRL, 0x00},
79 {MAX98927_R0037_AMP_DSP_CFG, 0x02},
80 {MAX98927_R0038_TONE_GEN_DC_CFG, 0x00},
81 {MAX98927_R0039_DRE_CTRL, 0x01},
82 {MAX98927_R003A_AMP_EN, 0x00},
83 {MAX98927_R003B_SPK_SRC_SEL, 0x00},
84 {MAX98927_R003C_SPK_GAIN, 0x00},
85 {MAX98927_R003D_SSM_CFG, 0x04},
86 {MAX98927_R003E_MEAS_EN, 0x00},
87 {MAX98927_R003F_MEAS_DSP_CFG, 0x04},
88 {MAX98927_R0040_BOOST_CTRL0, 0x00},
89 {MAX98927_R0041_BOOST_CTRL3, 0x00},
90 {MAX98927_R0042_BOOST_CTRL1, 0x00},
91 {MAX98927_R0043_MEAS_ADC_CFG, 0x00},
92 {MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x01},
93 {MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x00},
94 {MAX98927_R0046_ADC_CH0_DIVIDE, 0x00},
95 {MAX98927_R0047_ADC_CH1_DIVIDE, 0x00},
96 {MAX98927_R0048_ADC_CH2_DIVIDE, 0x00},
97 {MAX98927_R0049_ADC_CH0_FILT_CFG, 0x00},
98 {MAX98927_R004A_ADC_CH1_FILT_CFG, 0x00},
99 {MAX98927_R004B_ADC_CH2_FILT_CFG, 0x00},
100 {MAX98927_R004C_MEAS_ADC_CH0_READ, 0x00},
101 {MAX98927_R004D_MEAS_ADC_CH1_READ, 0x00},
102 {MAX98927_R004E_MEAS_ADC_CH2_READ, 0x00},
103 {MAX98927_R0051_BROWNOUT_STATUS, 0x00},
104 {MAX98927_R0052_BROWNOUT_EN, 0x00},
105 {MAX98927_R0053_BROWNOUT_INFINITE_HOLD, 0x00},
106 {MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
107 {MAX98927_R0055_BROWNOUT_LVL_HOLD, 0x00},
108 {MAX98927_R005A_BROWNOUT_LVL1_THRESH, 0x00},
109 {MAX98927_R005B_BROWNOUT_LVL2_THRESH, 0x00},
110 {MAX98927_R005C_BROWNOUT_LVL3_THRESH, 0x00},
111 {MAX98927_R005D_BROWNOUT_LVL4_THRESH, 0x00},
112 {MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
113 {MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL, 0x00},
114 {MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
115 {MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE, 0x00},
116 {MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
117 {MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
118 {MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
119 {MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
120 {MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
121 {MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
122 {MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
123 {MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
124 {MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
125 {MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
126 {MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
127 {MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
128 {MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
129 {MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
130 {MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
131 {MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
132 {MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 0x00},
133 {MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY, 0x00},
134 {MAX98927_R0084_ENV_TRACK_REL_RATE, 0x00},
135 {MAX98927_R0085_ENV_TRACK_HOLD_RATE, 0x00},
136 {MAX98927_R0086_ENV_TRACK_CTRL, 0x00},
137 {MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 0x00},
138 {MAX98927_R00FF_GLOBAL_SHDN, 0x00},
139 {MAX98927_R0100_SOFT_RESET, 0x00},
140 {MAX98927_R01FF_REV_ID, 0x40},
141};
142
143static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
144{
145 struct snd_soc_component *component = codec_dai->component;
146 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
147 unsigned int mode = 0;
148 unsigned int format = 0;
149 bool use_pdm = false;
150 unsigned int invert = 0;
151
152 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
153
154 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
155 case SND_SOC_DAIFMT_CBS_CFS:
156 mode = MAX98927_PCM_MASTER_MODE_SLAVE;
157 break;
158 case SND_SOC_DAIFMT_CBM_CFM:
159 max98927->master = true;
160 mode = MAX98927_PCM_MASTER_MODE_MASTER;
161 break;
162 default:
163 dev_err(component->dev, "DAI clock mode unsupported\n");
164 return -EINVAL;
165 }
166
167 regmap_update_bits(max98927->regmap,
168 MAX98927_R0021_PCM_MASTER_MODE,
169 MAX98927_PCM_MASTER_MODE_MASK,
170 mode);
171
172 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
173 case SND_SOC_DAIFMT_NB_NF:
174 break;
175 case SND_SOC_DAIFMT_IB_NF:
176 invert = MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE;
177 break;
178 default:
179 dev_err(component->dev, "DAI invert mode unsupported\n");
180 return -EINVAL;
181 }
182
183 regmap_update_bits(max98927->regmap,
184 MAX98927_R0020_PCM_MODE_CFG,
185 MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE,
186 invert);
187
188 /* interface format */
189 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
190 case SND_SOC_DAIFMT_I2S:
191 format = MAX98927_PCM_FORMAT_I2S;
192 break;
193 case SND_SOC_DAIFMT_LEFT_J:
194 format = MAX98927_PCM_FORMAT_LJ;
195 break;
196 case SND_SOC_DAIFMT_DSP_A:
197 format = MAX98927_PCM_FORMAT_TDM_MODE1;
198 break;
199 case SND_SOC_DAIFMT_DSP_B:
200 format = MAX98927_PCM_FORMAT_TDM_MODE0;
201 break;
202 case SND_SOC_DAIFMT_PDM:
203 use_pdm = true;
204 break;
205 default:
206 return -EINVAL;
207 }
208 max98927->iface = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
209
210 if (!use_pdm) {
211 /* pcm channel configuration */
212 regmap_update_bits(max98927->regmap,
213 MAX98927_R0018_PCM_RX_EN_A,
214 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
215 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN);
216
217 regmap_update_bits(max98927->regmap,
218 MAX98927_R0020_PCM_MODE_CFG,
219 MAX98927_PCM_MODE_CFG_FORMAT_MASK,
220 format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT);
221
222 regmap_update_bits(max98927->regmap,
223 MAX98927_R003B_SPK_SRC_SEL,
224 MAX98927_SPK_SRC_MASK, 0);
225
226 regmap_update_bits(max98927->regmap,
227 MAX98927_R0035_PDM_RX_CTRL,
228 MAX98927_PDM_RX_EN_MASK, 0);
229 } else {
230 /* pdm channel configuration */
231 regmap_update_bits(max98927->regmap,
232 MAX98927_R0035_PDM_RX_CTRL,
233 MAX98927_PDM_RX_EN_MASK, 1);
234
235 regmap_update_bits(max98927->regmap,
236 MAX98927_R003B_SPK_SRC_SEL,
237 MAX98927_SPK_SRC_MASK, 3);
238
239 regmap_update_bits(max98927->regmap,
240 MAX98927_R0018_PCM_RX_EN_A,
241 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN, 0);
242 }
243 return 0;
244}
245
246/* codec MCLK rate in master mode */
247static const int rate_table[] = {
248 5644800, 6000000, 6144000, 6500000,
249 9600000, 11289600, 12000000, 12288000,
250 13000000, 19200000,
251};
252
253/* BCLKs per LRCLK */
254static const int bclk_sel_table[] = {
255 32, 48, 64, 96, 128, 192, 256, 384, 512,
256};
257
258static int max98927_get_bclk_sel(int bclk)
259{
260 int i;
261 /* match BCLKs per LRCLK */
262 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
263 if (bclk_sel_table[i] == bclk)
264 return i + 2;
265 }
266 return 0;
267}
268static int max98927_set_clock(struct max98927_priv *max98927,
269 struct snd_pcm_hw_params *params)
270{
271 struct snd_soc_component *component = max98927->component;
272 /* BCLK/LRCLK ratio calculation */
273 int blr_clk_ratio = params_channels(params) * max98927->ch_size;
274 int value;
275
276 if (max98927->master) {
277 int i;
278 /* match rate to closest value */
279 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
280 if (rate_table[i] >= max98927->sysclk)
281 break;
282 }
283 if (i == ARRAY_SIZE(rate_table)) {
284 dev_err(component->dev, "failed to find proper clock rate.\n");
285 return -EINVAL;
286 }
287 regmap_update_bits(max98927->regmap,
288 MAX98927_R0021_PCM_MASTER_MODE,
289 MAX98927_PCM_MASTER_MODE_MCLK_MASK,
290 i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
291 }
292
293 if (!max98927->tdm_mode) {
294 /* BCLK configuration */
295 value = max98927_get_bclk_sel(blr_clk_ratio);
296 if (!value) {
297 dev_err(component->dev, "format unsupported %d\n",
298 params_format(params));
299 return -EINVAL;
300 }
301
302 regmap_update_bits(max98927->regmap,
303 MAX98927_R0022_PCM_CLK_SETUP,
304 MAX98927_PCM_CLK_SETUP_BSEL_MASK,
305 value);
306 }
307 return 0;
308}
309
310static int max98927_dai_hw_params(struct snd_pcm_substream *substream,
311 struct snd_pcm_hw_params *params,
312 struct snd_soc_dai *dai)
313{
314 struct snd_soc_component *component = dai->component;
315 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
316 unsigned int sampling_rate = 0;
317 unsigned int chan_sz = 0;
318
319 /* pcm mode configuration */
320 switch (snd_pcm_format_width(params_format(params))) {
321 case 16:
322 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
323 break;
324 case 24:
325 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
326 break;
327 case 32:
328 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
329 break;
330 default:
331 dev_err(component->dev, "format unsupported %d\n",
332 params_format(params));
333 goto err;
334 }
335
336 max98927->ch_size = snd_pcm_format_width(params_format(params));
337
338 regmap_update_bits(max98927->regmap,
339 MAX98927_R0020_PCM_MODE_CFG,
340 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
341
342 dev_dbg(component->dev, "format supported %d",
343 params_format(params));
344
345 /* sampling rate configuration */
346 switch (params_rate(params)) {
347 case 8000:
348 sampling_rate = MAX98927_PCM_SR_SET1_SR_8000;
349 break;
350 case 11025:
351 sampling_rate = MAX98927_PCM_SR_SET1_SR_11025;
352 break;
353 case 12000:
354 sampling_rate = MAX98927_PCM_SR_SET1_SR_12000;
355 break;
356 case 16000:
357 sampling_rate = MAX98927_PCM_SR_SET1_SR_16000;
358 break;
359 case 22050:
360 sampling_rate = MAX98927_PCM_SR_SET1_SR_22050;
361 break;
362 case 24000:
363 sampling_rate = MAX98927_PCM_SR_SET1_SR_24000;
364 break;
365 case 32000:
366 sampling_rate = MAX98927_PCM_SR_SET1_SR_32000;
367 break;
368 case 44100:
369 sampling_rate = MAX98927_PCM_SR_SET1_SR_44100;
370 break;
371 case 48000:
372 sampling_rate = MAX98927_PCM_SR_SET1_SR_48000;
373 break;
374 default:
375 dev_err(component->dev, "rate %d not supported\n",
376 params_rate(params));
377 goto err;
378 }
379 /* set DAI_SR to correct LRCLK frequency */
380 regmap_update_bits(max98927->regmap,
381 MAX98927_R0023_PCM_SR_SETUP1,
382 MAX98927_PCM_SR_SET1_SR_MASK,
383 sampling_rate);
384 regmap_update_bits(max98927->regmap,
385 MAX98927_R0024_PCM_SR_SETUP2,
386 MAX98927_PCM_SR_SET2_SR_MASK,
387 sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT);
388
389 /* set sampling rate of IV */
390 if (max98927->interleave_mode &&
391 sampling_rate > MAX98927_PCM_SR_SET1_SR_16000)
392 regmap_update_bits(max98927->regmap,
393 MAX98927_R0024_PCM_SR_SETUP2,
394 MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
395 sampling_rate - 3);
396 else
397 regmap_update_bits(max98927->regmap,
398 MAX98927_R0024_PCM_SR_SETUP2,
399 MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
400 sampling_rate);
401 return max98927_set_clock(max98927, params);
402err:
403 return -EINVAL;
404}
405
406static int max98927_dai_tdm_slot(struct snd_soc_dai *dai,
407 unsigned int tx_mask, unsigned int rx_mask,
408 int slots, int slot_width)
409{
410 struct snd_soc_component *component = dai->component;
411 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
412 int bsel = 0;
413 unsigned int chan_sz = 0;
414
415 max98927->tdm_mode = true;
416
417 /* BCLK configuration */
418 bsel = max98927_get_bclk_sel(slots * slot_width);
419 if (bsel == 0) {
420 dev_err(component->dev, "BCLK %d not supported\n",
421 slots * slot_width);
422 return -EINVAL;
423 }
424
425 regmap_update_bits(max98927->regmap,
426 MAX98927_R0022_PCM_CLK_SETUP,
427 MAX98927_PCM_CLK_SETUP_BSEL_MASK,
428 bsel);
429
430 /* Channel size configuration */
431 switch (slot_width) {
432 case 16:
433 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
434 break;
435 case 24:
436 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
437 break;
438 case 32:
439 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
440 break;
441 default:
442 dev_err(component->dev, "format unsupported %d\n",
443 slot_width);
444 return -EINVAL;
445 }
446
447 regmap_update_bits(max98927->regmap,
448 MAX98927_R0020_PCM_MODE_CFG,
449 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
450
451 /* Rx slot configuration */
452 regmap_write(max98927->regmap,
453 MAX98927_R0018_PCM_RX_EN_A,
454 rx_mask & 0xFF);
455 regmap_write(max98927->regmap,
456 MAX98927_R0019_PCM_RX_EN_B,
457 (rx_mask & 0xFF00) >> 8);
458
459 /* Tx slot configuration */
460 regmap_write(max98927->regmap,
461 MAX98927_R001A_PCM_TX_EN_A,
462 tx_mask & 0xFF);
463 regmap_write(max98927->regmap,
464 MAX98927_R001B_PCM_TX_EN_B,
465 (tx_mask & 0xFF00) >> 8);
466
467 /* Tx slot Hi-Z configuration */
468 regmap_write(max98927->regmap,
469 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
470 ~tx_mask & 0xFF);
471 regmap_write(max98927->regmap,
472 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
473 (~tx_mask & 0xFF00) >> 8);
474
475 return 0;
476}
477
478#define MAX98927_RATES SNDRV_PCM_RATE_8000_48000
479
480#define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
481 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
482
483static int max98927_dai_set_sysclk(struct snd_soc_dai *dai,
484 int clk_id, unsigned int freq, int dir)
485{
486 struct snd_soc_component *component = dai->component;
487 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
488
489 max98927->sysclk = freq;
490 return 0;
491}
492
493static const struct snd_soc_dai_ops max98927_dai_ops = {
494 .set_sysclk = max98927_dai_set_sysclk,
495 .set_fmt = max98927_dai_set_fmt,
496 .hw_params = max98927_dai_hw_params,
497 .set_tdm_slot = max98927_dai_tdm_slot,
498};
499
500static int max98927_dac_event(struct snd_soc_dapm_widget *w,
501 struct snd_kcontrol *kcontrol, int event)
502{
503 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
504 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
505
506 switch (event) {
507 case SND_SOC_DAPM_PRE_PMU:
508 max98927->tdm_mode = 0;
509 break;
510 case SND_SOC_DAPM_POST_PMU:
511 regmap_update_bits(max98927->regmap,
512 MAX98927_R003A_AMP_EN,
513 MAX98927_AMP_EN_MASK, 1);
514 regmap_update_bits(max98927->regmap,
515 MAX98927_R00FF_GLOBAL_SHDN,
516 MAX98927_GLOBAL_EN_MASK, 1);
517 break;
518 case SND_SOC_DAPM_POST_PMD:
519 regmap_update_bits(max98927->regmap,
520 MAX98927_R00FF_GLOBAL_SHDN,
521 MAX98927_GLOBAL_EN_MASK, 0);
522 regmap_update_bits(max98927->regmap,
523 MAX98927_R003A_AMP_EN,
524 MAX98927_AMP_EN_MASK, 0);
525 break;
526 default:
527 return 0;
528 }
529 return 0;
530}
531
532static const char * const max98927_switch_text[] = {
533 "Left", "Right", "LeftRight"};
534
535static const struct soc_enum dai_sel_enum =
536 SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
537 MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
538 3, max98927_switch_text);
539
540static const struct snd_kcontrol_new max98927_dai_controls =
541 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
542
543static const struct snd_kcontrol_new max98927_vi_control =
544 SOC_DAPM_SINGLE("Switch", MAX98927_R003F_MEAS_DSP_CFG, 2, 1, 0);
545
546static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
547 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN,
548 0, 0, max98927_dac_event,
549 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
550 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
551 &max98927_dai_controls),
552 SND_SOC_DAPM_OUTPUT("BE_OUT"),
553 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
554 MAX98927_R003E_MEAS_EN, 0, 0),
555 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
556 MAX98927_R003E_MEAS_EN, 1, 0),
557 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
558 &max98927_vi_control),
559 SND_SOC_DAPM_SIGGEN("VMON"),
560 SND_SOC_DAPM_SIGGEN("IMON"),
561};
562
563static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0);
564static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0);
565
566static bool max98927_readable_register(struct device *dev, unsigned int reg)
567{
568 switch (reg) {
569 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0028_ICC_RX_EN_B:
570 case MAX98927_R002B_ICC_TX_EN_A ... MAX98927_R002C_ICC_TX_EN_B:
571 case MAX98927_R002E_ICC_HIZ_MANUAL_MODE
572 ... MAX98927_R004E_MEAS_ADC_CH2_READ:
573 case MAX98927_R0051_BROWNOUT_STATUS
574 ... MAX98927_R0055_BROWNOUT_LVL_HOLD:
575 case MAX98927_R005A_BROWNOUT_LVL1_THRESH
576 ... MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE:
577 case MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT
578 ... MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
579 case MAX98927_R00FF_GLOBAL_SHDN:
580 case MAX98927_R0100_SOFT_RESET:
581 case MAX98927_R01FF_REV_ID:
582 return true;
583 default:
584 return false;
585 }
586};
587
588static bool max98927_volatile_reg(struct device *dev, unsigned int reg)
589{
590 switch (reg) {
591 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0009_INT_FLAG3:
592 case MAX98927_R004C_MEAS_ADC_CH0_READ:
593 case MAX98927_R004D_MEAS_ADC_CH1_READ:
594 case MAX98927_R004E_MEAS_ADC_CH2_READ:
595 case MAX98927_R0051_BROWNOUT_STATUS:
596 case MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
597 case MAX98927_R01FF_REV_ID:
598 case MAX98927_R0100_SOFT_RESET:
599 return true;
600 default:
601 return false;
602 }
603}
604
605static const char * const max98927_boost_voltage_text[] = {
606 "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
607 "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
608 "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
609 "9.5V", "9.625V", "9.75V", "9.875V", "10V"
610};
611
612static SOC_ENUM_SINGLE_DECL(max98927_boost_voltage,
613 MAX98927_R0040_BOOST_CTRL0, 0,
614 max98927_boost_voltage_text);
615
616static const char * const max98927_current_limit_text[] = {
617 "1.00A", "1.10A", "1.20A", "1.30A", "1.40A", "1.50A", "1.60A", "1.70A",
618 "1.80A", "1.90A", "2.00A", "2.10A", "2.20A", "2.30A", "2.40A", "2.50A",
619 "2.60A", "2.70A", "2.80A", "2.90A", "3.00A", "3.10A", "3.20A", "3.30A",
620 "3.40A", "3.50A", "3.60A", "3.70A", "3.80A", "3.90A", "4.00A", "4.10A"
621};
622
623static SOC_ENUM_SINGLE_DECL(max98927_current_limit,
624 MAX98927_R0042_BOOST_CTRL1, 1,
625 max98927_current_limit_text);
626
627static const struct snd_kcontrol_new max98927_snd_controls[] = {
628 SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN,
629 0, 6, 0,
630 max98927_spk_tlv),
631 SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL,
632 0, (1<<MAX98927_AMP_VOL_WIDTH)-1, 0,
633 max98927_digital_tlv),
634 SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN,
635 MAX98927_BROWNOUT_DSP_SHIFT, 1, 0),
636 SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG,
637 MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0),
638 SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL,
639 MAX98927_DRE_EN_SHIFT, 1, 0),
640 SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL,
641 MAX98927_AMP_VOL_SEL_SHIFT, 1, 0),
642 SOC_ENUM("Boost Output Voltage", max98927_boost_voltage),
643 SOC_ENUM("Current Limit", max98927_current_limit),
644};
645
646static const struct snd_soc_dapm_route max98927_audio_map[] = {
647 /* Plabyack */
648 {"DAI Sel Mux", "Left", "Amp Enable"},
649 {"DAI Sel Mux", "Right", "Amp Enable"},
650 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
651 {"BE_OUT", NULL, "DAI Sel Mux"},
652 /* Capture */
653 { "VI Sense", "Switch", "VMON" },
654 { "VI Sense", "Switch", "IMON" },
655 { "Voltage Sense", NULL, "VI Sense" },
656 { "Current Sense", NULL, "VI Sense" },
657};
658
659static struct snd_soc_dai_driver max98927_dai[] = {
660 {
661 .name = "max98927-aif1",
662 .playback = {
663 .stream_name = "HiFi Playback",
664 .channels_min = 1,
665 .channels_max = 2,
666 .rates = MAX98927_RATES,
667 .formats = MAX98927_FORMATS,
668 },
669 .capture = {
670 .stream_name = "HiFi Capture",
671 .channels_min = 1,
672 .channels_max = 2,
673 .rates = MAX98927_RATES,
674 .formats = MAX98927_FORMATS,
675 },
676 .ops = &max98927_dai_ops,
677 }
678};
679
680static int max98927_probe(struct snd_soc_component *component)
681{
682 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
683
684 max98927->component = component;
685
686 /* Software Reset */
687 regmap_write(max98927->regmap,
688 MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
689
690 /* IV default slot configuration */
691 regmap_write(max98927->regmap,
692 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
693 0xFF);
694 regmap_write(max98927->regmap,
695 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
696 0xFF);
697 regmap_write(max98927->regmap,
698 MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
699 0x80);
700 regmap_write(max98927->regmap,
701 MAX98927_R0026_PCM_TO_SPK_MONOMIX_B,
702 0x1);
703 /* Set inital volume (+13dB) */
704 regmap_write(max98927->regmap,
705 MAX98927_R0036_AMP_VOL_CTRL,
706 0x38);
707 regmap_write(max98927->regmap,
708 MAX98927_R003C_SPK_GAIN,
709 0x05);
710 /* Enable DC blocker */
711 regmap_write(max98927->regmap,
712 MAX98927_R0037_AMP_DSP_CFG,
713 0x03);
714 /* Enable IMON VMON DC blocker */
715 regmap_write(max98927->regmap,
716 MAX98927_R003F_MEAS_DSP_CFG,
717 0xF7);
718 /* Boost Output Voltage & Current limit */
719 regmap_write(max98927->regmap,
720 MAX98927_R0040_BOOST_CTRL0,
721 0x1C);
722 regmap_write(max98927->regmap,
723 MAX98927_R0042_BOOST_CTRL1,
724 0x3E);
725 /* Measurement ADC config */
726 regmap_write(max98927->regmap,
727 MAX98927_R0043_MEAS_ADC_CFG,
728 0x04);
729 regmap_write(max98927->regmap,
730 MAX98927_R0044_MEAS_ADC_BASE_MSB,
731 0x00);
732 regmap_write(max98927->regmap,
733 MAX98927_R0045_MEAS_ADC_BASE_LSB,
734 0x24);
735 /* Brownout Level */
736 regmap_write(max98927->regmap,
737 MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1,
738 0x06);
739 /* Envelope Tracking configuration */
740 regmap_write(max98927->regmap,
741 MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM,
742 0x08);
743 regmap_write(max98927->regmap,
744 MAX98927_R0086_ENV_TRACK_CTRL,
745 0x01);
746 regmap_write(max98927->regmap,
747 MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ,
748 0x10);
749
750 /* voltage, current slot configuration */
751 regmap_write(max98927->regmap,
752 MAX98927_R001E_PCM_TX_CH_SRC_A,
753 (max98927->i_l_slot<<MAX98927_PCM_TX_CH_SRC_A_I_SHIFT|
754 max98927->v_l_slot)&0xFF);
755
756 if (max98927->v_l_slot < 8) {
757 regmap_update_bits(max98927->regmap,
758 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
759 1 << max98927->v_l_slot, 0);
760 regmap_update_bits(max98927->regmap,
761 MAX98927_R001A_PCM_TX_EN_A,
762 1 << max98927->v_l_slot,
763 1 << max98927->v_l_slot);
764 } else {
765 regmap_update_bits(max98927->regmap,
766 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
767 1 << (max98927->v_l_slot - 8), 0);
768 regmap_update_bits(max98927->regmap,
769 MAX98927_R001B_PCM_TX_EN_B,
770 1 << (max98927->v_l_slot - 8),
771 1 << (max98927->v_l_slot - 8));
772 }
773
774 if (max98927->i_l_slot < 8) {
775 regmap_update_bits(max98927->regmap,
776 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
777 1 << max98927->i_l_slot, 0);
778 regmap_update_bits(max98927->regmap,
779 MAX98927_R001A_PCM_TX_EN_A,
780 1 << max98927->i_l_slot,
781 1 << max98927->i_l_slot);
782 } else {
783 regmap_update_bits(max98927->regmap,
784 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
785 1 << (max98927->i_l_slot - 8), 0);
786 regmap_update_bits(max98927->regmap,
787 MAX98927_R001B_PCM_TX_EN_B,
788 1 << (max98927->i_l_slot - 8),
789 1 << (max98927->i_l_slot - 8));
790 }
791
792 /* Set interleave mode */
793 if (max98927->interleave_mode)
794 regmap_update_bits(max98927->regmap,
795 MAX98927_R001F_PCM_TX_CH_SRC_B,
796 MAX98927_PCM_TX_CH_INTERLEAVE_MASK,
797 MAX98927_PCM_TX_CH_INTERLEAVE_MASK);
798 return 0;
799}
800
801#ifdef CONFIG_PM_SLEEP
802static int max98927_suspend(struct device *dev)
803{
804 struct max98927_priv *max98927 = dev_get_drvdata(dev);
805
806 regcache_cache_only(max98927->regmap, true);
807 regcache_mark_dirty(max98927->regmap);
808 return 0;
809}
810static int max98927_resume(struct device *dev)
811{
812 struct max98927_priv *max98927 = dev_get_drvdata(dev);
813
814 regmap_write(max98927->regmap,
815 MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
816 regcache_cache_only(max98927->regmap, false);
817 regcache_sync(max98927->regmap);
818 return 0;
819}
820#endif
821
822static const struct dev_pm_ops max98927_pm = {
823 SET_SYSTEM_SLEEP_PM_OPS(max98927_suspend, max98927_resume)
824};
825
826static const struct snd_soc_component_driver soc_component_dev_max98927 = {
827 .probe = max98927_probe,
828 .controls = max98927_snd_controls,
829 .num_controls = ARRAY_SIZE(max98927_snd_controls),
830 .dapm_widgets = max98927_dapm_widgets,
831 .num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets),
832 .dapm_routes = max98927_audio_map,
833 .num_dapm_routes = ARRAY_SIZE(max98927_audio_map),
834 .idle_bias_on = 1,
835 .use_pmdown_time = 1,
836 .endianness = 1,
837 .non_legacy_dai_naming = 1,
838};
839
840static const struct regmap_config max98927_regmap = {
841 .reg_bits = 16,
842 .val_bits = 8,
843 .max_register = MAX98927_R01FF_REV_ID,
844 .reg_defaults = max98927_reg,
845 .num_reg_defaults = ARRAY_SIZE(max98927_reg),
846 .readable_reg = max98927_readable_register,
847 .volatile_reg = max98927_volatile_reg,
848 .cache_type = REGCACHE_RBTREE,
849};
850
851static void max98927_slot_config(struct i2c_client *i2c,
852 struct max98927_priv *max98927)
853{
854 int value;
855 struct device *dev = &i2c->dev;
856
857 if (!device_property_read_u32(dev, "vmon-slot-no", &value))
858 max98927->v_l_slot = value & 0xF;
859 else
860 max98927->v_l_slot = 0;
861
862 if (!device_property_read_u32(dev, "imon-slot-no", &value))
863 max98927->i_l_slot = value & 0xF;
864 else
865 max98927->i_l_slot = 1;
866}
867
868static int max98927_i2c_probe(struct i2c_client *i2c,
869 const struct i2c_device_id *id)
870{
871
872 int ret = 0, value;
873 int reg = 0;
874 struct max98927_priv *max98927 = NULL;
875
876 max98927 = devm_kzalloc(&i2c->dev,
877 sizeof(*max98927), GFP_KERNEL);
878
879 if (!max98927) {
880 ret = -ENOMEM;
881 return ret;
882 }
883 i2c_set_clientdata(i2c, max98927);
884
885 /* update interleave mode info */
886 if (!of_property_read_u32(i2c->dev.of_node,
887 "interleave_mode", &value)) {
888 if (value > 0)
889 max98927->interleave_mode = 1;
890 else
891 max98927->interleave_mode = 0;
892 } else
893 max98927->interleave_mode = 0;
894
895 /* regmap initialization */
896 max98927->regmap
897 = devm_regmap_init_i2c(i2c, &max98927_regmap);
898 if (IS_ERR(max98927->regmap)) {
899 ret = PTR_ERR(max98927->regmap);
900 dev_err(&i2c->dev,
901 "Failed to allocate regmap: %d\n", ret);
902 return ret;
903 }
904
905 /* Check Revision ID */
906 ret = regmap_read(max98927->regmap,
907 MAX98927_R01FF_REV_ID, ®);
908 if (ret < 0) {
909 dev_err(&i2c->dev,
910 "Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID);
911 return ret;
912 }
913 dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg);
914
915 /* voltage/current slot configuration */
916 max98927_slot_config(i2c, max98927);
917
918 /* codec registeration */
919 ret = devm_snd_soc_register_component(&i2c->dev,
920 &soc_component_dev_max98927,
921 max98927_dai, ARRAY_SIZE(max98927_dai));
922 if (ret < 0)
923 dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
924
925 return ret;
926}
927
928static const struct i2c_device_id max98927_i2c_id[] = {
929 { "max98927", 0},
930 { },
931};
932
933MODULE_DEVICE_TABLE(i2c, max98927_i2c_id);
934
935#if defined(CONFIG_OF)
936static const struct of_device_id max98927_of_match[] = {
937 { .compatible = "maxim,max98927", },
938 { }
939};
940MODULE_DEVICE_TABLE(of, max98927_of_match);
941#endif
942
943#ifdef CONFIG_ACPI
944static const struct acpi_device_id max98927_acpi_match[] = {
945 { "MX98927", 0 },
946 {},
947};
948MODULE_DEVICE_TABLE(acpi, max98927_acpi_match);
949#endif
950
951static struct i2c_driver max98927_i2c_driver = {
952 .driver = {
953 .name = "max98927",
954 .of_match_table = of_match_ptr(max98927_of_match),
955 .acpi_match_table = ACPI_PTR(max98927_acpi_match),
956 .pm = &max98927_pm,
957 },
958 .probe = max98927_i2c_probe,
959 .id_table = max98927_i2c_id,
960};
961
962module_i2c_driver(max98927_i2c_driver)
963
964MODULE_DESCRIPTION("ALSA SoC MAX98927 driver");
965MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
966MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * max98927.c -- MAX98927 ALSA Soc Audio driver
4 *
5 * Copyright (C) 2016-2017 Maxim Integrated Products
6 * Author: Ryan Lee <ryans.lee@maximintegrated.com>
7 */
8
9#include <linux/acpi.h>
10#include <linux/i2c.h>
11#include <linux/module.h>
12#include <linux/regmap.h>
13#include <linux/slab.h>
14#include <linux/cdev.h>
15#include <sound/pcm.h>
16#include <sound/pcm_params.h>
17#include <sound/soc.h>
18#include <linux/gpio.h>
19#include <linux/of_gpio.h>
20#include <sound/tlv.h>
21#include "max98927.h"
22
23static struct reg_default max98927_reg[] = {
24 {MAX98927_R0001_INT_RAW1, 0x00},
25 {MAX98927_R0002_INT_RAW2, 0x00},
26 {MAX98927_R0003_INT_RAW3, 0x00},
27 {MAX98927_R0004_INT_STATE1, 0x00},
28 {MAX98927_R0005_INT_STATE2, 0x00},
29 {MAX98927_R0006_INT_STATE3, 0x00},
30 {MAX98927_R0007_INT_FLAG1, 0x00},
31 {MAX98927_R0008_INT_FLAG2, 0x00},
32 {MAX98927_R0009_INT_FLAG3, 0x00},
33 {MAX98927_R000A_INT_EN1, 0x00},
34 {MAX98927_R000B_INT_EN2, 0x00},
35 {MAX98927_R000C_INT_EN3, 0x00},
36 {MAX98927_R000D_INT_FLAG_CLR1, 0x00},
37 {MAX98927_R000E_INT_FLAG_CLR2, 0x00},
38 {MAX98927_R000F_INT_FLAG_CLR3, 0x00},
39 {MAX98927_R0010_IRQ_CTRL, 0x00},
40 {MAX98927_R0011_CLK_MON, 0x00},
41 {MAX98927_R0012_WDOG_CTRL, 0x00},
42 {MAX98927_R0013_WDOG_RST, 0x00},
43 {MAX98927_R0014_MEAS_ADC_THERM_WARN_THRESH, 0x75},
44 {MAX98927_R0015_MEAS_ADC_THERM_SHDN_THRESH, 0x8c},
45 {MAX98927_R0016_MEAS_ADC_THERM_HYSTERESIS, 0x08},
46 {MAX98927_R0017_PIN_CFG, 0x55},
47 {MAX98927_R0018_PCM_RX_EN_A, 0x00},
48 {MAX98927_R0019_PCM_RX_EN_B, 0x00},
49 {MAX98927_R001A_PCM_TX_EN_A, 0x00},
50 {MAX98927_R001B_PCM_TX_EN_B, 0x00},
51 {MAX98927_R001C_PCM_TX_HIZ_CTRL_A, 0x00},
52 {MAX98927_R001D_PCM_TX_HIZ_CTRL_B, 0x00},
53 {MAX98927_R001E_PCM_TX_CH_SRC_A, 0x00},
54 {MAX98927_R001F_PCM_TX_CH_SRC_B, 0x00},
55 {MAX98927_R0020_PCM_MODE_CFG, 0x40},
56 {MAX98927_R0021_PCM_MASTER_MODE, 0x00},
57 {MAX98927_R0022_PCM_CLK_SETUP, 0x22},
58 {MAX98927_R0023_PCM_SR_SETUP1, 0x00},
59 {MAX98927_R0024_PCM_SR_SETUP2, 0x00},
60 {MAX98927_R0025_PCM_TO_SPK_MONOMIX_A, 0x00},
61 {MAX98927_R0026_PCM_TO_SPK_MONOMIX_B, 0x00},
62 {MAX98927_R0027_ICC_RX_EN_A, 0x00},
63 {MAX98927_R0028_ICC_RX_EN_B, 0x00},
64 {MAX98927_R002B_ICC_TX_EN_A, 0x00},
65 {MAX98927_R002C_ICC_TX_EN_B, 0x00},
66 {MAX98927_R002E_ICC_HIZ_MANUAL_MODE, 0x00},
67 {MAX98927_R002F_ICC_TX_HIZ_EN_A, 0x00},
68 {MAX98927_R0030_ICC_TX_HIZ_EN_B, 0x00},
69 {MAX98927_R0031_ICC_LNK_EN, 0x00},
70 {MAX98927_R0032_PDM_TX_EN, 0x00},
71 {MAX98927_R0033_PDM_TX_HIZ_CTRL, 0x00},
72 {MAX98927_R0034_PDM_TX_CTRL, 0x00},
73 {MAX98927_R0035_PDM_RX_CTRL, 0x00},
74 {MAX98927_R0036_AMP_VOL_CTRL, 0x00},
75 {MAX98927_R0037_AMP_DSP_CFG, 0x02},
76 {MAX98927_R0038_TONE_GEN_DC_CFG, 0x00},
77 {MAX98927_R0039_DRE_CTRL, 0x01},
78 {MAX98927_R003A_AMP_EN, 0x00},
79 {MAX98927_R003B_SPK_SRC_SEL, 0x00},
80 {MAX98927_R003C_SPK_GAIN, 0x00},
81 {MAX98927_R003D_SSM_CFG, 0x04},
82 {MAX98927_R003E_MEAS_EN, 0x00},
83 {MAX98927_R003F_MEAS_DSP_CFG, 0x04},
84 {MAX98927_R0040_BOOST_CTRL0, 0x00},
85 {MAX98927_R0041_BOOST_CTRL3, 0x00},
86 {MAX98927_R0042_BOOST_CTRL1, 0x00},
87 {MAX98927_R0043_MEAS_ADC_CFG, 0x00},
88 {MAX98927_R0044_MEAS_ADC_BASE_MSB, 0x01},
89 {MAX98927_R0045_MEAS_ADC_BASE_LSB, 0x00},
90 {MAX98927_R0046_ADC_CH0_DIVIDE, 0x00},
91 {MAX98927_R0047_ADC_CH1_DIVIDE, 0x00},
92 {MAX98927_R0048_ADC_CH2_DIVIDE, 0x00},
93 {MAX98927_R0049_ADC_CH0_FILT_CFG, 0x00},
94 {MAX98927_R004A_ADC_CH1_FILT_CFG, 0x00},
95 {MAX98927_R004B_ADC_CH2_FILT_CFG, 0x00},
96 {MAX98927_R004C_MEAS_ADC_CH0_READ, 0x00},
97 {MAX98927_R004D_MEAS_ADC_CH1_READ, 0x00},
98 {MAX98927_R004E_MEAS_ADC_CH2_READ, 0x00},
99 {MAX98927_R0051_BROWNOUT_STATUS, 0x00},
100 {MAX98927_R0052_BROWNOUT_EN, 0x00},
101 {MAX98927_R0053_BROWNOUT_INFINITE_HOLD, 0x00},
102 {MAX98927_R0054_BROWNOUT_INFINITE_HOLD_CLR, 0x00},
103 {MAX98927_R0055_BROWNOUT_LVL_HOLD, 0x00},
104 {MAX98927_R005A_BROWNOUT_LVL1_THRESH, 0x00},
105 {MAX98927_R005B_BROWNOUT_LVL2_THRESH, 0x00},
106 {MAX98927_R005C_BROWNOUT_LVL3_THRESH, 0x00},
107 {MAX98927_R005D_BROWNOUT_LVL4_THRESH, 0x00},
108 {MAX98927_R005E_BROWNOUT_THRESH_HYSTERYSIS, 0x00},
109 {MAX98927_R005F_BROWNOUT_AMP_LIMITER_ATK_REL, 0x00},
110 {MAX98927_R0060_BROWNOUT_AMP_GAIN_ATK_REL, 0x00},
111 {MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE, 0x00},
112 {MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT, 0x00},
113 {MAX98927_R0073_BROWNOUT_LVL1_AMP1_CTRL1, 0x00},
114 {MAX98927_R0074_BROWNOUT_LVL1_AMP1_CTRL2, 0x00},
115 {MAX98927_R0075_BROWNOUT_LVL1_AMP1_CTRL3, 0x00},
116 {MAX98927_R0076_BROWNOUT_LVL2_CUR_LIMIT, 0x00},
117 {MAX98927_R0077_BROWNOUT_LVL2_AMP1_CTRL1, 0x00},
118 {MAX98927_R0078_BROWNOUT_LVL2_AMP1_CTRL2, 0x00},
119 {MAX98927_R0079_BROWNOUT_LVL2_AMP1_CTRL3, 0x00},
120 {MAX98927_R007A_BROWNOUT_LVL3_CUR_LIMIT, 0x00},
121 {MAX98927_R007B_BROWNOUT_LVL3_AMP1_CTRL1, 0x00},
122 {MAX98927_R007C_BROWNOUT_LVL3_AMP1_CTRL2, 0x00},
123 {MAX98927_R007D_BROWNOUT_LVL3_AMP1_CTRL3, 0x00},
124 {MAX98927_R007E_BROWNOUT_LVL4_CUR_LIMIT, 0x00},
125 {MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1, 0x00},
126 {MAX98927_R0080_BROWNOUT_LVL4_AMP1_CTRL2, 0x00},
127 {MAX98927_R0081_BROWNOUT_LVL4_AMP1_CTRL3, 0x00},
128 {MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM, 0x00},
129 {MAX98927_R0083_ENV_TRACK_BOOST_VOUT_DELAY, 0x00},
130 {MAX98927_R0084_ENV_TRACK_REL_RATE, 0x00},
131 {MAX98927_R0085_ENV_TRACK_HOLD_RATE, 0x00},
132 {MAX98927_R0086_ENV_TRACK_CTRL, 0x00},
133 {MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ, 0x00},
134 {MAX98927_R00FF_GLOBAL_SHDN, 0x00},
135 {MAX98927_R0100_SOFT_RESET, 0x00},
136 {MAX98927_R01FF_REV_ID, 0x40},
137};
138
139static int max98927_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
140{
141 struct snd_soc_component *component = codec_dai->component;
142 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
143 unsigned int mode = 0;
144 unsigned int format = 0;
145 bool use_pdm = false;
146 unsigned int invert = 0;
147
148 dev_dbg(component->dev, "%s: fmt 0x%08X\n", __func__, fmt);
149
150 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
151 case SND_SOC_DAIFMT_CBS_CFS:
152 mode = MAX98927_PCM_MASTER_MODE_SLAVE;
153 break;
154 case SND_SOC_DAIFMT_CBM_CFM:
155 max98927->master = true;
156 mode = MAX98927_PCM_MASTER_MODE_MASTER;
157 break;
158 default:
159 dev_err(component->dev, "DAI clock mode unsupported\n");
160 return -EINVAL;
161 }
162
163 regmap_update_bits(max98927->regmap,
164 MAX98927_R0021_PCM_MASTER_MODE,
165 MAX98927_PCM_MASTER_MODE_MASK,
166 mode);
167
168 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
169 case SND_SOC_DAIFMT_NB_NF:
170 break;
171 case SND_SOC_DAIFMT_IB_NF:
172 invert = MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE;
173 break;
174 default:
175 dev_err(component->dev, "DAI invert mode unsupported\n");
176 return -EINVAL;
177 }
178
179 regmap_update_bits(max98927->regmap,
180 MAX98927_R0020_PCM_MODE_CFG,
181 MAX98927_PCM_MODE_CFG_PCM_BCLKEDGE,
182 invert);
183
184 /* interface format */
185 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
186 case SND_SOC_DAIFMT_I2S:
187 format = MAX98927_PCM_FORMAT_I2S;
188 break;
189 case SND_SOC_DAIFMT_LEFT_J:
190 format = MAX98927_PCM_FORMAT_LJ;
191 break;
192 case SND_SOC_DAIFMT_DSP_A:
193 format = MAX98927_PCM_FORMAT_TDM_MODE1;
194 break;
195 case SND_SOC_DAIFMT_DSP_B:
196 format = MAX98927_PCM_FORMAT_TDM_MODE0;
197 break;
198 case SND_SOC_DAIFMT_PDM:
199 use_pdm = true;
200 break;
201 default:
202 return -EINVAL;
203 }
204 max98927->iface = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
205
206 if (!use_pdm) {
207 /* pcm channel configuration */
208 regmap_update_bits(max98927->regmap,
209 MAX98927_R0018_PCM_RX_EN_A,
210 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN,
211 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN);
212
213 regmap_update_bits(max98927->regmap,
214 MAX98927_R0020_PCM_MODE_CFG,
215 MAX98927_PCM_MODE_CFG_FORMAT_MASK,
216 format << MAX98927_PCM_MODE_CFG_FORMAT_SHIFT);
217
218 regmap_update_bits(max98927->regmap,
219 MAX98927_R003B_SPK_SRC_SEL,
220 MAX98927_SPK_SRC_MASK, 0);
221
222 regmap_update_bits(max98927->regmap,
223 MAX98927_R0035_PDM_RX_CTRL,
224 MAX98927_PDM_RX_EN_MASK, 0);
225 } else {
226 /* pdm channel configuration */
227 regmap_update_bits(max98927->regmap,
228 MAX98927_R0035_PDM_RX_CTRL,
229 MAX98927_PDM_RX_EN_MASK, 1);
230
231 regmap_update_bits(max98927->regmap,
232 MAX98927_R003B_SPK_SRC_SEL,
233 MAX98927_SPK_SRC_MASK, 3);
234
235 regmap_update_bits(max98927->regmap,
236 MAX98927_R0018_PCM_RX_EN_A,
237 MAX98927_PCM_RX_CH0_EN | MAX98927_PCM_RX_CH1_EN, 0);
238 }
239 return 0;
240}
241
242/* codec MCLK rate in master mode */
243static const int rate_table[] = {
244 5644800, 6000000, 6144000, 6500000,
245 9600000, 11289600, 12000000, 12288000,
246 13000000, 19200000,
247};
248
249/* BCLKs per LRCLK */
250static const int bclk_sel_table[] = {
251 32, 48, 64, 96, 128, 192, 256, 384, 512,
252};
253
254static int max98927_get_bclk_sel(int bclk)
255{
256 int i;
257 /* match BCLKs per LRCLK */
258 for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
259 if (bclk_sel_table[i] == bclk)
260 return i + 2;
261 }
262 return 0;
263}
264static int max98927_set_clock(struct max98927_priv *max98927,
265 struct snd_pcm_hw_params *params)
266{
267 struct snd_soc_component *component = max98927->component;
268 /* BCLK/LRCLK ratio calculation */
269 int blr_clk_ratio = params_channels(params) * max98927->ch_size;
270 int value;
271
272 if (max98927->master) {
273 int i;
274 /* match rate to closest value */
275 for (i = 0; i < ARRAY_SIZE(rate_table); i++) {
276 if (rate_table[i] >= max98927->sysclk)
277 break;
278 }
279 if (i == ARRAY_SIZE(rate_table)) {
280 dev_err(component->dev, "failed to find proper clock rate.\n");
281 return -EINVAL;
282 }
283 regmap_update_bits(max98927->regmap,
284 MAX98927_R0021_PCM_MASTER_MODE,
285 MAX98927_PCM_MASTER_MODE_MCLK_MASK,
286 i << MAX98927_PCM_MASTER_MODE_MCLK_RATE_SHIFT);
287 }
288
289 if (!max98927->tdm_mode) {
290 /* BCLK configuration */
291 value = max98927_get_bclk_sel(blr_clk_ratio);
292 if (!value) {
293 dev_err(component->dev, "format unsupported %d\n",
294 params_format(params));
295 return -EINVAL;
296 }
297
298 regmap_update_bits(max98927->regmap,
299 MAX98927_R0022_PCM_CLK_SETUP,
300 MAX98927_PCM_CLK_SETUP_BSEL_MASK,
301 value);
302 }
303 return 0;
304}
305
306static int max98927_dai_hw_params(struct snd_pcm_substream *substream,
307 struct snd_pcm_hw_params *params,
308 struct snd_soc_dai *dai)
309{
310 struct snd_soc_component *component = dai->component;
311 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
312 unsigned int sampling_rate = 0;
313 unsigned int chan_sz = 0;
314
315 /* pcm mode configuration */
316 switch (snd_pcm_format_width(params_format(params))) {
317 case 16:
318 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
319 break;
320 case 24:
321 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
322 break;
323 case 32:
324 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
325 break;
326 default:
327 dev_err(component->dev, "format unsupported %d\n",
328 params_format(params));
329 goto err;
330 }
331
332 max98927->ch_size = snd_pcm_format_width(params_format(params));
333
334 regmap_update_bits(max98927->regmap,
335 MAX98927_R0020_PCM_MODE_CFG,
336 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
337
338 dev_dbg(component->dev, "format supported %d",
339 params_format(params));
340
341 /* sampling rate configuration */
342 switch (params_rate(params)) {
343 case 8000:
344 sampling_rate = MAX98927_PCM_SR_SET1_SR_8000;
345 break;
346 case 11025:
347 sampling_rate = MAX98927_PCM_SR_SET1_SR_11025;
348 break;
349 case 12000:
350 sampling_rate = MAX98927_PCM_SR_SET1_SR_12000;
351 break;
352 case 16000:
353 sampling_rate = MAX98927_PCM_SR_SET1_SR_16000;
354 break;
355 case 22050:
356 sampling_rate = MAX98927_PCM_SR_SET1_SR_22050;
357 break;
358 case 24000:
359 sampling_rate = MAX98927_PCM_SR_SET1_SR_24000;
360 break;
361 case 32000:
362 sampling_rate = MAX98927_PCM_SR_SET1_SR_32000;
363 break;
364 case 44100:
365 sampling_rate = MAX98927_PCM_SR_SET1_SR_44100;
366 break;
367 case 48000:
368 sampling_rate = MAX98927_PCM_SR_SET1_SR_48000;
369 break;
370 default:
371 dev_err(component->dev, "rate %d not supported\n",
372 params_rate(params));
373 goto err;
374 }
375 /* set DAI_SR to correct LRCLK frequency */
376 regmap_update_bits(max98927->regmap,
377 MAX98927_R0023_PCM_SR_SETUP1,
378 MAX98927_PCM_SR_SET1_SR_MASK,
379 sampling_rate);
380 regmap_update_bits(max98927->regmap,
381 MAX98927_R0024_PCM_SR_SETUP2,
382 MAX98927_PCM_SR_SET2_SR_MASK,
383 sampling_rate << MAX98927_PCM_SR_SET2_SR_SHIFT);
384
385 /* set sampling rate of IV */
386 if (max98927->interleave_mode &&
387 sampling_rate > MAX98927_PCM_SR_SET1_SR_16000)
388 regmap_update_bits(max98927->regmap,
389 MAX98927_R0024_PCM_SR_SETUP2,
390 MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
391 sampling_rate - 3);
392 else
393 regmap_update_bits(max98927->regmap,
394 MAX98927_R0024_PCM_SR_SETUP2,
395 MAX98927_PCM_SR_SET2_IVADC_SR_MASK,
396 sampling_rate);
397 return max98927_set_clock(max98927, params);
398err:
399 return -EINVAL;
400}
401
402static int max98927_dai_tdm_slot(struct snd_soc_dai *dai,
403 unsigned int tx_mask, unsigned int rx_mask,
404 int slots, int slot_width)
405{
406 struct snd_soc_component *component = dai->component;
407 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
408 int bsel = 0;
409 unsigned int chan_sz = 0;
410
411 max98927->tdm_mode = true;
412
413 /* BCLK configuration */
414 bsel = max98927_get_bclk_sel(slots * slot_width);
415 if (bsel == 0) {
416 dev_err(component->dev, "BCLK %d not supported\n",
417 slots * slot_width);
418 return -EINVAL;
419 }
420
421 regmap_update_bits(max98927->regmap,
422 MAX98927_R0022_PCM_CLK_SETUP,
423 MAX98927_PCM_CLK_SETUP_BSEL_MASK,
424 bsel);
425
426 /* Channel size configuration */
427 switch (slot_width) {
428 case 16:
429 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_16;
430 break;
431 case 24:
432 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_24;
433 break;
434 case 32:
435 chan_sz = MAX98927_PCM_MODE_CFG_CHANSZ_32;
436 break;
437 default:
438 dev_err(component->dev, "format unsupported %d\n",
439 slot_width);
440 return -EINVAL;
441 }
442
443 regmap_update_bits(max98927->regmap,
444 MAX98927_R0020_PCM_MODE_CFG,
445 MAX98927_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
446
447 /* Rx slot configuration */
448 regmap_write(max98927->regmap,
449 MAX98927_R0018_PCM_RX_EN_A,
450 rx_mask & 0xFF);
451 regmap_write(max98927->regmap,
452 MAX98927_R0019_PCM_RX_EN_B,
453 (rx_mask & 0xFF00) >> 8);
454
455 /* Tx slot configuration */
456 regmap_write(max98927->regmap,
457 MAX98927_R001A_PCM_TX_EN_A,
458 tx_mask & 0xFF);
459 regmap_write(max98927->regmap,
460 MAX98927_R001B_PCM_TX_EN_B,
461 (tx_mask & 0xFF00) >> 8);
462
463 /* Tx slot Hi-Z configuration */
464 regmap_write(max98927->regmap,
465 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
466 ~tx_mask & 0xFF);
467 regmap_write(max98927->regmap,
468 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
469 (~tx_mask & 0xFF00) >> 8);
470
471 return 0;
472}
473
474#define MAX98927_RATES SNDRV_PCM_RATE_8000_48000
475
476#define MAX98927_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
477 SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
478
479static int max98927_dai_set_sysclk(struct snd_soc_dai *dai,
480 int clk_id, unsigned int freq, int dir)
481{
482 struct snd_soc_component *component = dai->component;
483 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
484
485 max98927->sysclk = freq;
486 return 0;
487}
488
489static const struct snd_soc_dai_ops max98927_dai_ops = {
490 .set_sysclk = max98927_dai_set_sysclk,
491 .set_fmt = max98927_dai_set_fmt,
492 .hw_params = max98927_dai_hw_params,
493 .set_tdm_slot = max98927_dai_tdm_slot,
494};
495
496static int max98927_dac_event(struct snd_soc_dapm_widget *w,
497 struct snd_kcontrol *kcontrol, int event)
498{
499 struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
500 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
501
502 switch (event) {
503 case SND_SOC_DAPM_PRE_PMU:
504 max98927->tdm_mode = false;
505 break;
506 case SND_SOC_DAPM_POST_PMU:
507 regmap_update_bits(max98927->regmap,
508 MAX98927_R003A_AMP_EN,
509 MAX98927_AMP_EN_MASK, 1);
510 regmap_update_bits(max98927->regmap,
511 MAX98927_R00FF_GLOBAL_SHDN,
512 MAX98927_GLOBAL_EN_MASK, 1);
513 break;
514 case SND_SOC_DAPM_POST_PMD:
515 regmap_update_bits(max98927->regmap,
516 MAX98927_R00FF_GLOBAL_SHDN,
517 MAX98927_GLOBAL_EN_MASK, 0);
518 regmap_update_bits(max98927->regmap,
519 MAX98927_R003A_AMP_EN,
520 MAX98927_AMP_EN_MASK, 0);
521 break;
522 default:
523 return 0;
524 }
525 return 0;
526}
527
528static const char * const max98927_switch_text[] = {
529 "Left", "Right", "LeftRight"};
530
531static const struct soc_enum dai_sel_enum =
532 SOC_ENUM_SINGLE(MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
533 MAX98927_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
534 3, max98927_switch_text);
535
536static const struct snd_kcontrol_new max98927_dai_controls =
537 SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
538
539static const struct snd_kcontrol_new max98927_vi_control =
540 SOC_DAPM_SINGLE("Switch", MAX98927_R003F_MEAS_DSP_CFG, 2, 1, 0);
541
542static const struct snd_soc_dapm_widget max98927_dapm_widgets[] = {
543 SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback", MAX98927_R003A_AMP_EN,
544 0, 0, max98927_dac_event,
545 SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
546 SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
547 &max98927_dai_controls),
548 SND_SOC_DAPM_OUTPUT("BE_OUT"),
549 SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
550 MAX98927_R003E_MEAS_EN, 0, 0),
551 SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
552 MAX98927_R003E_MEAS_EN, 1, 0),
553 SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
554 &max98927_vi_control),
555 SND_SOC_DAPM_SIGGEN("VMON"),
556 SND_SOC_DAPM_SIGGEN("IMON"),
557};
558
559static DECLARE_TLV_DB_SCALE(max98927_spk_tlv, 300, 300, 0);
560static DECLARE_TLV_DB_SCALE(max98927_digital_tlv, -1600, 25, 0);
561
562static bool max98927_readable_register(struct device *dev, unsigned int reg)
563{
564 switch (reg) {
565 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0028_ICC_RX_EN_B:
566 case MAX98927_R002B_ICC_TX_EN_A ... MAX98927_R002C_ICC_TX_EN_B:
567 case MAX98927_R002E_ICC_HIZ_MANUAL_MODE
568 ... MAX98927_R004E_MEAS_ADC_CH2_READ:
569 case MAX98927_R0051_BROWNOUT_STATUS
570 ... MAX98927_R0055_BROWNOUT_LVL_HOLD:
571 case MAX98927_R005A_BROWNOUT_LVL1_THRESH
572 ... MAX98927_R0061_BROWNOUT_AMP1_CLIP_MODE:
573 case MAX98927_R0072_BROWNOUT_LVL1_CUR_LIMIT
574 ... MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
575 case MAX98927_R00FF_GLOBAL_SHDN:
576 case MAX98927_R0100_SOFT_RESET:
577 case MAX98927_R01FF_REV_ID:
578 return true;
579 default:
580 return false;
581 }
582};
583
584static bool max98927_volatile_reg(struct device *dev, unsigned int reg)
585{
586 switch (reg) {
587 case MAX98927_R0001_INT_RAW1 ... MAX98927_R0009_INT_FLAG3:
588 case MAX98927_R004C_MEAS_ADC_CH0_READ:
589 case MAX98927_R004D_MEAS_ADC_CH1_READ:
590 case MAX98927_R004E_MEAS_ADC_CH2_READ:
591 case MAX98927_R0051_BROWNOUT_STATUS:
592 case MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ:
593 case MAX98927_R01FF_REV_ID:
594 case MAX98927_R0100_SOFT_RESET:
595 return true;
596 default:
597 return false;
598 }
599}
600
601static const char * const max98927_boost_voltage_text[] = {
602 "6.5V", "6.625V", "6.75V", "6.875V", "7V", "7.125V", "7.25V", "7.375V",
603 "7.5V", "7.625V", "7.75V", "7.875V", "8V", "8.125V", "8.25V", "8.375V",
604 "8.5V", "8.625V", "8.75V", "8.875V", "9V", "9.125V", "9.25V", "9.375V",
605 "9.5V", "9.625V", "9.75V", "9.875V", "10V"
606};
607
608static SOC_ENUM_SINGLE_DECL(max98927_boost_voltage,
609 MAX98927_R0040_BOOST_CTRL0, 0,
610 max98927_boost_voltage_text);
611
612static const char * const max98927_current_limit_text[] = {
613 "1.00A", "1.10A", "1.20A", "1.30A", "1.40A", "1.50A", "1.60A", "1.70A",
614 "1.80A", "1.90A", "2.00A", "2.10A", "2.20A", "2.30A", "2.40A", "2.50A",
615 "2.60A", "2.70A", "2.80A", "2.90A", "3.00A", "3.10A", "3.20A", "3.30A",
616 "3.40A", "3.50A", "3.60A", "3.70A", "3.80A", "3.90A", "4.00A", "4.10A"
617};
618
619static SOC_ENUM_SINGLE_DECL(max98927_current_limit,
620 MAX98927_R0042_BOOST_CTRL1, 1,
621 max98927_current_limit_text);
622
623static const struct snd_kcontrol_new max98927_snd_controls[] = {
624 SOC_SINGLE_TLV("Speaker Volume", MAX98927_R003C_SPK_GAIN,
625 0, 6, 0,
626 max98927_spk_tlv),
627 SOC_SINGLE_TLV("Digital Volume", MAX98927_R0036_AMP_VOL_CTRL,
628 0, (1<<MAX98927_AMP_VOL_WIDTH)-1, 0,
629 max98927_digital_tlv),
630 SOC_SINGLE("Amp DSP Switch", MAX98927_R0052_BROWNOUT_EN,
631 MAX98927_BROWNOUT_DSP_SHIFT, 1, 0),
632 SOC_SINGLE("Ramp Switch", MAX98927_R0037_AMP_DSP_CFG,
633 MAX98927_AMP_DSP_CFG_RMP_SHIFT, 1, 0),
634 SOC_SINGLE("DRE Switch", MAX98927_R0039_DRE_CTRL,
635 MAX98927_DRE_EN_SHIFT, 1, 0),
636 SOC_SINGLE("Volume Location Switch", MAX98927_R0036_AMP_VOL_CTRL,
637 MAX98927_AMP_VOL_SEL_SHIFT, 1, 0),
638 SOC_ENUM("Boost Output Voltage", max98927_boost_voltage),
639 SOC_ENUM("Current Limit", max98927_current_limit),
640};
641
642static const struct snd_soc_dapm_route max98927_audio_map[] = {
643 /* Plabyack */
644 {"DAI Sel Mux", "Left", "Amp Enable"},
645 {"DAI Sel Mux", "Right", "Amp Enable"},
646 {"DAI Sel Mux", "LeftRight", "Amp Enable"},
647 {"BE_OUT", NULL, "DAI Sel Mux"},
648 /* Capture */
649 { "VI Sense", "Switch", "VMON" },
650 { "VI Sense", "Switch", "IMON" },
651 { "Voltage Sense", NULL, "VI Sense" },
652 { "Current Sense", NULL, "VI Sense" },
653};
654
655static struct snd_soc_dai_driver max98927_dai[] = {
656 {
657 .name = "max98927-aif1",
658 .playback = {
659 .stream_name = "HiFi Playback",
660 .channels_min = 1,
661 .channels_max = 2,
662 .rates = MAX98927_RATES,
663 .formats = MAX98927_FORMATS,
664 },
665 .capture = {
666 .stream_name = "HiFi Capture",
667 .channels_min = 1,
668 .channels_max = 2,
669 .rates = MAX98927_RATES,
670 .formats = MAX98927_FORMATS,
671 },
672 .ops = &max98927_dai_ops,
673 }
674};
675
676static int max98927_probe(struct snd_soc_component *component)
677{
678 struct max98927_priv *max98927 = snd_soc_component_get_drvdata(component);
679
680 max98927->component = component;
681
682 /* Software Reset */
683 regmap_write(max98927->regmap,
684 MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
685
686 /* IV default slot configuration */
687 regmap_write(max98927->regmap,
688 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
689 0xFF);
690 regmap_write(max98927->regmap,
691 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
692 0xFF);
693 regmap_write(max98927->regmap,
694 MAX98927_R0025_PCM_TO_SPK_MONOMIX_A,
695 0x80);
696 regmap_write(max98927->regmap,
697 MAX98927_R0026_PCM_TO_SPK_MONOMIX_B,
698 0x1);
699 /* Set inital volume (+13dB) */
700 regmap_write(max98927->regmap,
701 MAX98927_R0036_AMP_VOL_CTRL,
702 0x38);
703 regmap_write(max98927->regmap,
704 MAX98927_R003C_SPK_GAIN,
705 0x05);
706 /* Enable DC blocker */
707 regmap_write(max98927->regmap,
708 MAX98927_R0037_AMP_DSP_CFG,
709 0x03);
710 /* Enable IMON VMON DC blocker */
711 regmap_write(max98927->regmap,
712 MAX98927_R003F_MEAS_DSP_CFG,
713 0xF7);
714 /* Boost Output Voltage & Current limit */
715 regmap_write(max98927->regmap,
716 MAX98927_R0040_BOOST_CTRL0,
717 0x1C);
718 regmap_write(max98927->regmap,
719 MAX98927_R0042_BOOST_CTRL1,
720 0x3E);
721 /* Measurement ADC config */
722 regmap_write(max98927->regmap,
723 MAX98927_R0043_MEAS_ADC_CFG,
724 0x04);
725 regmap_write(max98927->regmap,
726 MAX98927_R0044_MEAS_ADC_BASE_MSB,
727 0x00);
728 regmap_write(max98927->regmap,
729 MAX98927_R0045_MEAS_ADC_BASE_LSB,
730 0x24);
731 /* Brownout Level */
732 regmap_write(max98927->regmap,
733 MAX98927_R007F_BROWNOUT_LVL4_AMP1_CTRL1,
734 0x06);
735 /* Envelope Tracking configuration */
736 regmap_write(max98927->regmap,
737 MAX98927_R0082_ENV_TRACK_VOUT_HEADROOM,
738 0x08);
739 regmap_write(max98927->regmap,
740 MAX98927_R0086_ENV_TRACK_CTRL,
741 0x01);
742 regmap_write(max98927->regmap,
743 MAX98927_R0087_ENV_TRACK_BOOST_VOUT_READ,
744 0x10);
745
746 /* voltage, current slot configuration */
747 regmap_write(max98927->regmap,
748 MAX98927_R001E_PCM_TX_CH_SRC_A,
749 (max98927->i_l_slot<<MAX98927_PCM_TX_CH_SRC_A_I_SHIFT|
750 max98927->v_l_slot)&0xFF);
751
752 if (max98927->v_l_slot < 8) {
753 regmap_update_bits(max98927->regmap,
754 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
755 1 << max98927->v_l_slot, 0);
756 regmap_update_bits(max98927->regmap,
757 MAX98927_R001A_PCM_TX_EN_A,
758 1 << max98927->v_l_slot,
759 1 << max98927->v_l_slot);
760 } else {
761 regmap_update_bits(max98927->regmap,
762 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
763 1 << (max98927->v_l_slot - 8), 0);
764 regmap_update_bits(max98927->regmap,
765 MAX98927_R001B_PCM_TX_EN_B,
766 1 << (max98927->v_l_slot - 8),
767 1 << (max98927->v_l_slot - 8));
768 }
769
770 if (max98927->i_l_slot < 8) {
771 regmap_update_bits(max98927->regmap,
772 MAX98927_R001C_PCM_TX_HIZ_CTRL_A,
773 1 << max98927->i_l_slot, 0);
774 regmap_update_bits(max98927->regmap,
775 MAX98927_R001A_PCM_TX_EN_A,
776 1 << max98927->i_l_slot,
777 1 << max98927->i_l_slot);
778 } else {
779 regmap_update_bits(max98927->regmap,
780 MAX98927_R001D_PCM_TX_HIZ_CTRL_B,
781 1 << (max98927->i_l_slot - 8), 0);
782 regmap_update_bits(max98927->regmap,
783 MAX98927_R001B_PCM_TX_EN_B,
784 1 << (max98927->i_l_slot - 8),
785 1 << (max98927->i_l_slot - 8));
786 }
787
788 /* Set interleave mode */
789 if (max98927->interleave_mode)
790 regmap_update_bits(max98927->regmap,
791 MAX98927_R001F_PCM_TX_CH_SRC_B,
792 MAX98927_PCM_TX_CH_INTERLEAVE_MASK,
793 MAX98927_PCM_TX_CH_INTERLEAVE_MASK);
794 return 0;
795}
796
797#ifdef CONFIG_PM_SLEEP
798static int max98927_suspend(struct device *dev)
799{
800 struct max98927_priv *max98927 = dev_get_drvdata(dev);
801
802 regcache_cache_only(max98927->regmap, true);
803 regcache_mark_dirty(max98927->regmap);
804 return 0;
805}
806static int max98927_resume(struct device *dev)
807{
808 struct max98927_priv *max98927 = dev_get_drvdata(dev);
809
810 regmap_write(max98927->regmap,
811 MAX98927_R0100_SOFT_RESET, MAX98927_SOFT_RESET);
812 regcache_cache_only(max98927->regmap, false);
813 regcache_sync(max98927->regmap);
814 return 0;
815}
816#endif
817
818static const struct dev_pm_ops max98927_pm = {
819 SET_SYSTEM_SLEEP_PM_OPS(max98927_suspend, max98927_resume)
820};
821
822static const struct snd_soc_component_driver soc_component_dev_max98927 = {
823 .probe = max98927_probe,
824 .controls = max98927_snd_controls,
825 .num_controls = ARRAY_SIZE(max98927_snd_controls),
826 .dapm_widgets = max98927_dapm_widgets,
827 .num_dapm_widgets = ARRAY_SIZE(max98927_dapm_widgets),
828 .dapm_routes = max98927_audio_map,
829 .num_dapm_routes = ARRAY_SIZE(max98927_audio_map),
830 .idle_bias_on = 1,
831 .use_pmdown_time = 1,
832 .endianness = 1,
833 .non_legacy_dai_naming = 1,
834};
835
836static const struct regmap_config max98927_regmap = {
837 .reg_bits = 16,
838 .val_bits = 8,
839 .max_register = MAX98927_R01FF_REV_ID,
840 .reg_defaults = max98927_reg,
841 .num_reg_defaults = ARRAY_SIZE(max98927_reg),
842 .readable_reg = max98927_readable_register,
843 .volatile_reg = max98927_volatile_reg,
844 .cache_type = REGCACHE_RBTREE,
845};
846
847static void max98927_slot_config(struct i2c_client *i2c,
848 struct max98927_priv *max98927)
849{
850 int value;
851 struct device *dev = &i2c->dev;
852
853 if (!device_property_read_u32(dev, "vmon-slot-no", &value))
854 max98927->v_l_slot = value & 0xF;
855 else
856 max98927->v_l_slot = 0;
857
858 if (!device_property_read_u32(dev, "imon-slot-no", &value))
859 max98927->i_l_slot = value & 0xF;
860 else
861 max98927->i_l_slot = 1;
862}
863
864static int max98927_i2c_probe(struct i2c_client *i2c,
865 const struct i2c_device_id *id)
866{
867
868 int ret = 0, value;
869 int reg = 0;
870 struct max98927_priv *max98927 = NULL;
871
872 max98927 = devm_kzalloc(&i2c->dev,
873 sizeof(*max98927), GFP_KERNEL);
874
875 if (!max98927) {
876 ret = -ENOMEM;
877 return ret;
878 }
879 i2c_set_clientdata(i2c, max98927);
880
881 /* update interleave mode info */
882 if (!of_property_read_u32(i2c->dev.of_node,
883 "interleave_mode", &value)) {
884 if (value > 0)
885 max98927->interleave_mode = true;
886 else
887 max98927->interleave_mode = false;
888 } else
889 max98927->interleave_mode = false;
890
891 /* regmap initialization */
892 max98927->regmap
893 = devm_regmap_init_i2c(i2c, &max98927_regmap);
894 if (IS_ERR(max98927->regmap)) {
895 ret = PTR_ERR(max98927->regmap);
896 dev_err(&i2c->dev,
897 "Failed to allocate regmap: %d\n", ret);
898 return ret;
899 }
900
901 /* Check Revision ID */
902 ret = regmap_read(max98927->regmap,
903 MAX98927_R01FF_REV_ID, ®);
904 if (ret < 0) {
905 dev_err(&i2c->dev,
906 "Failed to read: 0x%02X\n", MAX98927_R01FF_REV_ID);
907 return ret;
908 }
909 dev_info(&i2c->dev, "MAX98927 revisionID: 0x%02X\n", reg);
910
911 /* voltage/current slot configuration */
912 max98927_slot_config(i2c, max98927);
913
914 /* codec registeration */
915 ret = devm_snd_soc_register_component(&i2c->dev,
916 &soc_component_dev_max98927,
917 max98927_dai, ARRAY_SIZE(max98927_dai));
918 if (ret < 0)
919 dev_err(&i2c->dev, "Failed to register component: %d\n", ret);
920
921 return ret;
922}
923
924static const struct i2c_device_id max98927_i2c_id[] = {
925 { "max98927", 0},
926 { },
927};
928
929MODULE_DEVICE_TABLE(i2c, max98927_i2c_id);
930
931#if defined(CONFIG_OF)
932static const struct of_device_id max98927_of_match[] = {
933 { .compatible = "maxim,max98927", },
934 { }
935};
936MODULE_DEVICE_TABLE(of, max98927_of_match);
937#endif
938
939#ifdef CONFIG_ACPI
940static const struct acpi_device_id max98927_acpi_match[] = {
941 { "MX98927", 0 },
942 {},
943};
944MODULE_DEVICE_TABLE(acpi, max98927_acpi_match);
945#endif
946
947static struct i2c_driver max98927_i2c_driver = {
948 .driver = {
949 .name = "max98927",
950 .of_match_table = of_match_ptr(max98927_of_match),
951 .acpi_match_table = ACPI_PTR(max98927_acpi_match),
952 .pm = &max98927_pm,
953 },
954 .probe = max98927_i2c_probe,
955 .id_table = max98927_i2c_id,
956};
957
958module_i2c_driver(max98927_i2c_driver)
959
960MODULE_DESCRIPTION("ALSA SoC MAX98927 driver");
961MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
962MODULE_LICENSE("GPL");