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1/*
2 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
3 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
4 * Takashi Iwai <tiwai@suse.de>
5 *
6 * Most of the driver code comes from Zach Brown(zab@redhat.com)
7 * Alan Cox OSS Driver
8 * Rewritted from card-es1938.c source.
9 *
10 * TODO:
11 * Perhaps Synth
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 *
27 *
28 * Notes from Zach Brown about the driver code
29 *
30 * Hardware Description
31 *
32 * A working Maestro setup contains the Maestro chip wired to a
33 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
34 * Wavecache. The APUs can be though of as virtual audio routing
35 * channels. They can take data from a number of sources and perform
36 * basic encodings of the data. The wavecache is a storehouse for
37 * PCM data. Typically it deals with PCI and interracts with the
38 * APUs. The ASSP is a wacky DSP like device that ESS is loth
39 * to release docs on. Thankfully it isn't required on the Maestro
40 * until you start doing insane things like FM emulation and surround
41 * encoding. The codecs are almost always AC-97 compliant codecs,
42 * but it appears that early Maestros may have had PT101 (an ESS
43 * part?) wired to them. The only real difference in the Maestro
44 * families is external goop like docking capability, memory for
45 * the ASSP, and initialization differences.
46 *
47 * Driver Operation
48 *
49 * We only drive the APU/Wavecache as typical DACs and drive the
50 * mixers in the codecs. There are 64 APUs. We assign 6 to each
51 * /dev/dsp? device. 2 channels for output, and 4 channels for
52 * input.
53 *
54 * Each APU can do a number of things, but we only really use
55 * 3 basic functions. For playback we use them to convert PCM
56 * data fetched over PCI by the wavecahche into analog data that
57 * is handed to the codec. One APU for mono, and a pair for stereo.
58 * When in stereo, the combination of smarts in the APU and Wavecache
59 * decide which wavecache gets the left or right channel.
60 *
61 * For record we still use the old overly mono system. For each in
62 * coming channel the data comes in from the codec, through a 'input'
63 * APU, through another rate converter APU, and then into memory via
64 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
65 * software. The pass between the 2 APUs is supposedly what requires us
66 * to have a 512 byte buffer sitting around in wavecache/memory.
67 *
68 * The wavecache makes our life even more fun. First off, it can
69 * only address the first 28 bits of PCI address space, making it
70 * useless on quite a few architectures. Secondly, its insane.
71 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
72 * But that doesn't really work. You can only use 1 region. So all our
73 * allocations have to be in 4meg of each other. Booo. Hiss.
74 * So we have a module parameter, dsps_order, that is the order of
75 * the number of dsps to provide. All their buffer space is allocated
76 * on open time. The sonicvibes OSS routines we inherited really want
77 * power of 2 buffers, so we have all those next to each other, then
78 * 512 byte regions for the recording wavecaches. This ends up
79 * wasting quite a bit of memory. The only fixes I can see would be
80 * getting a kernel allocator that could work in zones, or figuring out
81 * just how to coerce the WP into doing what we want.
82 *
83 * The indirection of the various registers means we have to spinlock
84 * nearly all register accesses. We have the main register indirection
85 * like the wave cache, maestro registers, etc. Then we have beasts
86 * like the APU interface that is indirect registers gotten at through
87 * the main maestro indirection. Ouch. We spinlock around the actual
88 * ports on a per card basis. This means spinlock activity at each IO
89 * operation, but the only IO operation clusters are in non critical
90 * paths and it makes the code far easier to follow. Interrupts are
91 * blocked while holding the locks because the int handler has to
92 * get at some of them :(. The mixer interface doesn't, however.
93 * We also have an OSS state lock that is thrown around in a few
94 * places.
95 */
96
97#include <linux/io.h>
98#include <linux/delay.h>
99#include <linux/interrupt.h>
100#include <linux/init.h>
101#include <linux/pci.h>
102#include <linux/dma-mapping.h>
103#include <linux/slab.h>
104#include <linux/gameport.h>
105#include <linux/module.h>
106#include <linux/mutex.h>
107#include <linux/input.h>
108
109#include <sound/core.h>
110#include <sound/pcm.h>
111#include <sound/mpu401.h>
112#include <sound/ac97_codec.h>
113#include <sound/initval.h>
114
115#ifdef CONFIG_SND_ES1968_RADIO
116#include <media/drv-intf/tea575x.h>
117#endif
118
119#define CARD_NAME "ESS Maestro1/2"
120#define DRIVER_NAME "ES1968"
121
122MODULE_DESCRIPTION("ESS Maestro");
123MODULE_LICENSE("GPL");
124MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
125 "{ESS,Maestro 2},"
126 "{ESS,Maestro 1},"
127 "{TerraTec,DMX}}");
128
129#if IS_REACHABLE(CONFIG_GAMEPORT)
130#define SUPPORT_JOYSTICK 1
131#endif
132
133static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
134static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
135static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
136static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
137static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
138static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
139static int clock[SNDRV_CARDS];
140static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
141static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
142#ifdef SUPPORT_JOYSTICK
143static bool joystick[SNDRV_CARDS];
144#endif
145static int radio_nr[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
146
147module_param_array(index, int, NULL, 0444);
148MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
149module_param_array(id, charp, NULL, 0444);
150MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
151module_param_array(enable, bool, NULL, 0444);
152MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
153module_param_array(total_bufsize, int, NULL, 0444);
154MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
155module_param_array(pcm_substreams_p, int, NULL, 0444);
156MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
157module_param_array(pcm_substreams_c, int, NULL, 0444);
158MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
159module_param_array(clock, int, NULL, 0444);
160MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
161module_param_array(use_pm, int, NULL, 0444);
162MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
163module_param_array(enable_mpu, int, NULL, 0444);
164MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
165#ifdef SUPPORT_JOYSTICK
166module_param_array(joystick, bool, NULL, 0444);
167MODULE_PARM_DESC(joystick, "Enable joystick.");
168#endif
169module_param_array(radio_nr, int, NULL, 0444);
170MODULE_PARM_DESC(radio_nr, "Radio device numbers");
171
172
173
174#define NR_APUS 64
175#define NR_APU_REGS 16
176
177/* NEC Versas ? */
178#define NEC_VERSA_SUBID1 0x80581033
179#define NEC_VERSA_SUBID2 0x803c1033
180
181/* Mode Flags */
182#define ESS_FMT_STEREO 0x01
183#define ESS_FMT_16BIT 0x02
184
185#define DAC_RUNNING 1
186#define ADC_RUNNING 2
187
188/* Values for the ESM_LEGACY_AUDIO_CONTROL */
189
190#define ESS_DISABLE_AUDIO 0x8000
191#define ESS_ENABLE_SERIAL_IRQ 0x4000
192#define IO_ADRESS_ALIAS 0x0020
193#define MPU401_IRQ_ENABLE 0x0010
194#define MPU401_IO_ENABLE 0x0008
195#define GAME_IO_ENABLE 0x0004
196#define FM_IO_ENABLE 0x0002
197#define SB_IO_ENABLE 0x0001
198
199/* Values for the ESM_CONFIG_A */
200
201#define PIC_SNOOP1 0x4000
202#define PIC_SNOOP2 0x2000
203#define SAFEGUARD 0x0800
204#define DMA_CLEAR 0x0700
205#define DMA_DDMA 0x0000
206#define DMA_TDMA 0x0100
207#define DMA_PCPCI 0x0200
208#define POST_WRITE 0x0080
209#define PCI_TIMING 0x0040
210#define SWAP_LR 0x0020
211#define SUBTR_DECODE 0x0002
212
213/* Values for the ESM_CONFIG_B */
214
215#define SPDIF_CONFB 0x0100
216#define HWV_CONFB 0x0080
217#define DEBOUNCE 0x0040
218#define GPIO_CONFB 0x0020
219#define CHI_CONFB 0x0010
220#define IDMA_CONFB 0x0008 /*undoc */
221#define MIDI_FIX 0x0004 /*undoc */
222#define IRQ_TO_ISA 0x0001 /*undoc */
223
224/* Values for Ring Bus Control B */
225#define RINGB_2CODEC_ID_MASK 0x0003
226#define RINGB_DIS_VALIDATION 0x0008
227#define RINGB_EN_SPDIF 0x0010
228#define RINGB_EN_2CODEC 0x0020
229#define RINGB_SING_BIT_DUAL 0x0040
230
231/* ****Port Addresses**** */
232
233/* Write & Read */
234#define ESM_INDEX 0x02
235#define ESM_DATA 0x00
236
237/* AC97 + RingBus */
238#define ESM_AC97_INDEX 0x30
239#define ESM_AC97_DATA 0x32
240#define ESM_RING_BUS_DEST 0x34
241#define ESM_RING_BUS_CONTR_A 0x36
242#define ESM_RING_BUS_CONTR_B 0x38
243#define ESM_RING_BUS_SDO 0x3A
244
245/* WaveCache*/
246#define WC_INDEX 0x10
247#define WC_DATA 0x12
248#define WC_CONTROL 0x14
249
250/* ASSP*/
251#define ASSP_INDEX 0x80
252#define ASSP_MEMORY 0x82
253#define ASSP_DATA 0x84
254#define ASSP_CONTROL_A 0xA2
255#define ASSP_CONTROL_B 0xA4
256#define ASSP_CONTROL_C 0xA6
257#define ASSP_HOSTW_INDEX 0xA8
258#define ASSP_HOSTW_DATA 0xAA
259#define ASSP_HOSTW_IRQ 0xAC
260/* Midi */
261#define ESM_MPU401_PORT 0x98
262/* Others */
263#define ESM_PORT_HOST_IRQ 0x18
264
265#define IDR0_DATA_PORT 0x00
266#define IDR1_CRAM_POINTER 0x01
267#define IDR2_CRAM_DATA 0x02
268#define IDR3_WAVE_DATA 0x03
269#define IDR4_WAVE_PTR_LOW 0x04
270#define IDR5_WAVE_PTR_HI 0x05
271#define IDR6_TIMER_CTRL 0x06
272#define IDR7_WAVE_ROMRAM 0x07
273
274#define WRITEABLE_MAP 0xEFFFFF
275#define READABLE_MAP 0x64003F
276
277/* PCI Register */
278
279#define ESM_LEGACY_AUDIO_CONTROL 0x40
280#define ESM_ACPI_COMMAND 0x54
281#define ESM_CONFIG_A 0x50
282#define ESM_CONFIG_B 0x52
283#define ESM_DDMA 0x60
284
285/* Bob Bits */
286#define ESM_BOB_ENABLE 0x0001
287#define ESM_BOB_START 0x0001
288
289/* Host IRQ Control Bits */
290#define ESM_RESET_MAESTRO 0x8000
291#define ESM_RESET_DIRECTSOUND 0x4000
292#define ESM_HIRQ_ClkRun 0x0100
293#define ESM_HIRQ_HW_VOLUME 0x0040
294#define ESM_HIRQ_HARPO 0x0030 /* What's that? */
295#define ESM_HIRQ_ASSP 0x0010
296#define ESM_HIRQ_DSIE 0x0004
297#define ESM_HIRQ_MPU401 0x0002
298#define ESM_HIRQ_SB 0x0001
299
300/* Host IRQ Status Bits */
301#define ESM_MPU401_IRQ 0x02
302#define ESM_SB_IRQ 0x01
303#define ESM_SOUND_IRQ 0x04
304#define ESM_ASSP_IRQ 0x10
305#define ESM_HWVOL_IRQ 0x40
306
307#define ESS_SYSCLK 50000000
308#define ESM_BOB_FREQ 200
309#define ESM_BOB_FREQ_MAX 800
310
311#define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
312#define ESM_FREQ_ESM2 (50000000L / 1024L)
313
314/* APU Modes: reg 0x00, bit 4-7 */
315#define ESM_APU_MODE_SHIFT 4
316#define ESM_APU_MODE_MASK (0xf << 4)
317#define ESM_APU_OFF 0x00
318#define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
319#define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
320#define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
321#define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
322#define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
323#define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
324#define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
325#define ESM_APU_CORRELATOR 0x08 /* Correlator */
326#define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
327#define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
328#define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
329#define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
330#define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
331#define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
332#define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
333
334/* reg 0x00 */
335#define ESM_APU_FILTER_Q_SHIFT 0
336#define ESM_APU_FILTER_Q_MASK (3 << 0)
337/* APU Filtey Q Control */
338#define ESM_APU_FILTER_LESSQ 0x00
339#define ESM_APU_FILTER_MOREQ 0x03
340
341#define ESM_APU_FILTER_TYPE_SHIFT 2
342#define ESM_APU_FILTER_TYPE_MASK (3 << 2)
343#define ESM_APU_ENV_TYPE_SHIFT 8
344#define ESM_APU_ENV_TYPE_MASK (3 << 8)
345#define ESM_APU_ENV_STATE_SHIFT 10
346#define ESM_APU_ENV_STATE_MASK (3 << 10)
347#define ESM_APU_END_CURVE (1 << 12)
348#define ESM_APU_INT_ON_LOOP (1 << 13)
349#define ESM_APU_DMA_ENABLE (1 << 14)
350
351/* reg 0x02 */
352#define ESM_APU_SUBMIX_GROUP_SHIRT 0
353#define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
354#define ESM_APU_SUBMIX_MODE (1 << 3)
355#define ESM_APU_6dB (1 << 4)
356#define ESM_APU_DUAL_EFFECT (1 << 5)
357#define ESM_APU_EFFECT_CHANNELS_SHIFT 6
358#define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
359
360/* reg 0x03 */
361#define ESM_APU_STEP_SIZE_MASK 0x0fff
362
363/* reg 0x04 */
364#define ESM_APU_PHASE_SHIFT 0
365#define ESM_APU_PHASE_MASK (0xff << 0)
366#define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
367#define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
368
369/* reg 0x05 - wave start offset */
370/* reg 0x06 - wave end offset */
371/* reg 0x07 - wave loop length */
372
373/* reg 0x08 */
374#define ESM_APU_EFFECT_GAIN_SHIFT 0
375#define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
376#define ESM_APU_TREMOLO_DEPTH_SHIFT 8
377#define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
378#define ESM_APU_TREMOLO_RATE_SHIFT 12
379#define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
380
381/* reg 0x09 */
382/* bit 0-7 amplitude dest? */
383#define ESM_APU_AMPLITUDE_NOW_SHIFT 8
384#define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
385
386/* reg 0x0a */
387#define ESM_APU_POLAR_PAN_SHIFT 0
388#define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
389/* Polar Pan Control */
390#define ESM_APU_PAN_CENTER_CIRCLE 0x00
391#define ESM_APU_PAN_MIDDLE_RADIUS 0x01
392#define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
393
394#define ESM_APU_FILTER_TUNING_SHIFT 8
395#define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
396
397/* reg 0x0b */
398#define ESM_APU_DATA_SRC_A_SHIFT 0
399#define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
400#define ESM_APU_INV_POL_A (1 << 7)
401#define ESM_APU_DATA_SRC_B_SHIFT 8
402#define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
403#define ESM_APU_INV_POL_B (1 << 15)
404
405#define ESM_APU_VIBRATO_RATE_SHIFT 0
406#define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
407#define ESM_APU_VIBRATO_DEPTH_SHIFT 4
408#define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
409#define ESM_APU_VIBRATO_PHASE_SHIFT 8
410#define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
411
412/* reg 0x0c */
413#define ESM_APU_RADIUS_SELECT (1 << 6)
414
415/* APU Filter Control */
416#define ESM_APU_FILTER_2POLE_LOPASS 0x00
417#define ESM_APU_FILTER_2POLE_BANDPASS 0x01
418#define ESM_APU_FILTER_2POLE_HIPASS 0x02
419#define ESM_APU_FILTER_1POLE_LOPASS 0x03
420#define ESM_APU_FILTER_1POLE_HIPASS 0x04
421#define ESM_APU_FILTER_OFF 0x05
422
423/* APU ATFP Type */
424#define ESM_APU_ATFP_AMPLITUDE 0x00
425#define ESM_APU_ATFP_TREMELO 0x01
426#define ESM_APU_ATFP_FILTER 0x02
427#define ESM_APU_ATFP_PAN 0x03
428
429/* APU ATFP Flags */
430#define ESM_APU_ATFP_FLG_OFF 0x00
431#define ESM_APU_ATFP_FLG_WAIT 0x01
432#define ESM_APU_ATFP_FLG_DONE 0x02
433#define ESM_APU_ATFP_FLG_INPROCESS 0x03
434
435
436/* capture mixing buffer size */
437#define ESM_MEM_ALIGN 0x1000
438#define ESM_MIXBUF_SIZE 0x400
439
440#define ESM_MODE_PLAY 0
441#define ESM_MODE_CAPTURE 1
442
443
444/* APU use in the driver */
445enum snd_enum_apu_type {
446 ESM_APU_PCM_PLAY,
447 ESM_APU_PCM_CAPTURE,
448 ESM_APU_PCM_RATECONV,
449 ESM_APU_FREE
450};
451
452/* chip type */
453enum {
454 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
455};
456
457/* DMA Hack! */
458struct esm_memory {
459 struct snd_dma_buffer buf;
460 int empty; /* status */
461 struct list_head list;
462};
463
464/* Playback Channel */
465struct esschan {
466 int running;
467
468 u8 apu[4];
469 u8 apu_mode[4];
470
471 /* playback/capture pcm buffer */
472 struct esm_memory *memory;
473 /* capture mixer buffer */
474 struct esm_memory *mixbuf;
475
476 unsigned int hwptr; /* current hw pointer in bytes */
477 unsigned int count; /* sample counter in bytes */
478 unsigned int dma_size; /* total buffer size in bytes */
479 unsigned int frag_size; /* period size in bytes */
480 unsigned int wav_shift;
481 u16 base[4]; /* offset for ptr */
482
483 /* stereo/16bit flag */
484 unsigned char fmt;
485 int mode; /* playback / capture */
486
487 int bob_freq; /* required timer frequency */
488
489 struct snd_pcm_substream *substream;
490
491 /* linked list */
492 struct list_head list;
493
494#ifdef CONFIG_PM_SLEEP
495 u16 wc_map[4];
496#endif
497};
498
499struct es1968 {
500 /* Module Config */
501 int total_bufsize; /* in bytes */
502
503 int playback_streams, capture_streams;
504
505 unsigned int clock; /* clock */
506 /* for clock measurement */
507 unsigned int in_measurement: 1;
508 unsigned int measure_apu;
509 unsigned int measure_lastpos;
510 unsigned int measure_count;
511
512 /* buffer */
513 struct snd_dma_buffer dma;
514
515 /* Resources... */
516 int irq;
517 unsigned long io_port;
518 int type;
519 struct pci_dev *pci;
520 struct snd_card *card;
521 struct snd_pcm *pcm;
522 int do_pm; /* power-management enabled */
523
524 /* DMA memory block */
525 struct list_head buf_list;
526
527 /* ALSA Stuff */
528 struct snd_ac97 *ac97;
529 struct snd_rawmidi *rmidi;
530
531 spinlock_t reg_lock;
532 unsigned int in_suspend;
533
534 /* Maestro Stuff */
535 u16 maestro_map[32];
536 int bobclient; /* active timer instancs */
537 int bob_freq; /* timer frequency */
538 struct mutex memory_mutex; /* memory lock */
539
540 /* APU states */
541 unsigned char apu[NR_APUS];
542
543 /* active substreams */
544 struct list_head substream_list;
545 spinlock_t substream_lock;
546
547#ifdef CONFIG_PM_SLEEP
548 u16 apu_map[NR_APUS][NR_APU_REGS];
549#endif
550
551#ifdef SUPPORT_JOYSTICK
552 struct gameport *gameport;
553#endif
554
555#ifdef CONFIG_SND_ES1968_INPUT
556 struct input_dev *input_dev;
557 char phys[64]; /* physical device path */
558#else
559 struct snd_kcontrol *master_switch; /* for h/w volume control */
560 struct snd_kcontrol *master_volume;
561#endif
562 struct work_struct hwvol_work;
563
564#ifdef CONFIG_SND_ES1968_RADIO
565 struct v4l2_device v4l2_dev;
566 struct snd_tea575x tea;
567 unsigned int tea575x_tuner;
568#endif
569};
570
571static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id);
572
573static const struct pci_device_id snd_es1968_ids[] = {
574 /* Maestro 1 */
575 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
576 /* Maestro 2 */
577 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
578 /* Maestro 2E */
579 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
580 { 0, }
581};
582
583MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
584
585/* *********************
586 * Low Level Funcs! *
587 *********************/
588
589/* no spinlock */
590static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
591{
592 outw(reg, chip->io_port + ESM_INDEX);
593 outw(data, chip->io_port + ESM_DATA);
594 chip->maestro_map[reg] = data;
595}
596
597static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
598{
599 unsigned long flags;
600 spin_lock_irqsave(&chip->reg_lock, flags);
601 __maestro_write(chip, reg, data);
602 spin_unlock_irqrestore(&chip->reg_lock, flags);
603}
604
605/* no spinlock */
606static u16 __maestro_read(struct es1968 *chip, u16 reg)
607{
608 if (READABLE_MAP & (1 << reg)) {
609 outw(reg, chip->io_port + ESM_INDEX);
610 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
611 }
612 return chip->maestro_map[reg];
613}
614
615static inline u16 maestro_read(struct es1968 *chip, u16 reg)
616{
617 unsigned long flags;
618 u16 result;
619 spin_lock_irqsave(&chip->reg_lock, flags);
620 result = __maestro_read(chip, reg);
621 spin_unlock_irqrestore(&chip->reg_lock, flags);
622 return result;
623}
624
625/* Wait for the codec bus to be free */
626static int snd_es1968_ac97_wait(struct es1968 *chip)
627{
628 int timeout = 100000;
629
630 while (timeout-- > 0) {
631 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
632 return 0;
633 cond_resched();
634 }
635 dev_dbg(chip->card->dev, "ac97 timeout\n");
636 return 1; /* timeout */
637}
638
639static int snd_es1968_ac97_wait_poll(struct es1968 *chip)
640{
641 int timeout = 100000;
642
643 while (timeout-- > 0) {
644 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
645 return 0;
646 }
647 dev_dbg(chip->card->dev, "ac97 timeout\n");
648 return 1; /* timeout */
649}
650
651static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
652{
653 struct es1968 *chip = ac97->private_data;
654
655 snd_es1968_ac97_wait(chip);
656
657 /* Write the bus */
658 outw(val, chip->io_port + ESM_AC97_DATA);
659 /*msleep(1);*/
660 outb(reg, chip->io_port + ESM_AC97_INDEX);
661 /*msleep(1);*/
662}
663
664static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
665{
666 u16 data = 0;
667 struct es1968 *chip = ac97->private_data;
668
669 snd_es1968_ac97_wait(chip);
670
671 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
672 /*msleep(1);*/
673
674 if (!snd_es1968_ac97_wait_poll(chip)) {
675 data = inw(chip->io_port + ESM_AC97_DATA);
676 /*msleep(1);*/
677 }
678
679 return data;
680}
681
682/* no spinlock */
683static void apu_index_set(struct es1968 *chip, u16 index)
684{
685 int i;
686 __maestro_write(chip, IDR1_CRAM_POINTER, index);
687 for (i = 0; i < 1000; i++)
688 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
689 return;
690 dev_dbg(chip->card->dev, "APU register select failed. (Timeout)\n");
691}
692
693/* no spinlock */
694static void apu_data_set(struct es1968 *chip, u16 data)
695{
696 int i;
697 for (i = 0; i < 1000; i++) {
698 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
699 return;
700 __maestro_write(chip, IDR0_DATA_PORT, data);
701 }
702 dev_dbg(chip->card->dev, "APU register set probably failed (Timeout)!\n");
703}
704
705/* no spinlock */
706static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
707{
708 if (snd_BUG_ON(channel >= NR_APUS))
709 return;
710#ifdef CONFIG_PM_SLEEP
711 chip->apu_map[channel][reg] = data;
712#endif
713 reg |= (channel << 4);
714 apu_index_set(chip, reg);
715 apu_data_set(chip, data);
716}
717
718static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
719{
720 unsigned long flags;
721 spin_lock_irqsave(&chip->reg_lock, flags);
722 __apu_set_register(chip, channel, reg, data);
723 spin_unlock_irqrestore(&chip->reg_lock, flags);
724}
725
726static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
727{
728 if (snd_BUG_ON(channel >= NR_APUS))
729 return 0;
730 reg |= (channel << 4);
731 apu_index_set(chip, reg);
732 return __maestro_read(chip, IDR0_DATA_PORT);
733}
734
735static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
736{
737 unsigned long flags;
738 u16 v;
739 spin_lock_irqsave(&chip->reg_lock, flags);
740 v = __apu_get_register(chip, channel, reg);
741 spin_unlock_irqrestore(&chip->reg_lock, flags);
742 return v;
743}
744
745#if 0 /* ASSP is not supported */
746
747static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
748{
749 unsigned long flags;
750
751 spin_lock_irqsave(&chip->reg_lock, flags);
752 outl(reg, chip->io_port + ASSP_INDEX);
753 outl(value, chip->io_port + ASSP_DATA);
754 spin_unlock_irqrestore(&chip->reg_lock, flags);
755}
756
757static u32 assp_get_register(struct es1968 *chip, u32 reg)
758{
759 unsigned long flags;
760 u32 value;
761
762 spin_lock_irqsave(&chip->reg_lock, flags);
763 outl(reg, chip->io_port + ASSP_INDEX);
764 value = inl(chip->io_port + ASSP_DATA);
765 spin_unlock_irqrestore(&chip->reg_lock, flags);
766
767 return value;
768}
769
770#endif
771
772static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
773{
774 unsigned long flags;
775
776 spin_lock_irqsave(&chip->reg_lock, flags);
777 outw(reg, chip->io_port + WC_INDEX);
778 outw(value, chip->io_port + WC_DATA);
779 spin_unlock_irqrestore(&chip->reg_lock, flags);
780}
781
782static u16 wave_get_register(struct es1968 *chip, u16 reg)
783{
784 unsigned long flags;
785 u16 value;
786
787 spin_lock_irqsave(&chip->reg_lock, flags);
788 outw(reg, chip->io_port + WC_INDEX);
789 value = inw(chip->io_port + WC_DATA);
790 spin_unlock_irqrestore(&chip->reg_lock, flags);
791
792 return value;
793}
794
795/* *******************
796 * Bob the Timer! *
797 *******************/
798
799static void snd_es1968_bob_stop(struct es1968 *chip)
800{
801 u16 reg;
802
803 reg = __maestro_read(chip, 0x11);
804 reg &= ~ESM_BOB_ENABLE;
805 __maestro_write(chip, 0x11, reg);
806 reg = __maestro_read(chip, 0x17);
807 reg &= ~ESM_BOB_START;
808 __maestro_write(chip, 0x17, reg);
809}
810
811static void snd_es1968_bob_start(struct es1968 *chip)
812{
813 int prescale;
814 int divide;
815
816 /* compute ideal interrupt frequency for buffer size & play rate */
817 /* first, find best prescaler value to match freq */
818 for (prescale = 5; prescale < 12; prescale++)
819 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
820 break;
821
822 /* next, back off prescaler whilst getting divider into optimum range */
823 divide = 1;
824 while ((prescale > 5) && (divide < 32)) {
825 prescale--;
826 divide <<= 1;
827 }
828 divide >>= 1;
829
830 /* now fine-tune the divider for best match */
831 for (; divide < 31; divide++)
832 if (chip->bob_freq >
833 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
834
835 /* divide = 0 is illegal, but don't let prescale = 4! */
836 if (divide == 0) {
837 divide++;
838 if (prescale > 5)
839 prescale--;
840 } else if (divide > 1)
841 divide--;
842
843 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
844
845 /* Now set IDR 11/17 */
846 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
847 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
848}
849
850/* call with substream spinlock */
851static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
852{
853 chip->bobclient++;
854 if (chip->bobclient == 1) {
855 chip->bob_freq = freq;
856 snd_es1968_bob_start(chip);
857 } else if (chip->bob_freq < freq) {
858 snd_es1968_bob_stop(chip);
859 chip->bob_freq = freq;
860 snd_es1968_bob_start(chip);
861 }
862}
863
864/* call with substream spinlock */
865static void snd_es1968_bob_dec(struct es1968 *chip)
866{
867 chip->bobclient--;
868 if (chip->bobclient <= 0)
869 snd_es1968_bob_stop(chip);
870 else if (chip->bob_freq > ESM_BOB_FREQ) {
871 /* check reduction of timer frequency */
872 int max_freq = ESM_BOB_FREQ;
873 struct esschan *es;
874 list_for_each_entry(es, &chip->substream_list, list) {
875 if (max_freq < es->bob_freq)
876 max_freq = es->bob_freq;
877 }
878 if (max_freq != chip->bob_freq) {
879 snd_es1968_bob_stop(chip);
880 chip->bob_freq = max_freq;
881 snd_es1968_bob_start(chip);
882 }
883 }
884}
885
886static int
887snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
888 struct snd_pcm_runtime *runtime)
889{
890 /* we acquire 4 interrupts per period for precise control.. */
891 int freq = runtime->rate * 4;
892 if (es->fmt & ESS_FMT_STEREO)
893 freq <<= 1;
894 if (es->fmt & ESS_FMT_16BIT)
895 freq <<= 1;
896 freq /= es->frag_size;
897 if (freq < ESM_BOB_FREQ)
898 freq = ESM_BOB_FREQ;
899 else if (freq > ESM_BOB_FREQ_MAX)
900 freq = ESM_BOB_FREQ_MAX;
901 return freq;
902}
903
904
905/*************
906 * PCM Part *
907 *************/
908
909static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
910{
911 u32 rate = (freq << 16) / chip->clock;
912#if 0 /* XXX: do we need this? */
913 if (rate > 0x10000)
914 rate = 0x10000;
915#endif
916 return rate;
917}
918
919/* get current pointer */
920static inline unsigned int
921snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
922{
923 unsigned int offset;
924
925 offset = apu_get_register(chip, es->apu[0], 5);
926
927 offset -= es->base[0];
928
929 return (offset & 0xFFFE); /* hardware is in words */
930}
931
932static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
933{
934 apu_set_register(chip, apu, 2,
935 (apu_get_register(chip, apu, 2) & 0x00FF) |
936 ((freq & 0xff) << 8) | 0x10);
937 apu_set_register(chip, apu, 3, freq >> 8);
938}
939
940/* spin lock held */
941static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
942{
943 /* set the APU mode */
944 __apu_set_register(esm, apu, 0,
945 (__apu_get_register(esm, apu, 0) & 0xff0f) |
946 (mode << 4));
947}
948
949static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
950{
951 spin_lock(&chip->reg_lock);
952 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
953 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
954 if (es->mode == ESM_MODE_CAPTURE) {
955 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
956 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
957 }
958 if (es->fmt & ESS_FMT_STEREO) {
959 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
960 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
961 if (es->mode == ESM_MODE_CAPTURE) {
962 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
963 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
964 }
965 }
966 spin_unlock(&chip->reg_lock);
967}
968
969static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
970{
971 spin_lock(&chip->reg_lock);
972 snd_es1968_trigger_apu(chip, es->apu[0], 0);
973 snd_es1968_trigger_apu(chip, es->apu[1], 0);
974 if (es->mode == ESM_MODE_CAPTURE) {
975 snd_es1968_trigger_apu(chip, es->apu[2], 0);
976 snd_es1968_trigger_apu(chip, es->apu[3], 0);
977 }
978 spin_unlock(&chip->reg_lock);
979}
980
981/* set the wavecache control reg */
982static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
983 int channel, u32 addr, int capture)
984{
985 u32 tmpval = (addr - 0x10) & 0xFFF8;
986
987 if (! capture) {
988 if (!(es->fmt & ESS_FMT_16BIT))
989 tmpval |= 4; /* 8bit */
990 if (es->fmt & ESS_FMT_STEREO)
991 tmpval |= 2; /* stereo */
992 }
993
994 /* set the wavecache control reg */
995 wave_set_register(chip, es->apu[channel] << 3, tmpval);
996
997#ifdef CONFIG_PM_SLEEP
998 es->wc_map[channel] = tmpval;
999#endif
1000}
1001
1002
1003static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
1004 struct snd_pcm_runtime *runtime)
1005{
1006 u32 pa;
1007 int high_apu = 0;
1008 int channel, apu;
1009 int i, size;
1010 unsigned long flags;
1011 u32 freq;
1012
1013 size = es->dma_size >> es->wav_shift;
1014
1015 if (es->fmt & ESS_FMT_STEREO)
1016 high_apu++;
1017
1018 for (channel = 0; channel <= high_apu; channel++) {
1019 apu = es->apu[channel];
1020
1021 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
1022
1023 /* Offset to PCMBAR */
1024 pa = es->memory->buf.addr;
1025 pa -= chip->dma.addr;
1026 pa >>= 1; /* words */
1027
1028 pa |= 0x00400000; /* System RAM (Bit 22) */
1029
1030 if (es->fmt & ESS_FMT_STEREO) {
1031 /* Enable stereo */
1032 if (channel)
1033 pa |= 0x00800000; /* (Bit 23) */
1034 if (es->fmt & ESS_FMT_16BIT)
1035 pa >>= 1;
1036 }
1037
1038 /* base offset of dma calcs when reading the pointer
1039 on this left one */
1040 es->base[channel] = pa & 0xFFFF;
1041
1042 for (i = 0; i < 16; i++)
1043 apu_set_register(chip, apu, i, 0x0000);
1044
1045 /* Load the buffer into the wave engine */
1046 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1047 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1048 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1049 /* setting loop == sample len */
1050 apu_set_register(chip, apu, 7, size);
1051
1052 /* clear effects/env.. */
1053 apu_set_register(chip, apu, 8, 0x0000);
1054 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1055 apu_set_register(chip, apu, 9, 0xD000);
1056
1057 /* clear routing stuff */
1058 apu_set_register(chip, apu, 11, 0x0000);
1059 /* dma on, no envelopes, filter to all 1s) */
1060 apu_set_register(chip, apu, 0, 0x400F);
1061
1062 if (es->fmt & ESS_FMT_16BIT)
1063 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1064 else
1065 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1066
1067 if (es->fmt & ESS_FMT_STEREO) {
1068 /* set panning: left or right */
1069 /* Check: different panning. On my Canyon 3D Chipset the
1070 Channels are swapped. I don't know, about the output
1071 to the SPDif Link. Perhaps you have to change this
1072 and not the APU Regs 4-5. */
1073 apu_set_register(chip, apu, 10,
1074 0x8F00 | (channel ? 0 : 0x10));
1075 es->apu_mode[channel] += 1; /* stereo */
1076 } else
1077 apu_set_register(chip, apu, 10, 0x8F08);
1078 }
1079
1080 spin_lock_irqsave(&chip->reg_lock, flags);
1081 /* clear WP interrupts */
1082 outw(1, chip->io_port + 0x04);
1083 /* enable WP ints */
1084 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1085 spin_unlock_irqrestore(&chip->reg_lock, flags);
1086
1087 freq = runtime->rate;
1088 /* set frequency */
1089 if (freq > 48000)
1090 freq = 48000;
1091 if (freq < 4000)
1092 freq = 4000;
1093
1094 /* hmmm.. */
1095 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1096 freq >>= 1;
1097
1098 freq = snd_es1968_compute_rate(chip, freq);
1099
1100 /* Load the frequency, turn on 6dB */
1101 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1102 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1103}
1104
1105
1106static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
1107 unsigned int pa, unsigned int bsize,
1108 int mode, int route)
1109{
1110 int i, apu = es->apu[channel];
1111
1112 es->apu_mode[channel] = mode;
1113
1114 /* set the wavecache control reg */
1115 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1116
1117 /* Offset to PCMBAR */
1118 pa -= chip->dma.addr;
1119 pa >>= 1; /* words */
1120
1121 /* base offset of dma calcs when reading the pointer
1122 on this left one */
1123 es->base[channel] = pa & 0xFFFF;
1124 pa |= 0x00400000; /* bit 22 -> System RAM */
1125
1126 /* Begin loading the APU */
1127 for (i = 0; i < 16; i++)
1128 apu_set_register(chip, apu, i, 0x0000);
1129
1130 /* need to enable subgroups.. and we should probably
1131 have different groups for different /dev/dsps.. */
1132 apu_set_register(chip, apu, 2, 0x8);
1133
1134 /* Load the buffer into the wave engine */
1135 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1136 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1137 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1138 apu_set_register(chip, apu, 7, bsize);
1139 /* clear effects/env.. */
1140 apu_set_register(chip, apu, 8, 0x00F0);
1141 /* amplitude now? sure. why not. */
1142 apu_set_register(chip, apu, 9, 0x0000);
1143 /* set filter tune, radius, polar pan */
1144 apu_set_register(chip, apu, 10, 0x8F08);
1145 /* route input */
1146 apu_set_register(chip, apu, 11, route);
1147 /* dma on, no envelopes, filter to all 1s) */
1148 apu_set_register(chip, apu, 0, 0x400F);
1149}
1150
1151static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
1152 struct snd_pcm_runtime *runtime)
1153{
1154 int size;
1155 u32 freq;
1156 unsigned long flags;
1157
1158 size = es->dma_size >> es->wav_shift;
1159
1160 /* APU assignments:
1161 0 = mono/left SRC
1162 1 = right SRC
1163 2 = mono/left Input Mixer
1164 3 = right Input Mixer
1165 */
1166 /* data seems to flow from the codec, through an apu into
1167 the 'mixbuf' bit of page, then through the SRC apu
1168 and out to the real 'buffer'. ok. sure. */
1169
1170 /* input mixer (left/mono) */
1171 /* parallel in crap, see maestro reg 0xC [8-11] */
1172 init_capture_apu(chip, es, 2,
1173 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1174 ESM_APU_INPUTMIXER, 0x14);
1175 /* SRC (left/mono); get input from inputing apu */
1176 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1177 ESM_APU_SRCONVERTOR, es->apu[2]);
1178 if (es->fmt & ESS_FMT_STEREO) {
1179 /* input mixer (right) */
1180 init_capture_apu(chip, es, 3,
1181 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1182 ESM_MIXBUF_SIZE/4, /* in words */
1183 ESM_APU_INPUTMIXER, 0x15);
1184 /* SRC (right) */
1185 init_capture_apu(chip, es, 1,
1186 es->memory->buf.addr + size*2, size,
1187 ESM_APU_SRCONVERTOR, es->apu[3]);
1188 }
1189
1190 freq = runtime->rate;
1191 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1192 if (freq > 47999)
1193 freq = 47999;
1194 if (freq < 4000)
1195 freq = 4000;
1196
1197 freq = snd_es1968_compute_rate(chip, freq);
1198
1199 /* Load the frequency, turn on 6dB */
1200 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1201 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1202
1203 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1204 freq = 0x10000;
1205 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1206 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1207
1208 spin_lock_irqsave(&chip->reg_lock, flags);
1209 /* clear WP interrupts */
1210 outw(1, chip->io_port + 0x04);
1211 /* enable WP ints */
1212 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1213 spin_unlock_irqrestore(&chip->reg_lock, flags);
1214}
1215
1216/*******************
1217 * ALSA Interface *
1218 *******************/
1219
1220static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
1221{
1222 struct es1968 *chip = snd_pcm_substream_chip(substream);
1223 struct snd_pcm_runtime *runtime = substream->runtime;
1224 struct esschan *es = runtime->private_data;
1225
1226 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1227 es->frag_size = snd_pcm_lib_period_bytes(substream);
1228
1229 es->wav_shift = 1; /* maestro handles always 16bit */
1230 es->fmt = 0;
1231 if (snd_pcm_format_width(runtime->format) == 16)
1232 es->fmt |= ESS_FMT_16BIT;
1233 if (runtime->channels > 1) {
1234 es->fmt |= ESS_FMT_STEREO;
1235 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1236 es->wav_shift++;
1237 }
1238 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1239
1240 switch (es->mode) {
1241 case ESM_MODE_PLAY:
1242 snd_es1968_playback_setup(chip, es, runtime);
1243 break;
1244 case ESM_MODE_CAPTURE:
1245 snd_es1968_capture_setup(chip, es, runtime);
1246 break;
1247 }
1248
1249 return 0;
1250}
1251
1252static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1253{
1254 struct es1968 *chip = snd_pcm_substream_chip(substream);
1255 struct esschan *es = substream->runtime->private_data;
1256
1257 spin_lock(&chip->substream_lock);
1258 switch (cmd) {
1259 case SNDRV_PCM_TRIGGER_START:
1260 case SNDRV_PCM_TRIGGER_RESUME:
1261 if (es->running)
1262 break;
1263 snd_es1968_bob_inc(chip, es->bob_freq);
1264 es->count = 0;
1265 es->hwptr = 0;
1266 snd_es1968_pcm_start(chip, es);
1267 es->running = 1;
1268 break;
1269 case SNDRV_PCM_TRIGGER_STOP:
1270 case SNDRV_PCM_TRIGGER_SUSPEND:
1271 if (! es->running)
1272 break;
1273 snd_es1968_pcm_stop(chip, es);
1274 es->running = 0;
1275 snd_es1968_bob_dec(chip);
1276 break;
1277 }
1278 spin_unlock(&chip->substream_lock);
1279 return 0;
1280}
1281
1282static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
1283{
1284 struct es1968 *chip = snd_pcm_substream_chip(substream);
1285 struct esschan *es = substream->runtime->private_data;
1286 unsigned int ptr;
1287
1288 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1289
1290 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1291}
1292
1293static const struct snd_pcm_hardware snd_es1968_playback = {
1294 .info = (SNDRV_PCM_INFO_MMAP |
1295 SNDRV_PCM_INFO_MMAP_VALID |
1296 SNDRV_PCM_INFO_INTERLEAVED |
1297 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1298 /*SNDRV_PCM_INFO_PAUSE |*/
1299 SNDRV_PCM_INFO_RESUME),
1300 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1301 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1302 .rate_min = 4000,
1303 .rate_max = 48000,
1304 .channels_min = 1,
1305 .channels_max = 2,
1306 .buffer_bytes_max = 65536,
1307 .period_bytes_min = 256,
1308 .period_bytes_max = 65536,
1309 .periods_min = 1,
1310 .periods_max = 1024,
1311 .fifo_size = 0,
1312};
1313
1314static const struct snd_pcm_hardware snd_es1968_capture = {
1315 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1316 SNDRV_PCM_INFO_MMAP |
1317 SNDRV_PCM_INFO_MMAP_VALID |
1318 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1319 /*SNDRV_PCM_INFO_PAUSE |*/
1320 SNDRV_PCM_INFO_RESUME),
1321 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1322 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1323 .rate_min = 4000,
1324 .rate_max = 48000,
1325 .channels_min = 1,
1326 .channels_max = 2,
1327 .buffer_bytes_max = 65536,
1328 .period_bytes_min = 256,
1329 .period_bytes_max = 65536,
1330 .periods_min = 1,
1331 .periods_max = 1024,
1332 .fifo_size = 0,
1333};
1334
1335/* *************************
1336 * DMA memory management *
1337 *************************/
1338
1339/* Because the Maestro can only take addresses relative to the PCM base address
1340 register :( */
1341
1342static int calc_available_memory_size(struct es1968 *chip)
1343{
1344 int max_size = 0;
1345 struct esm_memory *buf;
1346
1347 mutex_lock(&chip->memory_mutex);
1348 list_for_each_entry(buf, &chip->buf_list, list) {
1349 if (buf->empty && buf->buf.bytes > max_size)
1350 max_size = buf->buf.bytes;
1351 }
1352 mutex_unlock(&chip->memory_mutex);
1353 if (max_size >= 128*1024)
1354 max_size = 127*1024;
1355 return max_size;
1356}
1357
1358/* allocate a new memory chunk with the specified size */
1359static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
1360{
1361 struct esm_memory *buf;
1362
1363 size = ALIGN(size, ESM_MEM_ALIGN);
1364 mutex_lock(&chip->memory_mutex);
1365 list_for_each_entry(buf, &chip->buf_list, list) {
1366 if (buf->empty && buf->buf.bytes >= size)
1367 goto __found;
1368 }
1369 mutex_unlock(&chip->memory_mutex);
1370 return NULL;
1371
1372__found:
1373 if (buf->buf.bytes > size) {
1374 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1375 if (chunk == NULL) {
1376 mutex_unlock(&chip->memory_mutex);
1377 return NULL;
1378 }
1379 chunk->buf = buf->buf;
1380 chunk->buf.bytes -= size;
1381 chunk->buf.area += size;
1382 chunk->buf.addr += size;
1383 chunk->empty = 1;
1384 buf->buf.bytes = size;
1385 list_add(&chunk->list, &buf->list);
1386 }
1387 buf->empty = 0;
1388 mutex_unlock(&chip->memory_mutex);
1389 return buf;
1390}
1391
1392/* free a memory chunk */
1393static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
1394{
1395 struct esm_memory *chunk;
1396
1397 mutex_lock(&chip->memory_mutex);
1398 buf->empty = 1;
1399 if (buf->list.prev != &chip->buf_list) {
1400 chunk = list_entry(buf->list.prev, struct esm_memory, list);
1401 if (chunk->empty) {
1402 chunk->buf.bytes += buf->buf.bytes;
1403 list_del(&buf->list);
1404 kfree(buf);
1405 buf = chunk;
1406 }
1407 }
1408 if (buf->list.next != &chip->buf_list) {
1409 chunk = list_entry(buf->list.next, struct esm_memory, list);
1410 if (chunk->empty) {
1411 buf->buf.bytes += chunk->buf.bytes;
1412 list_del(&chunk->list);
1413 kfree(chunk);
1414 }
1415 }
1416 mutex_unlock(&chip->memory_mutex);
1417}
1418
1419static void snd_es1968_free_dmabuf(struct es1968 *chip)
1420{
1421 struct list_head *p;
1422
1423 if (! chip->dma.area)
1424 return;
1425 snd_dma_free_pages(&chip->dma);
1426 while ((p = chip->buf_list.next) != &chip->buf_list) {
1427 struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
1428 list_del(p);
1429 kfree(chunk);
1430 }
1431}
1432
1433static int
1434snd_es1968_init_dmabuf(struct es1968 *chip)
1435{
1436 int err;
1437 struct esm_memory *chunk;
1438
1439 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
1440 chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
1441 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1442 snd_dma_pci_data(chip->pci),
1443 chip->total_bufsize, &chip->dma);
1444 if (err < 0 || ! chip->dma.area) {
1445 dev_err(chip->card->dev,
1446 "can't allocate dma pages for size %d\n",
1447 chip->total_bufsize);
1448 return -ENOMEM;
1449 }
1450 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1451 snd_dma_free_pages(&chip->dma);
1452 dev_err(chip->card->dev, "DMA buffer beyond 256MB.\n");
1453 return -ENOMEM;
1454 }
1455
1456 INIT_LIST_HEAD(&chip->buf_list);
1457 /* allocate an empty chunk */
1458 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1459 if (chunk == NULL) {
1460 snd_es1968_free_dmabuf(chip);
1461 return -ENOMEM;
1462 }
1463 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1464 chunk->buf = chip->dma;
1465 chunk->buf.area += ESM_MEM_ALIGN;
1466 chunk->buf.addr += ESM_MEM_ALIGN;
1467 chunk->buf.bytes -= ESM_MEM_ALIGN;
1468 chunk->empty = 1;
1469 list_add(&chunk->list, &chip->buf_list);
1470
1471 return 0;
1472}
1473
1474/* setup the dma_areas */
1475/* buffer is extracted from the pre-allocated memory chunk */
1476static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
1477 struct snd_pcm_hw_params *hw_params)
1478{
1479 struct es1968 *chip = snd_pcm_substream_chip(substream);
1480 struct snd_pcm_runtime *runtime = substream->runtime;
1481 struct esschan *chan = runtime->private_data;
1482 int size = params_buffer_bytes(hw_params);
1483
1484 if (chan->memory) {
1485 if (chan->memory->buf.bytes >= size) {
1486 runtime->dma_bytes = size;
1487 return 0;
1488 }
1489 snd_es1968_free_memory(chip, chan->memory);
1490 }
1491 chan->memory = snd_es1968_new_memory(chip, size);
1492 if (chan->memory == NULL) {
1493 dev_dbg(chip->card->dev,
1494 "cannot allocate dma buffer: size = %d\n", size);
1495 return -ENOMEM;
1496 }
1497 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1498 return 1; /* area was changed */
1499}
1500
1501/* remove dma areas if allocated */
1502static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
1503{
1504 struct es1968 *chip = snd_pcm_substream_chip(substream);
1505 struct snd_pcm_runtime *runtime = substream->runtime;
1506 struct esschan *chan;
1507
1508 if (runtime->private_data == NULL)
1509 return 0;
1510 chan = runtime->private_data;
1511 if (chan->memory) {
1512 snd_es1968_free_memory(chip, chan->memory);
1513 chan->memory = NULL;
1514 }
1515 return 0;
1516}
1517
1518
1519/*
1520 * allocate APU pair
1521 */
1522static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
1523{
1524 int apu;
1525
1526 for (apu = 0; apu < NR_APUS; apu += 2) {
1527 if (chip->apu[apu] == ESM_APU_FREE &&
1528 chip->apu[apu + 1] == ESM_APU_FREE) {
1529 chip->apu[apu] = chip->apu[apu + 1] = type;
1530 return apu;
1531 }
1532 }
1533 return -EBUSY;
1534}
1535
1536/*
1537 * release APU pair
1538 */
1539static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
1540{
1541 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1542}
1543
1544
1545/******************
1546 * PCM open/close *
1547 ******************/
1548
1549static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
1550{
1551 struct es1968 *chip = snd_pcm_substream_chip(substream);
1552 struct snd_pcm_runtime *runtime = substream->runtime;
1553 struct esschan *es;
1554 int apu1;
1555
1556 /* search 2 APUs */
1557 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1558 if (apu1 < 0)
1559 return apu1;
1560
1561 es = kzalloc(sizeof(*es), GFP_KERNEL);
1562 if (!es) {
1563 snd_es1968_free_apu_pair(chip, apu1);
1564 return -ENOMEM;
1565 }
1566
1567 es->apu[0] = apu1;
1568 es->apu[1] = apu1 + 1;
1569 es->apu_mode[0] = 0;
1570 es->apu_mode[1] = 0;
1571 es->running = 0;
1572 es->substream = substream;
1573 es->mode = ESM_MODE_PLAY;
1574
1575 runtime->private_data = es;
1576 runtime->hw = snd_es1968_playback;
1577 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1578 calc_available_memory_size(chip);
1579
1580 spin_lock_irq(&chip->substream_lock);
1581 list_add(&es->list, &chip->substream_list);
1582 spin_unlock_irq(&chip->substream_lock);
1583
1584 return 0;
1585}
1586
1587static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
1588{
1589 struct snd_pcm_runtime *runtime = substream->runtime;
1590 struct es1968 *chip = snd_pcm_substream_chip(substream);
1591 struct esschan *es;
1592 int apu1, apu2;
1593
1594 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1595 if (apu1 < 0)
1596 return apu1;
1597 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1598 if (apu2 < 0) {
1599 snd_es1968_free_apu_pair(chip, apu1);
1600 return apu2;
1601 }
1602
1603 es = kzalloc(sizeof(*es), GFP_KERNEL);
1604 if (!es) {
1605 snd_es1968_free_apu_pair(chip, apu1);
1606 snd_es1968_free_apu_pair(chip, apu2);
1607 return -ENOMEM;
1608 }
1609
1610 es->apu[0] = apu1;
1611 es->apu[1] = apu1 + 1;
1612 es->apu[2] = apu2;
1613 es->apu[3] = apu2 + 1;
1614 es->apu_mode[0] = 0;
1615 es->apu_mode[1] = 0;
1616 es->apu_mode[2] = 0;
1617 es->apu_mode[3] = 0;
1618 es->running = 0;
1619 es->substream = substream;
1620 es->mode = ESM_MODE_CAPTURE;
1621
1622 /* get mixbuffer */
1623 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1624 snd_es1968_free_apu_pair(chip, apu1);
1625 snd_es1968_free_apu_pair(chip, apu2);
1626 kfree(es);
1627 return -ENOMEM;
1628 }
1629 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1630
1631 runtime->private_data = es;
1632 runtime->hw = snd_es1968_capture;
1633 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1634 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1635 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
1636
1637 spin_lock_irq(&chip->substream_lock);
1638 list_add(&es->list, &chip->substream_list);
1639 spin_unlock_irq(&chip->substream_lock);
1640
1641 return 0;
1642}
1643
1644static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
1645{
1646 struct es1968 *chip = snd_pcm_substream_chip(substream);
1647 struct esschan *es;
1648
1649 if (substream->runtime->private_data == NULL)
1650 return 0;
1651 es = substream->runtime->private_data;
1652 spin_lock_irq(&chip->substream_lock);
1653 list_del(&es->list);
1654 spin_unlock_irq(&chip->substream_lock);
1655 snd_es1968_free_apu_pair(chip, es->apu[0]);
1656 kfree(es);
1657
1658 return 0;
1659}
1660
1661static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
1662{
1663 struct es1968 *chip = snd_pcm_substream_chip(substream);
1664 struct esschan *es;
1665
1666 if (substream->runtime->private_data == NULL)
1667 return 0;
1668 es = substream->runtime->private_data;
1669 spin_lock_irq(&chip->substream_lock);
1670 list_del(&es->list);
1671 spin_unlock_irq(&chip->substream_lock);
1672 snd_es1968_free_memory(chip, es->mixbuf);
1673 snd_es1968_free_apu_pair(chip, es->apu[0]);
1674 snd_es1968_free_apu_pair(chip, es->apu[2]);
1675 kfree(es);
1676
1677 return 0;
1678}
1679
1680static const struct snd_pcm_ops snd_es1968_playback_ops = {
1681 .open = snd_es1968_playback_open,
1682 .close = snd_es1968_playback_close,
1683 .ioctl = snd_pcm_lib_ioctl,
1684 .hw_params = snd_es1968_hw_params,
1685 .hw_free = snd_es1968_hw_free,
1686 .prepare = snd_es1968_pcm_prepare,
1687 .trigger = snd_es1968_pcm_trigger,
1688 .pointer = snd_es1968_pcm_pointer,
1689};
1690
1691static const struct snd_pcm_ops snd_es1968_capture_ops = {
1692 .open = snd_es1968_capture_open,
1693 .close = snd_es1968_capture_close,
1694 .ioctl = snd_pcm_lib_ioctl,
1695 .hw_params = snd_es1968_hw_params,
1696 .hw_free = snd_es1968_hw_free,
1697 .prepare = snd_es1968_pcm_prepare,
1698 .trigger = snd_es1968_pcm_trigger,
1699 .pointer = snd_es1968_pcm_pointer,
1700};
1701
1702
1703/*
1704 * measure clock
1705 */
1706#define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1707
1708static void es1968_measure_clock(struct es1968 *chip)
1709{
1710 int i, apu;
1711 unsigned int pa, offset, t;
1712 struct esm_memory *memory;
1713 ktime_t start_time, stop_time;
1714 ktime_t diff;
1715
1716 if (chip->clock == 0)
1717 chip->clock = 48000; /* default clock value */
1718
1719 /* search 2 APUs (although one apu is enough) */
1720 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
1721 dev_err(chip->card->dev, "Hmm, cannot find empty APU pair!?\n");
1722 return;
1723 }
1724 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
1725 dev_warn(chip->card->dev,
1726 "cannot allocate dma buffer - using default clock %d\n",
1727 chip->clock);
1728 snd_es1968_free_apu_pair(chip, apu);
1729 return;
1730 }
1731
1732 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1733
1734 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1735
1736 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1737 pa |= 0x00400000; /* System RAM (Bit 22) */
1738
1739 /* initialize apu */
1740 for (i = 0; i < 16; i++)
1741 apu_set_register(chip, apu, i, 0x0000);
1742
1743 apu_set_register(chip, apu, 0, 0x400f);
1744 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1745 apu_set_register(chip, apu, 5, pa & 0xffff);
1746 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1747 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1748 apu_set_register(chip, apu, 8, 0x0000);
1749 apu_set_register(chip, apu, 9, 0xD000);
1750 apu_set_register(chip, apu, 10, 0x8F08);
1751 apu_set_register(chip, apu, 11, 0x0000);
1752 spin_lock_irq(&chip->reg_lock);
1753 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1754 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1755 spin_unlock_irq(&chip->reg_lock);
1756
1757 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1758
1759 chip->in_measurement = 1;
1760 chip->measure_apu = apu;
1761 spin_lock_irq(&chip->reg_lock);
1762 snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1763 __apu_set_register(chip, apu, 5, pa & 0xffff);
1764 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1765 start_time = ktime_get();
1766 spin_unlock_irq(&chip->reg_lock);
1767 msleep(50);
1768 spin_lock_irq(&chip->reg_lock);
1769 offset = __apu_get_register(chip, apu, 5);
1770 stop_time = ktime_get();
1771 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1772 snd_es1968_bob_dec(chip);
1773 chip->in_measurement = 0;
1774 spin_unlock_irq(&chip->reg_lock);
1775
1776 /* check the current position */
1777 offset -= (pa & 0xffff);
1778 offset &= 0xfffe;
1779 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1780
1781 diff = ktime_sub(stop_time, start_time);
1782 t = ktime_to_us(diff);
1783 if (t == 0) {
1784 dev_err(chip->card->dev, "?? calculation error..\n");
1785 } else {
1786 offset *= 1000;
1787 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1788 if (offset < 47500 || offset > 48500) {
1789 if (offset >= 40000 && offset <= 50000)
1790 chip->clock = (chip->clock * offset) / 48000;
1791 }
1792 dev_info(chip->card->dev, "clocking to %d\n", chip->clock);
1793 }
1794 snd_es1968_free_memory(chip, memory);
1795 snd_es1968_free_apu_pair(chip, apu);
1796}
1797
1798
1799/*
1800 */
1801
1802static void snd_es1968_pcm_free(struct snd_pcm *pcm)
1803{
1804 struct es1968 *esm = pcm->private_data;
1805 snd_es1968_free_dmabuf(esm);
1806 esm->pcm = NULL;
1807}
1808
1809static int
1810snd_es1968_pcm(struct es1968 *chip, int device)
1811{
1812 struct snd_pcm *pcm;
1813 int err;
1814
1815 /* get DMA buffer */
1816 if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1817 return err;
1818
1819 /* set PCMBAR */
1820 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1821 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1822 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1823 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1824
1825 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1826 chip->playback_streams,
1827 chip->capture_streams, &pcm)) < 0)
1828 return err;
1829
1830 pcm->private_data = chip;
1831 pcm->private_free = snd_es1968_pcm_free;
1832
1833 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1834 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1835
1836 pcm->info_flags = 0;
1837
1838 strcpy(pcm->name, "ESS Maestro");
1839
1840 chip->pcm = pcm;
1841
1842 return 0;
1843}
1844/*
1845 * suppress jitter on some maestros when playing stereo
1846 */
1847static void snd_es1968_suppress_jitter(struct es1968 *chip, struct esschan *es)
1848{
1849 unsigned int cp1;
1850 unsigned int cp2;
1851 unsigned int diff;
1852
1853 cp1 = __apu_get_register(chip, 0, 5);
1854 cp2 = __apu_get_register(chip, 1, 5);
1855 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1856
1857 if (diff > 1)
1858 __maestro_write(chip, IDR0_DATA_PORT, cp1);
1859}
1860
1861/*
1862 * update pointer
1863 */
1864static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
1865{
1866 unsigned int hwptr;
1867 unsigned int diff;
1868 struct snd_pcm_substream *subs = es->substream;
1869
1870 if (subs == NULL || !es->running)
1871 return;
1872
1873 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1874 hwptr %= es->dma_size;
1875
1876 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1877
1878 es->hwptr = hwptr;
1879 es->count += diff;
1880
1881 if (es->count > es->frag_size) {
1882 spin_unlock(&chip->substream_lock);
1883 snd_pcm_period_elapsed(subs);
1884 spin_lock(&chip->substream_lock);
1885 es->count %= es->frag_size;
1886 }
1887}
1888
1889/* The hardware volume works by incrementing / decrementing 2 counters
1890 (without wrap around) in response to volume button presses and then
1891 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1892 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1893static void es1968_update_hw_volume(struct work_struct *work)
1894{
1895 struct es1968 *chip = container_of(work, struct es1968, hwvol_work);
1896 int x, val;
1897
1898 /* Figure out which volume control button was pushed,
1899 based on differences from the default register
1900 values. */
1901 x = inb(chip->io_port + 0x1c) & 0xee;
1902 /* Reset the volume control registers. */
1903 outb(0x88, chip->io_port + 0x1c);
1904 outb(0x88, chip->io_port + 0x1d);
1905 outb(0x88, chip->io_port + 0x1e);
1906 outb(0x88, chip->io_port + 0x1f);
1907
1908 if (chip->in_suspend)
1909 return;
1910
1911#ifndef CONFIG_SND_ES1968_INPUT
1912 if (! chip->master_switch || ! chip->master_volume)
1913 return;
1914
1915 val = snd_ac97_read(chip->ac97, AC97_MASTER);
1916 switch (x) {
1917 case 0x88:
1918 /* mute */
1919 val ^= 0x8000;
1920 break;
1921 case 0xaa:
1922 /* volume up */
1923 if ((val & 0x7f) > 0)
1924 val--;
1925 if ((val & 0x7f00) > 0)
1926 val -= 0x0100;
1927 break;
1928 case 0x66:
1929 /* volume down */
1930 if ((val & 0x7f) < 0x1f)
1931 val++;
1932 if ((val & 0x7f00) < 0x1f00)
1933 val += 0x0100;
1934 break;
1935 }
1936 if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1937 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1938 &chip->master_volume->id);
1939#else
1940 if (!chip->input_dev)
1941 return;
1942
1943 val = 0;
1944 switch (x) {
1945 case 0x88:
1946 /* The counters have not changed, yet we've received a HV
1947 interrupt. According to tests run by various people this
1948 happens when pressing the mute button. */
1949 val = KEY_MUTE;
1950 break;
1951 case 0xaa:
1952 /* counters increased by 1 -> volume up */
1953 val = KEY_VOLUMEUP;
1954 break;
1955 case 0x66:
1956 /* counters decreased by 1 -> volume down */
1957 val = KEY_VOLUMEDOWN;
1958 break;
1959 }
1960
1961 if (val) {
1962 input_report_key(chip->input_dev, val, 1);
1963 input_sync(chip->input_dev);
1964 input_report_key(chip->input_dev, val, 0);
1965 input_sync(chip->input_dev);
1966 }
1967#endif
1968}
1969
1970/*
1971 * interrupt handler
1972 */
1973static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id)
1974{
1975 struct es1968 *chip = dev_id;
1976 u32 event;
1977
1978 if (!(event = inb(chip->io_port + 0x1A)))
1979 return IRQ_NONE;
1980
1981 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1982
1983 if (event & ESM_HWVOL_IRQ)
1984 schedule_work(&chip->hwvol_work);
1985
1986 /* else ack 'em all, i imagine */
1987 outb(0xFF, chip->io_port + 0x1A);
1988
1989 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
1990 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1991 }
1992
1993 if (event & ESM_SOUND_IRQ) {
1994 struct esschan *es;
1995 spin_lock(&chip->substream_lock);
1996 list_for_each_entry(es, &chip->substream_list, list) {
1997 if (es->running) {
1998 snd_es1968_update_pcm(chip, es);
1999 if (es->fmt & ESS_FMT_STEREO)
2000 snd_es1968_suppress_jitter(chip, es);
2001 }
2002 }
2003 spin_unlock(&chip->substream_lock);
2004 if (chip->in_measurement) {
2005 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
2006 if (curp < chip->measure_lastpos)
2007 chip->measure_count++;
2008 chip->measure_lastpos = curp;
2009 }
2010 }
2011
2012 return IRQ_HANDLED;
2013}
2014
2015/*
2016 * Mixer stuff
2017 */
2018
2019static int
2020snd_es1968_mixer(struct es1968 *chip)
2021{
2022 struct snd_ac97_bus *pbus;
2023 struct snd_ac97_template ac97;
2024#ifndef CONFIG_SND_ES1968_INPUT
2025 struct snd_ctl_elem_id elem_id;
2026#endif
2027 int err;
2028 static struct snd_ac97_bus_ops ops = {
2029 .write = snd_es1968_ac97_write,
2030 .read = snd_es1968_ac97_read,
2031 };
2032
2033 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2034 return err;
2035 pbus->no_vra = 1; /* ES1968 doesn't need VRA */
2036
2037 memset(&ac97, 0, sizeof(ac97));
2038 ac97.private_data = chip;
2039 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2040 return err;
2041
2042#ifndef CONFIG_SND_ES1968_INPUT
2043 /* attach master switch / volumes for h/w volume control */
2044 memset(&elem_id, 0, sizeof(elem_id));
2045 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2046 strcpy(elem_id.name, "Master Playback Switch");
2047 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2048 memset(&elem_id, 0, sizeof(elem_id));
2049 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2050 strcpy(elem_id.name, "Master Playback Volume");
2051 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2052#endif
2053
2054 return 0;
2055}
2056
2057/*
2058 * reset ac97 codec
2059 */
2060
2061static void snd_es1968_ac97_reset(struct es1968 *chip)
2062{
2063 unsigned long ioaddr = chip->io_port;
2064
2065 unsigned short save_ringbus_a;
2066 unsigned short save_68;
2067 unsigned short w;
2068 unsigned int vend;
2069
2070 /* save configuration */
2071 save_ringbus_a = inw(ioaddr + 0x36);
2072
2073 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2074 /* set command/status address i/o to 1st codec */
2075 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2076 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2077
2078 /* disable ac link */
2079 outw(0x0000, ioaddr + 0x36);
2080 save_68 = inw(ioaddr + 0x68);
2081 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2082 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2083 if (w & 1)
2084 save_68 |= 0x10;
2085 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2086 outw(0x0001, ioaddr + 0x68); /* gpio write */
2087 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2088 udelay(20);
2089 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
2090 msleep(20);
2091
2092 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2093 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2094 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2095 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2096
2097 /* now the second codec */
2098 /* disable ac link */
2099 outw(0x0000, ioaddr + 0x36);
2100 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2101 save_68 = inw(ioaddr + 0x68);
2102 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2103 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2104 udelay(20);
2105 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
2106 msleep(500);
2107 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2108 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2109 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2110
2111#if 0 /* the loop here needs to be much better if we want it.. */
2112 dev_info(chip->card->dev, "trying software reset\n");
2113 /* try and do a software reset */
2114 outb(0x80 | 0x7c, ioaddr + 0x30);
2115 for (w = 0;; w++) {
2116 if ((inw(ioaddr + 0x30) & 1) == 0) {
2117 if (inb(ioaddr + 0x32) != 0)
2118 break;
2119
2120 outb(0x80 | 0x7d, ioaddr + 0x30);
2121 if (((inw(ioaddr + 0x30) & 1) == 0)
2122 && (inb(ioaddr + 0x32) != 0))
2123 break;
2124 outb(0x80 | 0x7f, ioaddr + 0x30);
2125 if (((inw(ioaddr + 0x30) & 1) == 0)
2126 && (inb(ioaddr + 0x32) != 0))
2127 break;
2128 }
2129
2130 if (w > 10000) {
2131 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
2132 msleep(500); /* oh my.. */
2133 outb(inb(ioaddr + 0x37) & ~0x08,
2134 ioaddr + 0x37);
2135 udelay(1);
2136 outw(0x80, ioaddr + 0x30);
2137 for (w = 0; w < 10000; w++) {
2138 if ((inw(ioaddr + 0x30) & 1) == 0)
2139 break;
2140 }
2141 }
2142 }
2143#endif
2144 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2145 /* turn on external amp? */
2146 outw(0xf9ff, ioaddr + 0x64);
2147 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2148 outw(0x0209, ioaddr + 0x60);
2149 }
2150
2151 /* restore.. */
2152 outw(save_ringbus_a, ioaddr + 0x36);
2153
2154 /* Turn on the 978 docking chip.
2155 First frob the "master output enable" bit,
2156 then set most of the playback volume control registers to max. */
2157 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2158 outb(0xff, ioaddr+0xc3);
2159 outb(0xff, ioaddr+0xc4);
2160 outb(0xff, ioaddr+0xc6);
2161 outb(0xff, ioaddr+0xc8);
2162 outb(0x3f, ioaddr+0xcf);
2163 outb(0x3f, ioaddr+0xd0);
2164}
2165
2166static void snd_es1968_reset(struct es1968 *chip)
2167{
2168 /* Reset */
2169 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2170 chip->io_port + ESM_PORT_HOST_IRQ);
2171 udelay(10);
2172 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2173 udelay(10);
2174}
2175
2176/*
2177 * initialize maestro chip
2178 */
2179static void snd_es1968_chip_init(struct es1968 *chip)
2180{
2181 struct pci_dev *pci = chip->pci;
2182 int i;
2183 unsigned long iobase = chip->io_port;
2184 u16 w;
2185 u32 n;
2186
2187 /* We used to muck around with pci config space that
2188 * we had no business messing with. We don't know enough
2189 * about the machine to know which DMA mode is appropriate,
2190 * etc. We were guessing wrong on some machines and making
2191 * them unhappy. We now trust in the BIOS to do things right,
2192 * which almost certainly means a new host of problems will
2193 * arise with broken BIOS implementations. screw 'em.
2194 * We're already intolerant of machines that don't assign
2195 * IRQs.
2196 */
2197
2198 /* Config Reg A */
2199 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2200
2201 w &= ~DMA_CLEAR; /* Clear DMA bits */
2202 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2203 w &= ~SAFEGUARD; /* Safeguard off */
2204 w |= POST_WRITE; /* Posted write */
2205 w |= PCI_TIMING; /* PCI timing on */
2206 /* XXX huh? claims to be reserved.. */
2207 w &= ~SWAP_LR; /* swap left/right
2208 seems to only have effect on SB
2209 Emulation */
2210 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2211
2212 pci_write_config_word(pci, ESM_CONFIG_A, w);
2213
2214 /* Config Reg B */
2215
2216 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2217
2218 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2219 /* XXX how do we know which to use? */
2220 w &= ~(1 << 14); /* External clock */
2221
2222 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2223 w |= HWV_CONFB; /* HWV on */
2224 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2225 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2226 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2227 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2228 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2229 w &= ~(1 << 1); /* reserved, always write 0 */
2230 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2231
2232 pci_write_config_word(pci, ESM_CONFIG_B, w);
2233
2234 /* DDMA off */
2235
2236 pci_read_config_word(pci, ESM_DDMA, &w);
2237 w &= ~(1 << 0);
2238 pci_write_config_word(pci, ESM_DDMA, w);
2239
2240 /*
2241 * Legacy mode
2242 */
2243
2244 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2245
2246 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */
2247 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2248 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2249
2250 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2251
2252 /* Set up 978 docking control chip. */
2253 pci_read_config_word(pci, 0x58, &w);
2254 w|=1<<2; /* Enable 978. */
2255 w|=1<<3; /* Turn on 978 hardware volume control. */
2256 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2257 pci_write_config_word(pci, 0x58, w);
2258
2259 /* Sound Reset */
2260
2261 snd_es1968_reset(chip);
2262
2263 /*
2264 * Ring Bus Setup
2265 */
2266
2267 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2268 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2269 udelay(20);
2270 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2271 udelay(20);
2272
2273 /*
2274 * Reset the CODEC
2275 */
2276
2277 snd_es1968_ac97_reset(chip);
2278
2279 /* Ring Bus Control B */
2280
2281 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2282 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2283 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2284 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2285
2286 /* Set hardware volume control registers to midpoints.
2287 We can tell which button was pushed based on how they change. */
2288 outb(0x88, iobase+0x1c);
2289 outb(0x88, iobase+0x1d);
2290 outb(0x88, iobase+0x1e);
2291 outb(0x88, iobase+0x1f);
2292
2293 /* it appears some maestros (dell 7500) only work if these are set,
2294 regardless of whether we use the assp or not. */
2295
2296 outb(0, iobase + ASSP_CONTROL_B);
2297 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2298 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2299
2300 /*
2301 * set up wavecache
2302 */
2303 for (i = 0; i < 16; i++) {
2304 /* Write 0 into the buffer area 0x1E0->1EF */
2305 outw(0x01E0 + i, iobase + WC_INDEX);
2306 outw(0x0000, iobase + WC_DATA);
2307
2308 /* The 1.10 test program seem to write 0 into the buffer area
2309 * 0x1D0-0x1DF too.*/
2310 outw(0x01D0 + i, iobase + WC_INDEX);
2311 outw(0x0000, iobase + WC_DATA);
2312 }
2313 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2314 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2315 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2316 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2317 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2318 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2319 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2320 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2321
2322
2323 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2324 /* Now back to the DirectSound stuff */
2325 /* audio serial configuration.. ? */
2326 maestro_write(chip, 0x08, 0xB004);
2327 maestro_write(chip, 0x09, 0x001B);
2328 maestro_write(chip, 0x0A, 0x8000);
2329 maestro_write(chip, 0x0B, 0x3F37);
2330 maestro_write(chip, 0x0C, 0x0098);
2331
2332 /* parallel in, has something to do with recording :) */
2333 maestro_write(chip, 0x0C,
2334 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2335 /* parallel out */
2336 maestro_write(chip, 0x0C,
2337 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2338
2339 maestro_write(chip, 0x0D, 0x7632);
2340
2341 /* Wave cache control on - test off, sg off,
2342 enable, enable extra chans 1Mb */
2343
2344 w = inw(iobase + WC_CONTROL);
2345
2346 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2347 w |= 0xA000; /* reserved... I don't know */
2348 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2349 Seems to crash the Computer if enabled... */
2350 w |= 0x0100; /* Wave Cache Operation Enabled */
2351 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2352 w &= ~0x0060; /* Clear Wavtable Size */
2353 w |= 0x0020; /* Wavetable Size : 1MB */
2354 /* Bit 4 is reserved */
2355 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2356 /* Bit 1 is reserved */
2357 w &= ~0x0001; /* Test Mode off */
2358
2359 outw(w, iobase + WC_CONTROL);
2360
2361 /* Now clear the APU control ram */
2362 for (i = 0; i < NR_APUS; i++) {
2363 for (w = 0; w < NR_APU_REGS; w++)
2364 apu_set_register(chip, i, w, 0);
2365
2366 }
2367}
2368
2369/* Enable IRQ's */
2370static void snd_es1968_start_irq(struct es1968 *chip)
2371{
2372 unsigned short w;
2373 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2374 if (chip->rmidi)
2375 w |= ESM_HIRQ_MPU401;
2376 outb(w, chip->io_port + 0x1A);
2377 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2378}
2379
2380#ifdef CONFIG_PM_SLEEP
2381/*
2382 * PM support
2383 */
2384static int es1968_suspend(struct device *dev)
2385{
2386 struct snd_card *card = dev_get_drvdata(dev);
2387 struct es1968 *chip = card->private_data;
2388
2389 if (! chip->do_pm)
2390 return 0;
2391
2392 chip->in_suspend = 1;
2393 cancel_work_sync(&chip->hwvol_work);
2394 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2395 snd_pcm_suspend_all(chip->pcm);
2396 snd_ac97_suspend(chip->ac97);
2397 snd_es1968_bob_stop(chip);
2398 return 0;
2399}
2400
2401static int es1968_resume(struct device *dev)
2402{
2403 struct snd_card *card = dev_get_drvdata(dev);
2404 struct es1968 *chip = card->private_data;
2405 struct esschan *es;
2406
2407 if (! chip->do_pm)
2408 return 0;
2409
2410 snd_es1968_chip_init(chip);
2411
2412 /* need to restore the base pointers.. */
2413 if (chip->dma.addr) {
2414 /* set PCMBAR */
2415 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2416 }
2417
2418 snd_es1968_start_irq(chip);
2419
2420 /* restore ac97 state */
2421 snd_ac97_resume(chip->ac97);
2422
2423 list_for_each_entry(es, &chip->substream_list, list) {
2424 switch (es->mode) {
2425 case ESM_MODE_PLAY:
2426 snd_es1968_playback_setup(chip, es, es->substream->runtime);
2427 break;
2428 case ESM_MODE_CAPTURE:
2429 snd_es1968_capture_setup(chip, es, es->substream->runtime);
2430 break;
2431 }
2432 }
2433
2434 /* start timer again */
2435 if (chip->bobclient)
2436 snd_es1968_bob_start(chip);
2437
2438 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2439 chip->in_suspend = 0;
2440 return 0;
2441}
2442
2443static SIMPLE_DEV_PM_OPS(es1968_pm, es1968_suspend, es1968_resume);
2444#define ES1968_PM_OPS &es1968_pm
2445#else
2446#define ES1968_PM_OPS NULL
2447#endif /* CONFIG_PM_SLEEP */
2448
2449#ifdef SUPPORT_JOYSTICK
2450#define JOYSTICK_ADDR 0x200
2451static int snd_es1968_create_gameport(struct es1968 *chip, int dev)
2452{
2453 struct gameport *gp;
2454 struct resource *r;
2455 u16 val;
2456
2457 if (!joystick[dev])
2458 return -ENODEV;
2459
2460 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2461 if (!r)
2462 return -EBUSY;
2463
2464 chip->gameport = gp = gameport_allocate_port();
2465 if (!gp) {
2466 dev_err(chip->card->dev,
2467 "cannot allocate memory for gameport\n");
2468 release_and_free_resource(r);
2469 return -ENOMEM;
2470 }
2471
2472 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2473 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2474
2475 gameport_set_name(gp, "ES1968 Gameport");
2476 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2477 gameport_set_dev_parent(gp, &chip->pci->dev);
2478 gp->io = JOYSTICK_ADDR;
2479 gameport_set_port_data(gp, r);
2480
2481 gameport_register_port(gp);
2482
2483 return 0;
2484}
2485
2486static void snd_es1968_free_gameport(struct es1968 *chip)
2487{
2488 if (chip->gameport) {
2489 struct resource *r = gameport_get_port_data(chip->gameport);
2490
2491 gameport_unregister_port(chip->gameport);
2492 chip->gameport = NULL;
2493
2494 release_and_free_resource(r);
2495 }
2496}
2497#else
2498static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
2499static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
2500#endif
2501
2502#ifdef CONFIG_SND_ES1968_INPUT
2503static int snd_es1968_input_register(struct es1968 *chip)
2504{
2505 struct input_dev *input_dev;
2506 int err;
2507
2508 input_dev = input_allocate_device();
2509 if (!input_dev)
2510 return -ENOMEM;
2511
2512 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2513 pci_name(chip->pci));
2514
2515 input_dev->name = chip->card->driver;
2516 input_dev->phys = chip->phys;
2517 input_dev->id.bustype = BUS_PCI;
2518 input_dev->id.vendor = chip->pci->vendor;
2519 input_dev->id.product = chip->pci->device;
2520 input_dev->dev.parent = &chip->pci->dev;
2521
2522 __set_bit(EV_KEY, input_dev->evbit);
2523 __set_bit(KEY_MUTE, input_dev->keybit);
2524 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2525 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2526
2527 err = input_register_device(input_dev);
2528 if (err) {
2529 input_free_device(input_dev);
2530 return err;
2531 }
2532
2533 chip->input_dev = input_dev;
2534 return 0;
2535}
2536#endif /* CONFIG_SND_ES1968_INPUT */
2537
2538#ifdef CONFIG_SND_ES1968_RADIO
2539#define GPIO_DATA 0x60
2540#define IO_MASK 4 /* mask register offset from GPIO_DATA
2541 bits 1=unmask write to given bit */
2542#define IO_DIR 8 /* direction register offset from GPIO_DATA
2543 bits 0/1=read/write direction */
2544
2545/* GPIO to TEA575x maps */
2546struct snd_es1968_tea575x_gpio {
2547 u8 data, clk, wren, most;
2548 char *name;
2549};
2550
2551static struct snd_es1968_tea575x_gpio snd_es1968_tea575x_gpios[] = {
2552 { .data = 6, .clk = 7, .wren = 8, .most = 9, .name = "SF64-PCE2" },
2553 { .data = 7, .clk = 8, .wren = 6, .most = 10, .name = "M56VAP" },
2554};
2555
2556#define get_tea575x_gpio(chip) \
2557 (&snd_es1968_tea575x_gpios[(chip)->tea575x_tuner])
2558
2559
2560static void snd_es1968_tea575x_set_pins(struct snd_tea575x *tea, u8 pins)
2561{
2562 struct es1968 *chip = tea->private_data;
2563 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2564 u16 val = 0;
2565
2566 val |= (pins & TEA575X_DATA) ? (1 << gpio.data) : 0;
2567 val |= (pins & TEA575X_CLK) ? (1 << gpio.clk) : 0;
2568 val |= (pins & TEA575X_WREN) ? (1 << gpio.wren) : 0;
2569
2570 outw(val, chip->io_port + GPIO_DATA);
2571}
2572
2573static u8 snd_es1968_tea575x_get_pins(struct snd_tea575x *tea)
2574{
2575 struct es1968 *chip = tea->private_data;
2576 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2577 u16 val = inw(chip->io_port + GPIO_DATA);
2578 u8 ret = 0;
2579
2580 if (val & (1 << gpio.data))
2581 ret |= TEA575X_DATA;
2582 if (val & (1 << gpio.most))
2583 ret |= TEA575X_MOST;
2584
2585 return ret;
2586}
2587
2588static void snd_es1968_tea575x_set_direction(struct snd_tea575x *tea, bool output)
2589{
2590 struct es1968 *chip = tea->private_data;
2591 unsigned long io = chip->io_port + GPIO_DATA;
2592 u16 odir = inw(io + IO_DIR);
2593 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2594
2595 if (output) {
2596 outw(~((1 << gpio.data) | (1 << gpio.clk) | (1 << gpio.wren)),
2597 io + IO_MASK);
2598 outw(odir | (1 << gpio.data) | (1 << gpio.clk) | (1 << gpio.wren),
2599 io + IO_DIR);
2600 } else {
2601 outw(~((1 << gpio.clk) | (1 << gpio.wren) | (1 << gpio.data) | (1 << gpio.most)),
2602 io + IO_MASK);
2603 outw((odir & ~((1 << gpio.data) | (1 << gpio.most)))
2604 | (1 << gpio.clk) | (1 << gpio.wren), io + IO_DIR);
2605 }
2606}
2607
2608static const struct snd_tea575x_ops snd_es1968_tea_ops = {
2609 .set_pins = snd_es1968_tea575x_set_pins,
2610 .get_pins = snd_es1968_tea575x_get_pins,
2611 .set_direction = snd_es1968_tea575x_set_direction,
2612};
2613#endif
2614
2615static int snd_es1968_free(struct es1968 *chip)
2616{
2617 cancel_work_sync(&chip->hwvol_work);
2618#ifdef CONFIG_SND_ES1968_INPUT
2619 if (chip->input_dev)
2620 input_unregister_device(chip->input_dev);
2621#endif
2622
2623 if (chip->io_port) {
2624 if (chip->irq >= 0)
2625 synchronize_irq(chip->irq);
2626 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2627 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2628 }
2629
2630#ifdef CONFIG_SND_ES1968_RADIO
2631 snd_tea575x_exit(&chip->tea);
2632 v4l2_device_unregister(&chip->v4l2_dev);
2633#endif
2634
2635 if (chip->irq >= 0)
2636 free_irq(chip->irq, chip);
2637 snd_es1968_free_gameport(chip);
2638 pci_release_regions(chip->pci);
2639 pci_disable_device(chip->pci);
2640 kfree(chip);
2641 return 0;
2642}
2643
2644static int snd_es1968_dev_free(struct snd_device *device)
2645{
2646 struct es1968 *chip = device->device_data;
2647 return snd_es1968_free(chip);
2648}
2649
2650struct ess_device_list {
2651 unsigned short type; /* chip type */
2652 unsigned short vendor; /* subsystem vendor id */
2653};
2654
2655static struct ess_device_list pm_whitelist[] = {
2656 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2657 { TYPE_MAESTRO2E, 0x1028 },
2658 { TYPE_MAESTRO2E, 0x103c },
2659 { TYPE_MAESTRO2E, 0x1179 },
2660 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
2661 { TYPE_MAESTRO2E, 0x1558 },
2662 { TYPE_MAESTRO2E, 0x125d }, /* a PCI card, e.g. Terratec DMX */
2663 { TYPE_MAESTRO2, 0x125d }, /* a PCI card, e.g. SF64-PCE2 */
2664};
2665
2666static struct ess_device_list mpu_blacklist[] = {
2667 { TYPE_MAESTRO2, 0x125d },
2668};
2669
2670static int snd_es1968_create(struct snd_card *card,
2671 struct pci_dev *pci,
2672 int total_bufsize,
2673 int play_streams,
2674 int capt_streams,
2675 int chip_type,
2676 int do_pm,
2677 int radio_nr,
2678 struct es1968 **chip_ret)
2679{
2680 static struct snd_device_ops ops = {
2681 .dev_free = snd_es1968_dev_free,
2682 };
2683 struct es1968 *chip;
2684 int i, err;
2685
2686 *chip_ret = NULL;
2687
2688 /* enable PCI device */
2689 if ((err = pci_enable_device(pci)) < 0)
2690 return err;
2691 /* check, if we can restrict PCI DMA transfers to 28 bits */
2692 if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
2693 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
2694 dev_err(card->dev,
2695 "architecture does not support 28bit PCI busmaster DMA\n");
2696 pci_disable_device(pci);
2697 return -ENXIO;
2698 }
2699
2700 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2701 if (! chip) {
2702 pci_disable_device(pci);
2703 return -ENOMEM;
2704 }
2705
2706 /* Set Vars */
2707 chip->type = chip_type;
2708 spin_lock_init(&chip->reg_lock);
2709 spin_lock_init(&chip->substream_lock);
2710 INIT_LIST_HEAD(&chip->buf_list);
2711 INIT_LIST_HEAD(&chip->substream_list);
2712 mutex_init(&chip->memory_mutex);
2713 INIT_WORK(&chip->hwvol_work, es1968_update_hw_volume);
2714 chip->card = card;
2715 chip->pci = pci;
2716 chip->irq = -1;
2717 chip->total_bufsize = total_bufsize; /* in bytes */
2718 chip->playback_streams = play_streams;
2719 chip->capture_streams = capt_streams;
2720
2721 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2722 kfree(chip);
2723 pci_disable_device(pci);
2724 return err;
2725 }
2726 chip->io_port = pci_resource_start(pci, 0);
2727 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED,
2728 KBUILD_MODNAME, chip)) {
2729 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2730 snd_es1968_free(chip);
2731 return -EBUSY;
2732 }
2733 chip->irq = pci->irq;
2734
2735 /* Clear Maestro_map */
2736 for (i = 0; i < 32; i++)
2737 chip->maestro_map[i] = 0;
2738
2739 /* Clear Apu Map */
2740 for (i = 0; i < NR_APUS; i++)
2741 chip->apu[i] = ESM_APU_FREE;
2742
2743 /* just to be sure */
2744 pci_set_master(pci);
2745
2746 if (do_pm > 1) {
2747 /* disable power-management if not on the whitelist */
2748 unsigned short vend;
2749 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2750 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
2751 if (chip->type == pm_whitelist[i].type &&
2752 vend == pm_whitelist[i].vendor) {
2753 do_pm = 1;
2754 break;
2755 }
2756 }
2757 if (do_pm > 1) {
2758 /* not matched; disabling pm */
2759 dev_info(card->dev, "not attempting power management.\n");
2760 do_pm = 0;
2761 }
2762 }
2763 chip->do_pm = do_pm;
2764
2765 snd_es1968_chip_init(chip);
2766
2767 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2768 snd_es1968_free(chip);
2769 return err;
2770 }
2771
2772#ifdef CONFIG_SND_ES1968_RADIO
2773 /* don't play with GPIOs on laptops */
2774 if (chip->pci->subsystem_vendor != 0x125d)
2775 goto no_radio;
2776 err = v4l2_device_register(&pci->dev, &chip->v4l2_dev);
2777 if (err < 0) {
2778 snd_es1968_free(chip);
2779 return err;
2780 }
2781 chip->tea.v4l2_dev = &chip->v4l2_dev;
2782 chip->tea.private_data = chip;
2783 chip->tea.radio_nr = radio_nr;
2784 chip->tea.ops = &snd_es1968_tea_ops;
2785 sprintf(chip->tea.bus_info, "PCI:%s", pci_name(pci));
2786 for (i = 0; i < ARRAY_SIZE(snd_es1968_tea575x_gpios); i++) {
2787 chip->tea575x_tuner = i;
2788 if (!snd_tea575x_init(&chip->tea, THIS_MODULE)) {
2789 dev_info(card->dev, "detected TEA575x radio type %s\n",
2790 get_tea575x_gpio(chip)->name);
2791 strlcpy(chip->tea.card, get_tea575x_gpio(chip)->name,
2792 sizeof(chip->tea.card));
2793 break;
2794 }
2795 }
2796no_radio:
2797#endif
2798
2799 *chip_ret = chip;
2800
2801 return 0;
2802}
2803
2804
2805/*
2806 */
2807static int snd_es1968_probe(struct pci_dev *pci,
2808 const struct pci_device_id *pci_id)
2809{
2810 static int dev;
2811 struct snd_card *card;
2812 struct es1968 *chip;
2813 unsigned int i;
2814 int err;
2815
2816 if (dev >= SNDRV_CARDS)
2817 return -ENODEV;
2818 if (!enable[dev]) {
2819 dev++;
2820 return -ENOENT;
2821 }
2822
2823 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2824 0, &card);
2825 if (err < 0)
2826 return err;
2827
2828 if (total_bufsize[dev] < 128)
2829 total_bufsize[dev] = 128;
2830 if (total_bufsize[dev] > 4096)
2831 total_bufsize[dev] = 4096;
2832 if ((err = snd_es1968_create(card, pci,
2833 total_bufsize[dev] * 1024, /* in bytes */
2834 pcm_substreams_p[dev],
2835 pcm_substreams_c[dev],
2836 pci_id->driver_data,
2837 use_pm[dev],
2838 radio_nr[dev],
2839 &chip)) < 0) {
2840 snd_card_free(card);
2841 return err;
2842 }
2843 card->private_data = chip;
2844
2845 switch (chip->type) {
2846 case TYPE_MAESTRO2E:
2847 strcpy(card->driver, "ES1978");
2848 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2849 break;
2850 case TYPE_MAESTRO2:
2851 strcpy(card->driver, "ES1968");
2852 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2853 break;
2854 case TYPE_MAESTRO:
2855 strcpy(card->driver, "ESM1");
2856 strcpy(card->shortname, "ESS Maestro 1");
2857 break;
2858 }
2859
2860 if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2861 snd_card_free(card);
2862 return err;
2863 }
2864
2865 if ((err = snd_es1968_mixer(chip)) < 0) {
2866 snd_card_free(card);
2867 return err;
2868 }
2869
2870 if (enable_mpu[dev] == 2) {
2871 /* check the black list */
2872 unsigned short vend;
2873 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2874 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
2875 if (chip->type == mpu_blacklist[i].type &&
2876 vend == mpu_blacklist[i].vendor) {
2877 enable_mpu[dev] = 0;
2878 break;
2879 }
2880 }
2881 }
2882 if (enable_mpu[dev]) {
2883 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2884 chip->io_port + ESM_MPU401_PORT,
2885 MPU401_INFO_INTEGRATED |
2886 MPU401_INFO_IRQ_HOOK,
2887 -1, &chip->rmidi)) < 0) {
2888 dev_warn(card->dev, "skipping MPU-401 MIDI support..\n");
2889 }
2890 }
2891
2892 snd_es1968_create_gameport(chip, dev);
2893
2894#ifdef CONFIG_SND_ES1968_INPUT
2895 err = snd_es1968_input_register(chip);
2896 if (err)
2897 dev_warn(card->dev,
2898 "Input device registration failed with error %i", err);
2899#endif
2900
2901 snd_es1968_start_irq(chip);
2902
2903 chip->clock = clock[dev];
2904 if (! chip->clock)
2905 es1968_measure_clock(chip);
2906
2907 sprintf(card->longname, "%s at 0x%lx, irq %i",
2908 card->shortname, chip->io_port, chip->irq);
2909
2910 if ((err = snd_card_register(card)) < 0) {
2911 snd_card_free(card);
2912 return err;
2913 }
2914 pci_set_drvdata(pci, card);
2915 dev++;
2916 return 0;
2917}
2918
2919static void snd_es1968_remove(struct pci_dev *pci)
2920{
2921 snd_card_free(pci_get_drvdata(pci));
2922}
2923
2924static struct pci_driver es1968_driver = {
2925 .name = KBUILD_MODNAME,
2926 .id_table = snd_es1968_ids,
2927 .probe = snd_es1968_probe,
2928 .remove = snd_es1968_remove,
2929 .driver = {
2930 .pm = ES1968_PM_OPS,
2931 },
2932};
2933
2934module_pci_driver(es1968_driver);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Driver for ESS Maestro 1/2/2E Sound Card (started 21.8.99)
4 * Copyright (c) by Matze Braun <MatzeBraun@gmx.de>.
5 * Takashi Iwai <tiwai@suse.de>
6 *
7 * Most of the driver code comes from Zach Brown(zab@redhat.com)
8 * Alan Cox OSS Driver
9 * Rewritted from card-es1938.c source.
10 *
11 * TODO:
12 * Perhaps Synth
13 *
14 * Notes from Zach Brown about the driver code
15 *
16 * Hardware Description
17 *
18 * A working Maestro setup contains the Maestro chip wired to a
19 * codec or 2. In the Maestro we have the APUs, the ASSP, and the
20 * Wavecache. The APUs can be though of as virtual audio routing
21 * channels. They can take data from a number of sources and perform
22 * basic encodings of the data. The wavecache is a storehouse for
23 * PCM data. Typically it deals with PCI and interracts with the
24 * APUs. The ASSP is a wacky DSP like device that ESS is loth
25 * to release docs on. Thankfully it isn't required on the Maestro
26 * until you start doing insane things like FM emulation and surround
27 * encoding. The codecs are almost always AC-97 compliant codecs,
28 * but it appears that early Maestros may have had PT101 (an ESS
29 * part?) wired to them. The only real difference in the Maestro
30 * families is external goop like docking capability, memory for
31 * the ASSP, and initialization differences.
32 *
33 * Driver Operation
34 *
35 * We only drive the APU/Wavecache as typical DACs and drive the
36 * mixers in the codecs. There are 64 APUs. We assign 6 to each
37 * /dev/dsp? device. 2 channels for output, and 4 channels for
38 * input.
39 *
40 * Each APU can do a number of things, but we only really use
41 * 3 basic functions. For playback we use them to convert PCM
42 * data fetched over PCI by the wavecahche into analog data that
43 * is handed to the codec. One APU for mono, and a pair for stereo.
44 * When in stereo, the combination of smarts in the APU and Wavecache
45 * decide which wavecache gets the left or right channel.
46 *
47 * For record we still use the old overly mono system. For each in
48 * coming channel the data comes in from the codec, through a 'input'
49 * APU, through another rate converter APU, and then into memory via
50 * the wavecache and PCI. If its stereo, we mash it back into LRLR in
51 * software. The pass between the 2 APUs is supposedly what requires us
52 * to have a 512 byte buffer sitting around in wavecache/memory.
53 *
54 * The wavecache makes our life even more fun. First off, it can
55 * only address the first 28 bits of PCI address space, making it
56 * useless on quite a few architectures. Secondly, its insane.
57 * It claims to fetch from 4 regions of PCI space, each 4 meg in length.
58 * But that doesn't really work. You can only use 1 region. So all our
59 * allocations have to be in 4meg of each other. Booo. Hiss.
60 * So we have a module parameter, dsps_order, that is the order of
61 * the number of dsps to provide. All their buffer space is allocated
62 * on open time. The sonicvibes OSS routines we inherited really want
63 * power of 2 buffers, so we have all those next to each other, then
64 * 512 byte regions for the recording wavecaches. This ends up
65 * wasting quite a bit of memory. The only fixes I can see would be
66 * getting a kernel allocator that could work in zones, or figuring out
67 * just how to coerce the WP into doing what we want.
68 *
69 * The indirection of the various registers means we have to spinlock
70 * nearly all register accesses. We have the main register indirection
71 * like the wave cache, maestro registers, etc. Then we have beasts
72 * like the APU interface that is indirect registers gotten at through
73 * the main maestro indirection. Ouch. We spinlock around the actual
74 * ports on a per card basis. This means spinlock activity at each IO
75 * operation, but the only IO operation clusters are in non critical
76 * paths and it makes the code far easier to follow. Interrupts are
77 * blocked while holding the locks because the int handler has to
78 * get at some of them :(. The mixer interface doesn't, however.
79 * We also have an OSS state lock that is thrown around in a few
80 * places.
81 */
82
83#include <linux/io.h>
84#include <linux/delay.h>
85#include <linux/interrupt.h>
86#include <linux/init.h>
87#include <linux/pci.h>
88#include <linux/dma-mapping.h>
89#include <linux/slab.h>
90#include <linux/gameport.h>
91#include <linux/module.h>
92#include <linux/mutex.h>
93#include <linux/input.h>
94
95#include <sound/core.h>
96#include <sound/pcm.h>
97#include <sound/mpu401.h>
98#include <sound/ac97_codec.h>
99#include <sound/initval.h>
100
101#ifdef CONFIG_SND_ES1968_RADIO
102#include <media/drv-intf/tea575x.h>
103#endif
104
105#define CARD_NAME "ESS Maestro1/2"
106#define DRIVER_NAME "ES1968"
107
108MODULE_DESCRIPTION("ESS Maestro");
109MODULE_LICENSE("GPL");
110MODULE_SUPPORTED_DEVICE("{{ESS,Maestro 2e},"
111 "{ESS,Maestro 2},"
112 "{ESS,Maestro 1},"
113 "{TerraTec,DMX}}");
114
115#if IS_REACHABLE(CONFIG_GAMEPORT)
116#define SUPPORT_JOYSTICK 1
117#endif
118
119static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 1-MAX */
120static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
121static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
122static int total_bufsize[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1024 };
123static int pcm_substreams_p[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 4 };
124static int pcm_substreams_c[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 1 };
125static int clock[SNDRV_CARDS];
126static int use_pm[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
127static int enable_mpu[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = 2};
128#ifdef SUPPORT_JOYSTICK
129static bool joystick[SNDRV_CARDS];
130#endif
131static int radio_nr[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS - 1)] = -1};
132
133module_param_array(index, int, NULL, 0444);
134MODULE_PARM_DESC(index, "Index value for " CARD_NAME " soundcard.");
135module_param_array(id, charp, NULL, 0444);
136MODULE_PARM_DESC(id, "ID string for " CARD_NAME " soundcard.");
137module_param_array(enable, bool, NULL, 0444);
138MODULE_PARM_DESC(enable, "Enable " CARD_NAME " soundcard.");
139module_param_array(total_bufsize, int, NULL, 0444);
140MODULE_PARM_DESC(total_bufsize, "Total buffer size in kB.");
141module_param_array(pcm_substreams_p, int, NULL, 0444);
142MODULE_PARM_DESC(pcm_substreams_p, "PCM Playback substreams for " CARD_NAME " soundcard.");
143module_param_array(pcm_substreams_c, int, NULL, 0444);
144MODULE_PARM_DESC(pcm_substreams_c, "PCM Capture substreams for " CARD_NAME " soundcard.");
145module_param_array(clock, int, NULL, 0444);
146MODULE_PARM_DESC(clock, "Clock on " CARD_NAME " soundcard. (0 = auto-detect)");
147module_param_array(use_pm, int, NULL, 0444);
148MODULE_PARM_DESC(use_pm, "Toggle power-management. (0 = off, 1 = on, 2 = auto)");
149module_param_array(enable_mpu, int, NULL, 0444);
150MODULE_PARM_DESC(enable_mpu, "Enable MPU401. (0 = off, 1 = on, 2 = auto)");
151#ifdef SUPPORT_JOYSTICK
152module_param_array(joystick, bool, NULL, 0444);
153MODULE_PARM_DESC(joystick, "Enable joystick.");
154#endif
155module_param_array(radio_nr, int, NULL, 0444);
156MODULE_PARM_DESC(radio_nr, "Radio device numbers");
157
158
159
160#define NR_APUS 64
161#define NR_APU_REGS 16
162
163/* NEC Versas ? */
164#define NEC_VERSA_SUBID1 0x80581033
165#define NEC_VERSA_SUBID2 0x803c1033
166
167/* Mode Flags */
168#define ESS_FMT_STEREO 0x01
169#define ESS_FMT_16BIT 0x02
170
171#define DAC_RUNNING 1
172#define ADC_RUNNING 2
173
174/* Values for the ESM_LEGACY_AUDIO_CONTROL */
175
176#define ESS_DISABLE_AUDIO 0x8000
177#define ESS_ENABLE_SERIAL_IRQ 0x4000
178#define IO_ADRESS_ALIAS 0x0020
179#define MPU401_IRQ_ENABLE 0x0010
180#define MPU401_IO_ENABLE 0x0008
181#define GAME_IO_ENABLE 0x0004
182#define FM_IO_ENABLE 0x0002
183#define SB_IO_ENABLE 0x0001
184
185/* Values for the ESM_CONFIG_A */
186
187#define PIC_SNOOP1 0x4000
188#define PIC_SNOOP2 0x2000
189#define SAFEGUARD 0x0800
190#define DMA_CLEAR 0x0700
191#define DMA_DDMA 0x0000
192#define DMA_TDMA 0x0100
193#define DMA_PCPCI 0x0200
194#define POST_WRITE 0x0080
195#define PCI_TIMING 0x0040
196#define SWAP_LR 0x0020
197#define SUBTR_DECODE 0x0002
198
199/* Values for the ESM_CONFIG_B */
200
201#define SPDIF_CONFB 0x0100
202#define HWV_CONFB 0x0080
203#define DEBOUNCE 0x0040
204#define GPIO_CONFB 0x0020
205#define CHI_CONFB 0x0010
206#define IDMA_CONFB 0x0008 /*undoc */
207#define MIDI_FIX 0x0004 /*undoc */
208#define IRQ_TO_ISA 0x0001 /*undoc */
209
210/* Values for Ring Bus Control B */
211#define RINGB_2CODEC_ID_MASK 0x0003
212#define RINGB_DIS_VALIDATION 0x0008
213#define RINGB_EN_SPDIF 0x0010
214#define RINGB_EN_2CODEC 0x0020
215#define RINGB_SING_BIT_DUAL 0x0040
216
217/* ****Port Addresses**** */
218
219/* Write & Read */
220#define ESM_INDEX 0x02
221#define ESM_DATA 0x00
222
223/* AC97 + RingBus */
224#define ESM_AC97_INDEX 0x30
225#define ESM_AC97_DATA 0x32
226#define ESM_RING_BUS_DEST 0x34
227#define ESM_RING_BUS_CONTR_A 0x36
228#define ESM_RING_BUS_CONTR_B 0x38
229#define ESM_RING_BUS_SDO 0x3A
230
231/* WaveCache*/
232#define WC_INDEX 0x10
233#define WC_DATA 0x12
234#define WC_CONTROL 0x14
235
236/* ASSP*/
237#define ASSP_INDEX 0x80
238#define ASSP_MEMORY 0x82
239#define ASSP_DATA 0x84
240#define ASSP_CONTROL_A 0xA2
241#define ASSP_CONTROL_B 0xA4
242#define ASSP_CONTROL_C 0xA6
243#define ASSP_HOSTW_INDEX 0xA8
244#define ASSP_HOSTW_DATA 0xAA
245#define ASSP_HOSTW_IRQ 0xAC
246/* Midi */
247#define ESM_MPU401_PORT 0x98
248/* Others */
249#define ESM_PORT_HOST_IRQ 0x18
250
251#define IDR0_DATA_PORT 0x00
252#define IDR1_CRAM_POINTER 0x01
253#define IDR2_CRAM_DATA 0x02
254#define IDR3_WAVE_DATA 0x03
255#define IDR4_WAVE_PTR_LOW 0x04
256#define IDR5_WAVE_PTR_HI 0x05
257#define IDR6_TIMER_CTRL 0x06
258#define IDR7_WAVE_ROMRAM 0x07
259
260#define WRITEABLE_MAP 0xEFFFFF
261#define READABLE_MAP 0x64003F
262
263/* PCI Register */
264
265#define ESM_LEGACY_AUDIO_CONTROL 0x40
266#define ESM_ACPI_COMMAND 0x54
267#define ESM_CONFIG_A 0x50
268#define ESM_CONFIG_B 0x52
269#define ESM_DDMA 0x60
270
271/* Bob Bits */
272#define ESM_BOB_ENABLE 0x0001
273#define ESM_BOB_START 0x0001
274
275/* Host IRQ Control Bits */
276#define ESM_RESET_MAESTRO 0x8000
277#define ESM_RESET_DIRECTSOUND 0x4000
278#define ESM_HIRQ_ClkRun 0x0100
279#define ESM_HIRQ_HW_VOLUME 0x0040
280#define ESM_HIRQ_HARPO 0x0030 /* What's that? */
281#define ESM_HIRQ_ASSP 0x0010
282#define ESM_HIRQ_DSIE 0x0004
283#define ESM_HIRQ_MPU401 0x0002
284#define ESM_HIRQ_SB 0x0001
285
286/* Host IRQ Status Bits */
287#define ESM_MPU401_IRQ 0x02
288#define ESM_SB_IRQ 0x01
289#define ESM_SOUND_IRQ 0x04
290#define ESM_ASSP_IRQ 0x10
291#define ESM_HWVOL_IRQ 0x40
292
293#define ESS_SYSCLK 50000000
294#define ESM_BOB_FREQ 200
295#define ESM_BOB_FREQ_MAX 800
296
297#define ESM_FREQ_ESM1 (49152000L / 1024L) /* default rate 48000 */
298#define ESM_FREQ_ESM2 (50000000L / 1024L)
299
300/* APU Modes: reg 0x00, bit 4-7 */
301#define ESM_APU_MODE_SHIFT 4
302#define ESM_APU_MODE_MASK (0xf << 4)
303#define ESM_APU_OFF 0x00
304#define ESM_APU_16BITLINEAR 0x01 /* 16-Bit Linear Sample Player */
305#define ESM_APU_16BITSTEREO 0x02 /* 16-Bit Stereo Sample Player */
306#define ESM_APU_8BITLINEAR 0x03 /* 8-Bit Linear Sample Player */
307#define ESM_APU_8BITSTEREO 0x04 /* 8-Bit Stereo Sample Player */
308#define ESM_APU_8BITDIFF 0x05 /* 8-Bit Differential Sample Playrer */
309#define ESM_APU_DIGITALDELAY 0x06 /* Digital Delay Line */
310#define ESM_APU_DUALTAP 0x07 /* Dual Tap Reader */
311#define ESM_APU_CORRELATOR 0x08 /* Correlator */
312#define ESM_APU_INPUTMIXER 0x09 /* Input Mixer */
313#define ESM_APU_WAVETABLE 0x0A /* Wave Table Mode */
314#define ESM_APU_SRCONVERTOR 0x0B /* Sample Rate Convertor */
315#define ESM_APU_16BITPINGPONG 0x0C /* 16-Bit Ping-Pong Sample Player */
316#define ESM_APU_RESERVED1 0x0D /* Reserved 1 */
317#define ESM_APU_RESERVED2 0x0E /* Reserved 2 */
318#define ESM_APU_RESERVED3 0x0F /* Reserved 3 */
319
320/* reg 0x00 */
321#define ESM_APU_FILTER_Q_SHIFT 0
322#define ESM_APU_FILTER_Q_MASK (3 << 0)
323/* APU Filtey Q Control */
324#define ESM_APU_FILTER_LESSQ 0x00
325#define ESM_APU_FILTER_MOREQ 0x03
326
327#define ESM_APU_FILTER_TYPE_SHIFT 2
328#define ESM_APU_FILTER_TYPE_MASK (3 << 2)
329#define ESM_APU_ENV_TYPE_SHIFT 8
330#define ESM_APU_ENV_TYPE_MASK (3 << 8)
331#define ESM_APU_ENV_STATE_SHIFT 10
332#define ESM_APU_ENV_STATE_MASK (3 << 10)
333#define ESM_APU_END_CURVE (1 << 12)
334#define ESM_APU_INT_ON_LOOP (1 << 13)
335#define ESM_APU_DMA_ENABLE (1 << 14)
336
337/* reg 0x02 */
338#define ESM_APU_SUBMIX_GROUP_SHIRT 0
339#define ESM_APU_SUBMIX_GROUP_MASK (7 << 0)
340#define ESM_APU_SUBMIX_MODE (1 << 3)
341#define ESM_APU_6dB (1 << 4)
342#define ESM_APU_DUAL_EFFECT (1 << 5)
343#define ESM_APU_EFFECT_CHANNELS_SHIFT 6
344#define ESM_APU_EFFECT_CHANNELS_MASK (3 << 6)
345
346/* reg 0x03 */
347#define ESM_APU_STEP_SIZE_MASK 0x0fff
348
349/* reg 0x04 */
350#define ESM_APU_PHASE_SHIFT 0
351#define ESM_APU_PHASE_MASK (0xff << 0)
352#define ESM_APU_WAVE64K_PAGE_SHIFT 8 /* most 8bit of wave start offset */
353#define ESM_APU_WAVE64K_PAGE_MASK (0xff << 8)
354
355/* reg 0x05 - wave start offset */
356/* reg 0x06 - wave end offset */
357/* reg 0x07 - wave loop length */
358
359/* reg 0x08 */
360#define ESM_APU_EFFECT_GAIN_SHIFT 0
361#define ESM_APU_EFFECT_GAIN_MASK (0xff << 0)
362#define ESM_APU_TREMOLO_DEPTH_SHIFT 8
363#define ESM_APU_TREMOLO_DEPTH_MASK (0xf << 8)
364#define ESM_APU_TREMOLO_RATE_SHIFT 12
365#define ESM_APU_TREMOLO_RATE_MASK (0xf << 12)
366
367/* reg 0x09 */
368/* bit 0-7 amplitude dest? */
369#define ESM_APU_AMPLITUDE_NOW_SHIFT 8
370#define ESM_APU_AMPLITUDE_NOW_MASK (0xff << 8)
371
372/* reg 0x0a */
373#define ESM_APU_POLAR_PAN_SHIFT 0
374#define ESM_APU_POLAR_PAN_MASK (0x3f << 0)
375/* Polar Pan Control */
376#define ESM_APU_PAN_CENTER_CIRCLE 0x00
377#define ESM_APU_PAN_MIDDLE_RADIUS 0x01
378#define ESM_APU_PAN_OUTSIDE_RADIUS 0x02
379
380#define ESM_APU_FILTER_TUNING_SHIFT 8
381#define ESM_APU_FILTER_TUNING_MASK (0xff << 8)
382
383/* reg 0x0b */
384#define ESM_APU_DATA_SRC_A_SHIFT 0
385#define ESM_APU_DATA_SRC_A_MASK (0x7f << 0)
386#define ESM_APU_INV_POL_A (1 << 7)
387#define ESM_APU_DATA_SRC_B_SHIFT 8
388#define ESM_APU_DATA_SRC_B_MASK (0x7f << 8)
389#define ESM_APU_INV_POL_B (1 << 15)
390
391#define ESM_APU_VIBRATO_RATE_SHIFT 0
392#define ESM_APU_VIBRATO_RATE_MASK (0xf << 0)
393#define ESM_APU_VIBRATO_DEPTH_SHIFT 4
394#define ESM_APU_VIBRATO_DEPTH_MASK (0xf << 4)
395#define ESM_APU_VIBRATO_PHASE_SHIFT 8
396#define ESM_APU_VIBRATO_PHASE_MASK (0xff << 8)
397
398/* reg 0x0c */
399#define ESM_APU_RADIUS_SELECT (1 << 6)
400
401/* APU Filter Control */
402#define ESM_APU_FILTER_2POLE_LOPASS 0x00
403#define ESM_APU_FILTER_2POLE_BANDPASS 0x01
404#define ESM_APU_FILTER_2POLE_HIPASS 0x02
405#define ESM_APU_FILTER_1POLE_LOPASS 0x03
406#define ESM_APU_FILTER_1POLE_HIPASS 0x04
407#define ESM_APU_FILTER_OFF 0x05
408
409/* APU ATFP Type */
410#define ESM_APU_ATFP_AMPLITUDE 0x00
411#define ESM_APU_ATFP_TREMELO 0x01
412#define ESM_APU_ATFP_FILTER 0x02
413#define ESM_APU_ATFP_PAN 0x03
414
415/* APU ATFP Flags */
416#define ESM_APU_ATFP_FLG_OFF 0x00
417#define ESM_APU_ATFP_FLG_WAIT 0x01
418#define ESM_APU_ATFP_FLG_DONE 0x02
419#define ESM_APU_ATFP_FLG_INPROCESS 0x03
420
421
422/* capture mixing buffer size */
423#define ESM_MEM_ALIGN 0x1000
424#define ESM_MIXBUF_SIZE 0x400
425
426#define ESM_MODE_PLAY 0
427#define ESM_MODE_CAPTURE 1
428
429
430/* APU use in the driver */
431enum snd_enum_apu_type {
432 ESM_APU_PCM_PLAY,
433 ESM_APU_PCM_CAPTURE,
434 ESM_APU_PCM_RATECONV,
435 ESM_APU_FREE
436};
437
438/* chip type */
439enum {
440 TYPE_MAESTRO, TYPE_MAESTRO2, TYPE_MAESTRO2E
441};
442
443/* DMA Hack! */
444struct esm_memory {
445 struct snd_dma_buffer buf;
446 int empty; /* status */
447 struct list_head list;
448};
449
450/* Playback Channel */
451struct esschan {
452 int running;
453
454 u8 apu[4];
455 u8 apu_mode[4];
456
457 /* playback/capture pcm buffer */
458 struct esm_memory *memory;
459 /* capture mixer buffer */
460 struct esm_memory *mixbuf;
461
462 unsigned int hwptr; /* current hw pointer in bytes */
463 unsigned int count; /* sample counter in bytes */
464 unsigned int dma_size; /* total buffer size in bytes */
465 unsigned int frag_size; /* period size in bytes */
466 unsigned int wav_shift;
467 u16 base[4]; /* offset for ptr */
468
469 /* stereo/16bit flag */
470 unsigned char fmt;
471 int mode; /* playback / capture */
472
473 int bob_freq; /* required timer frequency */
474
475 struct snd_pcm_substream *substream;
476
477 /* linked list */
478 struct list_head list;
479
480#ifdef CONFIG_PM_SLEEP
481 u16 wc_map[4];
482#endif
483};
484
485struct es1968 {
486 /* Module Config */
487 int total_bufsize; /* in bytes */
488
489 int playback_streams, capture_streams;
490
491 unsigned int clock; /* clock */
492 /* for clock measurement */
493 unsigned int in_measurement: 1;
494 unsigned int measure_apu;
495 unsigned int measure_lastpos;
496 unsigned int measure_count;
497
498 /* buffer */
499 struct snd_dma_buffer dma;
500
501 /* Resources... */
502 int irq;
503 unsigned long io_port;
504 int type;
505 struct pci_dev *pci;
506 struct snd_card *card;
507 struct snd_pcm *pcm;
508 int do_pm; /* power-management enabled */
509
510 /* DMA memory block */
511 struct list_head buf_list;
512
513 /* ALSA Stuff */
514 struct snd_ac97 *ac97;
515 struct snd_rawmidi *rmidi;
516
517 spinlock_t reg_lock;
518 unsigned int in_suspend;
519
520 /* Maestro Stuff */
521 u16 maestro_map[32];
522 int bobclient; /* active timer instancs */
523 int bob_freq; /* timer frequency */
524 struct mutex memory_mutex; /* memory lock */
525
526 /* APU states */
527 unsigned char apu[NR_APUS];
528
529 /* active substreams */
530 struct list_head substream_list;
531 spinlock_t substream_lock;
532
533#ifdef CONFIG_PM_SLEEP
534 u16 apu_map[NR_APUS][NR_APU_REGS];
535#endif
536
537#ifdef SUPPORT_JOYSTICK
538 struct gameport *gameport;
539#endif
540
541#ifdef CONFIG_SND_ES1968_INPUT
542 struct input_dev *input_dev;
543 char phys[64]; /* physical device path */
544#else
545 struct snd_kcontrol *master_switch; /* for h/w volume control */
546 struct snd_kcontrol *master_volume;
547#endif
548 struct work_struct hwvol_work;
549
550#ifdef CONFIG_SND_ES1968_RADIO
551 struct v4l2_device v4l2_dev;
552 struct snd_tea575x tea;
553 unsigned int tea575x_tuner;
554#endif
555};
556
557static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id);
558
559static const struct pci_device_id snd_es1968_ids[] = {
560 /* Maestro 1 */
561 { 0x1285, 0x0100, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO },
562 /* Maestro 2 */
563 { 0x125d, 0x1968, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2 },
564 /* Maestro 2E */
565 { 0x125d, 0x1978, PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_MULTIMEDIA_AUDIO << 8, 0xffff00, TYPE_MAESTRO2E },
566 { 0, }
567};
568
569MODULE_DEVICE_TABLE(pci, snd_es1968_ids);
570
571/* *********************
572 * Low Level Funcs! *
573 *********************/
574
575/* no spinlock */
576static void __maestro_write(struct es1968 *chip, u16 reg, u16 data)
577{
578 outw(reg, chip->io_port + ESM_INDEX);
579 outw(data, chip->io_port + ESM_DATA);
580 chip->maestro_map[reg] = data;
581}
582
583static inline void maestro_write(struct es1968 *chip, u16 reg, u16 data)
584{
585 unsigned long flags;
586 spin_lock_irqsave(&chip->reg_lock, flags);
587 __maestro_write(chip, reg, data);
588 spin_unlock_irqrestore(&chip->reg_lock, flags);
589}
590
591/* no spinlock */
592static u16 __maestro_read(struct es1968 *chip, u16 reg)
593{
594 if (READABLE_MAP & (1 << reg)) {
595 outw(reg, chip->io_port + ESM_INDEX);
596 chip->maestro_map[reg] = inw(chip->io_port + ESM_DATA);
597 }
598 return chip->maestro_map[reg];
599}
600
601static inline u16 maestro_read(struct es1968 *chip, u16 reg)
602{
603 unsigned long flags;
604 u16 result;
605 spin_lock_irqsave(&chip->reg_lock, flags);
606 result = __maestro_read(chip, reg);
607 spin_unlock_irqrestore(&chip->reg_lock, flags);
608 return result;
609}
610
611/* Wait for the codec bus to be free */
612static int snd_es1968_ac97_wait(struct es1968 *chip)
613{
614 int timeout = 100000;
615
616 while (timeout-- > 0) {
617 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
618 return 0;
619 cond_resched();
620 }
621 dev_dbg(chip->card->dev, "ac97 timeout\n");
622 return 1; /* timeout */
623}
624
625static int snd_es1968_ac97_wait_poll(struct es1968 *chip)
626{
627 int timeout = 100000;
628
629 while (timeout-- > 0) {
630 if (!(inb(chip->io_port + ESM_AC97_INDEX) & 1))
631 return 0;
632 }
633 dev_dbg(chip->card->dev, "ac97 timeout\n");
634 return 1; /* timeout */
635}
636
637static void snd_es1968_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val)
638{
639 struct es1968 *chip = ac97->private_data;
640
641 snd_es1968_ac97_wait(chip);
642
643 /* Write the bus */
644 outw(val, chip->io_port + ESM_AC97_DATA);
645 /*msleep(1);*/
646 outb(reg, chip->io_port + ESM_AC97_INDEX);
647 /*msleep(1);*/
648}
649
650static unsigned short snd_es1968_ac97_read(struct snd_ac97 *ac97, unsigned short reg)
651{
652 u16 data = 0;
653 struct es1968 *chip = ac97->private_data;
654
655 snd_es1968_ac97_wait(chip);
656
657 outb(reg | 0x80, chip->io_port + ESM_AC97_INDEX);
658 /*msleep(1);*/
659
660 if (!snd_es1968_ac97_wait_poll(chip)) {
661 data = inw(chip->io_port + ESM_AC97_DATA);
662 /*msleep(1);*/
663 }
664
665 return data;
666}
667
668/* no spinlock */
669static void apu_index_set(struct es1968 *chip, u16 index)
670{
671 int i;
672 __maestro_write(chip, IDR1_CRAM_POINTER, index);
673 for (i = 0; i < 1000; i++)
674 if (__maestro_read(chip, IDR1_CRAM_POINTER) == index)
675 return;
676 dev_dbg(chip->card->dev, "APU register select failed. (Timeout)\n");
677}
678
679/* no spinlock */
680static void apu_data_set(struct es1968 *chip, u16 data)
681{
682 int i;
683 for (i = 0; i < 1000; i++) {
684 if (__maestro_read(chip, IDR0_DATA_PORT) == data)
685 return;
686 __maestro_write(chip, IDR0_DATA_PORT, data);
687 }
688 dev_dbg(chip->card->dev, "APU register set probably failed (Timeout)!\n");
689}
690
691/* no spinlock */
692static void __apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
693{
694 if (snd_BUG_ON(channel >= NR_APUS))
695 return;
696#ifdef CONFIG_PM_SLEEP
697 chip->apu_map[channel][reg] = data;
698#endif
699 reg |= (channel << 4);
700 apu_index_set(chip, reg);
701 apu_data_set(chip, data);
702}
703
704static void apu_set_register(struct es1968 *chip, u16 channel, u8 reg, u16 data)
705{
706 unsigned long flags;
707 spin_lock_irqsave(&chip->reg_lock, flags);
708 __apu_set_register(chip, channel, reg, data);
709 spin_unlock_irqrestore(&chip->reg_lock, flags);
710}
711
712static u16 __apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
713{
714 if (snd_BUG_ON(channel >= NR_APUS))
715 return 0;
716 reg |= (channel << 4);
717 apu_index_set(chip, reg);
718 return __maestro_read(chip, IDR0_DATA_PORT);
719}
720
721static u16 apu_get_register(struct es1968 *chip, u16 channel, u8 reg)
722{
723 unsigned long flags;
724 u16 v;
725 spin_lock_irqsave(&chip->reg_lock, flags);
726 v = __apu_get_register(chip, channel, reg);
727 spin_unlock_irqrestore(&chip->reg_lock, flags);
728 return v;
729}
730
731#if 0 /* ASSP is not supported */
732
733static void assp_set_register(struct es1968 *chip, u32 reg, u32 value)
734{
735 unsigned long flags;
736
737 spin_lock_irqsave(&chip->reg_lock, flags);
738 outl(reg, chip->io_port + ASSP_INDEX);
739 outl(value, chip->io_port + ASSP_DATA);
740 spin_unlock_irqrestore(&chip->reg_lock, flags);
741}
742
743static u32 assp_get_register(struct es1968 *chip, u32 reg)
744{
745 unsigned long flags;
746 u32 value;
747
748 spin_lock_irqsave(&chip->reg_lock, flags);
749 outl(reg, chip->io_port + ASSP_INDEX);
750 value = inl(chip->io_port + ASSP_DATA);
751 spin_unlock_irqrestore(&chip->reg_lock, flags);
752
753 return value;
754}
755
756#endif
757
758static void wave_set_register(struct es1968 *chip, u16 reg, u16 value)
759{
760 unsigned long flags;
761
762 spin_lock_irqsave(&chip->reg_lock, flags);
763 outw(reg, chip->io_port + WC_INDEX);
764 outw(value, chip->io_port + WC_DATA);
765 spin_unlock_irqrestore(&chip->reg_lock, flags);
766}
767
768static u16 wave_get_register(struct es1968 *chip, u16 reg)
769{
770 unsigned long flags;
771 u16 value;
772
773 spin_lock_irqsave(&chip->reg_lock, flags);
774 outw(reg, chip->io_port + WC_INDEX);
775 value = inw(chip->io_port + WC_DATA);
776 spin_unlock_irqrestore(&chip->reg_lock, flags);
777
778 return value;
779}
780
781/* *******************
782 * Bob the Timer! *
783 *******************/
784
785static void snd_es1968_bob_stop(struct es1968 *chip)
786{
787 u16 reg;
788
789 reg = __maestro_read(chip, 0x11);
790 reg &= ~ESM_BOB_ENABLE;
791 __maestro_write(chip, 0x11, reg);
792 reg = __maestro_read(chip, 0x17);
793 reg &= ~ESM_BOB_START;
794 __maestro_write(chip, 0x17, reg);
795}
796
797static void snd_es1968_bob_start(struct es1968 *chip)
798{
799 int prescale;
800 int divide;
801
802 /* compute ideal interrupt frequency for buffer size & play rate */
803 /* first, find best prescaler value to match freq */
804 for (prescale = 5; prescale < 12; prescale++)
805 if (chip->bob_freq > (ESS_SYSCLK >> (prescale + 9)))
806 break;
807
808 /* next, back off prescaler whilst getting divider into optimum range */
809 divide = 1;
810 while ((prescale > 5) && (divide < 32)) {
811 prescale--;
812 divide <<= 1;
813 }
814 divide >>= 1;
815
816 /* now fine-tune the divider for best match */
817 for (; divide < 31; divide++)
818 if (chip->bob_freq >
819 ((ESS_SYSCLK >> (prescale + 9)) / (divide + 1))) break;
820
821 /* divide = 0 is illegal, but don't let prescale = 4! */
822 if (divide == 0) {
823 divide++;
824 if (prescale > 5)
825 prescale--;
826 } else if (divide > 1)
827 divide--;
828
829 __maestro_write(chip, 6, 0x9000 | (prescale << 5) | divide); /* set reg */
830
831 /* Now set IDR 11/17 */
832 __maestro_write(chip, 0x11, __maestro_read(chip, 0x11) | 1);
833 __maestro_write(chip, 0x17, __maestro_read(chip, 0x17) | 1);
834}
835
836/* call with substream spinlock */
837static void snd_es1968_bob_inc(struct es1968 *chip, int freq)
838{
839 chip->bobclient++;
840 if (chip->bobclient == 1) {
841 chip->bob_freq = freq;
842 snd_es1968_bob_start(chip);
843 } else if (chip->bob_freq < freq) {
844 snd_es1968_bob_stop(chip);
845 chip->bob_freq = freq;
846 snd_es1968_bob_start(chip);
847 }
848}
849
850/* call with substream spinlock */
851static void snd_es1968_bob_dec(struct es1968 *chip)
852{
853 chip->bobclient--;
854 if (chip->bobclient <= 0)
855 snd_es1968_bob_stop(chip);
856 else if (chip->bob_freq > ESM_BOB_FREQ) {
857 /* check reduction of timer frequency */
858 int max_freq = ESM_BOB_FREQ;
859 struct esschan *es;
860 list_for_each_entry(es, &chip->substream_list, list) {
861 if (max_freq < es->bob_freq)
862 max_freq = es->bob_freq;
863 }
864 if (max_freq != chip->bob_freq) {
865 snd_es1968_bob_stop(chip);
866 chip->bob_freq = max_freq;
867 snd_es1968_bob_start(chip);
868 }
869 }
870}
871
872static int
873snd_es1968_calc_bob_rate(struct es1968 *chip, struct esschan *es,
874 struct snd_pcm_runtime *runtime)
875{
876 /* we acquire 4 interrupts per period for precise control.. */
877 int freq = runtime->rate * 4;
878 if (es->fmt & ESS_FMT_STEREO)
879 freq <<= 1;
880 if (es->fmt & ESS_FMT_16BIT)
881 freq <<= 1;
882 freq /= es->frag_size;
883 if (freq < ESM_BOB_FREQ)
884 freq = ESM_BOB_FREQ;
885 else if (freq > ESM_BOB_FREQ_MAX)
886 freq = ESM_BOB_FREQ_MAX;
887 return freq;
888}
889
890
891/*************
892 * PCM Part *
893 *************/
894
895static u32 snd_es1968_compute_rate(struct es1968 *chip, u32 freq)
896{
897 u32 rate = (freq << 16) / chip->clock;
898#if 0 /* XXX: do we need this? */
899 if (rate > 0x10000)
900 rate = 0x10000;
901#endif
902 return rate;
903}
904
905/* get current pointer */
906static inline unsigned int
907snd_es1968_get_dma_ptr(struct es1968 *chip, struct esschan *es)
908{
909 unsigned int offset;
910
911 offset = apu_get_register(chip, es->apu[0], 5);
912
913 offset -= es->base[0];
914
915 return (offset & 0xFFFE); /* hardware is in words */
916}
917
918static void snd_es1968_apu_set_freq(struct es1968 *chip, int apu, int freq)
919{
920 apu_set_register(chip, apu, 2,
921 (apu_get_register(chip, apu, 2) & 0x00FF) |
922 ((freq & 0xff) << 8) | 0x10);
923 apu_set_register(chip, apu, 3, freq >> 8);
924}
925
926/* spin lock held */
927static inline void snd_es1968_trigger_apu(struct es1968 *esm, int apu, int mode)
928{
929 /* set the APU mode */
930 __apu_set_register(esm, apu, 0,
931 (__apu_get_register(esm, apu, 0) & 0xff0f) |
932 (mode << 4));
933}
934
935static void snd_es1968_pcm_start(struct es1968 *chip, struct esschan *es)
936{
937 spin_lock(&chip->reg_lock);
938 __apu_set_register(chip, es->apu[0], 5, es->base[0]);
939 snd_es1968_trigger_apu(chip, es->apu[0], es->apu_mode[0]);
940 if (es->mode == ESM_MODE_CAPTURE) {
941 __apu_set_register(chip, es->apu[2], 5, es->base[2]);
942 snd_es1968_trigger_apu(chip, es->apu[2], es->apu_mode[2]);
943 }
944 if (es->fmt & ESS_FMT_STEREO) {
945 __apu_set_register(chip, es->apu[1], 5, es->base[1]);
946 snd_es1968_trigger_apu(chip, es->apu[1], es->apu_mode[1]);
947 if (es->mode == ESM_MODE_CAPTURE) {
948 __apu_set_register(chip, es->apu[3], 5, es->base[3]);
949 snd_es1968_trigger_apu(chip, es->apu[3], es->apu_mode[3]);
950 }
951 }
952 spin_unlock(&chip->reg_lock);
953}
954
955static void snd_es1968_pcm_stop(struct es1968 *chip, struct esschan *es)
956{
957 spin_lock(&chip->reg_lock);
958 snd_es1968_trigger_apu(chip, es->apu[0], 0);
959 snd_es1968_trigger_apu(chip, es->apu[1], 0);
960 if (es->mode == ESM_MODE_CAPTURE) {
961 snd_es1968_trigger_apu(chip, es->apu[2], 0);
962 snd_es1968_trigger_apu(chip, es->apu[3], 0);
963 }
964 spin_unlock(&chip->reg_lock);
965}
966
967/* set the wavecache control reg */
968static void snd_es1968_program_wavecache(struct es1968 *chip, struct esschan *es,
969 int channel, u32 addr, int capture)
970{
971 u32 tmpval = (addr - 0x10) & 0xFFF8;
972
973 if (! capture) {
974 if (!(es->fmt & ESS_FMT_16BIT))
975 tmpval |= 4; /* 8bit */
976 if (es->fmt & ESS_FMT_STEREO)
977 tmpval |= 2; /* stereo */
978 }
979
980 /* set the wavecache control reg */
981 wave_set_register(chip, es->apu[channel] << 3, tmpval);
982
983#ifdef CONFIG_PM_SLEEP
984 es->wc_map[channel] = tmpval;
985#endif
986}
987
988
989static void snd_es1968_playback_setup(struct es1968 *chip, struct esschan *es,
990 struct snd_pcm_runtime *runtime)
991{
992 u32 pa;
993 int high_apu = 0;
994 int channel, apu;
995 int i, size;
996 unsigned long flags;
997 u32 freq;
998
999 size = es->dma_size >> es->wav_shift;
1000
1001 if (es->fmt & ESS_FMT_STEREO)
1002 high_apu++;
1003
1004 for (channel = 0; channel <= high_apu; channel++) {
1005 apu = es->apu[channel];
1006
1007 snd_es1968_program_wavecache(chip, es, channel, es->memory->buf.addr, 0);
1008
1009 /* Offset to PCMBAR */
1010 pa = es->memory->buf.addr;
1011 pa -= chip->dma.addr;
1012 pa >>= 1; /* words */
1013
1014 pa |= 0x00400000; /* System RAM (Bit 22) */
1015
1016 if (es->fmt & ESS_FMT_STEREO) {
1017 /* Enable stereo */
1018 if (channel)
1019 pa |= 0x00800000; /* (Bit 23) */
1020 if (es->fmt & ESS_FMT_16BIT)
1021 pa >>= 1;
1022 }
1023
1024 /* base offset of dma calcs when reading the pointer
1025 on this left one */
1026 es->base[channel] = pa & 0xFFFF;
1027
1028 for (i = 0; i < 16; i++)
1029 apu_set_register(chip, apu, i, 0x0000);
1030
1031 /* Load the buffer into the wave engine */
1032 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1033 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1034 apu_set_register(chip, apu, 6, (pa + size) & 0xFFFF);
1035 /* setting loop == sample len */
1036 apu_set_register(chip, apu, 7, size);
1037
1038 /* clear effects/env.. */
1039 apu_set_register(chip, apu, 8, 0x0000);
1040 /* set amp now to 0xd0 (?), low byte is 'amplitude dest'? */
1041 apu_set_register(chip, apu, 9, 0xD000);
1042
1043 /* clear routing stuff */
1044 apu_set_register(chip, apu, 11, 0x0000);
1045 /* dma on, no envelopes, filter to all 1s) */
1046 apu_set_register(chip, apu, 0, 0x400F);
1047
1048 if (es->fmt & ESS_FMT_16BIT)
1049 es->apu_mode[channel] = ESM_APU_16BITLINEAR;
1050 else
1051 es->apu_mode[channel] = ESM_APU_8BITLINEAR;
1052
1053 if (es->fmt & ESS_FMT_STEREO) {
1054 /* set panning: left or right */
1055 /* Check: different panning. On my Canyon 3D Chipset the
1056 Channels are swapped. I don't know, about the output
1057 to the SPDif Link. Perhaps you have to change this
1058 and not the APU Regs 4-5. */
1059 apu_set_register(chip, apu, 10,
1060 0x8F00 | (channel ? 0 : 0x10));
1061 es->apu_mode[channel] += 1; /* stereo */
1062 } else
1063 apu_set_register(chip, apu, 10, 0x8F08);
1064 }
1065
1066 spin_lock_irqsave(&chip->reg_lock, flags);
1067 /* clear WP interrupts */
1068 outw(1, chip->io_port + 0x04);
1069 /* enable WP ints */
1070 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1071 spin_unlock_irqrestore(&chip->reg_lock, flags);
1072
1073 freq = runtime->rate;
1074 /* set frequency */
1075 if (freq > 48000)
1076 freq = 48000;
1077 if (freq < 4000)
1078 freq = 4000;
1079
1080 /* hmmm.. */
1081 if (!(es->fmt & ESS_FMT_16BIT) && !(es->fmt & ESS_FMT_STEREO))
1082 freq >>= 1;
1083
1084 freq = snd_es1968_compute_rate(chip, freq);
1085
1086 /* Load the frequency, turn on 6dB */
1087 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1088 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1089}
1090
1091
1092static void init_capture_apu(struct es1968 *chip, struct esschan *es, int channel,
1093 unsigned int pa, unsigned int bsize,
1094 int mode, int route)
1095{
1096 int i, apu = es->apu[channel];
1097
1098 es->apu_mode[channel] = mode;
1099
1100 /* set the wavecache control reg */
1101 snd_es1968_program_wavecache(chip, es, channel, pa, 1);
1102
1103 /* Offset to PCMBAR */
1104 pa -= chip->dma.addr;
1105 pa >>= 1; /* words */
1106
1107 /* base offset of dma calcs when reading the pointer
1108 on this left one */
1109 es->base[channel] = pa & 0xFFFF;
1110 pa |= 0x00400000; /* bit 22 -> System RAM */
1111
1112 /* Begin loading the APU */
1113 for (i = 0; i < 16; i++)
1114 apu_set_register(chip, apu, i, 0x0000);
1115
1116 /* need to enable subgroups.. and we should probably
1117 have different groups for different /dev/dsps.. */
1118 apu_set_register(chip, apu, 2, 0x8);
1119
1120 /* Load the buffer into the wave engine */
1121 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xFF) << 8);
1122 apu_set_register(chip, apu, 5, pa & 0xFFFF);
1123 apu_set_register(chip, apu, 6, (pa + bsize) & 0xFFFF);
1124 apu_set_register(chip, apu, 7, bsize);
1125 /* clear effects/env.. */
1126 apu_set_register(chip, apu, 8, 0x00F0);
1127 /* amplitude now? sure. why not. */
1128 apu_set_register(chip, apu, 9, 0x0000);
1129 /* set filter tune, radius, polar pan */
1130 apu_set_register(chip, apu, 10, 0x8F08);
1131 /* route input */
1132 apu_set_register(chip, apu, 11, route);
1133 /* dma on, no envelopes, filter to all 1s) */
1134 apu_set_register(chip, apu, 0, 0x400F);
1135}
1136
1137static void snd_es1968_capture_setup(struct es1968 *chip, struct esschan *es,
1138 struct snd_pcm_runtime *runtime)
1139{
1140 int size;
1141 u32 freq;
1142 unsigned long flags;
1143
1144 size = es->dma_size >> es->wav_shift;
1145
1146 /* APU assignments:
1147 0 = mono/left SRC
1148 1 = right SRC
1149 2 = mono/left Input Mixer
1150 3 = right Input Mixer
1151 */
1152 /* data seems to flow from the codec, through an apu into
1153 the 'mixbuf' bit of page, then through the SRC apu
1154 and out to the real 'buffer'. ok. sure. */
1155
1156 /* input mixer (left/mono) */
1157 /* parallel in crap, see maestro reg 0xC [8-11] */
1158 init_capture_apu(chip, es, 2,
1159 es->mixbuf->buf.addr, ESM_MIXBUF_SIZE/4, /* in words */
1160 ESM_APU_INPUTMIXER, 0x14);
1161 /* SRC (left/mono); get input from inputing apu */
1162 init_capture_apu(chip, es, 0, es->memory->buf.addr, size,
1163 ESM_APU_SRCONVERTOR, es->apu[2]);
1164 if (es->fmt & ESS_FMT_STEREO) {
1165 /* input mixer (right) */
1166 init_capture_apu(chip, es, 3,
1167 es->mixbuf->buf.addr + ESM_MIXBUF_SIZE/2,
1168 ESM_MIXBUF_SIZE/4, /* in words */
1169 ESM_APU_INPUTMIXER, 0x15);
1170 /* SRC (right) */
1171 init_capture_apu(chip, es, 1,
1172 es->memory->buf.addr + size*2, size,
1173 ESM_APU_SRCONVERTOR, es->apu[3]);
1174 }
1175
1176 freq = runtime->rate;
1177 /* Sample Rate conversion APUs don't like 0x10000 for their rate */
1178 if (freq > 47999)
1179 freq = 47999;
1180 if (freq < 4000)
1181 freq = 4000;
1182
1183 freq = snd_es1968_compute_rate(chip, freq);
1184
1185 /* Load the frequency, turn on 6dB */
1186 snd_es1968_apu_set_freq(chip, es->apu[0], freq);
1187 snd_es1968_apu_set_freq(chip, es->apu[1], freq);
1188
1189 /* fix mixer rate at 48khz. and its _must_ be 0x10000. */
1190 freq = 0x10000;
1191 snd_es1968_apu_set_freq(chip, es->apu[2], freq);
1192 snd_es1968_apu_set_freq(chip, es->apu[3], freq);
1193
1194 spin_lock_irqsave(&chip->reg_lock, flags);
1195 /* clear WP interrupts */
1196 outw(1, chip->io_port + 0x04);
1197 /* enable WP ints */
1198 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ);
1199 spin_unlock_irqrestore(&chip->reg_lock, flags);
1200}
1201
1202/*******************
1203 * ALSA Interface *
1204 *******************/
1205
1206static int snd_es1968_pcm_prepare(struct snd_pcm_substream *substream)
1207{
1208 struct es1968 *chip = snd_pcm_substream_chip(substream);
1209 struct snd_pcm_runtime *runtime = substream->runtime;
1210 struct esschan *es = runtime->private_data;
1211
1212 es->dma_size = snd_pcm_lib_buffer_bytes(substream);
1213 es->frag_size = snd_pcm_lib_period_bytes(substream);
1214
1215 es->wav_shift = 1; /* maestro handles always 16bit */
1216 es->fmt = 0;
1217 if (snd_pcm_format_width(runtime->format) == 16)
1218 es->fmt |= ESS_FMT_16BIT;
1219 if (runtime->channels > 1) {
1220 es->fmt |= ESS_FMT_STEREO;
1221 if (es->fmt & ESS_FMT_16BIT) /* 8bit is already word shifted */
1222 es->wav_shift++;
1223 }
1224 es->bob_freq = snd_es1968_calc_bob_rate(chip, es, runtime);
1225
1226 switch (es->mode) {
1227 case ESM_MODE_PLAY:
1228 snd_es1968_playback_setup(chip, es, runtime);
1229 break;
1230 case ESM_MODE_CAPTURE:
1231 snd_es1968_capture_setup(chip, es, runtime);
1232 break;
1233 }
1234
1235 return 0;
1236}
1237
1238static int snd_es1968_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1239{
1240 struct es1968 *chip = snd_pcm_substream_chip(substream);
1241 struct esschan *es = substream->runtime->private_data;
1242
1243 spin_lock(&chip->substream_lock);
1244 switch (cmd) {
1245 case SNDRV_PCM_TRIGGER_START:
1246 case SNDRV_PCM_TRIGGER_RESUME:
1247 if (es->running)
1248 break;
1249 snd_es1968_bob_inc(chip, es->bob_freq);
1250 es->count = 0;
1251 es->hwptr = 0;
1252 snd_es1968_pcm_start(chip, es);
1253 es->running = 1;
1254 break;
1255 case SNDRV_PCM_TRIGGER_STOP:
1256 case SNDRV_PCM_TRIGGER_SUSPEND:
1257 if (! es->running)
1258 break;
1259 snd_es1968_pcm_stop(chip, es);
1260 es->running = 0;
1261 snd_es1968_bob_dec(chip);
1262 break;
1263 }
1264 spin_unlock(&chip->substream_lock);
1265 return 0;
1266}
1267
1268static snd_pcm_uframes_t snd_es1968_pcm_pointer(struct snd_pcm_substream *substream)
1269{
1270 struct es1968 *chip = snd_pcm_substream_chip(substream);
1271 struct esschan *es = substream->runtime->private_data;
1272 unsigned int ptr;
1273
1274 ptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1275
1276 return bytes_to_frames(substream->runtime, ptr % es->dma_size);
1277}
1278
1279static const struct snd_pcm_hardware snd_es1968_playback = {
1280 .info = (SNDRV_PCM_INFO_MMAP |
1281 SNDRV_PCM_INFO_MMAP_VALID |
1282 SNDRV_PCM_INFO_INTERLEAVED |
1283 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1284 /*SNDRV_PCM_INFO_PAUSE |*/
1285 SNDRV_PCM_INFO_RESUME),
1286 .formats = SNDRV_PCM_FMTBIT_U8 | SNDRV_PCM_FMTBIT_S16_LE,
1287 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1288 .rate_min = 4000,
1289 .rate_max = 48000,
1290 .channels_min = 1,
1291 .channels_max = 2,
1292 .buffer_bytes_max = 65536,
1293 .period_bytes_min = 256,
1294 .period_bytes_max = 65536,
1295 .periods_min = 1,
1296 .periods_max = 1024,
1297 .fifo_size = 0,
1298};
1299
1300static const struct snd_pcm_hardware snd_es1968_capture = {
1301 .info = (SNDRV_PCM_INFO_NONINTERLEAVED |
1302 SNDRV_PCM_INFO_MMAP |
1303 SNDRV_PCM_INFO_MMAP_VALID |
1304 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1305 /*SNDRV_PCM_INFO_PAUSE |*/
1306 SNDRV_PCM_INFO_RESUME),
1307 .formats = /*SNDRV_PCM_FMTBIT_U8 |*/ SNDRV_PCM_FMTBIT_S16_LE,
1308 .rates = SNDRV_PCM_RATE_CONTINUOUS | SNDRV_PCM_RATE_8000_48000,
1309 .rate_min = 4000,
1310 .rate_max = 48000,
1311 .channels_min = 1,
1312 .channels_max = 2,
1313 .buffer_bytes_max = 65536,
1314 .period_bytes_min = 256,
1315 .period_bytes_max = 65536,
1316 .periods_min = 1,
1317 .periods_max = 1024,
1318 .fifo_size = 0,
1319};
1320
1321/* *************************
1322 * DMA memory management *
1323 *************************/
1324
1325/* Because the Maestro can only take addresses relative to the PCM base address
1326 register :( */
1327
1328static int calc_available_memory_size(struct es1968 *chip)
1329{
1330 int max_size = 0;
1331 struct esm_memory *buf;
1332
1333 mutex_lock(&chip->memory_mutex);
1334 list_for_each_entry(buf, &chip->buf_list, list) {
1335 if (buf->empty && buf->buf.bytes > max_size)
1336 max_size = buf->buf.bytes;
1337 }
1338 mutex_unlock(&chip->memory_mutex);
1339 if (max_size >= 128*1024)
1340 max_size = 127*1024;
1341 return max_size;
1342}
1343
1344/* allocate a new memory chunk with the specified size */
1345static struct esm_memory *snd_es1968_new_memory(struct es1968 *chip, int size)
1346{
1347 struct esm_memory *buf;
1348
1349 size = ALIGN(size, ESM_MEM_ALIGN);
1350 mutex_lock(&chip->memory_mutex);
1351 list_for_each_entry(buf, &chip->buf_list, list) {
1352 if (buf->empty && buf->buf.bytes >= size)
1353 goto __found;
1354 }
1355 mutex_unlock(&chip->memory_mutex);
1356 return NULL;
1357
1358__found:
1359 if (buf->buf.bytes > size) {
1360 struct esm_memory *chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1361 if (chunk == NULL) {
1362 mutex_unlock(&chip->memory_mutex);
1363 return NULL;
1364 }
1365 chunk->buf = buf->buf;
1366 chunk->buf.bytes -= size;
1367 chunk->buf.area += size;
1368 chunk->buf.addr += size;
1369 chunk->empty = 1;
1370 buf->buf.bytes = size;
1371 list_add(&chunk->list, &buf->list);
1372 }
1373 buf->empty = 0;
1374 mutex_unlock(&chip->memory_mutex);
1375 return buf;
1376}
1377
1378/* free a memory chunk */
1379static void snd_es1968_free_memory(struct es1968 *chip, struct esm_memory *buf)
1380{
1381 struct esm_memory *chunk;
1382
1383 mutex_lock(&chip->memory_mutex);
1384 buf->empty = 1;
1385 if (buf->list.prev != &chip->buf_list) {
1386 chunk = list_entry(buf->list.prev, struct esm_memory, list);
1387 if (chunk->empty) {
1388 chunk->buf.bytes += buf->buf.bytes;
1389 list_del(&buf->list);
1390 kfree(buf);
1391 buf = chunk;
1392 }
1393 }
1394 if (buf->list.next != &chip->buf_list) {
1395 chunk = list_entry(buf->list.next, struct esm_memory, list);
1396 if (chunk->empty) {
1397 buf->buf.bytes += chunk->buf.bytes;
1398 list_del(&chunk->list);
1399 kfree(chunk);
1400 }
1401 }
1402 mutex_unlock(&chip->memory_mutex);
1403}
1404
1405static void snd_es1968_free_dmabuf(struct es1968 *chip)
1406{
1407 struct list_head *p;
1408
1409 if (! chip->dma.area)
1410 return;
1411 snd_dma_free_pages(&chip->dma);
1412 while ((p = chip->buf_list.next) != &chip->buf_list) {
1413 struct esm_memory *chunk = list_entry(p, struct esm_memory, list);
1414 list_del(p);
1415 kfree(chunk);
1416 }
1417}
1418
1419static int
1420snd_es1968_init_dmabuf(struct es1968 *chip)
1421{
1422 int err;
1423 struct esm_memory *chunk;
1424
1425 chip->dma.dev.type = SNDRV_DMA_TYPE_DEV;
1426 chip->dma.dev.dev = snd_dma_pci_data(chip->pci);
1427 err = snd_dma_alloc_pages_fallback(SNDRV_DMA_TYPE_DEV,
1428 snd_dma_pci_data(chip->pci),
1429 chip->total_bufsize, &chip->dma);
1430 if (err < 0 || ! chip->dma.area) {
1431 dev_err(chip->card->dev,
1432 "can't allocate dma pages for size %d\n",
1433 chip->total_bufsize);
1434 return -ENOMEM;
1435 }
1436 if ((chip->dma.addr + chip->dma.bytes - 1) & ~((1 << 28) - 1)) {
1437 snd_dma_free_pages(&chip->dma);
1438 dev_err(chip->card->dev, "DMA buffer beyond 256MB.\n");
1439 return -ENOMEM;
1440 }
1441
1442 INIT_LIST_HEAD(&chip->buf_list);
1443 /* allocate an empty chunk */
1444 chunk = kmalloc(sizeof(*chunk), GFP_KERNEL);
1445 if (chunk == NULL) {
1446 snd_es1968_free_dmabuf(chip);
1447 return -ENOMEM;
1448 }
1449 memset(chip->dma.area, 0, ESM_MEM_ALIGN);
1450 chunk->buf = chip->dma;
1451 chunk->buf.area += ESM_MEM_ALIGN;
1452 chunk->buf.addr += ESM_MEM_ALIGN;
1453 chunk->buf.bytes -= ESM_MEM_ALIGN;
1454 chunk->empty = 1;
1455 list_add(&chunk->list, &chip->buf_list);
1456
1457 return 0;
1458}
1459
1460/* setup the dma_areas */
1461/* buffer is extracted from the pre-allocated memory chunk */
1462static int snd_es1968_hw_params(struct snd_pcm_substream *substream,
1463 struct snd_pcm_hw_params *hw_params)
1464{
1465 struct es1968 *chip = snd_pcm_substream_chip(substream);
1466 struct snd_pcm_runtime *runtime = substream->runtime;
1467 struct esschan *chan = runtime->private_data;
1468 int size = params_buffer_bytes(hw_params);
1469
1470 if (chan->memory) {
1471 if (chan->memory->buf.bytes >= size) {
1472 runtime->dma_bytes = size;
1473 return 0;
1474 }
1475 snd_es1968_free_memory(chip, chan->memory);
1476 }
1477 chan->memory = snd_es1968_new_memory(chip, size);
1478 if (chan->memory == NULL) {
1479 dev_dbg(chip->card->dev,
1480 "cannot allocate dma buffer: size = %d\n", size);
1481 return -ENOMEM;
1482 }
1483 snd_pcm_set_runtime_buffer(substream, &chan->memory->buf);
1484 return 1; /* area was changed */
1485}
1486
1487/* remove dma areas if allocated */
1488static int snd_es1968_hw_free(struct snd_pcm_substream *substream)
1489{
1490 struct es1968 *chip = snd_pcm_substream_chip(substream);
1491 struct snd_pcm_runtime *runtime = substream->runtime;
1492 struct esschan *chan;
1493
1494 if (runtime->private_data == NULL)
1495 return 0;
1496 chan = runtime->private_data;
1497 if (chan->memory) {
1498 snd_es1968_free_memory(chip, chan->memory);
1499 chan->memory = NULL;
1500 }
1501 return 0;
1502}
1503
1504
1505/*
1506 * allocate APU pair
1507 */
1508static int snd_es1968_alloc_apu_pair(struct es1968 *chip, int type)
1509{
1510 int apu;
1511
1512 for (apu = 0; apu < NR_APUS; apu += 2) {
1513 if (chip->apu[apu] == ESM_APU_FREE &&
1514 chip->apu[apu + 1] == ESM_APU_FREE) {
1515 chip->apu[apu] = chip->apu[apu + 1] = type;
1516 return apu;
1517 }
1518 }
1519 return -EBUSY;
1520}
1521
1522/*
1523 * release APU pair
1524 */
1525static void snd_es1968_free_apu_pair(struct es1968 *chip, int apu)
1526{
1527 chip->apu[apu] = chip->apu[apu + 1] = ESM_APU_FREE;
1528}
1529
1530
1531/******************
1532 * PCM open/close *
1533 ******************/
1534
1535static int snd_es1968_playback_open(struct snd_pcm_substream *substream)
1536{
1537 struct es1968 *chip = snd_pcm_substream_chip(substream);
1538 struct snd_pcm_runtime *runtime = substream->runtime;
1539 struct esschan *es;
1540 int apu1;
1541
1542 /* search 2 APUs */
1543 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY);
1544 if (apu1 < 0)
1545 return apu1;
1546
1547 es = kzalloc(sizeof(*es), GFP_KERNEL);
1548 if (!es) {
1549 snd_es1968_free_apu_pair(chip, apu1);
1550 return -ENOMEM;
1551 }
1552
1553 es->apu[0] = apu1;
1554 es->apu[1] = apu1 + 1;
1555 es->apu_mode[0] = 0;
1556 es->apu_mode[1] = 0;
1557 es->running = 0;
1558 es->substream = substream;
1559 es->mode = ESM_MODE_PLAY;
1560
1561 runtime->private_data = es;
1562 runtime->hw = snd_es1968_playback;
1563 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1564 calc_available_memory_size(chip);
1565
1566 spin_lock_irq(&chip->substream_lock);
1567 list_add(&es->list, &chip->substream_list);
1568 spin_unlock_irq(&chip->substream_lock);
1569
1570 return 0;
1571}
1572
1573static int snd_es1968_capture_open(struct snd_pcm_substream *substream)
1574{
1575 struct snd_pcm_runtime *runtime = substream->runtime;
1576 struct es1968 *chip = snd_pcm_substream_chip(substream);
1577 struct esschan *es;
1578 int apu1, apu2;
1579
1580 apu1 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_CAPTURE);
1581 if (apu1 < 0)
1582 return apu1;
1583 apu2 = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_RATECONV);
1584 if (apu2 < 0) {
1585 snd_es1968_free_apu_pair(chip, apu1);
1586 return apu2;
1587 }
1588
1589 es = kzalloc(sizeof(*es), GFP_KERNEL);
1590 if (!es) {
1591 snd_es1968_free_apu_pair(chip, apu1);
1592 snd_es1968_free_apu_pair(chip, apu2);
1593 return -ENOMEM;
1594 }
1595
1596 es->apu[0] = apu1;
1597 es->apu[1] = apu1 + 1;
1598 es->apu[2] = apu2;
1599 es->apu[3] = apu2 + 1;
1600 es->apu_mode[0] = 0;
1601 es->apu_mode[1] = 0;
1602 es->apu_mode[2] = 0;
1603 es->apu_mode[3] = 0;
1604 es->running = 0;
1605 es->substream = substream;
1606 es->mode = ESM_MODE_CAPTURE;
1607
1608 /* get mixbuffer */
1609 if ((es->mixbuf = snd_es1968_new_memory(chip, ESM_MIXBUF_SIZE)) == NULL) {
1610 snd_es1968_free_apu_pair(chip, apu1);
1611 snd_es1968_free_apu_pair(chip, apu2);
1612 kfree(es);
1613 return -ENOMEM;
1614 }
1615 memset(es->mixbuf->buf.area, 0, ESM_MIXBUF_SIZE);
1616
1617 runtime->private_data = es;
1618 runtime->hw = snd_es1968_capture;
1619 runtime->hw.buffer_bytes_max = runtime->hw.period_bytes_max =
1620 calc_available_memory_size(chip) - 1024; /* keep MIXBUF size */
1621 snd_pcm_hw_constraint_pow2(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES);
1622
1623 spin_lock_irq(&chip->substream_lock);
1624 list_add(&es->list, &chip->substream_list);
1625 spin_unlock_irq(&chip->substream_lock);
1626
1627 return 0;
1628}
1629
1630static int snd_es1968_playback_close(struct snd_pcm_substream *substream)
1631{
1632 struct es1968 *chip = snd_pcm_substream_chip(substream);
1633 struct esschan *es;
1634
1635 if (substream->runtime->private_data == NULL)
1636 return 0;
1637 es = substream->runtime->private_data;
1638 spin_lock_irq(&chip->substream_lock);
1639 list_del(&es->list);
1640 spin_unlock_irq(&chip->substream_lock);
1641 snd_es1968_free_apu_pair(chip, es->apu[0]);
1642 kfree(es);
1643
1644 return 0;
1645}
1646
1647static int snd_es1968_capture_close(struct snd_pcm_substream *substream)
1648{
1649 struct es1968 *chip = snd_pcm_substream_chip(substream);
1650 struct esschan *es;
1651
1652 if (substream->runtime->private_data == NULL)
1653 return 0;
1654 es = substream->runtime->private_data;
1655 spin_lock_irq(&chip->substream_lock);
1656 list_del(&es->list);
1657 spin_unlock_irq(&chip->substream_lock);
1658 snd_es1968_free_memory(chip, es->mixbuf);
1659 snd_es1968_free_apu_pair(chip, es->apu[0]);
1660 snd_es1968_free_apu_pair(chip, es->apu[2]);
1661 kfree(es);
1662
1663 return 0;
1664}
1665
1666static const struct snd_pcm_ops snd_es1968_playback_ops = {
1667 .open = snd_es1968_playback_open,
1668 .close = snd_es1968_playback_close,
1669 .ioctl = snd_pcm_lib_ioctl,
1670 .hw_params = snd_es1968_hw_params,
1671 .hw_free = snd_es1968_hw_free,
1672 .prepare = snd_es1968_pcm_prepare,
1673 .trigger = snd_es1968_pcm_trigger,
1674 .pointer = snd_es1968_pcm_pointer,
1675};
1676
1677static const struct snd_pcm_ops snd_es1968_capture_ops = {
1678 .open = snd_es1968_capture_open,
1679 .close = snd_es1968_capture_close,
1680 .ioctl = snd_pcm_lib_ioctl,
1681 .hw_params = snd_es1968_hw_params,
1682 .hw_free = snd_es1968_hw_free,
1683 .prepare = snd_es1968_pcm_prepare,
1684 .trigger = snd_es1968_pcm_trigger,
1685 .pointer = snd_es1968_pcm_pointer,
1686};
1687
1688
1689/*
1690 * measure clock
1691 */
1692#define CLOCK_MEASURE_BUFSIZE 16768 /* enough large for a single shot */
1693
1694static void es1968_measure_clock(struct es1968 *chip)
1695{
1696 int i, apu;
1697 unsigned int pa, offset, t;
1698 struct esm_memory *memory;
1699 ktime_t start_time, stop_time;
1700 ktime_t diff;
1701
1702 if (chip->clock == 0)
1703 chip->clock = 48000; /* default clock value */
1704
1705 /* search 2 APUs (although one apu is enough) */
1706 if ((apu = snd_es1968_alloc_apu_pair(chip, ESM_APU_PCM_PLAY)) < 0) {
1707 dev_err(chip->card->dev, "Hmm, cannot find empty APU pair!?\n");
1708 return;
1709 }
1710 if ((memory = snd_es1968_new_memory(chip, CLOCK_MEASURE_BUFSIZE)) == NULL) {
1711 dev_warn(chip->card->dev,
1712 "cannot allocate dma buffer - using default clock %d\n",
1713 chip->clock);
1714 snd_es1968_free_apu_pair(chip, apu);
1715 return;
1716 }
1717
1718 memset(memory->buf.area, 0, CLOCK_MEASURE_BUFSIZE);
1719
1720 wave_set_register(chip, apu << 3, (memory->buf.addr - 0x10) & 0xfff8);
1721
1722 pa = (unsigned int)((memory->buf.addr - chip->dma.addr) >> 1);
1723 pa |= 0x00400000; /* System RAM (Bit 22) */
1724
1725 /* initialize apu */
1726 for (i = 0; i < 16; i++)
1727 apu_set_register(chip, apu, i, 0x0000);
1728
1729 apu_set_register(chip, apu, 0, 0x400f);
1730 apu_set_register(chip, apu, 4, ((pa >> 16) & 0xff) << 8);
1731 apu_set_register(chip, apu, 5, pa & 0xffff);
1732 apu_set_register(chip, apu, 6, (pa + CLOCK_MEASURE_BUFSIZE/2) & 0xffff);
1733 apu_set_register(chip, apu, 7, CLOCK_MEASURE_BUFSIZE/2);
1734 apu_set_register(chip, apu, 8, 0x0000);
1735 apu_set_register(chip, apu, 9, 0xD000);
1736 apu_set_register(chip, apu, 10, 0x8F08);
1737 apu_set_register(chip, apu, 11, 0x0000);
1738 spin_lock_irq(&chip->reg_lock);
1739 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
1740 outw(inw(chip->io_port + ESM_PORT_HOST_IRQ) | ESM_HIRQ_DSIE, chip->io_port + ESM_PORT_HOST_IRQ); /* enable WP ints */
1741 spin_unlock_irq(&chip->reg_lock);
1742
1743 snd_es1968_apu_set_freq(chip, apu, ((unsigned int)48000 << 16) / chip->clock); /* 48000 Hz */
1744
1745 chip->in_measurement = 1;
1746 chip->measure_apu = apu;
1747 spin_lock_irq(&chip->reg_lock);
1748 snd_es1968_bob_inc(chip, ESM_BOB_FREQ);
1749 __apu_set_register(chip, apu, 5, pa & 0xffff);
1750 snd_es1968_trigger_apu(chip, apu, ESM_APU_16BITLINEAR);
1751 start_time = ktime_get();
1752 spin_unlock_irq(&chip->reg_lock);
1753 msleep(50);
1754 spin_lock_irq(&chip->reg_lock);
1755 offset = __apu_get_register(chip, apu, 5);
1756 stop_time = ktime_get();
1757 snd_es1968_trigger_apu(chip, apu, 0); /* stop */
1758 snd_es1968_bob_dec(chip);
1759 chip->in_measurement = 0;
1760 spin_unlock_irq(&chip->reg_lock);
1761
1762 /* check the current position */
1763 offset -= (pa & 0xffff);
1764 offset &= 0xfffe;
1765 offset += chip->measure_count * (CLOCK_MEASURE_BUFSIZE/2);
1766
1767 diff = ktime_sub(stop_time, start_time);
1768 t = ktime_to_us(diff);
1769 if (t == 0) {
1770 dev_err(chip->card->dev, "?? calculation error..\n");
1771 } else {
1772 offset *= 1000;
1773 offset = (offset / t) * 1000 + ((offset % t) * 1000) / t;
1774 if (offset < 47500 || offset > 48500) {
1775 if (offset >= 40000 && offset <= 50000)
1776 chip->clock = (chip->clock * offset) / 48000;
1777 }
1778 dev_info(chip->card->dev, "clocking to %d\n", chip->clock);
1779 }
1780 snd_es1968_free_memory(chip, memory);
1781 snd_es1968_free_apu_pair(chip, apu);
1782}
1783
1784
1785/*
1786 */
1787
1788static void snd_es1968_pcm_free(struct snd_pcm *pcm)
1789{
1790 struct es1968 *esm = pcm->private_data;
1791 snd_es1968_free_dmabuf(esm);
1792 esm->pcm = NULL;
1793}
1794
1795static int
1796snd_es1968_pcm(struct es1968 *chip, int device)
1797{
1798 struct snd_pcm *pcm;
1799 int err;
1800
1801 /* get DMA buffer */
1802 if ((err = snd_es1968_init_dmabuf(chip)) < 0)
1803 return err;
1804
1805 /* set PCMBAR */
1806 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
1807 wave_set_register(chip, 0x01FD, chip->dma.addr >> 12);
1808 wave_set_register(chip, 0x01FE, chip->dma.addr >> 12);
1809 wave_set_register(chip, 0x01FF, chip->dma.addr >> 12);
1810
1811 if ((err = snd_pcm_new(chip->card, "ESS Maestro", device,
1812 chip->playback_streams,
1813 chip->capture_streams, &pcm)) < 0)
1814 return err;
1815
1816 pcm->private_data = chip;
1817 pcm->private_free = snd_es1968_pcm_free;
1818
1819 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_es1968_playback_ops);
1820 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_es1968_capture_ops);
1821
1822 pcm->info_flags = 0;
1823
1824 strcpy(pcm->name, "ESS Maestro");
1825
1826 chip->pcm = pcm;
1827
1828 return 0;
1829}
1830/*
1831 * suppress jitter on some maestros when playing stereo
1832 */
1833static void snd_es1968_suppress_jitter(struct es1968 *chip, struct esschan *es)
1834{
1835 unsigned int cp1;
1836 unsigned int cp2;
1837 unsigned int diff;
1838
1839 cp1 = __apu_get_register(chip, 0, 5);
1840 cp2 = __apu_get_register(chip, 1, 5);
1841 diff = (cp1 > cp2 ? cp1 - cp2 : cp2 - cp1);
1842
1843 if (diff > 1)
1844 __maestro_write(chip, IDR0_DATA_PORT, cp1);
1845}
1846
1847/*
1848 * update pointer
1849 */
1850static void snd_es1968_update_pcm(struct es1968 *chip, struct esschan *es)
1851{
1852 unsigned int hwptr;
1853 unsigned int diff;
1854 struct snd_pcm_substream *subs = es->substream;
1855
1856 if (subs == NULL || !es->running)
1857 return;
1858
1859 hwptr = snd_es1968_get_dma_ptr(chip, es) << es->wav_shift;
1860 hwptr %= es->dma_size;
1861
1862 diff = (es->dma_size + hwptr - es->hwptr) % es->dma_size;
1863
1864 es->hwptr = hwptr;
1865 es->count += diff;
1866
1867 if (es->count > es->frag_size) {
1868 spin_unlock(&chip->substream_lock);
1869 snd_pcm_period_elapsed(subs);
1870 spin_lock(&chip->substream_lock);
1871 es->count %= es->frag_size;
1872 }
1873}
1874
1875/* The hardware volume works by incrementing / decrementing 2 counters
1876 (without wrap around) in response to volume button presses and then
1877 generating an interrupt. The pair of counters is stored in bits 1-3 and 5-7
1878 of a byte wide register. The meaning of bits 0 and 4 is unknown. */
1879static void es1968_update_hw_volume(struct work_struct *work)
1880{
1881 struct es1968 *chip = container_of(work, struct es1968, hwvol_work);
1882 int x, val;
1883
1884 /* Figure out which volume control button was pushed,
1885 based on differences from the default register
1886 values. */
1887 x = inb(chip->io_port + 0x1c) & 0xee;
1888 /* Reset the volume control registers. */
1889 outb(0x88, chip->io_port + 0x1c);
1890 outb(0x88, chip->io_port + 0x1d);
1891 outb(0x88, chip->io_port + 0x1e);
1892 outb(0x88, chip->io_port + 0x1f);
1893
1894 if (chip->in_suspend)
1895 return;
1896
1897#ifndef CONFIG_SND_ES1968_INPUT
1898 if (! chip->master_switch || ! chip->master_volume)
1899 return;
1900
1901 val = snd_ac97_read(chip->ac97, AC97_MASTER);
1902 switch (x) {
1903 case 0x88:
1904 /* mute */
1905 val ^= 0x8000;
1906 break;
1907 case 0xaa:
1908 /* volume up */
1909 if ((val & 0x7f) > 0)
1910 val--;
1911 if ((val & 0x7f00) > 0)
1912 val -= 0x0100;
1913 break;
1914 case 0x66:
1915 /* volume down */
1916 if ((val & 0x7f) < 0x1f)
1917 val++;
1918 if ((val & 0x7f00) < 0x1f00)
1919 val += 0x0100;
1920 break;
1921 }
1922 if (snd_ac97_update(chip->ac97, AC97_MASTER, val))
1923 snd_ctl_notify(chip->card, SNDRV_CTL_EVENT_MASK_VALUE,
1924 &chip->master_volume->id);
1925#else
1926 if (!chip->input_dev)
1927 return;
1928
1929 val = 0;
1930 switch (x) {
1931 case 0x88:
1932 /* The counters have not changed, yet we've received a HV
1933 interrupt. According to tests run by various people this
1934 happens when pressing the mute button. */
1935 val = KEY_MUTE;
1936 break;
1937 case 0xaa:
1938 /* counters increased by 1 -> volume up */
1939 val = KEY_VOLUMEUP;
1940 break;
1941 case 0x66:
1942 /* counters decreased by 1 -> volume down */
1943 val = KEY_VOLUMEDOWN;
1944 break;
1945 }
1946
1947 if (val) {
1948 input_report_key(chip->input_dev, val, 1);
1949 input_sync(chip->input_dev);
1950 input_report_key(chip->input_dev, val, 0);
1951 input_sync(chip->input_dev);
1952 }
1953#endif
1954}
1955
1956/*
1957 * interrupt handler
1958 */
1959static irqreturn_t snd_es1968_interrupt(int irq, void *dev_id)
1960{
1961 struct es1968 *chip = dev_id;
1962 u32 event;
1963
1964 if (!(event = inb(chip->io_port + 0x1A)))
1965 return IRQ_NONE;
1966
1967 outw(inw(chip->io_port + 4) & 1, chip->io_port + 4);
1968
1969 if (event & ESM_HWVOL_IRQ)
1970 schedule_work(&chip->hwvol_work);
1971
1972 /* else ack 'em all, i imagine */
1973 outb(0xFF, chip->io_port + 0x1A);
1974
1975 if ((event & ESM_MPU401_IRQ) && chip->rmidi) {
1976 snd_mpu401_uart_interrupt(irq, chip->rmidi->private_data);
1977 }
1978
1979 if (event & ESM_SOUND_IRQ) {
1980 struct esschan *es;
1981 spin_lock(&chip->substream_lock);
1982 list_for_each_entry(es, &chip->substream_list, list) {
1983 if (es->running) {
1984 snd_es1968_update_pcm(chip, es);
1985 if (es->fmt & ESS_FMT_STEREO)
1986 snd_es1968_suppress_jitter(chip, es);
1987 }
1988 }
1989 spin_unlock(&chip->substream_lock);
1990 if (chip->in_measurement) {
1991 unsigned int curp = __apu_get_register(chip, chip->measure_apu, 5);
1992 if (curp < chip->measure_lastpos)
1993 chip->measure_count++;
1994 chip->measure_lastpos = curp;
1995 }
1996 }
1997
1998 return IRQ_HANDLED;
1999}
2000
2001/*
2002 * Mixer stuff
2003 */
2004
2005static int
2006snd_es1968_mixer(struct es1968 *chip)
2007{
2008 struct snd_ac97_bus *pbus;
2009 struct snd_ac97_template ac97;
2010#ifndef CONFIG_SND_ES1968_INPUT
2011 struct snd_ctl_elem_id elem_id;
2012#endif
2013 int err;
2014 static struct snd_ac97_bus_ops ops = {
2015 .write = snd_es1968_ac97_write,
2016 .read = snd_es1968_ac97_read,
2017 };
2018
2019 if ((err = snd_ac97_bus(chip->card, 0, &ops, NULL, &pbus)) < 0)
2020 return err;
2021 pbus->no_vra = 1; /* ES1968 doesn't need VRA */
2022
2023 memset(&ac97, 0, sizeof(ac97));
2024 ac97.private_data = chip;
2025 if ((err = snd_ac97_mixer(pbus, &ac97, &chip->ac97)) < 0)
2026 return err;
2027
2028#ifndef CONFIG_SND_ES1968_INPUT
2029 /* attach master switch / volumes for h/w volume control */
2030 memset(&elem_id, 0, sizeof(elem_id));
2031 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2032 strcpy(elem_id.name, "Master Playback Switch");
2033 chip->master_switch = snd_ctl_find_id(chip->card, &elem_id);
2034 memset(&elem_id, 0, sizeof(elem_id));
2035 elem_id.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
2036 strcpy(elem_id.name, "Master Playback Volume");
2037 chip->master_volume = snd_ctl_find_id(chip->card, &elem_id);
2038#endif
2039
2040 return 0;
2041}
2042
2043/*
2044 * reset ac97 codec
2045 */
2046
2047static void snd_es1968_ac97_reset(struct es1968 *chip)
2048{
2049 unsigned long ioaddr = chip->io_port;
2050
2051 unsigned short save_ringbus_a;
2052 unsigned short save_68;
2053 unsigned short w;
2054 unsigned int vend;
2055
2056 /* save configuration */
2057 save_ringbus_a = inw(ioaddr + 0x36);
2058
2059 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38); /* clear second codec id? */
2060 /* set command/status address i/o to 1st codec */
2061 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2062 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2063
2064 /* disable ac link */
2065 outw(0x0000, ioaddr + 0x36);
2066 save_68 = inw(ioaddr + 0x68);
2067 pci_read_config_word(chip->pci, 0x58, &w); /* something magical with gpio and bus arb. */
2068 pci_read_config_dword(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2069 if (w & 1)
2070 save_68 |= 0x10;
2071 outw(0xfffe, ioaddr + 0x64); /* unmask gpio 0 */
2072 outw(0x0001, ioaddr + 0x68); /* gpio write */
2073 outw(0x0000, ioaddr + 0x60); /* write 0 to gpio 0 */
2074 udelay(20);
2075 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio 1 */
2076 msleep(20);
2077
2078 outw(save_68 | 0x1, ioaddr + 0x68); /* now restore .. */
2079 outw((inw(ioaddr + 0x38) & 0xfffc) | 0x1, ioaddr + 0x38);
2080 outw((inw(ioaddr + 0x3a) & 0xfffc) | 0x1, ioaddr + 0x3a);
2081 outw((inw(ioaddr + 0x3c) & 0xfffc) | 0x1, ioaddr + 0x3c);
2082
2083 /* now the second codec */
2084 /* disable ac link */
2085 outw(0x0000, ioaddr + 0x36);
2086 outw(0xfff7, ioaddr + 0x64); /* unmask gpio 3 */
2087 save_68 = inw(ioaddr + 0x68);
2088 outw(0x0009, ioaddr + 0x68); /* gpio write 0 & 3 ?? */
2089 outw(0x0001, ioaddr + 0x60); /* write 1 to gpio */
2090 udelay(20);
2091 outw(0x0009, ioaddr + 0x60); /* write 9 to gpio */
2092 msleep(500);
2093 //outw(inw(ioaddr + 0x38) & 0xfffc, ioaddr + 0x38);
2094 outw(inw(ioaddr + 0x3a) & 0xfffc, ioaddr + 0x3a);
2095 outw(inw(ioaddr + 0x3c) & 0xfffc, ioaddr + 0x3c);
2096
2097#if 0 /* the loop here needs to be much better if we want it.. */
2098 dev_info(chip->card->dev, "trying software reset\n");
2099 /* try and do a software reset */
2100 outb(0x80 | 0x7c, ioaddr + 0x30);
2101 for (w = 0;; w++) {
2102 if ((inw(ioaddr + 0x30) & 1) == 0) {
2103 if (inb(ioaddr + 0x32) != 0)
2104 break;
2105
2106 outb(0x80 | 0x7d, ioaddr + 0x30);
2107 if (((inw(ioaddr + 0x30) & 1) == 0)
2108 && (inb(ioaddr + 0x32) != 0))
2109 break;
2110 outb(0x80 | 0x7f, ioaddr + 0x30);
2111 if (((inw(ioaddr + 0x30) & 1) == 0)
2112 && (inb(ioaddr + 0x32) != 0))
2113 break;
2114 }
2115
2116 if (w > 10000) {
2117 outb(inb(ioaddr + 0x37) | 0x08, ioaddr + 0x37); /* do a software reset */
2118 msleep(500); /* oh my.. */
2119 outb(inb(ioaddr + 0x37) & ~0x08,
2120 ioaddr + 0x37);
2121 udelay(1);
2122 outw(0x80, ioaddr + 0x30);
2123 for (w = 0; w < 10000; w++) {
2124 if ((inw(ioaddr + 0x30) & 1) == 0)
2125 break;
2126 }
2127 }
2128 }
2129#endif
2130 if (vend == NEC_VERSA_SUBID1 || vend == NEC_VERSA_SUBID2) {
2131 /* turn on external amp? */
2132 outw(0xf9ff, ioaddr + 0x64);
2133 outw(inw(ioaddr + 0x68) | 0x600, ioaddr + 0x68);
2134 outw(0x0209, ioaddr + 0x60);
2135 }
2136
2137 /* restore.. */
2138 outw(save_ringbus_a, ioaddr + 0x36);
2139
2140 /* Turn on the 978 docking chip.
2141 First frob the "master output enable" bit,
2142 then set most of the playback volume control registers to max. */
2143 outb(inb(ioaddr+0xc0)|(1<<5), ioaddr+0xc0);
2144 outb(0xff, ioaddr+0xc3);
2145 outb(0xff, ioaddr+0xc4);
2146 outb(0xff, ioaddr+0xc6);
2147 outb(0xff, ioaddr+0xc8);
2148 outb(0x3f, ioaddr+0xcf);
2149 outb(0x3f, ioaddr+0xd0);
2150}
2151
2152static void snd_es1968_reset(struct es1968 *chip)
2153{
2154 /* Reset */
2155 outw(ESM_RESET_MAESTRO | ESM_RESET_DIRECTSOUND,
2156 chip->io_port + ESM_PORT_HOST_IRQ);
2157 udelay(10);
2158 outw(0x0000, chip->io_port + ESM_PORT_HOST_IRQ);
2159 udelay(10);
2160}
2161
2162/*
2163 * initialize maestro chip
2164 */
2165static void snd_es1968_chip_init(struct es1968 *chip)
2166{
2167 struct pci_dev *pci = chip->pci;
2168 int i;
2169 unsigned long iobase = chip->io_port;
2170 u16 w;
2171 u32 n;
2172
2173 /* We used to muck around with pci config space that
2174 * we had no business messing with. We don't know enough
2175 * about the machine to know which DMA mode is appropriate,
2176 * etc. We were guessing wrong on some machines and making
2177 * them unhappy. We now trust in the BIOS to do things right,
2178 * which almost certainly means a new host of problems will
2179 * arise with broken BIOS implementations. screw 'em.
2180 * We're already intolerant of machines that don't assign
2181 * IRQs.
2182 */
2183
2184 /* Config Reg A */
2185 pci_read_config_word(pci, ESM_CONFIG_A, &w);
2186
2187 w &= ~DMA_CLEAR; /* Clear DMA bits */
2188 w &= ~(PIC_SNOOP1 | PIC_SNOOP2); /* Clear Pic Snoop Mode Bits */
2189 w &= ~SAFEGUARD; /* Safeguard off */
2190 w |= POST_WRITE; /* Posted write */
2191 w |= PCI_TIMING; /* PCI timing on */
2192 /* XXX huh? claims to be reserved.. */
2193 w &= ~SWAP_LR; /* swap left/right
2194 seems to only have effect on SB
2195 Emulation */
2196 w &= ~SUBTR_DECODE; /* Subtractive decode off */
2197
2198 pci_write_config_word(pci, ESM_CONFIG_A, w);
2199
2200 /* Config Reg B */
2201
2202 pci_read_config_word(pci, ESM_CONFIG_B, &w);
2203
2204 w &= ~(1 << 15); /* Turn off internal clock multiplier */
2205 /* XXX how do we know which to use? */
2206 w &= ~(1 << 14); /* External clock */
2207
2208 w &= ~SPDIF_CONFB; /* disable S/PDIF output */
2209 w |= HWV_CONFB; /* HWV on */
2210 w |= DEBOUNCE; /* Debounce off: easier to push the HW buttons */
2211 w &= ~GPIO_CONFB; /* GPIO 4:5 */
2212 w |= CHI_CONFB; /* Disconnect from the CHI. Enabling this made a dell 7500 work. */
2213 w &= ~IDMA_CONFB; /* IDMA off (undocumented) */
2214 w &= ~MIDI_FIX; /* MIDI fix off (undoc) */
2215 w &= ~(1 << 1); /* reserved, always write 0 */
2216 w &= ~IRQ_TO_ISA; /* IRQ to ISA off (undoc) */
2217
2218 pci_write_config_word(pci, ESM_CONFIG_B, w);
2219
2220 /* DDMA off */
2221
2222 pci_read_config_word(pci, ESM_DDMA, &w);
2223 w &= ~(1 << 0);
2224 pci_write_config_word(pci, ESM_DDMA, w);
2225
2226 /*
2227 * Legacy mode
2228 */
2229
2230 pci_read_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, &w);
2231
2232 w |= ESS_DISABLE_AUDIO; /* Disable Legacy Audio */
2233 w &= ~ESS_ENABLE_SERIAL_IRQ; /* Disable SIRQ */
2234 w &= ~(0x1f); /* disable mpu irq/io, game port, fm, SB */
2235
2236 pci_write_config_word(pci, ESM_LEGACY_AUDIO_CONTROL, w);
2237
2238 /* Set up 978 docking control chip. */
2239 pci_read_config_word(pci, 0x58, &w);
2240 w|=1<<2; /* Enable 978. */
2241 w|=1<<3; /* Turn on 978 hardware volume control. */
2242 w&=~(1<<11); /* Turn on 978 mixer volume control. */
2243 pci_write_config_word(pci, 0x58, w);
2244
2245 /* Sound Reset */
2246
2247 snd_es1968_reset(chip);
2248
2249 /*
2250 * Ring Bus Setup
2251 */
2252
2253 /* setup usual 0x34 stuff.. 0x36 may be chip specific */
2254 outw(0xC090, iobase + ESM_RING_BUS_DEST); /* direct sound, stereo */
2255 udelay(20);
2256 outw(0x3000, iobase + ESM_RING_BUS_CONTR_A); /* enable ringbus/serial */
2257 udelay(20);
2258
2259 /*
2260 * Reset the CODEC
2261 */
2262
2263 snd_es1968_ac97_reset(chip);
2264
2265 /* Ring Bus Control B */
2266
2267 n = inl(iobase + ESM_RING_BUS_CONTR_B);
2268 n &= ~RINGB_EN_SPDIF; /* SPDIF off */
2269 //w |= RINGB_EN_2CODEC; /* enable 2nd codec */
2270 outl(n, iobase + ESM_RING_BUS_CONTR_B);
2271
2272 /* Set hardware volume control registers to midpoints.
2273 We can tell which button was pushed based on how they change. */
2274 outb(0x88, iobase+0x1c);
2275 outb(0x88, iobase+0x1d);
2276 outb(0x88, iobase+0x1e);
2277 outb(0x88, iobase+0x1f);
2278
2279 /* it appears some maestros (dell 7500) only work if these are set,
2280 regardless of whether we use the assp or not. */
2281
2282 outb(0, iobase + ASSP_CONTROL_B);
2283 outb(3, iobase + ASSP_CONTROL_A); /* M: Reserved bits... */
2284 outb(0, iobase + ASSP_CONTROL_C); /* M: Disable ASSP, ASSP IRQ's and FM Port */
2285
2286 /*
2287 * set up wavecache
2288 */
2289 for (i = 0; i < 16; i++) {
2290 /* Write 0 into the buffer area 0x1E0->1EF */
2291 outw(0x01E0 + i, iobase + WC_INDEX);
2292 outw(0x0000, iobase + WC_DATA);
2293
2294 /* The 1.10 test program seem to write 0 into the buffer area
2295 * 0x1D0-0x1DF too.*/
2296 outw(0x01D0 + i, iobase + WC_INDEX);
2297 outw(0x0000, iobase + WC_DATA);
2298 }
2299 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2300 (wave_get_register(chip, IDR7_WAVE_ROMRAM) & 0xFF00));
2301 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2302 wave_get_register(chip, IDR7_WAVE_ROMRAM) | 0x100);
2303 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2304 wave_get_register(chip, IDR7_WAVE_ROMRAM) & ~0x200);
2305 wave_set_register(chip, IDR7_WAVE_ROMRAM,
2306 wave_get_register(chip, IDR7_WAVE_ROMRAM) | ~0x400);
2307
2308
2309 maestro_write(chip, IDR2_CRAM_DATA, 0x0000);
2310 /* Now back to the DirectSound stuff */
2311 /* audio serial configuration.. ? */
2312 maestro_write(chip, 0x08, 0xB004);
2313 maestro_write(chip, 0x09, 0x001B);
2314 maestro_write(chip, 0x0A, 0x8000);
2315 maestro_write(chip, 0x0B, 0x3F37);
2316 maestro_write(chip, 0x0C, 0x0098);
2317
2318 /* parallel in, has something to do with recording :) */
2319 maestro_write(chip, 0x0C,
2320 (maestro_read(chip, 0x0C) & ~0xF000) | 0x8000);
2321 /* parallel out */
2322 maestro_write(chip, 0x0C,
2323 (maestro_read(chip, 0x0C) & ~0x0F00) | 0x0500);
2324
2325 maestro_write(chip, 0x0D, 0x7632);
2326
2327 /* Wave cache control on - test off, sg off,
2328 enable, enable extra chans 1Mb */
2329
2330 w = inw(iobase + WC_CONTROL);
2331
2332 w &= ~0xFA00; /* Seems to be reserved? I don't know */
2333 w |= 0xA000; /* reserved... I don't know */
2334 w &= ~0x0200; /* Channels 56,57,58,59 as Extra Play,Rec Channel enable
2335 Seems to crash the Computer if enabled... */
2336 w |= 0x0100; /* Wave Cache Operation Enabled */
2337 w |= 0x0080; /* Channels 60/61 as Placback/Record enabled */
2338 w &= ~0x0060; /* Clear Wavtable Size */
2339 w |= 0x0020; /* Wavetable Size : 1MB */
2340 /* Bit 4 is reserved */
2341 w &= ~0x000C; /* DMA Stuff? I don't understand what the datasheet means */
2342 /* Bit 1 is reserved */
2343 w &= ~0x0001; /* Test Mode off */
2344
2345 outw(w, iobase + WC_CONTROL);
2346
2347 /* Now clear the APU control ram */
2348 for (i = 0; i < NR_APUS; i++) {
2349 for (w = 0; w < NR_APU_REGS; w++)
2350 apu_set_register(chip, i, w, 0);
2351
2352 }
2353}
2354
2355/* Enable IRQ's */
2356static void snd_es1968_start_irq(struct es1968 *chip)
2357{
2358 unsigned short w;
2359 w = ESM_HIRQ_DSIE | ESM_HIRQ_HW_VOLUME;
2360 if (chip->rmidi)
2361 w |= ESM_HIRQ_MPU401;
2362 outb(w, chip->io_port + 0x1A);
2363 outw(w, chip->io_port + ESM_PORT_HOST_IRQ);
2364}
2365
2366#ifdef CONFIG_PM_SLEEP
2367/*
2368 * PM support
2369 */
2370static int es1968_suspend(struct device *dev)
2371{
2372 struct snd_card *card = dev_get_drvdata(dev);
2373 struct es1968 *chip = card->private_data;
2374
2375 if (! chip->do_pm)
2376 return 0;
2377
2378 chip->in_suspend = 1;
2379 cancel_work_sync(&chip->hwvol_work);
2380 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2381 snd_ac97_suspend(chip->ac97);
2382 snd_es1968_bob_stop(chip);
2383 return 0;
2384}
2385
2386static int es1968_resume(struct device *dev)
2387{
2388 struct snd_card *card = dev_get_drvdata(dev);
2389 struct es1968 *chip = card->private_data;
2390 struct esschan *es;
2391
2392 if (! chip->do_pm)
2393 return 0;
2394
2395 snd_es1968_chip_init(chip);
2396
2397 /* need to restore the base pointers.. */
2398 if (chip->dma.addr) {
2399 /* set PCMBAR */
2400 wave_set_register(chip, 0x01FC, chip->dma.addr >> 12);
2401 }
2402
2403 snd_es1968_start_irq(chip);
2404
2405 /* restore ac97 state */
2406 snd_ac97_resume(chip->ac97);
2407
2408 list_for_each_entry(es, &chip->substream_list, list) {
2409 switch (es->mode) {
2410 case ESM_MODE_PLAY:
2411 snd_es1968_playback_setup(chip, es, es->substream->runtime);
2412 break;
2413 case ESM_MODE_CAPTURE:
2414 snd_es1968_capture_setup(chip, es, es->substream->runtime);
2415 break;
2416 }
2417 }
2418
2419 /* start timer again */
2420 if (chip->bobclient)
2421 snd_es1968_bob_start(chip);
2422
2423 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2424 chip->in_suspend = 0;
2425 return 0;
2426}
2427
2428static SIMPLE_DEV_PM_OPS(es1968_pm, es1968_suspend, es1968_resume);
2429#define ES1968_PM_OPS &es1968_pm
2430#else
2431#define ES1968_PM_OPS NULL
2432#endif /* CONFIG_PM_SLEEP */
2433
2434#ifdef SUPPORT_JOYSTICK
2435#define JOYSTICK_ADDR 0x200
2436static int snd_es1968_create_gameport(struct es1968 *chip, int dev)
2437{
2438 struct gameport *gp;
2439 struct resource *r;
2440 u16 val;
2441
2442 if (!joystick[dev])
2443 return -ENODEV;
2444
2445 r = request_region(JOYSTICK_ADDR, 8, "ES1968 gameport");
2446 if (!r)
2447 return -EBUSY;
2448
2449 chip->gameport = gp = gameport_allocate_port();
2450 if (!gp) {
2451 dev_err(chip->card->dev,
2452 "cannot allocate memory for gameport\n");
2453 release_and_free_resource(r);
2454 return -ENOMEM;
2455 }
2456
2457 pci_read_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, &val);
2458 pci_write_config_word(chip->pci, ESM_LEGACY_AUDIO_CONTROL, val | 0x04);
2459
2460 gameport_set_name(gp, "ES1968 Gameport");
2461 gameport_set_phys(gp, "pci%s/gameport0", pci_name(chip->pci));
2462 gameport_set_dev_parent(gp, &chip->pci->dev);
2463 gp->io = JOYSTICK_ADDR;
2464 gameport_set_port_data(gp, r);
2465
2466 gameport_register_port(gp);
2467
2468 return 0;
2469}
2470
2471static void snd_es1968_free_gameport(struct es1968 *chip)
2472{
2473 if (chip->gameport) {
2474 struct resource *r = gameport_get_port_data(chip->gameport);
2475
2476 gameport_unregister_port(chip->gameport);
2477 chip->gameport = NULL;
2478
2479 release_and_free_resource(r);
2480 }
2481}
2482#else
2483static inline int snd_es1968_create_gameport(struct es1968 *chip, int dev) { return -ENOSYS; }
2484static inline void snd_es1968_free_gameport(struct es1968 *chip) { }
2485#endif
2486
2487#ifdef CONFIG_SND_ES1968_INPUT
2488static int snd_es1968_input_register(struct es1968 *chip)
2489{
2490 struct input_dev *input_dev;
2491 int err;
2492
2493 input_dev = input_allocate_device();
2494 if (!input_dev)
2495 return -ENOMEM;
2496
2497 snprintf(chip->phys, sizeof(chip->phys), "pci-%s/input0",
2498 pci_name(chip->pci));
2499
2500 input_dev->name = chip->card->driver;
2501 input_dev->phys = chip->phys;
2502 input_dev->id.bustype = BUS_PCI;
2503 input_dev->id.vendor = chip->pci->vendor;
2504 input_dev->id.product = chip->pci->device;
2505 input_dev->dev.parent = &chip->pci->dev;
2506
2507 __set_bit(EV_KEY, input_dev->evbit);
2508 __set_bit(KEY_MUTE, input_dev->keybit);
2509 __set_bit(KEY_VOLUMEDOWN, input_dev->keybit);
2510 __set_bit(KEY_VOLUMEUP, input_dev->keybit);
2511
2512 err = input_register_device(input_dev);
2513 if (err) {
2514 input_free_device(input_dev);
2515 return err;
2516 }
2517
2518 chip->input_dev = input_dev;
2519 return 0;
2520}
2521#endif /* CONFIG_SND_ES1968_INPUT */
2522
2523#ifdef CONFIG_SND_ES1968_RADIO
2524#define GPIO_DATA 0x60
2525#define IO_MASK 4 /* mask register offset from GPIO_DATA
2526 bits 1=unmask write to given bit */
2527#define IO_DIR 8 /* direction register offset from GPIO_DATA
2528 bits 0/1=read/write direction */
2529
2530/* GPIO to TEA575x maps */
2531struct snd_es1968_tea575x_gpio {
2532 u8 data, clk, wren, most;
2533 char *name;
2534};
2535
2536static struct snd_es1968_tea575x_gpio snd_es1968_tea575x_gpios[] = {
2537 { .data = 6, .clk = 7, .wren = 8, .most = 9, .name = "SF64-PCE2" },
2538 { .data = 7, .clk = 8, .wren = 6, .most = 10, .name = "M56VAP" },
2539};
2540
2541#define get_tea575x_gpio(chip) \
2542 (&snd_es1968_tea575x_gpios[(chip)->tea575x_tuner])
2543
2544
2545static void snd_es1968_tea575x_set_pins(struct snd_tea575x *tea, u8 pins)
2546{
2547 struct es1968 *chip = tea->private_data;
2548 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2549 u16 val = 0;
2550
2551 val |= (pins & TEA575X_DATA) ? (1 << gpio.data) : 0;
2552 val |= (pins & TEA575X_CLK) ? (1 << gpio.clk) : 0;
2553 val |= (pins & TEA575X_WREN) ? (1 << gpio.wren) : 0;
2554
2555 outw(val, chip->io_port + GPIO_DATA);
2556}
2557
2558static u8 snd_es1968_tea575x_get_pins(struct snd_tea575x *tea)
2559{
2560 struct es1968 *chip = tea->private_data;
2561 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2562 u16 val = inw(chip->io_port + GPIO_DATA);
2563 u8 ret = 0;
2564
2565 if (val & (1 << gpio.data))
2566 ret |= TEA575X_DATA;
2567 if (val & (1 << gpio.most))
2568 ret |= TEA575X_MOST;
2569
2570 return ret;
2571}
2572
2573static void snd_es1968_tea575x_set_direction(struct snd_tea575x *tea, bool output)
2574{
2575 struct es1968 *chip = tea->private_data;
2576 unsigned long io = chip->io_port + GPIO_DATA;
2577 u16 odir = inw(io + IO_DIR);
2578 struct snd_es1968_tea575x_gpio gpio = *get_tea575x_gpio(chip);
2579
2580 if (output) {
2581 outw(~((1 << gpio.data) | (1 << gpio.clk) | (1 << gpio.wren)),
2582 io + IO_MASK);
2583 outw(odir | (1 << gpio.data) | (1 << gpio.clk) | (1 << gpio.wren),
2584 io + IO_DIR);
2585 } else {
2586 outw(~((1 << gpio.clk) | (1 << gpio.wren) | (1 << gpio.data) | (1 << gpio.most)),
2587 io + IO_MASK);
2588 outw((odir & ~((1 << gpio.data) | (1 << gpio.most)))
2589 | (1 << gpio.clk) | (1 << gpio.wren), io + IO_DIR);
2590 }
2591}
2592
2593static const struct snd_tea575x_ops snd_es1968_tea_ops = {
2594 .set_pins = snd_es1968_tea575x_set_pins,
2595 .get_pins = snd_es1968_tea575x_get_pins,
2596 .set_direction = snd_es1968_tea575x_set_direction,
2597};
2598#endif
2599
2600static int snd_es1968_free(struct es1968 *chip)
2601{
2602 cancel_work_sync(&chip->hwvol_work);
2603#ifdef CONFIG_SND_ES1968_INPUT
2604 if (chip->input_dev)
2605 input_unregister_device(chip->input_dev);
2606#endif
2607
2608 if (chip->io_port) {
2609 if (chip->irq >= 0)
2610 synchronize_irq(chip->irq);
2611 outw(1, chip->io_port + 0x04); /* clear WP interrupts */
2612 outw(0, chip->io_port + ESM_PORT_HOST_IRQ); /* disable IRQ */
2613 }
2614
2615#ifdef CONFIG_SND_ES1968_RADIO
2616 snd_tea575x_exit(&chip->tea);
2617 v4l2_device_unregister(&chip->v4l2_dev);
2618#endif
2619
2620 if (chip->irq >= 0)
2621 free_irq(chip->irq, chip);
2622 snd_es1968_free_gameport(chip);
2623 pci_release_regions(chip->pci);
2624 pci_disable_device(chip->pci);
2625 kfree(chip);
2626 return 0;
2627}
2628
2629static int snd_es1968_dev_free(struct snd_device *device)
2630{
2631 struct es1968 *chip = device->device_data;
2632 return snd_es1968_free(chip);
2633}
2634
2635struct ess_device_list {
2636 unsigned short type; /* chip type */
2637 unsigned short vendor; /* subsystem vendor id */
2638};
2639
2640static struct ess_device_list pm_whitelist[] = {
2641 { TYPE_MAESTRO2E, 0x0e11 }, /* Compaq Armada */
2642 { TYPE_MAESTRO2E, 0x1028 },
2643 { TYPE_MAESTRO2E, 0x103c },
2644 { TYPE_MAESTRO2E, 0x1179 },
2645 { TYPE_MAESTRO2E, 0x14c0 }, /* HP omnibook 4150 */
2646 { TYPE_MAESTRO2E, 0x1558 },
2647 { TYPE_MAESTRO2E, 0x125d }, /* a PCI card, e.g. Terratec DMX */
2648 { TYPE_MAESTRO2, 0x125d }, /* a PCI card, e.g. SF64-PCE2 */
2649};
2650
2651static struct ess_device_list mpu_blacklist[] = {
2652 { TYPE_MAESTRO2, 0x125d },
2653};
2654
2655static int snd_es1968_create(struct snd_card *card,
2656 struct pci_dev *pci,
2657 int total_bufsize,
2658 int play_streams,
2659 int capt_streams,
2660 int chip_type,
2661 int do_pm,
2662 int radio_nr,
2663 struct es1968 **chip_ret)
2664{
2665 static struct snd_device_ops ops = {
2666 .dev_free = snd_es1968_dev_free,
2667 };
2668 struct es1968 *chip;
2669 int i, err;
2670
2671 *chip_ret = NULL;
2672
2673 /* enable PCI device */
2674 if ((err = pci_enable_device(pci)) < 0)
2675 return err;
2676 /* check, if we can restrict PCI DMA transfers to 28 bits */
2677 if (dma_set_mask(&pci->dev, DMA_BIT_MASK(28)) < 0 ||
2678 dma_set_coherent_mask(&pci->dev, DMA_BIT_MASK(28)) < 0) {
2679 dev_err(card->dev,
2680 "architecture does not support 28bit PCI busmaster DMA\n");
2681 pci_disable_device(pci);
2682 return -ENXIO;
2683 }
2684
2685 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2686 if (! chip) {
2687 pci_disable_device(pci);
2688 return -ENOMEM;
2689 }
2690
2691 /* Set Vars */
2692 chip->type = chip_type;
2693 spin_lock_init(&chip->reg_lock);
2694 spin_lock_init(&chip->substream_lock);
2695 INIT_LIST_HEAD(&chip->buf_list);
2696 INIT_LIST_HEAD(&chip->substream_list);
2697 mutex_init(&chip->memory_mutex);
2698 INIT_WORK(&chip->hwvol_work, es1968_update_hw_volume);
2699 chip->card = card;
2700 chip->pci = pci;
2701 chip->irq = -1;
2702 chip->total_bufsize = total_bufsize; /* in bytes */
2703 chip->playback_streams = play_streams;
2704 chip->capture_streams = capt_streams;
2705
2706 if ((err = pci_request_regions(pci, "ESS Maestro")) < 0) {
2707 kfree(chip);
2708 pci_disable_device(pci);
2709 return err;
2710 }
2711 chip->io_port = pci_resource_start(pci, 0);
2712 if (request_irq(pci->irq, snd_es1968_interrupt, IRQF_SHARED,
2713 KBUILD_MODNAME, chip)) {
2714 dev_err(card->dev, "unable to grab IRQ %d\n", pci->irq);
2715 snd_es1968_free(chip);
2716 return -EBUSY;
2717 }
2718 chip->irq = pci->irq;
2719
2720 /* Clear Maestro_map */
2721 for (i = 0; i < 32; i++)
2722 chip->maestro_map[i] = 0;
2723
2724 /* Clear Apu Map */
2725 for (i = 0; i < NR_APUS; i++)
2726 chip->apu[i] = ESM_APU_FREE;
2727
2728 /* just to be sure */
2729 pci_set_master(pci);
2730
2731 if (do_pm > 1) {
2732 /* disable power-management if not on the whitelist */
2733 unsigned short vend;
2734 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2735 for (i = 0; i < (int)ARRAY_SIZE(pm_whitelist); i++) {
2736 if (chip->type == pm_whitelist[i].type &&
2737 vend == pm_whitelist[i].vendor) {
2738 do_pm = 1;
2739 break;
2740 }
2741 }
2742 if (do_pm > 1) {
2743 /* not matched; disabling pm */
2744 dev_info(card->dev, "not attempting power management.\n");
2745 do_pm = 0;
2746 }
2747 }
2748 chip->do_pm = do_pm;
2749
2750 snd_es1968_chip_init(chip);
2751
2752 if ((err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops)) < 0) {
2753 snd_es1968_free(chip);
2754 return err;
2755 }
2756
2757#ifdef CONFIG_SND_ES1968_RADIO
2758 /* don't play with GPIOs on laptops */
2759 if (chip->pci->subsystem_vendor != 0x125d)
2760 goto no_radio;
2761 err = v4l2_device_register(&pci->dev, &chip->v4l2_dev);
2762 if (err < 0) {
2763 snd_es1968_free(chip);
2764 return err;
2765 }
2766 chip->tea.v4l2_dev = &chip->v4l2_dev;
2767 chip->tea.private_data = chip;
2768 chip->tea.radio_nr = radio_nr;
2769 chip->tea.ops = &snd_es1968_tea_ops;
2770 sprintf(chip->tea.bus_info, "PCI:%s", pci_name(pci));
2771 for (i = 0; i < ARRAY_SIZE(snd_es1968_tea575x_gpios); i++) {
2772 chip->tea575x_tuner = i;
2773 if (!snd_tea575x_init(&chip->tea, THIS_MODULE)) {
2774 dev_info(card->dev, "detected TEA575x radio type %s\n",
2775 get_tea575x_gpio(chip)->name);
2776 strlcpy(chip->tea.card, get_tea575x_gpio(chip)->name,
2777 sizeof(chip->tea.card));
2778 break;
2779 }
2780 }
2781no_radio:
2782#endif
2783
2784 *chip_ret = chip;
2785
2786 return 0;
2787}
2788
2789
2790/*
2791 */
2792static int snd_es1968_probe(struct pci_dev *pci,
2793 const struct pci_device_id *pci_id)
2794{
2795 static int dev;
2796 struct snd_card *card;
2797 struct es1968 *chip;
2798 unsigned int i;
2799 int err;
2800
2801 if (dev >= SNDRV_CARDS)
2802 return -ENODEV;
2803 if (!enable[dev]) {
2804 dev++;
2805 return -ENOENT;
2806 }
2807
2808 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2809 0, &card);
2810 if (err < 0)
2811 return err;
2812
2813 if (total_bufsize[dev] < 128)
2814 total_bufsize[dev] = 128;
2815 if (total_bufsize[dev] > 4096)
2816 total_bufsize[dev] = 4096;
2817 if ((err = snd_es1968_create(card, pci,
2818 total_bufsize[dev] * 1024, /* in bytes */
2819 pcm_substreams_p[dev],
2820 pcm_substreams_c[dev],
2821 pci_id->driver_data,
2822 use_pm[dev],
2823 radio_nr[dev],
2824 &chip)) < 0) {
2825 snd_card_free(card);
2826 return err;
2827 }
2828 card->private_data = chip;
2829
2830 switch (chip->type) {
2831 case TYPE_MAESTRO2E:
2832 strcpy(card->driver, "ES1978");
2833 strcpy(card->shortname, "ESS ES1978 (Maestro 2E)");
2834 break;
2835 case TYPE_MAESTRO2:
2836 strcpy(card->driver, "ES1968");
2837 strcpy(card->shortname, "ESS ES1968 (Maestro 2)");
2838 break;
2839 case TYPE_MAESTRO:
2840 strcpy(card->driver, "ESM1");
2841 strcpy(card->shortname, "ESS Maestro 1");
2842 break;
2843 }
2844
2845 if ((err = snd_es1968_pcm(chip, 0)) < 0) {
2846 snd_card_free(card);
2847 return err;
2848 }
2849
2850 if ((err = snd_es1968_mixer(chip)) < 0) {
2851 snd_card_free(card);
2852 return err;
2853 }
2854
2855 if (enable_mpu[dev] == 2) {
2856 /* check the black list */
2857 unsigned short vend;
2858 pci_read_config_word(chip->pci, PCI_SUBSYSTEM_VENDOR_ID, &vend);
2859 for (i = 0; i < ARRAY_SIZE(mpu_blacklist); i++) {
2860 if (chip->type == mpu_blacklist[i].type &&
2861 vend == mpu_blacklist[i].vendor) {
2862 enable_mpu[dev] = 0;
2863 break;
2864 }
2865 }
2866 }
2867 if (enable_mpu[dev]) {
2868 if ((err = snd_mpu401_uart_new(card, 0, MPU401_HW_MPU401,
2869 chip->io_port + ESM_MPU401_PORT,
2870 MPU401_INFO_INTEGRATED |
2871 MPU401_INFO_IRQ_HOOK,
2872 -1, &chip->rmidi)) < 0) {
2873 dev_warn(card->dev, "skipping MPU-401 MIDI support..\n");
2874 }
2875 }
2876
2877 snd_es1968_create_gameport(chip, dev);
2878
2879#ifdef CONFIG_SND_ES1968_INPUT
2880 err = snd_es1968_input_register(chip);
2881 if (err)
2882 dev_warn(card->dev,
2883 "Input device registration failed with error %i", err);
2884#endif
2885
2886 snd_es1968_start_irq(chip);
2887
2888 chip->clock = clock[dev];
2889 if (! chip->clock)
2890 es1968_measure_clock(chip);
2891
2892 sprintf(card->longname, "%s at 0x%lx, irq %i",
2893 card->shortname, chip->io_port, chip->irq);
2894
2895 if ((err = snd_card_register(card)) < 0) {
2896 snd_card_free(card);
2897 return err;
2898 }
2899 pci_set_drvdata(pci, card);
2900 dev++;
2901 return 0;
2902}
2903
2904static void snd_es1968_remove(struct pci_dev *pci)
2905{
2906 snd_card_free(pci_get_drvdata(pci));
2907}
2908
2909static struct pci_driver es1968_driver = {
2910 .name = KBUILD_MODNAME,
2911 .id_table = snd_es1968_ids,
2912 .probe = snd_es1968_probe,
2913 .remove = snd_es1968_remove,
2914 .driver = {
2915 .pm = ES1968_PM_OPS,
2916 },
2917};
2918
2919module_pci_driver(es1968_driver);