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1/*
2 * Driver for Allwinner sun4i Pulse Width Modulation Controller
3 *
4 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 *
6 * Licensed under GPLv2.
7 */
8
9#include <linux/bitops.h>
10#include <linux/clk.h>
11#include <linux/delay.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/jiffies.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/pwm.h>
20#include <linux/slab.h>
21#include <linux/spinlock.h>
22#include <linux/time.h>
23
24#define PWM_CTRL_REG 0x0
25
26#define PWM_CH_PRD_BASE 0x4
27#define PWM_CH_PRD_OFFSET 0x4
28#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
29
30#define PWMCH_OFFSET 15
31#define PWM_PRESCAL_MASK GENMASK(3, 0)
32#define PWM_PRESCAL_OFF 0
33#define PWM_EN BIT(4)
34#define PWM_ACT_STATE BIT(5)
35#define PWM_CLK_GATING BIT(6)
36#define PWM_MODE BIT(7)
37#define PWM_PULSE BIT(8)
38#define PWM_BYPASS BIT(9)
39
40#define PWM_RDY_BASE 28
41#define PWM_RDY_OFFSET 1
42#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
43
44#define PWM_PRD(prd) (((prd) - 1) << 16)
45#define PWM_PRD_MASK GENMASK(15, 0)
46
47#define PWM_DTY_MASK GENMASK(15, 0)
48
49#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
50#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
51#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
52
53#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
54
55static const u32 prescaler_table[] = {
56 120,
57 180,
58 240,
59 360,
60 480,
61 0,
62 0,
63 0,
64 12000,
65 24000,
66 36000,
67 48000,
68 72000,
69 0,
70 0,
71 0, /* Actually 1 but tested separately */
72};
73
74struct sun4i_pwm_data {
75 bool has_prescaler_bypass;
76 unsigned int npwm;
77};
78
79struct sun4i_pwm_chip {
80 struct pwm_chip chip;
81 struct clk *clk;
82 void __iomem *base;
83 spinlock_t ctrl_lock;
84 const struct sun4i_pwm_data *data;
85 unsigned long next_period[2];
86 bool needs_delay[2];
87};
88
89static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
90{
91 return container_of(chip, struct sun4i_pwm_chip, chip);
92}
93
94static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
95 unsigned long offset)
96{
97 return readl(chip->base + offset);
98}
99
100static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
101 u32 val, unsigned long offset)
102{
103 writel(val, chip->base + offset);
104}
105
106static void sun4i_pwm_get_state(struct pwm_chip *chip,
107 struct pwm_device *pwm,
108 struct pwm_state *state)
109{
110 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
111 u64 clk_rate, tmp;
112 u32 val;
113 unsigned int prescaler;
114
115 clk_rate = clk_get_rate(sun4i_pwm->clk);
116
117 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
118
119 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
120 sun4i_pwm->data->has_prescaler_bypass)
121 prescaler = 1;
122 else
123 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
124
125 if (prescaler == 0)
126 return;
127
128 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
129 state->polarity = PWM_POLARITY_NORMAL;
130 else
131 state->polarity = PWM_POLARITY_INVERSED;
132
133 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
134 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
135 state->enabled = true;
136 else
137 state->enabled = false;
138
139 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
140
141 tmp = prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
142 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
143
144 tmp = prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
145 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
146}
147
148static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
149 struct pwm_state *state,
150 u32 *dty, u32 *prd, unsigned int *prsclr)
151{
152 u64 clk_rate, div = 0;
153 unsigned int pval, prescaler = 0;
154
155 clk_rate = clk_get_rate(sun4i_pwm->clk);
156
157 if (sun4i_pwm->data->has_prescaler_bypass) {
158 /* First, test without any prescaler when available */
159 prescaler = PWM_PRESCAL_MASK;
160 pval = 1;
161 /*
162 * When not using any prescaler, the clock period in nanoseconds
163 * is not an integer so round it half up instead of
164 * truncating to get less surprising values.
165 */
166 div = clk_rate * state->period + NSEC_PER_SEC / 2;
167 do_div(div, NSEC_PER_SEC);
168 if (div - 1 > PWM_PRD_MASK)
169 prescaler = 0;
170 }
171
172 if (prescaler == 0) {
173 /* Go up from the first divider */
174 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
175 if (!prescaler_table[prescaler])
176 continue;
177 pval = prescaler_table[prescaler];
178 div = clk_rate;
179 do_div(div, pval);
180 div = div * state->period;
181 do_div(div, NSEC_PER_SEC);
182 if (div - 1 <= PWM_PRD_MASK)
183 break;
184 }
185
186 if (div - 1 > PWM_PRD_MASK)
187 return -EINVAL;
188 }
189
190 *prd = div;
191 div *= state->duty_cycle;
192 do_div(div, state->period);
193 *dty = div;
194 *prsclr = prescaler;
195
196 div = (u64)pval * NSEC_PER_SEC * *prd;
197 state->period = DIV_ROUND_CLOSEST_ULL(div, clk_rate);
198
199 div = (u64)pval * NSEC_PER_SEC * *dty;
200 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(div, clk_rate);
201
202 return 0;
203}
204
205static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
206 struct pwm_state *state)
207{
208 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
209 struct pwm_state cstate;
210 u32 ctrl;
211 int ret;
212 unsigned int delay_us;
213 unsigned long now;
214
215 pwm_get_state(pwm, &cstate);
216
217 if (!cstate.enabled) {
218 ret = clk_prepare_enable(sun4i_pwm->clk);
219 if (ret) {
220 dev_err(chip->dev, "failed to enable PWM clock\n");
221 return ret;
222 }
223 }
224
225 spin_lock(&sun4i_pwm->ctrl_lock);
226 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
227
228 if ((cstate.period != state->period) ||
229 (cstate.duty_cycle != state->duty_cycle)) {
230 u32 period, duty, val;
231 unsigned int prescaler;
232
233 ret = sun4i_pwm_calculate(sun4i_pwm, state,
234 &duty, &period, &prescaler);
235 if (ret) {
236 dev_err(chip->dev, "period exceeds the maximum value\n");
237 spin_unlock(&sun4i_pwm->ctrl_lock);
238 if (!cstate.enabled)
239 clk_disable_unprepare(sun4i_pwm->clk);
240 return ret;
241 }
242
243 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
244 /* Prescaler changed, the clock has to be gated */
245 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
246 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
247
248 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
249 ctrl |= BIT_CH(prescaler, pwm->hwpwm);
250 }
251
252 val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
253 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
254 sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
255 usecs_to_jiffies(cstate.period / 1000 + 1);
256 sun4i_pwm->needs_delay[pwm->hwpwm] = true;
257 }
258
259 if (state->polarity != PWM_POLARITY_NORMAL)
260 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
261 else
262 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
263
264 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
265 if (state->enabled) {
266 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
267 } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
268 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
269 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
270 }
271
272 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
273
274 spin_unlock(&sun4i_pwm->ctrl_lock);
275
276 if (state->enabled)
277 return 0;
278
279 if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
280 clk_disable_unprepare(sun4i_pwm->clk);
281 return 0;
282 }
283
284 /* We need a full period to elapse before disabling the channel. */
285 now = jiffies;
286 if (sun4i_pwm->needs_delay[pwm->hwpwm] &&
287 time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
288 delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
289 now);
290 if ((delay_us / 500) > MAX_UDELAY_MS)
291 msleep(delay_us / 1000 + 1);
292 else
293 usleep_range(delay_us, delay_us * 2);
294 }
295 sun4i_pwm->needs_delay[pwm->hwpwm] = false;
296
297 spin_lock(&sun4i_pwm->ctrl_lock);
298 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
299 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
300 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
301 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
302 spin_unlock(&sun4i_pwm->ctrl_lock);
303
304 clk_disable_unprepare(sun4i_pwm->clk);
305
306 return 0;
307}
308
309static const struct pwm_ops sun4i_pwm_ops = {
310 .apply = sun4i_pwm_apply,
311 .get_state = sun4i_pwm_get_state,
312 .owner = THIS_MODULE,
313};
314
315static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
316 .has_prescaler_bypass = false,
317 .npwm = 2,
318};
319
320static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
321 .has_prescaler_bypass = true,
322 .npwm = 2,
323};
324
325static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
326 .has_prescaler_bypass = true,
327 .npwm = 1,
328};
329
330static const struct of_device_id sun4i_pwm_dt_ids[] = {
331 {
332 .compatible = "allwinner,sun4i-a10-pwm",
333 .data = &sun4i_pwm_dual_nobypass,
334 }, {
335 .compatible = "allwinner,sun5i-a10s-pwm",
336 .data = &sun4i_pwm_dual_bypass,
337 }, {
338 .compatible = "allwinner,sun5i-a13-pwm",
339 .data = &sun4i_pwm_single_bypass,
340 }, {
341 .compatible = "allwinner,sun7i-a20-pwm",
342 .data = &sun4i_pwm_dual_bypass,
343 }, {
344 .compatible = "allwinner,sun8i-h3-pwm",
345 .data = &sun4i_pwm_single_bypass,
346 }, {
347 /* sentinel */
348 },
349};
350MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
351
352static int sun4i_pwm_probe(struct platform_device *pdev)
353{
354 struct sun4i_pwm_chip *pwm;
355 struct resource *res;
356 int ret;
357
358 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
359 if (!pwm)
360 return -ENOMEM;
361
362 pwm->data = of_device_get_match_data(&pdev->dev);
363 if (!pwm->data)
364 return -ENODEV;
365
366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
367 pwm->base = devm_ioremap_resource(&pdev->dev, res);
368 if (IS_ERR(pwm->base))
369 return PTR_ERR(pwm->base);
370
371 pwm->clk = devm_clk_get(&pdev->dev, NULL);
372 if (IS_ERR(pwm->clk))
373 return PTR_ERR(pwm->clk);
374
375 pwm->chip.dev = &pdev->dev;
376 pwm->chip.ops = &sun4i_pwm_ops;
377 pwm->chip.base = -1;
378 pwm->chip.npwm = pwm->data->npwm;
379 pwm->chip.of_xlate = of_pwm_xlate_with_flags;
380 pwm->chip.of_pwm_n_cells = 3;
381
382 spin_lock_init(&pwm->ctrl_lock);
383
384 ret = pwmchip_add(&pwm->chip);
385 if (ret < 0) {
386 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
387 return ret;
388 }
389
390 platform_set_drvdata(pdev, pwm);
391
392 return 0;
393}
394
395static int sun4i_pwm_remove(struct platform_device *pdev)
396{
397 struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
398
399 return pwmchip_remove(&pwm->chip);
400}
401
402static struct platform_driver sun4i_pwm_driver = {
403 .driver = {
404 .name = "sun4i-pwm",
405 .of_match_table = sun4i_pwm_dt_ids,
406 },
407 .probe = sun4i_pwm_probe,
408 .remove = sun4i_pwm_remove,
409};
410module_platform_driver(sun4i_pwm_driver);
411
412MODULE_ALIAS("platform:sun4i-pwm");
413MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
414MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
415MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Driver for Allwinner sun4i Pulse Width Modulation Controller
4 *
5 * Copyright (C) 2014 Alexandre Belloni <alexandre.belloni@free-electrons.com>
6 */
7
8#include <linux/bitops.h>
9#include <linux/clk.h>
10#include <linux/delay.h>
11#include <linux/err.h>
12#include <linux/io.h>
13#include <linux/jiffies.h>
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/of_device.h>
17#include <linux/platform_device.h>
18#include <linux/pwm.h>
19#include <linux/slab.h>
20#include <linux/spinlock.h>
21#include <linux/time.h>
22
23#define PWM_CTRL_REG 0x0
24
25#define PWM_CH_PRD_BASE 0x4
26#define PWM_CH_PRD_OFFSET 0x4
27#define PWM_CH_PRD(ch) (PWM_CH_PRD_BASE + PWM_CH_PRD_OFFSET * (ch))
28
29#define PWMCH_OFFSET 15
30#define PWM_PRESCAL_MASK GENMASK(3, 0)
31#define PWM_PRESCAL_OFF 0
32#define PWM_EN BIT(4)
33#define PWM_ACT_STATE BIT(5)
34#define PWM_CLK_GATING BIT(6)
35#define PWM_MODE BIT(7)
36#define PWM_PULSE BIT(8)
37#define PWM_BYPASS BIT(9)
38
39#define PWM_RDY_BASE 28
40#define PWM_RDY_OFFSET 1
41#define PWM_RDY(ch) BIT(PWM_RDY_BASE + PWM_RDY_OFFSET * (ch))
42
43#define PWM_PRD(prd) (((prd) - 1) << 16)
44#define PWM_PRD_MASK GENMASK(15, 0)
45
46#define PWM_DTY_MASK GENMASK(15, 0)
47
48#define PWM_REG_PRD(reg) ((((reg) >> 16) & PWM_PRD_MASK) + 1)
49#define PWM_REG_DTY(reg) ((reg) & PWM_DTY_MASK)
50#define PWM_REG_PRESCAL(reg, chan) (((reg) >> ((chan) * PWMCH_OFFSET)) & PWM_PRESCAL_MASK)
51
52#define BIT_CH(bit, chan) ((bit) << ((chan) * PWMCH_OFFSET))
53
54static const u32 prescaler_table[] = {
55 120,
56 180,
57 240,
58 360,
59 480,
60 0,
61 0,
62 0,
63 12000,
64 24000,
65 36000,
66 48000,
67 72000,
68 0,
69 0,
70 0, /* Actually 1 but tested separately */
71};
72
73struct sun4i_pwm_data {
74 bool has_prescaler_bypass;
75 unsigned int npwm;
76};
77
78struct sun4i_pwm_chip {
79 struct pwm_chip chip;
80 struct clk *clk;
81 void __iomem *base;
82 spinlock_t ctrl_lock;
83 const struct sun4i_pwm_data *data;
84 unsigned long next_period[2];
85 bool needs_delay[2];
86};
87
88static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
89{
90 return container_of(chip, struct sun4i_pwm_chip, chip);
91}
92
93static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
94 unsigned long offset)
95{
96 return readl(chip->base + offset);
97}
98
99static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
100 u32 val, unsigned long offset)
101{
102 writel(val, chip->base + offset);
103}
104
105static void sun4i_pwm_get_state(struct pwm_chip *chip,
106 struct pwm_device *pwm,
107 struct pwm_state *state)
108{
109 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
110 u64 clk_rate, tmp;
111 u32 val;
112 unsigned int prescaler;
113
114 clk_rate = clk_get_rate(sun4i_pwm->clk);
115
116 val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
117
118 if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
119 sun4i_pwm->data->has_prescaler_bypass)
120 prescaler = 1;
121 else
122 prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
123
124 if (prescaler == 0)
125 return;
126
127 if (val & BIT_CH(PWM_ACT_STATE, pwm->hwpwm))
128 state->polarity = PWM_POLARITY_NORMAL;
129 else
130 state->polarity = PWM_POLARITY_INVERSED;
131
132 if ((val & BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm)) ==
133 BIT_CH(PWM_CLK_GATING | PWM_EN, pwm->hwpwm))
134 state->enabled = true;
135 else
136 state->enabled = false;
137
138 val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
139
140 tmp = prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
141 state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
142
143 tmp = prescaler * NSEC_PER_SEC * PWM_REG_PRD(val);
144 state->period = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
145}
146
147static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
148 const struct pwm_state *state,
149 u32 *dty, u32 *prd, unsigned int *prsclr)
150{
151 u64 clk_rate, div = 0;
152 unsigned int pval, prescaler = 0;
153
154 clk_rate = clk_get_rate(sun4i_pwm->clk);
155
156 if (sun4i_pwm->data->has_prescaler_bypass) {
157 /* First, test without any prescaler when available */
158 prescaler = PWM_PRESCAL_MASK;
159 pval = 1;
160 /*
161 * When not using any prescaler, the clock period in nanoseconds
162 * is not an integer so round it half up instead of
163 * truncating to get less surprising values.
164 */
165 div = clk_rate * state->period + NSEC_PER_SEC / 2;
166 do_div(div, NSEC_PER_SEC);
167 if (div - 1 > PWM_PRD_MASK)
168 prescaler = 0;
169 }
170
171 if (prescaler == 0) {
172 /* Go up from the first divider */
173 for (prescaler = 0; prescaler < PWM_PRESCAL_MASK; prescaler++) {
174 if (!prescaler_table[prescaler])
175 continue;
176 pval = prescaler_table[prescaler];
177 div = clk_rate;
178 do_div(div, pval);
179 div = div * state->period;
180 do_div(div, NSEC_PER_SEC);
181 if (div - 1 <= PWM_PRD_MASK)
182 break;
183 }
184
185 if (div - 1 > PWM_PRD_MASK)
186 return -EINVAL;
187 }
188
189 *prd = div;
190 div *= state->duty_cycle;
191 do_div(div, state->period);
192 *dty = div;
193 *prsclr = prescaler;
194
195 return 0;
196}
197
198static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
199 const struct pwm_state *state)
200{
201 struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
202 struct pwm_state cstate;
203 u32 ctrl;
204 int ret;
205 unsigned int delay_us;
206 unsigned long now;
207
208 pwm_get_state(pwm, &cstate);
209
210 if (!cstate.enabled) {
211 ret = clk_prepare_enable(sun4i_pwm->clk);
212 if (ret) {
213 dev_err(chip->dev, "failed to enable PWM clock\n");
214 return ret;
215 }
216 }
217
218 spin_lock(&sun4i_pwm->ctrl_lock);
219 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
220
221 if ((cstate.period != state->period) ||
222 (cstate.duty_cycle != state->duty_cycle)) {
223 u32 period, duty, val;
224 unsigned int prescaler;
225
226 ret = sun4i_pwm_calculate(sun4i_pwm, state,
227 &duty, &period, &prescaler);
228 if (ret) {
229 dev_err(chip->dev, "period exceeds the maximum value\n");
230 spin_unlock(&sun4i_pwm->ctrl_lock);
231 if (!cstate.enabled)
232 clk_disable_unprepare(sun4i_pwm->clk);
233 return ret;
234 }
235
236 if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
237 /* Prescaler changed, the clock has to be gated */
238 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
239 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
240
241 ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
242 ctrl |= BIT_CH(prescaler, pwm->hwpwm);
243 }
244
245 val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
246 sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
247 sun4i_pwm->next_period[pwm->hwpwm] = jiffies +
248 usecs_to_jiffies(cstate.period / 1000 + 1);
249 sun4i_pwm->needs_delay[pwm->hwpwm] = true;
250 }
251
252 if (state->polarity != PWM_POLARITY_NORMAL)
253 ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
254 else
255 ctrl |= BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
256
257 ctrl |= BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
258 if (state->enabled) {
259 ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
260 } else if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
261 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
262 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
263 }
264
265 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
266
267 spin_unlock(&sun4i_pwm->ctrl_lock);
268
269 if (state->enabled)
270 return 0;
271
272 if (!sun4i_pwm->needs_delay[pwm->hwpwm]) {
273 clk_disable_unprepare(sun4i_pwm->clk);
274 return 0;
275 }
276
277 /* We need a full period to elapse before disabling the channel. */
278 now = jiffies;
279 if (sun4i_pwm->needs_delay[pwm->hwpwm] &&
280 time_before(now, sun4i_pwm->next_period[pwm->hwpwm])) {
281 delay_us = jiffies_to_usecs(sun4i_pwm->next_period[pwm->hwpwm] -
282 now);
283 if ((delay_us / 500) > MAX_UDELAY_MS)
284 msleep(delay_us / 1000 + 1);
285 else
286 usleep_range(delay_us, delay_us * 2);
287 }
288 sun4i_pwm->needs_delay[pwm->hwpwm] = false;
289
290 spin_lock(&sun4i_pwm->ctrl_lock);
291 ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
292 ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
293 ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
294 sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
295 spin_unlock(&sun4i_pwm->ctrl_lock);
296
297 clk_disable_unprepare(sun4i_pwm->clk);
298
299 return 0;
300}
301
302static const struct pwm_ops sun4i_pwm_ops = {
303 .apply = sun4i_pwm_apply,
304 .get_state = sun4i_pwm_get_state,
305 .owner = THIS_MODULE,
306};
307
308static const struct sun4i_pwm_data sun4i_pwm_dual_nobypass = {
309 .has_prescaler_bypass = false,
310 .npwm = 2,
311};
312
313static const struct sun4i_pwm_data sun4i_pwm_dual_bypass = {
314 .has_prescaler_bypass = true,
315 .npwm = 2,
316};
317
318static const struct sun4i_pwm_data sun4i_pwm_single_bypass = {
319 .has_prescaler_bypass = true,
320 .npwm = 1,
321};
322
323static const struct of_device_id sun4i_pwm_dt_ids[] = {
324 {
325 .compatible = "allwinner,sun4i-a10-pwm",
326 .data = &sun4i_pwm_dual_nobypass,
327 }, {
328 .compatible = "allwinner,sun5i-a10s-pwm",
329 .data = &sun4i_pwm_dual_bypass,
330 }, {
331 .compatible = "allwinner,sun5i-a13-pwm",
332 .data = &sun4i_pwm_single_bypass,
333 }, {
334 .compatible = "allwinner,sun7i-a20-pwm",
335 .data = &sun4i_pwm_dual_bypass,
336 }, {
337 .compatible = "allwinner,sun8i-h3-pwm",
338 .data = &sun4i_pwm_single_bypass,
339 }, {
340 /* sentinel */
341 },
342};
343MODULE_DEVICE_TABLE(of, sun4i_pwm_dt_ids);
344
345static int sun4i_pwm_probe(struct platform_device *pdev)
346{
347 struct sun4i_pwm_chip *pwm;
348 struct resource *res;
349 int ret;
350
351 pwm = devm_kzalloc(&pdev->dev, sizeof(*pwm), GFP_KERNEL);
352 if (!pwm)
353 return -ENOMEM;
354
355 pwm->data = of_device_get_match_data(&pdev->dev);
356 if (!pwm->data)
357 return -ENODEV;
358
359 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360 pwm->base = devm_ioremap_resource(&pdev->dev, res);
361 if (IS_ERR(pwm->base))
362 return PTR_ERR(pwm->base);
363
364 pwm->clk = devm_clk_get(&pdev->dev, NULL);
365 if (IS_ERR(pwm->clk))
366 return PTR_ERR(pwm->clk);
367
368 pwm->chip.dev = &pdev->dev;
369 pwm->chip.ops = &sun4i_pwm_ops;
370 pwm->chip.base = -1;
371 pwm->chip.npwm = pwm->data->npwm;
372 pwm->chip.of_xlate = of_pwm_xlate_with_flags;
373 pwm->chip.of_pwm_n_cells = 3;
374
375 spin_lock_init(&pwm->ctrl_lock);
376
377 ret = pwmchip_add(&pwm->chip);
378 if (ret < 0) {
379 dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret);
380 return ret;
381 }
382
383 platform_set_drvdata(pdev, pwm);
384
385 return 0;
386}
387
388static int sun4i_pwm_remove(struct platform_device *pdev)
389{
390 struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev);
391
392 return pwmchip_remove(&pwm->chip);
393}
394
395static struct platform_driver sun4i_pwm_driver = {
396 .driver = {
397 .name = "sun4i-pwm",
398 .of_match_table = sun4i_pwm_dt_ids,
399 },
400 .probe = sun4i_pwm_probe,
401 .remove = sun4i_pwm_remove,
402};
403module_platform_driver(sun4i_pwm_driver);
404
405MODULE_ALIAS("platform:sun4i-pwm");
406MODULE_AUTHOR("Alexandre Belloni <alexandre.belloni@free-electrons.com>");
407MODULE_DESCRIPTION("Allwinner sun4i PWM driver");
408MODULE_LICENSE("GPL v2");