1/*
   2 *  Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved.
   3 *
   4 * This program is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU General Public License
   6 * version 2 as published by the Free Software Foundation.
   7 *
   8 */
   9
  10#include <linux/signal.h>
  11#include <linux/slab.h>
  12#include <linux/module.h>
  13#include <linux/netdevice.h>
  14#include <linux/etherdevice.h>
  15#include <linux/mii.h>
  16#include <linux/ethtool.h>
  17#include <linux/usb.h>
  18#include <linux/crc32.h>
  19#include <linux/if_vlan.h>
  20#include <linux/uaccess.h>
  21#include <linux/list.h>
  22#include <linux/ip.h>
  23#include <linux/ipv6.h>
  24#include <net/ip6_checksum.h>
  25#include <uapi/linux/mdio.h>
  26#include <linux/mdio.h>
  27#include <linux/usb/cdc.h>
  28#include <linux/suspend.h>
 
  29#include <linux/acpi.h>
  30
  31/* Information for net-next */
  32#define NETNEXT_VERSION		"09"
  33
  34/* Information for net */
  35#define NET_VERSION		"9"
  36
  37#define DRIVER_VERSION		"v1." NETNEXT_VERSION "." NET_VERSION
  38#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>"
  39#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters"
  40#define MODULENAME "r8152"
  41
  42#define R8152_PHY_ID		32
  43
  44#define PLA_IDR			0xc000
  45#define PLA_RCR			0xc010
  46#define PLA_RMS			0xc016
  47#define PLA_RXFIFO_CTRL0	0xc0a0
  48#define PLA_RXFIFO_CTRL1	0xc0a4
  49#define PLA_RXFIFO_CTRL2	0xc0a8
  50#define PLA_DMY_REG0		0xc0b0
  51#define PLA_FMC			0xc0b4
  52#define PLA_CFG_WOL		0xc0b6
  53#define PLA_TEREDO_CFG		0xc0bc
  54#define PLA_TEREDO_WAKE_BASE	0xc0c4
  55#define PLA_MAR			0xcd00
  56#define PLA_BACKUP		0xd000
  57#define PAL_BDC_CR		0xd1a0
  58#define PLA_TEREDO_TIMER	0xd2cc
  59#define PLA_REALWOW_TIMER	0xd2e8
 
 
 
  60#define PLA_EFUSE_DATA		0xdd00
  61#define PLA_EFUSE_CMD		0xdd02
  62#define PLA_LEDSEL		0xdd90
  63#define PLA_LED_FEATURE		0xdd92
  64#define PLA_PHYAR		0xde00
  65#define PLA_BOOT_CTRL		0xe004
  66#define PLA_GPHY_INTR_IMR	0xe022
  67#define PLA_EEE_CR		0xe040
  68#define PLA_EEEP_CR		0xe080
  69#define PLA_MAC_PWR_CTRL	0xe0c0
  70#define PLA_MAC_PWR_CTRL2	0xe0ca
  71#define PLA_MAC_PWR_CTRL3	0xe0cc
  72#define PLA_MAC_PWR_CTRL4	0xe0ce
  73#define PLA_WDT6_CTRL		0xe428
  74#define PLA_TCR0		0xe610
  75#define PLA_TCR1		0xe612
  76#define PLA_MTPS		0xe615
  77#define PLA_TXFIFO_CTRL		0xe618
  78#define PLA_RSTTALLY		0xe800
  79#define PLA_CR			0xe813
  80#define PLA_CRWECR		0xe81c
  81#define PLA_CONFIG12		0xe81e	/* CONFIG1, CONFIG2 */
  82#define PLA_CONFIG34		0xe820	/* CONFIG3, CONFIG4 */
  83#define PLA_CONFIG5		0xe822
  84#define PLA_PHY_PWR		0xe84c
  85#define PLA_OOB_CTRL		0xe84f
  86#define PLA_CPCR		0xe854
  87#define PLA_MISC_0		0xe858
  88#define PLA_MISC_1		0xe85a
  89#define PLA_OCP_GPHY_BASE	0xe86c
  90#define PLA_TALLYCNT		0xe890
  91#define PLA_SFF_STS_7		0xe8de
  92#define PLA_PHYSTATUS		0xe908
  93#define PLA_BP_BA		0xfc26
  94#define PLA_BP_0		0xfc28
  95#define PLA_BP_1		0xfc2a
  96#define PLA_BP_2		0xfc2c
  97#define PLA_BP_3		0xfc2e
  98#define PLA_BP_4		0xfc30
  99#define PLA_BP_5		0xfc32
 100#define PLA_BP_6		0xfc34
 101#define PLA_BP_7		0xfc36
 102#define PLA_BP_EN		0xfc38
 103
 104#define USB_USB2PHY		0xb41e
 105#define USB_SSPHYLINK2		0xb428
 106#define USB_U2P3_CTRL		0xb460
 107#define USB_CSR_DUMMY1		0xb464
 108#define USB_CSR_DUMMY2		0xb466
 109#define USB_DEV_STAT		0xb808
 110#define USB_CONNECT_TIMER	0xcbf8
 111#define USB_MSC_TIMER		0xcbfc
 112#define USB_BURST_SIZE		0xcfc0
 113#define USB_LPM_CONFIG		0xcfd8
 114#define USB_USB_CTRL		0xd406
 115#define USB_PHY_CTRL		0xd408
 116#define USB_TX_AGG		0xd40a
 117#define USB_RX_BUF_TH		0xd40c
 118#define USB_USB_TIMER		0xd428
 119#define USB_RX_EARLY_TIMEOUT	0xd42c
 120#define USB_RX_EARLY_SIZE	0xd42e
 121#define USB_PM_CTRL_STATUS	0xd432	/* RTL8153A */
 122#define USB_RX_EXTRA_AGGR_TMR	0xd432	/* RTL8153B */
 123#define USB_TX_DMA		0xd434
 124#define USB_UPT_RXDMA_OWN	0xd437
 125#define USB_TOLERANCE		0xd490
 126#define USB_LPM_CTRL		0xd41a
 127#define USB_BMU_RESET		0xd4b0
 128#define USB_U1U2_TIMER		0xd4da
 129#define USB_UPS_CTRL		0xd800
 130#define USB_POWER_CUT		0xd80a
 131#define USB_MISC_0		0xd81a
 
 132#define USB_AFE_CTRL2		0xd824
 133#define USB_UPS_CFG		0xd842
 134#define USB_UPS_FLAGS		0xd848
 135#define USB_WDT11_CTRL		0xe43c
 136#define USB_BP_BA		0xfc26
 137#define USB_BP_0		0xfc28
 138#define USB_BP_1		0xfc2a
 139#define USB_BP_2		0xfc2c
 140#define USB_BP_3		0xfc2e
 141#define USB_BP_4		0xfc30
 142#define USB_BP_5		0xfc32
 143#define USB_BP_6		0xfc34
 144#define USB_BP_7		0xfc36
 145#define USB_BP_EN		0xfc38
 146#define USB_BP_8		0xfc38
 147#define USB_BP_9		0xfc3a
 148#define USB_BP_10		0xfc3c
 149#define USB_BP_11		0xfc3e
 150#define USB_BP_12		0xfc40
 151#define USB_BP_13		0xfc42
 152#define USB_BP_14		0xfc44
 153#define USB_BP_15		0xfc46
 154#define USB_BP2_EN		0xfc48
 155
 156/* OCP Registers */
 157#define OCP_ALDPS_CONFIG	0x2010
 158#define OCP_EEE_CONFIG1		0x2080
 159#define OCP_EEE_CONFIG2		0x2092
 160#define OCP_EEE_CONFIG3		0x2094
 161#define OCP_BASE_MII		0xa400
 162#define OCP_EEE_AR		0xa41a
 163#define OCP_EEE_DATA		0xa41c
 164#define OCP_PHY_STATUS		0xa420
 165#define OCP_NCTL_CFG		0xa42c
 166#define OCP_POWER_CFG		0xa430
 167#define OCP_EEE_CFG		0xa432
 168#define OCP_SRAM_ADDR		0xa436
 169#define OCP_SRAM_DATA		0xa438
 170#define OCP_DOWN_SPEED		0xa442
 171#define OCP_EEE_ABLE		0xa5c4
 172#define OCP_EEE_ADV		0xa5d0
 173#define OCP_EEE_LPABLE		0xa5d2
 174#define OCP_PHY_STATE		0xa708		/* nway state for 8153 */
 175#define OCP_PHY_PATCH_STAT	0xb800
 176#define OCP_PHY_PATCH_CMD	0xb820
 177#define OCP_ADC_IOFFSET		0xbcfc
 178#define OCP_ADC_CFG		0xbc06
 179#define OCP_SYSCLK_CFG		0xc416
 180
 181/* SRAM Register */
 182#define SRAM_GREEN_CFG		0x8011
 183#define SRAM_LPF_CFG		0x8012
 184#define SRAM_10M_AMP1		0x8080
 185#define SRAM_10M_AMP2		0x8082
 186#define SRAM_IMPEDANCE		0x8084
 187
 188/* PLA_RCR */
 189#define RCR_AAP			0x00000001
 190#define RCR_APM			0x00000002
 191#define RCR_AM			0x00000004
 192#define RCR_AB			0x00000008
 193#define RCR_ACPT_ALL		(RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
 194
 195/* PLA_RXFIFO_CTRL0 */
 196#define RXFIFO_THR1_NORMAL	0x00080002
 197#define RXFIFO_THR1_OOB		0x01800003
 198
 199/* PLA_RXFIFO_CTRL1 */
 200#define RXFIFO_THR2_FULL	0x00000060
 201#define RXFIFO_THR2_HIGH	0x00000038
 202#define RXFIFO_THR2_OOB		0x0000004a
 203#define RXFIFO_THR2_NORMAL	0x00a0
 204
 205/* PLA_RXFIFO_CTRL2 */
 206#define RXFIFO_THR3_FULL	0x00000078
 207#define RXFIFO_THR3_HIGH	0x00000048
 208#define RXFIFO_THR3_OOB		0x0000005a
 209#define RXFIFO_THR3_NORMAL	0x0110
 210
 211/* PLA_TXFIFO_CTRL */
 212#define TXFIFO_THR_NORMAL	0x00400008
 213#define TXFIFO_THR_NORMAL2	0x01000008
 214
 215/* PLA_DMY_REG0 */
 216#define ECM_ALDPS		0x0002
 217
 218/* PLA_FMC */
 219#define FMC_FCR_MCU_EN		0x0001
 220
 221/* PLA_EEEP_CR */
 222#define EEEP_CR_EEEP_TX		0x0002
 223
 224/* PLA_WDT6_CTRL */
 225#define WDT6_SET_MODE		0x0010
 226
 227/* PLA_TCR0 */
 228#define TCR0_TX_EMPTY		0x0800
 229#define TCR0_AUTO_FIFO		0x0080
 230
 231/* PLA_TCR1 */
 232#define VERSION_MASK		0x7cf0
 233
 234/* PLA_MTPS */
 235#define MTPS_JUMBO		(12 * 1024 / 64)
 236#define MTPS_DEFAULT		(6 * 1024 / 64)
 237
 238/* PLA_RSTTALLY */
 239#define TALLY_RESET		0x0001
 240
 241/* PLA_CR */
 242#define CR_RST			0x10
 243#define CR_RE			0x08
 244#define CR_TE			0x04
 245
 246/* PLA_CRWECR */
 247#define CRWECR_NORAML		0x00
 248#define CRWECR_CONFIG		0xc0
 249
 250/* PLA_OOB_CTRL */
 251#define NOW_IS_OOB		0x80
 252#define TXFIFO_EMPTY		0x20
 253#define RXFIFO_EMPTY		0x10
 254#define LINK_LIST_READY		0x02
 255#define DIS_MCU_CLROOB		0x01
 256#define FIFO_EMPTY		(TXFIFO_EMPTY | RXFIFO_EMPTY)
 257
 258/* PLA_MISC_1 */
 259#define RXDY_GATED_EN		0x0008
 260
 261/* PLA_SFF_STS_7 */
 262#define RE_INIT_LL		0x8000
 263#define MCU_BORW_EN		0x4000
 264
 265/* PLA_CPCR */
 266#define CPCR_RX_VLAN		0x0040
 267
 268/* PLA_CFG_WOL */
 269#define MAGIC_EN		0x0001
 270
 271/* PLA_TEREDO_CFG */
 272#define TEREDO_SEL		0x8000
 273#define TEREDO_WAKE_MASK	0x7f00
 274#define TEREDO_RS_EVENT_MASK	0x00fe
 275#define OOB_TEREDO_EN		0x0001
 276
 277/* PAL_BDC_CR */
 278#define ALDPS_PROXY_MODE	0x0001
 279
 280/* PLA_EFUSE_CMD */
 281#define EFUSE_READ_CMD		BIT(15)
 282#define EFUSE_DATA_BIT16	BIT(7)
 283
 284/* PLA_CONFIG34 */
 285#define LINK_ON_WAKE_EN		0x0010
 286#define LINK_OFF_WAKE_EN	0x0008
 287
 288/* PLA_CONFIG5 */
 289#define BWF_EN			0x0040
 290#define MWF_EN			0x0020
 291#define UWF_EN			0x0010
 292#define LAN_WAKE_EN		0x0002
 293
 294/* PLA_LED_FEATURE */
 295#define LED_MODE_MASK		0x0700
 296
 297/* PLA_PHY_PWR */
 298#define TX_10M_IDLE_EN		0x0080
 299#define PFM_PWM_SWITCH		0x0040
 300
 301/* PLA_MAC_PWR_CTRL */
 302#define D3_CLK_GATED_EN		0x00004000
 303#define MCU_CLK_RATIO		0x07010f07
 304#define MCU_CLK_RATIO_MASK	0x0f0f0f0f
 305#define ALDPS_SPDWN_RATIO	0x0f87
 306
 307/* PLA_MAC_PWR_CTRL2 */
 308#define EEE_SPDWN_RATIO		0x8007
 309#define MAC_CLK_SPDWN_EN	BIT(15)
 310
 311/* PLA_MAC_PWR_CTRL3 */
 312#define PKT_AVAIL_SPDWN_EN	0x0100
 313#define SUSPEND_SPDWN_EN	0x0004
 314#define U1U2_SPDWN_EN		0x0002
 315#define L1_SPDWN_EN		0x0001
 316
 317/* PLA_MAC_PWR_CTRL4 */
 318#define PWRSAVE_SPDWN_EN	0x1000
 319#define RXDV_SPDWN_EN		0x0800
 320#define TX10MIDLE_EN		0x0100
 321#define TP100_SPDWN_EN		0x0020
 322#define TP500_SPDWN_EN		0x0010
 323#define TP1000_SPDWN_EN		0x0008
 324#define EEE_SPDWN_EN		0x0001
 325
 326/* PLA_GPHY_INTR_IMR */
 327#define GPHY_STS_MSK		0x0001
 328#define SPEED_DOWN_MSK		0x0002
 329#define SPDWN_RXDV_MSK		0x0004
 330#define SPDWN_LINKCHG_MSK	0x0008
 331
 332/* PLA_PHYAR */
 333#define PHYAR_FLAG		0x80000000
 334
 335/* PLA_EEE_CR */
 336#define EEE_RX_EN		0x0001
 337#define EEE_TX_EN		0x0002
 338
 339/* PLA_BOOT_CTRL */
 340#define AUTOLOAD_DONE		0x0002
 341
 
 
 
 
 
 
 
 
 
 342/* USB_USB2PHY */
 343#define USB2PHY_SUSPEND		0x0001
 344#define USB2PHY_L1		0x0002
 345
 346/* USB_SSPHYLINK2 */
 347#define pwd_dn_scale_mask	0x3ffe
 348#define pwd_dn_scale(x)		((x) << 1)
 349
 350/* USB_CSR_DUMMY1 */
 351#define DYNAMIC_BURST		0x0001
 352
 353/* USB_CSR_DUMMY2 */
 354#define EP4_FULL_FC		0x0001
 355
 356/* USB_DEV_STAT */
 357#define STAT_SPEED_MASK		0x0006
 358#define STAT_SPEED_HIGH		0x0000
 359#define STAT_SPEED_FULL		0x0002
 360
 361/* USB_LPM_CONFIG */
 362#define LPM_U1U2_EN		BIT(0)
 363
 364/* USB_TX_AGG */
 365#define TX_AGG_MAX_THRESHOLD	0x03
 366
 367/* USB_RX_BUF_TH */
 368#define RX_THR_SUPPER		0x0c350180
 369#define RX_THR_HIGH		0x7a120180
 370#define RX_THR_SLOW		0xffff0180
 371#define RX_THR_B		0x00010001
 372
 373/* USB_TX_DMA */
 374#define TEST_MODE_DISABLE	0x00000001
 375#define TX_SIZE_ADJUST1		0x00000100
 376
 377/* USB_BMU_RESET */
 378#define BMU_RESET_EP_IN		0x01
 379#define BMU_RESET_EP_OUT	0x02
 380
 381/* USB_UPT_RXDMA_OWN */
 382#define OWN_UPDATE		BIT(0)
 383#define OWN_CLEAR		BIT(1)
 384
 385/* USB_UPS_CTRL */
 386#define POWER_CUT		0x0100
 387
 388/* USB_PM_CTRL_STATUS */
 389#define RESUME_INDICATE		0x0001
 390
 391/* USB_USB_CTRL */
 392#define RX_AGG_DISABLE		0x0010
 393#define RX_ZERO_EN		0x0080
 394
 395/* USB_U2P3_CTRL */
 396#define U2P3_ENABLE		0x0001
 397
 398/* USB_POWER_CUT */
 399#define PWR_EN			0x0001
 400#define PHASE2_EN		0x0008
 401#define UPS_EN			BIT(4)
 402#define USP_PREWAKE		BIT(5)
 403
 404/* USB_MISC_0 */
 405#define PCUT_STATUS		0x0001
 406
 407/* USB_RX_EARLY_TIMEOUT */
 408#define COALESCE_SUPER		 85000U
 409#define COALESCE_HIGH		250000U
 410#define COALESCE_SLOW		524280U
 411
 412/* USB_WDT11_CTRL */
 413#define TIMER11_EN		0x0001
 414
 415/* USB_LPM_CTRL */
 416/* bit 4 ~ 5: fifo empty boundary */
 417#define FIFO_EMPTY_1FB		0x30	/* 0x1fb * 64 = 32448 bytes */
 418/* bit 2 ~ 3: LMP timer */
 419#define LPM_TIMER_MASK		0x0c
 420#define LPM_TIMER_500MS		0x04	/* 500 ms */
 421#define LPM_TIMER_500US		0x0c	/* 500 us */
 422#define ROK_EXIT_LPM		0x02
 423
 424/* USB_AFE_CTRL2 */
 425#define SEN_VAL_MASK		0xf800
 426#define SEN_VAL_NORMAL		0xa000
 427#define SEL_RXIDLE		0x0100
 428
 429/* USB_UPS_CFG */
 430#define SAW_CNT_1MS_MASK	0x0fff
 431
 432/* USB_UPS_FLAGS */
 433#define UPS_FLAGS_R_TUNE		BIT(0)
 434#define UPS_FLAGS_EN_10M_CKDIV		BIT(1)
 435#define UPS_FLAGS_250M_CKDIV		BIT(2)
 436#define UPS_FLAGS_EN_ALDPS		BIT(3)
 437#define UPS_FLAGS_CTAP_SHORT_DIS	BIT(4)
 438#define UPS_FLAGS_SPEED_MASK		(0xf << 16)
 439#define ups_flags_speed(x)		((x) << 16)
 440#define UPS_FLAGS_EN_EEE		BIT(20)
 441#define UPS_FLAGS_EN_500M_EEE		BIT(21)
 442#define UPS_FLAGS_EN_EEE_CKDIV		BIT(22)
 
 443#define UPS_FLAGS_EEE_PLLOFF_GIGA	BIT(24)
 444#define UPS_FLAGS_EEE_CMOD_LV_EN	BIT(25)
 445#define UPS_FLAGS_EN_GREEN		BIT(26)
 446#define UPS_FLAGS_EN_FLOW_CTR		BIT(27)
 447
 448enum spd_duplex {
 449	NWAY_10M_HALF = 1,
 450	NWAY_10M_FULL,
 451	NWAY_100M_HALF,
 452	NWAY_100M_FULL,
 453	NWAY_1000M_FULL,
 454	FORCE_10M_HALF,
 455	FORCE_10M_FULL,
 456	FORCE_100M_HALF,
 457	FORCE_100M_FULL,
 458};
 459
 460/* OCP_ALDPS_CONFIG */
 461#define ENPWRSAVE		0x8000
 462#define ENPDNPS			0x0200
 463#define LINKENA			0x0100
 464#define DIS_SDSAVE		0x0010
 465
 466/* OCP_PHY_STATUS */
 467#define PHY_STAT_MASK		0x0007
 468#define PHY_STAT_EXT_INIT	2
 469#define PHY_STAT_LAN_ON		3
 470#define PHY_STAT_PWRDN		5
 471
 472/* OCP_NCTL_CFG */
 473#define PGA_RETURN_EN		BIT(1)
 474
 475/* OCP_POWER_CFG */
 476#define EEE_CLKDIV_EN		0x8000
 477#define EN_ALDPS		0x0004
 478#define EN_10M_PLLOFF		0x0001
 479
 480/* OCP_EEE_CONFIG1 */
 481#define RG_TXLPI_MSK_HFDUP	0x8000
 482#define RG_MATCLR_EN		0x4000
 483#define EEE_10_CAP		0x2000
 484#define EEE_NWAY_EN		0x1000
 485#define TX_QUIET_EN		0x0200
 486#define RX_QUIET_EN		0x0100
 487#define sd_rise_time_mask	0x0070
 488#define sd_rise_time(x)		(min(x, 7) << 4)	/* bit 4 ~ 6 */
 489#define RG_RXLPI_MSK_HFDUP	0x0008
 490#define SDFALLTIME		0x0007	/* bit 0 ~ 2 */
 491
 492/* OCP_EEE_CONFIG2 */
 493#define RG_LPIHYS_NUM		0x7000	/* bit 12 ~ 15 */
 494#define RG_DACQUIET_EN		0x0400
 495#define RG_LDVQUIET_EN		0x0200
 496#define RG_CKRSEL		0x0020
 497#define RG_EEEPRG_EN		0x0010
 498
 499/* OCP_EEE_CONFIG3 */
 500#define fast_snr_mask		0xff80
 501#define fast_snr(x)		(min(x, 0x1ff) << 7)	/* bit 7 ~ 15 */
 502#define RG_LFS_SEL		0x0060	/* bit 6 ~ 5 */
 503#define MSK_PH			0x0006	/* bit 0 ~ 3 */
 504
 505/* OCP_EEE_AR */
 506/* bit[15:14] function */
 507#define FUN_ADDR		0x0000
 508#define FUN_DATA		0x4000
 509/* bit[4:0] device addr */
 510
 511/* OCP_EEE_CFG */
 512#define CTAP_SHORT_EN		0x0040
 513#define EEE10_EN		0x0010
 514
 515/* OCP_DOWN_SPEED */
 516#define EN_EEE_CMODE		BIT(14)
 517#define EN_EEE_1000		BIT(13)
 518#define EN_EEE_100		BIT(12)
 519#define EN_10M_CLKDIV		BIT(11)
 520#define EN_10M_BGOFF		0x0080
 521
 522/* OCP_PHY_STATE */
 523#define TXDIS_STATE		0x01
 524#define ABD_STATE		0x02
 525
 526/* OCP_PHY_PATCH_STAT */
 527#define PATCH_READY		BIT(6)
 528
 529/* OCP_PHY_PATCH_CMD */
 530#define PATCH_REQUEST		BIT(4)
 531
 532/* OCP_ADC_CFG */
 533#define CKADSEL_L		0x0100
 534#define ADC_EN			0x0080
 535#define EN_EMI_L		0x0040
 536
 537/* OCP_SYSCLK_CFG */
 538#define clk_div_expo(x)		(min(x, 5) << 8)
 539
 540/* SRAM_GREEN_CFG */
 541#define GREEN_ETH_EN		BIT(15)
 542#define R_TUNE_EN		BIT(11)
 543
 544/* SRAM_LPF_CFG */
 545#define LPF_AUTO_TUNE		0x8000
 546
 547/* SRAM_10M_AMP1 */
 548#define GDAC_IB_UPALL		0x0008
 549
 550/* SRAM_10M_AMP2 */
 551#define AMP_DN			0x0200
 552
 553/* SRAM_IMPEDANCE */
 554#define RX_DRIVING_MASK		0x6000
 555
 556/* MAC PASSTHRU */
 557#define AD_MASK			0xfee0
 
 
 558#define EFUSE			0xcfdb
 559#define PASS_THRU_MASK		0x1
 560
 561enum rtl_register_content {
 562	_1000bps	= 0x10,
 563	_100bps		= 0x08,
 564	_10bps		= 0x04,
 565	LINK_STATUS	= 0x02,
 566	FULL_DUP	= 0x01,
 567};
 568
 569#define RTL8152_MAX_TX		4
 570#define RTL8152_MAX_RX		10
 571#define INTBUFSIZE		2
 572#define TX_ALIGN		4
 573#define RX_ALIGN		8
 574
 
 
 
 575#define INTR_LINK		0x0004
 576
 577#define RTL8152_REQT_READ	0xc0
 578#define RTL8152_REQT_WRITE	0x40
 579#define RTL8152_REQ_GET_REGS	0x05
 580#define RTL8152_REQ_SET_REGS	0x05
 581
 582#define BYTE_EN_DWORD		0xff
 583#define BYTE_EN_WORD		0x33
 584#define BYTE_EN_BYTE		0x11
 585#define BYTE_EN_SIX_BYTES	0x3f
 586#define BYTE_EN_START_MASK	0x0f
 587#define BYTE_EN_END_MASK	0xf0
 588
 589#define RTL8153_MAX_PACKET	9216 /* 9K */
 590#define RTL8153_MAX_MTU		(RTL8153_MAX_PACKET - VLAN_ETH_HLEN - \
 591				 ETH_FCS_LEN)
 592#define RTL8152_RMS		(VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
 593#define RTL8153_RMS		RTL8153_MAX_PACKET
 594#define RTL8152_TX_TIMEOUT	(5 * HZ)
 595#define RTL8152_NAPI_WEIGHT	64
 596#define rx_reserved_size(x)	((x) + VLAN_ETH_HLEN + ETH_FCS_LEN + \
 597				 sizeof(struct rx_desc) + RX_ALIGN)
 598
 599/* rtl8152 flags */
 600enum rtl8152_flags {
 601	RTL8152_UNPLUG = 0,
 602	RTL8152_SET_RX_MODE,
 603	WORK_ENABLE,
 604	RTL8152_LINK_CHG,
 605	SELECTIVE_SUSPEND,
 606	PHY_RESET,
 607	SCHEDULE_NAPI,
 608	GREEN_ETHERNET,
 609	DELL_TB_RX_AGG_BUG,
 610};
 611
 612/* Define these values to match your device */
 613#define VENDOR_ID_REALTEK		0x0bda
 614#define VENDOR_ID_MICROSOFT		0x045e
 615#define VENDOR_ID_SAMSUNG		0x04e8
 616#define VENDOR_ID_LENOVO		0x17ef
 617#define VENDOR_ID_LINKSYS		0x13b1
 618#define VENDOR_ID_NVIDIA		0x0955
 619#define VENDOR_ID_TPLINK		0x2357
 620
 621#define MCU_TYPE_PLA			0x0100
 622#define MCU_TYPE_USB			0x0000
 623
 624struct tally_counter {
 625	__le64	tx_packets;
 626	__le64	rx_packets;
 627	__le64	tx_errors;
 628	__le32	rx_errors;
 629	__le16	rx_missed;
 630	__le16	align_errors;
 631	__le32	tx_one_collision;
 632	__le32	tx_multi_collision;
 633	__le64	rx_unicast;
 634	__le64	rx_broadcast;
 635	__le32	rx_multicast;
 636	__le16	tx_aborted;
 637	__le16	tx_underrun;
 638};
 639
 640struct rx_desc {
 641	__le32 opts1;
 642#define RX_LEN_MASK			0x7fff
 643
 644	__le32 opts2;
 645#define RD_UDP_CS			BIT(23)
 646#define RD_TCP_CS			BIT(22)
 647#define RD_IPV6_CS			BIT(20)
 648#define RD_IPV4_CS			BIT(19)
 649
 650	__le32 opts3;
 651#define IPF				BIT(23) /* IP checksum fail */
 652#define UDPF				BIT(22) /* UDP checksum fail */
 653#define TCPF				BIT(21) /* TCP checksum fail */
 654#define RX_VLAN_TAG			BIT(16)
 655
 656	__le32 opts4;
 657	__le32 opts5;
 658	__le32 opts6;
 659};
 660
 661struct tx_desc {
 662	__le32 opts1;
 663#define TX_FS			BIT(31) /* First segment of a packet */
 664#define TX_LS			BIT(30) /* Final segment of a packet */
 665#define GTSENDV4		BIT(28)
 666#define GTSENDV6		BIT(27)
 667#define GTTCPHO_SHIFT		18
 668#define GTTCPHO_MAX		0x7fU
 669#define TX_LEN_MAX		0x3ffffU
 670
 671	__le32 opts2;
 672#define UDP_CS			BIT(31) /* Calculate UDP/IP checksum */
 673#define TCP_CS			BIT(30) /* Calculate TCP/IP checksum */
 674#define IPV4_CS			BIT(29) /* Calculate IPv4 checksum */
 675#define IPV6_CS			BIT(28) /* Calculate IPv6 checksum */
 676#define MSS_SHIFT		17
 677#define MSS_MAX			0x7ffU
 678#define TCPHO_SHIFT		17
 679#define TCPHO_MAX		0x7ffU
 680#define TX_VLAN_TAG		BIT(16)
 681};
 682
 683struct r8152;
 684
 685struct rx_agg {
 686	struct list_head list;
 687	struct urb *urb;
 688	struct r8152 *context;
 
 689	void *buffer;
 690	void *head;
 691};
 692
 693struct tx_agg {
 694	struct list_head list;
 695	struct urb *urb;
 696	struct r8152 *context;
 697	void *buffer;
 698	void *head;
 699	u32 skb_num;
 700	u32 skb_len;
 701};
 702
 703struct r8152 {
 704	unsigned long flags;
 705	struct usb_device *udev;
 706	struct napi_struct napi;
 707	struct usb_interface *intf;
 708	struct net_device *netdev;
 709	struct urb *intr_urb;
 710	struct tx_agg tx_info[RTL8152_MAX_TX];
 711	struct rx_agg rx_info[RTL8152_MAX_RX];
 712	struct list_head rx_done, tx_free;
 713	struct sk_buff_head tx_queue, rx_queue;
 714	spinlock_t rx_lock, tx_lock;
 715	struct delayed_work schedule, hw_phy_work;
 716	struct mii_if_info mii;
 717	struct mutex control;	/* use for hw setting */
 718#ifdef CONFIG_PM_SLEEP
 719	struct notifier_block pm_notifier;
 720#endif
 
 721
 722	struct rtl_ops {
 723		void (*init)(struct r8152 *);
 724		int (*enable)(struct r8152 *);
 725		void (*disable)(struct r8152 *);
 726		void (*up)(struct r8152 *);
 727		void (*down)(struct r8152 *);
 728		void (*unload)(struct r8152 *);
 729		int (*eee_get)(struct r8152 *, struct ethtool_eee *);
 730		int (*eee_set)(struct r8152 *, struct ethtool_eee *);
 731		bool (*in_nway)(struct r8152 *);
 732		void (*hw_phy_cfg)(struct r8152 *);
 733		void (*autosuspend_en)(struct r8152 *tp, bool enable);
 734	} rtl_ops;
 735
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 736	int intr_interval;
 737	u32 saved_wolopts;
 738	u32 msg_enable;
 739	u32 tx_qlen;
 740	u32 coalesce;
 
 
 
 
 
 741	u16 ocp_base;
 742	u16 speed;
 
 743	u8 *intr_buff;
 744	u8 version;
 745	u8 duplex;
 746	u8 autoneg;
 747};
 748
 749enum rtl_version {
 750	RTL_VER_UNKNOWN = 0,
 751	RTL_VER_01,
 752	RTL_VER_02,
 753	RTL_VER_03,
 754	RTL_VER_04,
 755	RTL_VER_05,
 756	RTL_VER_06,
 757	RTL_VER_07,
 758	RTL_VER_08,
 759	RTL_VER_09,
 760	RTL_VER_MAX
 761};
 762
 763enum tx_csum_stat {
 764	TX_CSUM_SUCCESS = 0,
 765	TX_CSUM_TSO,
 766	TX_CSUM_NONE
 767};
 768
 
 
 
 
 
 
 
 769/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
 770 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
 771 */
 772static const int multicast_filter_limit = 32;
 773static unsigned int agg_buf_sz = 16384;
 774
 775#define RTL_LIMITED_TSO_SIZE	(agg_buf_sz - sizeof(struct tx_desc) - \
 776				 VLAN_ETH_HLEN - ETH_FCS_LEN)
 777
 778static
 779int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
 780{
 781	int ret;
 782	void *tmp;
 783
 784	tmp = kmalloc(size, GFP_KERNEL);
 785	if (!tmp)
 786		return -ENOMEM;
 787
 788	ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
 789			      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
 790			      value, index, tmp, size, 500);
 
 
 
 
 791
 792	memcpy(data, tmp, size);
 793	kfree(tmp);
 794
 795	return ret;
 796}
 797
 798static
 799int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
 800{
 801	int ret;
 802	void *tmp;
 803
 804	tmp = kmemdup(data, size, GFP_KERNEL);
 805	if (!tmp)
 806		return -ENOMEM;
 807
 808	ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
 809			      RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
 810			      value, index, tmp, size, 500);
 811
 812	kfree(tmp);
 813
 814	return ret;
 815}
 816
 
 
 
 
 
 
 
 
 817static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
 818			    void *data, u16 type)
 819{
 820	u16 limit = 64;
 821	int ret = 0;
 822
 823	if (test_bit(RTL8152_UNPLUG, &tp->flags))
 824		return -ENODEV;
 825
 826	/* both size and indix must be 4 bytes align */
 827	if ((size & 3) || !size || (index & 3) || !data)
 828		return -EPERM;
 829
 830	if ((u32)index + (u32)size > 0xffff)
 831		return -EPERM;
 832
 833	while (size) {
 834		if (size > limit) {
 835			ret = get_registers(tp, index, type, limit, data);
 836			if (ret < 0)
 837				break;
 838
 839			index += limit;
 840			data += limit;
 841			size -= limit;
 842		} else {
 843			ret = get_registers(tp, index, type, size, data);
 844			if (ret < 0)
 845				break;
 846
 847			index += size;
 848			data += size;
 849			size = 0;
 850			break;
 851		}
 852	}
 853
 854	if (ret == -ENODEV)
 855		set_bit(RTL8152_UNPLUG, &tp->flags);
 856
 857	return ret;
 858}
 859
 860static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
 861			     u16 size, void *data, u16 type)
 862{
 863	int ret;
 864	u16 byteen_start, byteen_end, byen;
 865	u16 limit = 512;
 866
 867	if (test_bit(RTL8152_UNPLUG, &tp->flags))
 868		return -ENODEV;
 869
 870	/* both size and indix must be 4 bytes align */
 871	if ((size & 3) || !size || (index & 3) || !data)
 872		return -EPERM;
 873
 874	if ((u32)index + (u32)size > 0xffff)
 875		return -EPERM;
 876
 877	byteen_start = byteen & BYTE_EN_START_MASK;
 878	byteen_end = byteen & BYTE_EN_END_MASK;
 879
 880	byen = byteen_start | (byteen_start << 4);
 881	ret = set_registers(tp, index, type | byen, 4, data);
 882	if (ret < 0)
 883		goto error1;
 884
 885	index += 4;
 886	data += 4;
 887	size -= 4;
 888
 889	if (size) {
 890		size -= 4;
 891
 892		while (size) {
 893			if (size > limit) {
 894				ret = set_registers(tp, index,
 895						    type | BYTE_EN_DWORD,
 896						    limit, data);
 897				if (ret < 0)
 898					goto error1;
 899
 900				index += limit;
 901				data += limit;
 902				size -= limit;
 903			} else {
 904				ret = set_registers(tp, index,
 905						    type | BYTE_EN_DWORD,
 906						    size, data);
 907				if (ret < 0)
 908					goto error1;
 909
 910				index += size;
 911				data += size;
 912				size = 0;
 913				break;
 914			}
 915		}
 916
 917		byen = byteen_end | (byteen_end >> 4);
 918		ret = set_registers(tp, index, type | byen, 4, data);
 919		if (ret < 0)
 920			goto error1;
 921	}
 922
 923error1:
 924	if (ret == -ENODEV)
 925		set_bit(RTL8152_UNPLUG, &tp->flags);
 926
 927	return ret;
 928}
 929
 930static inline
 931int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data)
 932{
 933	return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA);
 934}
 935
 936static inline
 937int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
 938{
 939	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA);
 940}
 941
 942static inline
 943int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data)
 944{
 945	return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB);
 946}
 947
 948static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index)
 949{
 950	__le32 data;
 951
 952	generic_ocp_read(tp, index, sizeof(data), &data, type);
 953
 954	return __le32_to_cpu(data);
 955}
 956
 957static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data)
 958{
 959	__le32 tmp = __cpu_to_le32(data);
 960
 961	generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type);
 962}
 963
 964static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index)
 965{
 966	u32 data;
 967	__le32 tmp;
 968	u16 byen = BYTE_EN_WORD;
 969	u8 shift = index & 2;
 970
 971	index &= ~3;
 972	byen <<= shift;
 973
 974	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen);
 975
 976	data = __le32_to_cpu(tmp);
 977	data >>= (shift * 8);
 978	data &= 0xffff;
 979
 980	return (u16)data;
 981}
 982
 983static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data)
 984{
 985	u32 mask = 0xffff;
 986	__le32 tmp;
 987	u16 byen = BYTE_EN_WORD;
 988	u8 shift = index & 2;
 989
 990	data &= mask;
 991
 992	if (index & 2) {
 993		byen <<= shift;
 994		mask <<= (shift * 8);
 995		data <<= (shift * 8);
 996		index &= ~3;
 997	}
 998
 999	tmp = __cpu_to_le32(data);
1000
1001	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1002}
1003
1004static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index)
1005{
1006	u32 data;
1007	__le32 tmp;
1008	u8 shift = index & 3;
1009
1010	index &= ~3;
1011
1012	generic_ocp_read(tp, index, sizeof(tmp), &tmp, type);
1013
1014	data = __le32_to_cpu(tmp);
1015	data >>= (shift * 8);
1016	data &= 0xff;
1017
1018	return (u8)data;
1019}
1020
1021static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data)
1022{
1023	u32 mask = 0xff;
1024	__le32 tmp;
1025	u16 byen = BYTE_EN_BYTE;
1026	u8 shift = index & 3;
1027
1028	data &= mask;
1029
1030	if (index & 3) {
1031		byen <<= shift;
1032		mask <<= (shift * 8);
1033		data <<= (shift * 8);
1034		index &= ~3;
1035	}
1036
1037	tmp = __cpu_to_le32(data);
1038
1039	generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type);
1040}
1041
1042static u16 ocp_reg_read(struct r8152 *tp, u16 addr)
1043{
1044	u16 ocp_base, ocp_index;
1045
1046	ocp_base = addr & 0xf000;
1047	if (ocp_base != tp->ocp_base) {
1048		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1049		tp->ocp_base = ocp_base;
1050	}
1051
1052	ocp_index = (addr & 0x0fff) | 0xb000;
1053	return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index);
1054}
1055
1056static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data)
1057{
1058	u16 ocp_base, ocp_index;
1059
1060	ocp_base = addr & 0xf000;
1061	if (ocp_base != tp->ocp_base) {
1062		ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base);
1063		tp->ocp_base = ocp_base;
1064	}
1065
1066	ocp_index = (addr & 0x0fff) | 0xb000;
1067	ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data);
1068}
1069
1070static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value)
1071{
1072	ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value);
1073}
1074
1075static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr)
1076{
1077	return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2);
1078}
1079
1080static void sram_write(struct r8152 *tp, u16 addr, u16 data)
1081{
1082	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1083	ocp_reg_write(tp, OCP_SRAM_DATA, data);
1084}
1085
1086static u16 sram_read(struct r8152 *tp, u16 addr)
1087{
1088	ocp_reg_write(tp, OCP_SRAM_ADDR, addr);
1089	return ocp_reg_read(tp, OCP_SRAM_DATA);
1090}
1091
1092static int read_mii_word(struct net_device *netdev, int phy_id, int reg)
1093{
1094	struct r8152 *tp = netdev_priv(netdev);
1095	int ret;
1096
1097	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1098		return -ENODEV;
1099
1100	if (phy_id != R8152_PHY_ID)
1101		return -EINVAL;
1102
1103	ret = r8152_mdio_read(tp, reg);
1104
1105	return ret;
1106}
1107
1108static
1109void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
1110{
1111	struct r8152 *tp = netdev_priv(netdev);
1112
1113	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1114		return;
1115
1116	if (phy_id != R8152_PHY_ID)
1117		return;
1118
1119	r8152_mdio_write(tp, reg, val);
1120}
1121
1122static int
1123r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
1124
1125static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
1126{
1127	struct r8152 *tp = netdev_priv(netdev);
1128	struct sockaddr *addr = p;
1129	int ret = -EADDRNOTAVAIL;
1130
1131	if (!is_valid_ether_addr(addr->sa_data))
1132		goto out1;
1133
1134	ret = usb_autopm_get_interface(tp->intf);
1135	if (ret < 0)
1136		goto out1;
1137
1138	mutex_lock(&tp->control);
1139
1140	memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
1141
1142	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1143	pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->sa_data);
1144	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1145
1146	mutex_unlock(&tp->control);
1147
1148	usb_autopm_put_interface(tp->intf);
1149out1:
1150	return ret;
1151}
1152
1153/* Devices containing RTL8153-AD can support a persistent
1154 * host system provided MAC address.
1155 * Examples of this are Dell TB15 and Dell WD15 docks
1156 */
1157static int vendor_mac_passthru_addr_read(struct r8152 *tp, struct sockaddr *sa)
1158{
1159	acpi_status status;
1160	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
1161	union acpi_object *obj;
1162	int ret = -EINVAL;
1163	u32 ocp_data;
1164	unsigned char buf[6];
1165
1166	/* test for -AD variant of RTL8153 */
1167	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1168	if ((ocp_data & AD_MASK) != 0x1000)
1169		return -ENODEV;
1170
1171	/* test for MAC address pass-through bit */
1172	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE);
1173	if ((ocp_data & PASS_THRU_MASK) != 1)
1174		return -ENODEV;
 
 
 
 
 
 
 
 
 
 
1175
1176	/* returns _AUXMAC_#AABBCCDDEEFF# */
1177	status = acpi_evaluate_object(NULL, "\\_SB.AMAC", NULL, &buffer);
1178	obj = (union acpi_object *)buffer.pointer;
1179	if (!ACPI_SUCCESS(status))
1180		return -ENODEV;
1181	if (obj->type != ACPI_TYPE_BUFFER || obj->string.length != 0x17) {
1182		netif_warn(tp, probe, tp->netdev,
1183			   "Invalid buffer for pass-thru MAC addr: (%d, %d)\n",
1184			   obj->type, obj->string.length);
1185		goto amacout;
1186	}
1187	if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 ||
1188	    strncmp(obj->string.pointer + 0x15, "#", 1) != 0) {
1189		netif_warn(tp, probe, tp->netdev,
1190			   "Invalid header when reading pass-thru MAC addr\n");
1191		goto amacout;
1192	}
1193	ret = hex2bin(buf, obj->string.pointer + 9, 6);
1194	if (!(ret == 0 && is_valid_ether_addr(buf))) {
1195		netif_warn(tp, probe, tp->netdev,
1196			   "Invalid MAC for pass-thru MAC addr: %d, %pM\n",
1197			   ret, buf);
1198		ret = -EINVAL;
1199		goto amacout;
1200	}
1201	memcpy(sa->sa_data, buf, 6);
1202	ether_addr_copy(tp->netdev->dev_addr, sa->sa_data);
1203	netif_info(tp, probe, tp->netdev,
1204		   "Using pass-thru MAC addr %pM\n", sa->sa_data);
1205
1206amacout:
1207	kfree(obj);
1208	return ret;
1209}
1210
1211static int set_ethernet_addr(struct r8152 *tp)
1212{
1213	struct net_device *dev = tp->netdev;
1214	struct sockaddr sa;
1215	int ret;
1216
 
 
1217	if (tp->version == RTL_VER_01) {
1218		ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
1219	} else {
1220		/* if this is not an RTL8153-AD, no eFuse mac pass thru set,
1221		 * or system doesn't provide valid _SB.AMAC this will be
1222		 * be expected to non-zero
1223		 */
1224		ret = vendor_mac_passthru_addr_read(tp, &sa);
1225		if (ret < 0)
1226			ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
1227	}
1228
1229	if (ret < 0) {
1230		netif_err(tp, probe, dev, "Get ether addr fail\n");
1231	} else if (!is_valid_ether_addr(sa.sa_data)) {
1232		netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
1233			  sa.sa_data);
1234		eth_hw_addr_random(dev);
1235		ether_addr_copy(sa.sa_data, dev->dev_addr);
1236		ret = rtl8152_set_mac_address(dev, &sa);
1237		netif_info(tp, probe, dev, "Random ether addr %pM\n",
1238			   sa.sa_data);
1239	} else {
1240		if (tp->version == RTL_VER_01)
1241			ether_addr_copy(dev->dev_addr, sa.sa_data);
1242		else
1243			ret = rtl8152_set_mac_address(dev, &sa);
1244	}
1245
1246	return ret;
1247}
1248
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1249static void read_bulk_callback(struct urb *urb)
1250{
1251	struct net_device *netdev;
1252	int status = urb->status;
1253	struct rx_agg *agg;
1254	struct r8152 *tp;
 
1255
1256	agg = urb->context;
1257	if (!agg)
1258		return;
1259
1260	tp = agg->context;
1261	if (!tp)
1262		return;
1263
1264	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1265		return;
1266
1267	if (!test_bit(WORK_ENABLE, &tp->flags))
1268		return;
1269
1270	netdev = tp->netdev;
1271
1272	/* When link down, the driver would cancel all bulks. */
1273	/* This avoid the re-submitting bulk */
1274	if (!netif_carrier_ok(netdev))
1275		return;
1276
1277	usb_mark_last_busy(tp->udev);
1278
1279	switch (status) {
1280	case 0:
1281		if (urb->actual_length < ETH_ZLEN)
1282			break;
1283
1284		spin_lock(&tp->rx_lock);
1285		list_add_tail(&agg->list, &tp->rx_done);
1286		spin_unlock(&tp->rx_lock);
1287		napi_schedule(&tp->napi);
1288		return;
1289	case -ESHUTDOWN:
1290		set_bit(RTL8152_UNPLUG, &tp->flags);
1291		netif_device_detach(tp->netdev);
1292		return;
1293	case -ENOENT:
1294		return;	/* the urb is in unlink state */
1295	case -ETIME:
1296		if (net_ratelimit())
1297			netdev_warn(netdev, "maybe reset is needed?\n");
1298		break;
1299	default:
1300		if (net_ratelimit())
1301			netdev_warn(netdev, "Rx status %d\n", status);
1302		break;
1303	}
1304
1305	r8152_submit_rx(tp, agg, GFP_ATOMIC);
1306}
1307
1308static void write_bulk_callback(struct urb *urb)
1309{
1310	struct net_device_stats *stats;
1311	struct net_device *netdev;
1312	struct tx_agg *agg;
1313	struct r8152 *tp;
 
1314	int status = urb->status;
1315
1316	agg = urb->context;
1317	if (!agg)
1318		return;
1319
1320	tp = agg->context;
1321	if (!tp)
1322		return;
1323
1324	netdev = tp->netdev;
1325	stats = &netdev->stats;
1326	if (status) {
1327		if (net_ratelimit())
1328			netdev_warn(netdev, "Tx status %d\n", status);
1329		stats->tx_errors += agg->skb_num;
1330	} else {
1331		stats->tx_packets += agg->skb_num;
1332		stats->tx_bytes += agg->skb_len;
1333	}
1334
1335	spin_lock(&tp->tx_lock);
1336	list_add_tail(&agg->list, &tp->tx_free);
1337	spin_unlock(&tp->tx_lock);
1338
1339	usb_autopm_put_interface_async(tp->intf);
1340
1341	if (!netif_carrier_ok(netdev))
1342		return;
1343
1344	if (!test_bit(WORK_ENABLE, &tp->flags))
1345		return;
1346
1347	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1348		return;
1349
1350	if (!skb_queue_empty(&tp->tx_queue))
1351		napi_schedule(&tp->napi);
1352}
1353
1354static void intr_callback(struct urb *urb)
1355{
1356	struct r8152 *tp;
1357	__le16 *d;
1358	int status = urb->status;
1359	int res;
1360
1361	tp = urb->context;
1362	if (!tp)
1363		return;
1364
1365	if (!test_bit(WORK_ENABLE, &tp->flags))
1366		return;
1367
1368	if (test_bit(RTL8152_UNPLUG, &tp->flags))
1369		return;
1370
1371	switch (status) {
1372	case 0:			/* success */
1373		break;
1374	case -ECONNRESET:	/* unlink */
1375	case -ESHUTDOWN:
1376		netif_device_detach(tp->netdev);
 
1377	case -ENOENT:
1378	case -EPROTO:
1379		netif_info(tp, intr, tp->netdev,
1380			   "Stop submitting intr, status %d\n", status);
1381		return;
1382	case -EOVERFLOW:
1383		netif_info(tp, intr, tp->netdev, "intr status -EOVERFLOW\n");
1384		goto resubmit;
1385	/* -EPIPE:  should clear the halt */
1386	default:
1387		netif_info(tp, intr, tp->netdev, "intr status %d\n", status);
1388		goto resubmit;
1389	}
1390
1391	d = urb->transfer_buffer;
1392	if (INTR_LINK & __le16_to_cpu(d[0])) {
1393		if (!netif_carrier_ok(tp->netdev)) {
1394			set_bit(RTL8152_LINK_CHG, &tp->flags);
1395			schedule_delayed_work(&tp->schedule, 0);
1396		}
1397	} else {
1398		if (netif_carrier_ok(tp->netdev)) {
1399			netif_stop_queue(tp->netdev);
1400			set_bit(RTL8152_LINK_CHG, &tp->flags);
1401			schedule_delayed_work(&tp->schedule, 0);
1402		}
1403	}
1404
1405resubmit:
1406	res = usb_submit_urb(urb, GFP_ATOMIC);
1407	if (res == -ENODEV) {
1408		set_bit(RTL8152_UNPLUG, &tp->flags);
1409		netif_device_detach(tp->netdev);
1410	} else if (res) {
1411		netif_err(tp, intr, tp->netdev,
1412			  "can't resubmit intr, status %d\n", res);
1413	}
1414}
1415
1416static inline void *rx_agg_align(void *data)
1417{
1418	return (void *)ALIGN((uintptr_t)data, RX_ALIGN);
1419}
1420
1421static inline void *tx_agg_align(void *data)
1422{
1423	return (void *)ALIGN((uintptr_t)data, TX_ALIGN);
1424}
1425
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1426static void free_all_mem(struct r8152 *tp)
1427{
 
 
1428	int i;
1429
1430	for (i = 0; i < RTL8152_MAX_RX; i++) {
1431		usb_free_urb(tp->rx_info[i].urb);
1432		tp->rx_info[i].urb = NULL;
1433
1434		kfree(tp->rx_info[i].buffer);
1435		tp->rx_info[i].buffer = NULL;
1436		tp->rx_info[i].head = NULL;
1437	}
 
 
1438
1439	for (i = 0; i < RTL8152_MAX_TX; i++) {
1440		usb_free_urb(tp->tx_info[i].urb);
1441		tp->tx_info[i].urb = NULL;
1442
1443		kfree(tp->tx_info[i].buffer);
1444		tp->tx_info[i].buffer = NULL;
1445		tp->tx_info[i].head = NULL;
1446	}
1447
1448	usb_free_urb(tp->intr_urb);
1449	tp->intr_urb = NULL;
1450
1451	kfree(tp->intr_buff);
1452	tp->intr_buff = NULL;
1453}
1454
1455static int alloc_all_mem(struct r8152 *tp)
1456{
1457	struct net_device *netdev = tp->netdev;
1458	struct usb_interface *intf = tp->intf;
1459	struct usb_host_interface *alt = intf->cur_altsetting;
1460	struct usb_host_endpoint *ep_intr = alt->endpoint + 2;
1461	struct urb *urb;
1462	int node, i;
1463	u8 *buf;
1464
1465	node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1;
1466
1467	spin_lock_init(&tp->rx_lock);
1468	spin_lock_init(&tp->tx_lock);
 
1469	INIT_LIST_HEAD(&tp->tx_free);
1470	INIT_LIST_HEAD(&tp->rx_done);
1471	skb_queue_head_init(&tp->tx_queue);
1472	skb_queue_head_init(&tp->rx_queue);
 
1473
1474	for (i = 0; i < RTL8152_MAX_RX; i++) {
1475		buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1476		if (!buf)
1477			goto err1;
1478
1479		if (buf != rx_agg_align(buf)) {
1480			kfree(buf);
1481			buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
1482					   node);
1483			if (!buf)
1484				goto err1;
1485		}
1486
1487		urb = usb_alloc_urb(0, GFP_KERNEL);
1488		if (!urb) {
1489			kfree(buf);
1490			goto err1;
1491		}
1492
1493		INIT_LIST_HEAD(&tp->rx_info[i].list);
1494		tp->rx_info[i].context = tp;
1495		tp->rx_info[i].urb = urb;
1496		tp->rx_info[i].buffer = buf;
1497		tp->rx_info[i].head = rx_agg_align(buf);
1498	}
1499
1500	for (i = 0; i < RTL8152_MAX_TX; i++) {
 
 
 
1501		buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
1502		if (!buf)
1503			goto err1;
1504
1505		if (buf != tx_agg_align(buf)) {
1506			kfree(buf);
1507			buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
1508					   node);
1509			if (!buf)
1510				goto err1;
1511		}
1512
1513		urb = usb_alloc_urb(0, GFP_KERNEL);
1514		if (!urb) {
1515			kfree(buf);
1516			goto err1;
1517		}
1518
1519		INIT_LIST_HEAD(&tp->tx_info[i].list);
1520		tp->tx_info[i].context = tp;
1521		tp->tx_info[i].urb = urb;
1522		tp->tx_info[i].buffer = buf;
1523		tp->tx_info[i].head = tx_agg_align(buf);
1524
1525		list_add_tail(&tp->tx_info[i].list, &tp->tx_free);
1526	}
1527
1528	tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL);
1529	if (!tp->intr_urb)
1530		goto err1;
1531
1532	tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL);
1533	if (!tp->intr_buff)
1534		goto err1;
1535
1536	tp->intr_interval = (int)ep_intr->desc.bInterval;
1537	usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
1538			 tp->intr_buff, INTBUFSIZE, intr_callback,
1539			 tp, tp->intr_interval);
1540
1541	return 0;
1542
1543err1:
1544	free_all_mem(tp);
1545	return -ENOMEM;
1546}
1547
1548static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp)
1549{
1550	struct tx_agg *agg = NULL;
1551	unsigned long flags;
1552
1553	if (list_empty(&tp->tx_free))
1554		return NULL;
1555
1556	spin_lock_irqsave(&tp->tx_lock, flags);
1557	if (!list_empty(&tp->tx_free)) {
1558		struct list_head *cursor;
1559
1560		cursor = tp->tx_free.next;
1561		list_del_init(cursor);
1562		agg = list_entry(cursor, struct tx_agg, list);
1563	}
1564	spin_unlock_irqrestore(&tp->tx_lock, flags);
1565
1566	return agg;
1567}
1568
1569/* r8152_csum_workaround()
1570 * The hw limites the value the transport offset. When the offset is out of the
1571 * range, calculate the checksum by sw.
1572 */
1573static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb,
1574				  struct sk_buff_head *list)
1575{
1576	if (skb_shinfo(skb)->gso_size) {
1577		netdev_features_t features = tp->netdev->features;
1578		struct sk_buff_head seg_list;
1579		struct sk_buff *segs, *nskb;
1580
1581		features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
1582		segs = skb_gso_segment(skb, features);
1583		if (IS_ERR(segs) || !segs)
1584			goto drop;
1585
1586		__skb_queue_head_init(&seg_list);
1587
1588		do {
1589			nskb = segs;
1590			segs = segs->next;
1591			nskb->next = NULL;
1592			__skb_queue_tail(&seg_list, nskb);
1593		} while (segs);
1594
1595		skb_queue_splice(&seg_list, list);
1596		dev_kfree_skb(skb);
1597	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1598		if (skb_checksum_help(skb) < 0)
1599			goto drop;
1600
1601		__skb_queue_head(list, skb);
1602	} else {
1603		struct net_device_stats *stats;
1604
1605drop:
1606		stats = &tp->netdev->stats;
1607		stats->tx_dropped++;
1608		dev_kfree_skb(skb);
1609	}
1610}
1611
1612/* msdn_giant_send_check()
1613 * According to the document of microsoft, the TCP Pseudo Header excludes the
1614 * packet length for IPv6 TCP large packets.
1615 */
1616static int msdn_giant_send_check(struct sk_buff *skb)
1617{
1618	const struct ipv6hdr *ipv6h;
1619	struct tcphdr *th;
1620	int ret;
1621
1622	ret = skb_cow_head(skb, 0);
1623	if (ret)
1624		return ret;
1625
1626	ipv6h = ipv6_hdr(skb);
1627	th = tcp_hdr(skb);
1628
1629	th->check = 0;
1630	th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
1631
1632	return ret;
1633}
1634
1635static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb)
1636{
1637	if (skb_vlan_tag_present(skb)) {
1638		u32 opts2;
1639
1640		opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb));
1641		desc->opts2 |= cpu_to_le32(opts2);
1642	}
1643}
1644
1645static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb)
1646{
1647	u32 opts2 = le32_to_cpu(desc->opts2);
1648
1649	if (opts2 & RX_VLAN_TAG)
1650		__vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
1651				       swab16(opts2 & 0xffff));
1652}
1653
1654static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc,
1655			 struct sk_buff *skb, u32 len, u32 transport_offset)
1656{
1657	u32 mss = skb_shinfo(skb)->gso_size;
1658	u32 opts1, opts2 = 0;
1659	int ret = TX_CSUM_SUCCESS;
1660
1661	WARN_ON_ONCE(len > TX_LEN_MAX);
1662
1663	opts1 = len | TX_FS | TX_LS;
1664
1665	if (mss) {
1666		if (transport_offset > GTTCPHO_MAX) {
1667			netif_warn(tp, tx_err, tp->netdev,
1668				   "Invalid transport offset 0x%x for TSO\n",
1669				   transport_offset);
1670			ret = TX_CSUM_TSO;
1671			goto unavailable;
1672		}
1673
1674		switch (vlan_get_protocol(skb)) {
1675		case htons(ETH_P_IP):
1676			opts1 |= GTSENDV4;
1677			break;
1678
1679		case htons(ETH_P_IPV6):
1680			if (msdn_giant_send_check(skb)) {
1681				ret = TX_CSUM_TSO;
1682				goto unavailable;
1683			}
1684			opts1 |= GTSENDV6;
1685			break;
1686
1687		default:
1688			WARN_ON_ONCE(1);
1689			break;
1690		}
1691
1692		opts1 |= transport_offset << GTTCPHO_SHIFT;
1693		opts2 |= min(mss, MSS_MAX) << MSS_SHIFT;
1694	} else if (skb->ip_summed == CHECKSUM_PARTIAL) {
1695		u8 ip_protocol;
1696
1697		if (transport_offset > TCPHO_MAX) {
1698			netif_warn(tp, tx_err, tp->netdev,
1699				   "Invalid transport offset 0x%x\n",
1700				   transport_offset);
1701			ret = TX_CSUM_NONE;
1702			goto unavailable;
1703		}
1704
1705		switch (vlan_get_protocol(skb)) {
1706		case htons(ETH_P_IP):
1707			opts2 |= IPV4_CS;
1708			ip_protocol = ip_hdr(skb)->protocol;
1709			break;
1710
1711		case htons(ETH_P_IPV6):
1712			opts2 |= IPV6_CS;
1713			ip_protocol = ipv6_hdr(skb)->nexthdr;
1714			break;
1715
1716		default:
1717			ip_protocol = IPPROTO_RAW;
1718			break;
1719		}
1720
1721		if (ip_protocol == IPPROTO_TCP)
1722			opts2 |= TCP_CS;
1723		else if (ip_protocol == IPPROTO_UDP)
1724			opts2 |= UDP_CS;
1725		else
1726			WARN_ON_ONCE(1);
1727
1728		opts2 |= transport_offset << TCPHO_SHIFT;
1729	}
1730
1731	desc->opts2 = cpu_to_le32(opts2);
1732	desc->opts1 = cpu_to_le32(opts1);
1733
1734unavailable:
1735	return ret;
1736}
1737
1738static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
1739{
1740	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
1741	int remain, ret;
1742	u8 *tx_data;
1743
1744	__skb_queue_head_init(&skb_head);
1745	spin_lock(&tx_queue->lock);
1746	skb_queue_splice_init(tx_queue, &skb_head);
1747	spin_unlock(&tx_queue->lock);
1748
1749	tx_data = agg->head;
1750	agg->skb_num = 0;
1751	agg->skb_len = 0;
1752	remain = agg_buf_sz;
1753
1754	while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
1755		struct tx_desc *tx_desc;
1756		struct sk_buff *skb;
1757		unsigned int len;
1758		u32 offset;
1759
1760		skb = __skb_dequeue(&skb_head);
1761		if (!skb)
1762			break;
1763
1764		len = skb->len + sizeof(*tx_desc);
1765
1766		if (len > remain) {
1767			__skb_queue_head(&skb_head, skb);
1768			break;
1769		}
1770
1771		tx_data = tx_agg_align(tx_data);
1772		tx_desc = (struct tx_desc *)tx_data;
1773
1774		offset = (u32)skb_transport_offset(skb);
1775
1776		if (r8152_tx_csum(tp, tx_desc, skb, skb->len, offset)) {
1777			r8152_csum_workaround(tp, skb, &skb_head);
1778			continue;
1779		}
1780
1781		rtl_tx_vlan_tag(tx_desc, skb);
1782
1783		tx_data += sizeof(*tx_desc);
1784
1785		len = skb->len;
1786		if (skb_copy_bits(skb, 0, tx_data, len) < 0) {
1787			struct net_device_stats *stats = &tp->netdev->stats;
1788
1789			stats->tx_dropped++;
1790			dev_kfree_skb_any(skb);
1791			tx_data -= sizeof(*tx_desc);
1792			continue;
1793		}
1794
1795		tx_data += len;
1796		agg->skb_len += len;
1797		agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1;
1798
1799		dev_kfree_skb_any(skb);
1800
1801		remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
1802
1803		if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
1804			break;
1805	}
1806
1807	if (!skb_queue_empty(&skb_head)) {
1808		spin_lock(&tx_queue->lock);
1809		skb_queue_splice(&skb_head, tx_queue);
1810		spin_unlock(&tx_queue->lock);
1811	}
1812
1813	netif_tx_lock(tp->netdev);
1814
1815	if (netif_queue_stopped(tp->netdev) &&
1816	    skb_queue_len(&tp->tx_queue) < tp->tx_qlen)
1817		netif_wake_queue(tp->netdev);
1818
1819	netif_tx_unlock(tp->netdev);
1820
1821	ret = usb_autopm_get_interface_async(tp->intf);
1822	if (ret < 0)
1823		goto out_tx_fill;
1824
1825	usb_fill_bulk_urb(agg->urb, tp->udev, usb_sndbulkpipe(tp->udev, 2),
1826			  agg->head, (int)(tx_data - (u8 *)agg->head),
1827			  (usb_complete_t)write_bulk_callback, agg);
1828
1829	ret = usb_submit_urb(agg->urb, GFP_ATOMIC);
1830	if (ret < 0)
1831		usb_autopm_put_interface_async(tp->intf);
1832
1833out_tx_fill:
1834	return ret;
1835}
1836
1837static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc)
1838{
1839	u8 checksum = CHECKSUM_NONE;
1840	u32 opts2, opts3;
1841
1842	if (!(tp->netdev->features & NETIF_F_RXCSUM))
1843		goto return_result;
1844
1845	opts2 = le32_to_cpu(rx_desc->opts2);
1846	opts3 = le32_to_cpu(rx_desc->opts3);
1847
1848	if (opts2 & RD_IPV4_CS) {
1849		if (opts3 & IPF)
1850			checksum = CHECKSUM_NONE;
1851		else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1852			checksum = CHECKSUM_UNNECESSARY;
1853		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1854			checksum = CHECKSUM_UNNECESSARY;
1855	} else if (opts2 & RD_IPV6_CS) {
1856		if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF))
1857			checksum = CHECKSUM_UNNECESSARY;
1858		else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF))
1859			checksum = CHECKSUM_UNNECESSARY;
1860	}
1861
1862return_result:
1863	return checksum;
1864}
1865
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1866static int rx_bottom(struct r8152 *tp, int budget)
1867{
1868	unsigned long flags;
1869	struct list_head *cursor, *next, rx_queue;
1870	int ret = 0, work_done = 0;
1871	struct napi_struct *napi = &tp->napi;
1872
1873	if (!skb_queue_empty(&tp->rx_queue)) {
1874		while (work_done < budget) {
1875			struct sk_buff *skb = __skb_dequeue(&tp->rx_queue);
1876			struct net_device *netdev = tp->netdev;
1877			struct net_device_stats *stats = &netdev->stats;
1878			unsigned int pkt_len;
1879
1880			if (!skb)
1881				break;
1882
1883			pkt_len = skb->len;
1884			napi_gro_receive(napi, skb);
1885			work_done++;
1886			stats->rx_packets++;
1887			stats->rx_bytes += pkt_len;
1888		}
1889	}
1890
1891	if (list_empty(&tp->rx_done))
1892		goto out1;
1893
1894	INIT_LIST_HEAD(&rx_queue);
1895	spin_lock_irqsave(&tp->rx_lock, flags);
1896	list_splice_init(&tp->rx_done, &rx_queue);
1897	spin_unlock_irqrestore(&tp->rx_lock, flags);
1898
1899	list_for_each_safe(cursor, next, &rx_queue) {
1900		struct rx_desc *rx_desc;
1901		struct rx_agg *agg;
1902		int len_used = 0;
1903		struct urb *urb;
1904		u8 *rx_data;
1905
1906		list_del_init(cursor);
1907
1908		agg = list_entry(cursor, struct rx_agg, list);
1909		urb = agg->urb;
1910		if (urb->actual_length < ETH_ZLEN)
1911			goto submit;
1912
1913		rx_desc = agg->head;
1914		rx_data = agg->head;
 
 
1915		len_used += sizeof(struct rx_desc);
1916
1917		while (urb->actual_length > len_used) {
1918			struct net_device *netdev = tp->netdev;
1919			struct net_device_stats *stats = &netdev->stats;
1920			unsigned int pkt_len;
1921			struct sk_buff *skb;
1922
1923			/* limite the skb numbers for rx_queue */
1924			if (unlikely(skb_queue_len(&tp->rx_queue) >= 1000))
1925				break;
1926
1927			pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK;
1928			if (pkt_len < ETH_ZLEN)
1929				break;
1930
1931			len_used += pkt_len;
1932			if (urb->actual_length < len_used)
1933				break;
1934
1935			pkt_len -= ETH_FCS_LEN;
1936			rx_data += sizeof(struct rx_desc);
1937
1938			skb = napi_alloc_skb(napi, pkt_len);
 
 
 
 
 
1939			if (!skb) {
1940				stats->rx_dropped++;
1941				goto find_next_rx;
1942			}
1943
1944			skb->ip_summed = r8152_rx_csum(tp, rx_desc);
1945			memcpy(skb->data, rx_data, pkt_len);
1946			skb_put(skb, pkt_len);
 
 
 
 
 
 
 
 
 
 
1947			skb->protocol = eth_type_trans(skb, netdev);
1948			rtl_rx_vlan_tag(rx_desc, skb);
1949			if (work_done < budget) {
1950				napi_gro_receive(napi, skb);
1951				work_done++;
1952				stats->rx_packets++;
1953				stats->rx_bytes += pkt_len;
 
1954			} else {
1955				__skb_queue_tail(&tp->rx_queue, skb);
1956			}
1957
1958find_next_rx:
1959			rx_data = rx_agg_align(rx_data + pkt_len + ETH_FCS_LEN);
1960			rx_desc = (struct rx_desc *)rx_data;
1961			len_used = (int)(rx_data - (u8 *)agg->head);
1962			len_used += sizeof(struct rx_desc);
1963		}
1964
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1965submit:
1966		if (!ret) {
1967			ret = r8152_submit_rx(tp, agg, GFP_ATOMIC);
1968		} else {
1969			urb->actual_length = 0;
1970			list_add_tail(&agg->list, next);
1971		}
1972	}
1973
1974	if (!list_empty(&rx_queue)) {
1975		spin_lock_irqsave(&tp->rx_lock, flags);
1976		list_splice_tail(&rx_queue, &tp->rx_done);
1977		spin_unlock_irqrestore(&tp->rx_lock, flags);
1978	}
1979
1980out1:
1981	return work_done;
1982}
1983
1984static void tx_bottom(struct r8152 *tp)
1985{
1986	int res;
1987
1988	do {
1989		struct tx_agg *agg;
1990
1991		if (skb_queue_empty(&tp->tx_queue))
1992			break;
1993
1994		agg = r8152_get_tx_agg(tp);
1995		if (!agg)
1996			break;
1997
1998		res = r8152_tx_agg_fill(tp, agg);
1999		if (res) {
2000			struct net_device *netdev = tp->netdev;
2001
2002			if (res == -ENODEV) {
2003				set_bit(RTL8152_UNPLUG, &tp->flags);
2004				netif_device_detach(netdev);
2005			} else {
2006				struct net_device_stats *stats = &netdev->stats;
2007				unsigned long flags;
2008
2009				netif_warn(tp, tx_err, netdev,
2010					   "failed tx_urb %d\n", res);
2011				stats->tx_dropped += agg->skb_num;
2012
2013				spin_lock_irqsave(&tp->tx_lock, flags);
2014				list_add_tail(&agg->list, &tp->tx_free);
2015				spin_unlock_irqrestore(&tp->tx_lock, flags);
2016			}
2017		}
2018	} while (res == 0);
2019}
2020
2021static void bottom_half(struct r8152 *tp)
2022{
 
 
 
 
2023	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2024		return;
2025
2026	if (!test_bit(WORK_ENABLE, &tp->flags))
2027		return;
2028
2029	/* When link down, the driver would cancel all bulks. */
2030	/* This avoid the re-submitting bulk */
2031	if (!netif_carrier_ok(tp->netdev))
2032		return;
2033
2034	clear_bit(SCHEDULE_NAPI, &tp->flags);
2035
2036	tx_bottom(tp);
2037}
2038
2039static int r8152_poll(struct napi_struct *napi, int budget)
2040{
2041	struct r8152 *tp = container_of(napi, struct r8152, napi);
2042	int work_done;
2043
2044	work_done = rx_bottom(tp, budget);
2045	bottom_half(tp);
2046
2047	if (work_done < budget) {
2048		if (!napi_complete_done(napi, work_done))
2049			goto out;
2050		if (!list_empty(&tp->rx_done))
2051			napi_schedule(napi);
2052		else if (!skb_queue_empty(&tp->tx_queue) &&
2053			 !list_empty(&tp->tx_free))
2054			napi_schedule(napi);
2055	}
2056
2057out:
2058	return work_done;
2059}
2060
2061static
2062int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
2063{
2064	int ret;
2065
2066	/* The rx would be stopped, so skip submitting */
2067	if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
2068	    !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
2069		return 0;
2070
2071	usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
2072			  agg->head, agg_buf_sz,
2073			  (usb_complete_t)read_bulk_callback, agg);
2074
2075	ret = usb_submit_urb(agg->urb, mem_flags);
2076	if (ret == -ENODEV) {
2077		set_bit(RTL8152_UNPLUG, &tp->flags);
2078		netif_device_detach(tp->netdev);
2079	} else if (ret) {
2080		struct urb *urb = agg->urb;
2081		unsigned long flags;
2082
2083		urb->actual_length = 0;
2084		spin_lock_irqsave(&tp->rx_lock, flags);
2085		list_add_tail(&agg->list, &tp->rx_done);
2086		spin_unlock_irqrestore(&tp->rx_lock, flags);
2087
2088		netif_err(tp, rx_err, tp->netdev,
2089			  "Couldn't submit rx[%p], ret = %d\n", agg, ret);
2090
2091		napi_schedule(&tp->napi);
2092	}
2093
2094	return ret;
2095}
2096
2097static void rtl_drop_queued_tx(struct r8152 *tp)
2098{
2099	struct net_device_stats *stats = &tp->netdev->stats;
2100	struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue;
2101	struct sk_buff *skb;
2102
2103	if (skb_queue_empty(tx_queue))
2104		return;
2105
2106	__skb_queue_head_init(&skb_head);
2107	spin_lock_bh(&tx_queue->lock);
2108	skb_queue_splice_init(tx_queue, &skb_head);
2109	spin_unlock_bh(&tx_queue->lock);
2110
2111	while ((skb = __skb_dequeue(&skb_head))) {
2112		dev_kfree_skb(skb);
2113		stats->tx_dropped++;
2114	}
2115}
2116
2117static void rtl8152_tx_timeout(struct net_device *netdev)
2118{
2119	struct r8152 *tp = netdev_priv(netdev);
2120
2121	netif_warn(tp, tx_err, netdev, "Tx timeout\n");
2122
2123	usb_queue_reset_device(tp->intf);
2124}
2125
2126static void rtl8152_set_rx_mode(struct net_device *netdev)
2127{
2128	struct r8152 *tp = netdev_priv(netdev);
2129
2130	if (netif_carrier_ok(netdev)) {
2131		set_bit(RTL8152_SET_RX_MODE, &tp->flags);
2132		schedule_delayed_work(&tp->schedule, 0);
2133	}
2134}
2135
2136static void _rtl8152_set_rx_mode(struct net_device *netdev)
2137{
2138	struct r8152 *tp = netdev_priv(netdev);
2139	u32 mc_filter[2];	/* Multicast hash filter */
2140	__le32 tmp[2];
2141	u32 ocp_data;
2142
2143	netif_stop_queue(netdev);
2144	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2145	ocp_data &= ~RCR_ACPT_ALL;
2146	ocp_data |= RCR_AB | RCR_APM;
2147
2148	if (netdev->flags & IFF_PROMISC) {
2149		/* Unconditionally log net taps. */
2150		netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
2151		ocp_data |= RCR_AM | RCR_AAP;
2152		mc_filter[1] = 0xffffffff;
2153		mc_filter[0] = 0xffffffff;
2154	} else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
2155		   (netdev->flags & IFF_ALLMULTI)) {
2156		/* Too many to filter perfectly -- accept all multicasts. */
2157		ocp_data |= RCR_AM;
2158		mc_filter[1] = 0xffffffff;
2159		mc_filter[0] = 0xffffffff;
2160	} else {
2161		struct netdev_hw_addr *ha;
2162
2163		mc_filter[1] = 0;
2164		mc_filter[0] = 0;
2165		netdev_for_each_mc_addr(ha, netdev) {
2166			int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
2167
2168			mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
2169			ocp_data |= RCR_AM;
2170		}
2171	}
2172
2173	tmp[0] = __cpu_to_le32(swab32(mc_filter[1]));
2174	tmp[1] = __cpu_to_le32(swab32(mc_filter[0]));
2175
2176	pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp);
2177	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2178	netif_wake_queue(netdev);
2179}
2180
2181static netdev_features_t
2182rtl8152_features_check(struct sk_buff *skb, struct net_device *dev,
2183		       netdev_features_t features)
2184{
2185	u32 mss = skb_shinfo(skb)->gso_size;
2186	int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX;
2187	int offset = skb_transport_offset(skb);
2188
2189	if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && offset > max_offset)
2190		features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
2191	else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz)
2192		features &= ~NETIF_F_GSO_MASK;
2193
2194	return features;
2195}
2196
2197static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
2198				      struct net_device *netdev)
2199{
2200	struct r8152 *tp = netdev_priv(netdev);
2201
2202	skb_tx_timestamp(skb);
2203
2204	skb_queue_tail(&tp->tx_queue, skb);
2205
2206	if (!list_empty(&tp->tx_free)) {
2207		if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) {
2208			set_bit(SCHEDULE_NAPI, &tp->flags);
2209			schedule_delayed_work(&tp->schedule, 0);
2210		} else {
2211			usb_mark_last_busy(tp->udev);
2212			napi_schedule(&tp->napi);
2213		}
2214	} else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
2215		netif_stop_queue(netdev);
2216	}
2217
2218	return NETDEV_TX_OK;
2219}
2220
2221static void r8152b_reset_packet_filter(struct r8152 *tp)
2222{
2223	u32	ocp_data;
2224
2225	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
2226	ocp_data &= ~FMC_FCR_MCU_EN;
2227	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2228	ocp_data |= FMC_FCR_MCU_EN;
2229	ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data);
2230}
2231
2232static void rtl8152_nic_reset(struct r8152 *tp)
2233{
2234	int	i;
2235
2236	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
2237
2238	for (i = 0; i < 1000; i++) {
2239		if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
2240			break;
2241		usleep_range(100, 400);
2242	}
2243}
2244
2245static void set_tx_qlen(struct r8152 *tp)
2246{
2247	struct net_device *netdev = tp->netdev;
2248
2249	tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN +
2250				    sizeof(struct tx_desc));
2251}
2252
2253static inline u8 rtl8152_get_speed(struct r8152 *tp)
2254{
2255	return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
2256}
2257
2258static void rtl_set_eee_plus(struct r8152 *tp)
2259{
2260	u32 ocp_data;
2261	u8 speed;
2262
2263	speed = rtl8152_get_speed(tp);
2264	if (speed & _10bps) {
2265		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2266		ocp_data |= EEEP_CR_EEEP_TX;
2267		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2268	} else {
2269		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR);
2270		ocp_data &= ~EEEP_CR_EEEP_TX;
2271		ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data);
2272	}
2273}
2274
2275static void rxdy_gated_en(struct r8152 *tp, bool enable)
2276{
2277	u32 ocp_data;
2278
2279	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1);
2280	if (enable)
2281		ocp_data |= RXDY_GATED_EN;
2282	else
2283		ocp_data &= ~RXDY_GATED_EN;
2284	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data);
2285}
2286
2287static int rtl_start_rx(struct r8152 *tp)
2288{
2289	int i, ret = 0;
 
 
 
2290
2291	INIT_LIST_HEAD(&tp->rx_done);
2292	for (i = 0; i < RTL8152_MAX_RX; i++) {
2293		INIT_LIST_HEAD(&tp->rx_info[i].list);
2294		ret = r8152_submit_rx(tp, &tp->rx_info[i], GFP_KERNEL);
2295		if (ret)
2296			break;
2297	}
2298
2299	if (ret && ++i < RTL8152_MAX_RX) {
2300		struct list_head rx_queue;
2301		unsigned long flags;
2302
2303		INIT_LIST_HEAD(&rx_queue);
 
2304
2305		do {
2306			struct rx_agg *agg = &tp->rx_info[i++];
2307			struct urb *urb = agg->urb;
2308
2309			urb->actual_length = 0;
2310			list_add_tail(&agg->list, &rx_queue);
2311		} while (i < RTL8152_MAX_RX);
2312
2313		spin_lock_irqsave(&tp->rx_lock, flags);
2314		list_splice_tail(&rx_queue, &tp->rx_done);
2315		spin_unlock_irqrestore(&tp->rx_lock, flags);
 
 
 
 
 
 
 
 
 
 
 
 
2316	}
2317
 
 
 
 
 
2318	return ret;
2319}
2320
2321static int rtl_stop_rx(struct r8152 *tp)
2322{
2323	int i;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2324
2325	for (i = 0; i < RTL8152_MAX_RX; i++)
2326		usb_kill_urb(tp->rx_info[i].urb);
 
 
 
 
 
 
 
 
 
 
 
 
 
2327
2328	while (!skb_queue_empty(&tp->rx_queue))
2329		dev_kfree_skb(__skb_dequeue(&tp->rx_queue));
2330
2331	return 0;
2332}
2333
 
 
 
 
 
 
2334static int rtl_enable(struct r8152 *tp)
2335{
2336	u32 ocp_data;
2337
2338	r8152b_reset_packet_filter(tp);
2339
2340	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
2341	ocp_data |= CR_RE | CR_TE;
2342	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
2343
 
 
 
 
 
 
 
 
 
2344	rxdy_gated_en(tp, false);
2345
2346	return 0;
2347}
2348
2349static int rtl8152_enable(struct r8152 *tp)
2350{
2351	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2352		return -ENODEV;
2353
2354	set_tx_qlen(tp);
2355	rtl_set_eee_plus(tp);
2356
2357	return rtl_enable(tp);
2358}
2359
2360static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp)
2361{
2362	ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN,
2363		       OWN_UPDATE | OWN_CLEAR);
2364}
2365
2366static void r8153_set_rx_early_timeout(struct r8152 *tp)
2367{
2368	u32 ocp_data = tp->coalesce / 8;
2369
2370	switch (tp->version) {
2371	case RTL_VER_03:
2372	case RTL_VER_04:
2373	case RTL_VER_05:
2374	case RTL_VER_06:
2375		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2376			       ocp_data);
2377		break;
2378
2379	case RTL_VER_08:
2380	case RTL_VER_09:
2381		/* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
2382		 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
2383		 */
2384		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
2385			       128 / 8);
2386		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
2387			       ocp_data);
2388		r8153b_rx_agg_chg_indicate(tp);
2389		break;
2390
2391	default:
2392		break;
2393	}
2394}
2395
2396static void r8153_set_rx_early_size(struct r8152 *tp)
2397{
2398	u32 ocp_data = agg_buf_sz - rx_reserved_size(tp->netdev->mtu);
2399
2400	switch (tp->version) {
2401	case RTL_VER_03:
2402	case RTL_VER_04:
2403	case RTL_VER_05:
2404	case RTL_VER_06:
2405		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2406			       ocp_data / 4);
2407		break;
2408	case RTL_VER_08:
2409	case RTL_VER_09:
2410		ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
2411			       ocp_data / 8);
2412		r8153b_rx_agg_chg_indicate(tp);
2413		break;
2414	default:
2415		WARN_ON_ONCE(1);
2416		break;
2417	}
2418}
2419
2420static int rtl8153_enable(struct r8152 *tp)
2421{
2422	if (test_bit(RTL8152_UNPLUG, &tp->flags))
2423		return -ENODEV;
2424
2425	set_tx_qlen(tp);
2426	rtl_set_eee_plus(tp);
2427	r8153_set_rx_early_timeout(tp);
2428	r8153_set_rx_early_size(tp);
2429
2430	return rtl_enable(tp);
2431}
2432
2433static void rtl_disable(struct r8152 *tp)
2434{
2435	u32 ocp_data;
2436	int i;
2437
2438	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
2439		rtl_drop_queued_tx(tp);
2440		return;
2441	}
2442
2443	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
2444	ocp_data &= ~RCR_ACPT_ALL;
2445	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2446
2447	rtl_drop_queued_tx(tp);
2448
2449	for (i = 0; i < RTL8152_MAX_TX; i++)
2450		usb_kill_urb(tp->tx_info[i].urb);
2451
2452	rxdy_gated_en(tp, true);
2453
2454	for (i = 0; i < 1000; i++) {
2455		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
2456		if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY)
2457			break;
2458		usleep_range(1000, 2000);
2459	}
2460
2461	for (i = 0; i < 1000; i++) {
2462		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY)
2463			break;
2464		usleep_range(1000, 2000);
2465	}
2466
2467	rtl_stop_rx(tp);
2468
2469	rtl8152_nic_reset(tp);
2470}
2471
2472static void r8152_power_cut_en(struct r8152 *tp, bool enable)
2473{
2474	u32 ocp_data;
2475
2476	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL);
2477	if (enable)
2478		ocp_data |= POWER_CUT;
2479	else
2480		ocp_data &= ~POWER_CUT;
2481	ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data);
2482
2483	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS);
2484	ocp_data &= ~RESUME_INDICATE;
2485	ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data);
2486}
2487
2488static void rtl_rx_vlan_en(struct r8152 *tp, bool enable)
2489{
2490	u32 ocp_data;
2491
2492	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2493	if (enable)
2494		ocp_data |= CPCR_RX_VLAN;
2495	else
2496		ocp_data &= ~CPCR_RX_VLAN;
2497	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2498}
2499
2500static int rtl8152_set_features(struct net_device *dev,
2501				netdev_features_t features)
2502{
2503	netdev_features_t changed = features ^ dev->features;
2504	struct r8152 *tp = netdev_priv(dev);
2505	int ret;
2506
2507	ret = usb_autopm_get_interface(tp->intf);
2508	if (ret < 0)
2509		goto out;
2510
2511	mutex_lock(&tp->control);
2512
2513	if (changed & NETIF_F_HW_VLAN_CTAG_RX) {
2514		if (features & NETIF_F_HW_VLAN_CTAG_RX)
2515			rtl_rx_vlan_en(tp, true);
2516		else
2517			rtl_rx_vlan_en(tp, false);
2518	}
2519
2520	mutex_unlock(&tp->control);
2521
2522	usb_autopm_put_interface(tp->intf);
2523
2524out:
2525	return ret;
2526}
2527
2528#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
2529
2530static u32 __rtl_get_wol(struct r8152 *tp)
2531{
2532	u32 ocp_data;
2533	u32 wolopts = 0;
2534
2535	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2536	if (ocp_data & LINK_ON_WAKE_EN)
2537		wolopts |= WAKE_PHY;
2538
2539	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2540	if (ocp_data & UWF_EN)
2541		wolopts |= WAKE_UCAST;
2542	if (ocp_data & BWF_EN)
2543		wolopts |= WAKE_BCAST;
2544	if (ocp_data & MWF_EN)
2545		wolopts |= WAKE_MCAST;
2546
2547	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2548	if (ocp_data & MAGIC_EN)
2549		wolopts |= WAKE_MAGIC;
2550
2551	return wolopts;
2552}
2553
2554static void __rtl_set_wol(struct r8152 *tp, u32 wolopts)
2555{
2556	u32 ocp_data;
2557
2558	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2559
2560	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2561	ocp_data &= ~LINK_ON_WAKE_EN;
2562	if (wolopts & WAKE_PHY)
2563		ocp_data |= LINK_ON_WAKE_EN;
2564	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2565
2566	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
2567	ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN);
2568	if (wolopts & WAKE_UCAST)
2569		ocp_data |= UWF_EN;
2570	if (wolopts & WAKE_BCAST)
2571		ocp_data |= BWF_EN;
2572	if (wolopts & WAKE_MCAST)
2573		ocp_data |= MWF_EN;
2574	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
2575
2576	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2577
2578	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL);
2579	ocp_data &= ~MAGIC_EN;
2580	if (wolopts & WAKE_MAGIC)
2581		ocp_data |= MAGIC_EN;
2582	ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data);
2583
2584	if (wolopts & WAKE_ANY)
2585		device_set_wakeup_enable(&tp->udev->dev, true);
2586	else
2587		device_set_wakeup_enable(&tp->udev->dev, false);
2588}
2589
2590static void r8153_mac_clk_spd(struct r8152 *tp, bool enable)
2591{
2592	/* MAC clock speed down */
2593	if (enable) {
2594		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
2595			       ALDPS_SPDWN_RATIO);
2596		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2,
2597			       EEE_SPDWN_RATIO);
2598		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3,
2599			       PKT_AVAIL_SPDWN_EN | SUSPEND_SPDWN_EN |
2600			       U1U2_SPDWN_EN | L1_SPDWN_EN);
2601		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4,
2602			       PWRSAVE_SPDWN_EN | RXDV_SPDWN_EN | TX10MIDLE_EN |
2603			       TP100_SPDWN_EN | TP500_SPDWN_EN | EEE_SPDWN_EN |
2604			       TP1000_SPDWN_EN);
2605	} else {
2606		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
2607		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
2608		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
2609		ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
2610	}
2611}
2612
2613static void r8153_u1u2en(struct r8152 *tp, bool enable)
2614{
2615	u8 u1u2[8];
2616
2617	if (enable)
2618		memset(u1u2, 0xff, sizeof(u1u2));
2619	else
2620		memset(u1u2, 0x00, sizeof(u1u2));
2621
2622	usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2);
2623}
2624
2625static void r8153b_u1u2en(struct r8152 *tp, bool enable)
2626{
2627	u32 ocp_data;
2628
2629	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG);
2630	if (enable)
2631		ocp_data |= LPM_U1U2_EN;
2632	else
2633		ocp_data &= ~LPM_U1U2_EN;
2634
2635	ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data);
2636}
2637
2638static void r8153_u2p3en(struct r8152 *tp, bool enable)
2639{
2640	u32 ocp_data;
2641
2642	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2643	if (enable)
2644		ocp_data |= U2P3_ENABLE;
2645	else
2646		ocp_data &= ~U2P3_ENABLE;
2647	ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2648}
2649
2650static void r8153b_ups_flags_w1w0(struct r8152 *tp, u32 set, u32 clear)
2651{
2652	u32 ocp_data;
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2653
2654	ocp_data = ocp_read_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS);
2655	ocp_data &= ~clear;
2656	ocp_data |= set;
2657	ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ocp_data);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2658}
2659
2660static void r8153b_green_en(struct r8152 *tp, bool enable)
2661{
2662	u16 data;
2663
2664	if (enable) {
2665		sram_write(tp, 0x8045, 0);	/* 10M abiq&ldvbias */
2666		sram_write(tp, 0x804d, 0x1222);	/* 100M short abiq&ldvbias */
2667		sram_write(tp, 0x805d, 0x0022);	/* 1000M short abiq&ldvbias */
2668	} else {
2669		sram_write(tp, 0x8045, 0x2444);	/* 10M abiq&ldvbias */
2670		sram_write(tp, 0x804d, 0x2444);	/* 100M short abiq&ldvbias */
2671		sram_write(tp, 0x805d, 0x2444);	/* 1000M short abiq&ldvbias */
2672	}
2673
2674	data = sram_read(tp, SRAM_GREEN_CFG);
2675	data |= GREEN_ETH_EN;
2676	sram_write(tp, SRAM_GREEN_CFG, data);
2677
2678	r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_GREEN, 0);
2679}
2680
2681static u16 r8153_phy_status(struct r8152 *tp, u16 desired)
2682{
2683	u16 data;
2684	int i;
2685
2686	for (i = 0; i < 500; i++) {
2687		data = ocp_reg_read(tp, OCP_PHY_STATUS);
2688		data &= PHY_STAT_MASK;
2689		if (desired) {
2690			if (data == desired)
2691				break;
2692		} else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN ||
2693			   data == PHY_STAT_EXT_INIT) {
2694			break;
2695		}
2696
2697		msleep(20);
2698	}
2699
2700	return data;
2701}
2702
2703static void r8153b_ups_en(struct r8152 *tp, bool enable)
2704{
2705	u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
2706
2707	if (enable) {
 
 
2708		ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
2709		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2710
2711		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2712		ocp_data |= BIT(0);
2713		ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2714	} else {
2715		u16 data;
2716
2717		ocp_data &= ~(UPS_EN | USP_PREWAKE);
2718		ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2719
2720		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
2721		ocp_data &= ~BIT(0);
2722		ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
2723
2724		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2725		ocp_data &= ~PCUT_STATUS;
2726		ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2727
2728		data = r8153_phy_status(tp, 0);
2729
2730		switch (data) {
2731		case PHY_STAT_PWRDN:
2732		case PHY_STAT_EXT_INIT:
2733			r8153b_green_en(tp,
2734					test_bit(GREEN_ETHERNET, &tp->flags));
2735
2736			data = r8152_mdio_read(tp, MII_BMCR);
2737			data &= ~BMCR_PDOWN;
2738			data |= BMCR_RESET;
2739			r8152_mdio_write(tp, MII_BMCR, data);
2740
2741			data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
 
2742
2743		default:
2744			if (data != PHY_STAT_LAN_ON)
2745				netif_warn(tp, link, tp->netdev,
2746					   "PHY not ready");
2747			break;
2748		}
2749	}
2750}
2751
2752static void r8153_power_cut_en(struct r8152 *tp, bool enable)
2753{
2754	u32 ocp_data;
2755
2756	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2757	if (enable)
2758		ocp_data |= PWR_EN | PHASE2_EN;
2759	else
2760		ocp_data &= ~(PWR_EN | PHASE2_EN);
2761	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2762
2763	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2764	ocp_data &= ~PCUT_STATUS;
2765	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2766}
2767
2768static void r8153b_power_cut_en(struct r8152 *tp, bool enable)
2769{
2770	u32 ocp_data;
2771
2772	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT);
2773	if (enable)
2774		ocp_data |= PWR_EN | PHASE2_EN;
2775	else
2776		ocp_data &= ~PWR_EN;
2777	ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
2778
2779	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2780	ocp_data &= ~PCUT_STATUS;
2781	ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2782}
2783
2784static void r8153b_queue_wake(struct r8152 *tp, bool enable)
2785{
2786	u32 ocp_data;
2787
2788	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38a);
2789	if (enable)
2790		ocp_data |= BIT(0);
2791	else
2792		ocp_data &= ~BIT(0);
2793	ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38a, ocp_data);
2794
2795	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 0xd38c);
2796	ocp_data &= ~BIT(0);
2797	ocp_write_byte(tp, MCU_TYPE_PLA, 0xd38c, ocp_data);
 
 
 
 
2798}
2799
2800static bool rtl_can_wakeup(struct r8152 *tp)
2801{
2802	struct usb_device *udev = tp->udev;
2803
2804	return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP);
2805}
2806
2807static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable)
2808{
2809	if (enable) {
2810		u32 ocp_data;
2811
2812		__rtl_set_wol(tp, WAKE_ANY);
2813
2814		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2815
2816		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2817		ocp_data |= LINK_OFF_WAKE_EN;
2818		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2819
2820		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2821	} else {
2822		u32 ocp_data;
2823
2824		__rtl_set_wol(tp, tp->saved_wolopts);
2825
2826		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
2827
2828		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
2829		ocp_data &= ~LINK_OFF_WAKE_EN;
2830		ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
2831
2832		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
2833	}
2834}
2835
2836static void rtl8153_runtime_enable(struct r8152 *tp, bool enable)
2837{
2838	if (enable) {
2839		r8153_u1u2en(tp, false);
2840		r8153_u2p3en(tp, false);
2841		r8153_mac_clk_spd(tp, true);
2842		rtl_runtime_suspend_enable(tp, true);
2843	} else {
2844		rtl_runtime_suspend_enable(tp, false);
2845		r8153_mac_clk_spd(tp, false);
2846
2847		switch (tp->version) {
2848		case RTL_VER_03:
2849		case RTL_VER_04:
2850			break;
2851		case RTL_VER_05:
2852		case RTL_VER_06:
2853		default:
2854			r8153_u2p3en(tp, true);
2855			break;
2856		}
2857
2858		r8153_u1u2en(tp, true);
2859	}
2860}
2861
2862static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable)
2863{
2864	if (enable) {
2865		r8153b_queue_wake(tp, true);
2866		r8153b_u1u2en(tp, false);
2867		r8153_u2p3en(tp, false);
2868		rtl_runtime_suspend_enable(tp, true);
2869		r8153b_ups_en(tp, true);
2870	} else {
2871		r8153b_ups_en(tp, false);
2872		r8153b_queue_wake(tp, false);
2873		rtl_runtime_suspend_enable(tp, false);
2874		r8153_u2p3en(tp, true);
2875		r8153b_u1u2en(tp, true);
2876	}
2877}
2878
2879static void r8153_teredo_off(struct r8152 *tp)
2880{
2881	u32 ocp_data;
2882
2883	switch (tp->version) {
2884	case RTL_VER_01:
2885	case RTL_VER_02:
2886	case RTL_VER_03:
2887	case RTL_VER_04:
2888	case RTL_VER_05:
2889	case RTL_VER_06:
2890	case RTL_VER_07:
2891		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
2892		ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK |
2893			      OOB_TEREDO_EN);
2894		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
2895		break;
2896
2897	case RTL_VER_08:
2898	case RTL_VER_09:
2899		/* The bit 0 ~ 7 are relative with teredo settings. They are
2900		 * W1C (write 1 to clear), so set all 1 to disable it.
2901		 */
2902		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
2903		break;
2904
2905	default:
2906		break;
2907	}
2908
2909	ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
2910	ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0);
2911	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0);
2912}
2913
2914static void rtl_reset_bmu(struct r8152 *tp)
2915{
2916	u32 ocp_data;
2917
2918	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET);
2919	ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT);
2920	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2921	ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT;
2922	ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
2923}
2924
2925static void r8152_aldps_en(struct r8152 *tp, bool enable)
2926{
2927	if (enable) {
2928		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS |
2929						    LINKENA | DIS_SDSAVE);
2930	} else {
2931		ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA |
2932						    DIS_SDSAVE);
2933		msleep(20);
2934	}
2935}
2936
2937static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg)
2938{
2939	ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev);
2940	ocp_reg_write(tp, OCP_EEE_DATA, reg);
2941	ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev);
2942}
2943
2944static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg)
2945{
2946	u16 data;
2947
2948	r8152_mmd_indirect(tp, dev, reg);
2949	data = ocp_reg_read(tp, OCP_EEE_DATA);
2950	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2951
2952	return data;
2953}
2954
2955static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data)
2956{
2957	r8152_mmd_indirect(tp, dev, reg);
2958	ocp_reg_write(tp, OCP_EEE_DATA, data);
2959	ocp_reg_write(tp, OCP_EEE_AR, 0x0000);
2960}
2961
2962static void r8152_eee_en(struct r8152 *tp, bool enable)
2963{
2964	u16 config1, config2, config3;
2965	u32 ocp_data;
2966
2967	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
2968	config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask;
2969	config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2);
2970	config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask;
2971
2972	if (enable) {
2973		ocp_data |= EEE_RX_EN | EEE_TX_EN;
2974		config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN;
2975		config1 |= sd_rise_time(1);
2976		config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN;
2977		config3 |= fast_snr(42);
2978	} else {
2979		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
2980		config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN |
2981			     RX_QUIET_EN);
2982		config1 |= sd_rise_time(7);
2983		config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN);
2984		config3 |= fast_snr(511);
2985	}
2986
2987	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
2988	ocp_reg_write(tp, OCP_EEE_CONFIG1, config1);
2989	ocp_reg_write(tp, OCP_EEE_CONFIG2, config2);
2990	ocp_reg_write(tp, OCP_EEE_CONFIG3, config3);
2991}
2992
2993static void r8152b_enable_eee(struct r8152 *tp)
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2994{
2995	r8152_eee_en(tp, true);
2996	r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, MDIO_EEE_100TX);
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
2997}
2998
2999static void r8152b_enable_fc(struct r8152 *tp)
3000{
3001	u16 anar;
3002
3003	anar = r8152_mdio_read(tp, MII_ADVERTISE);
3004	anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
3005	r8152_mdio_write(tp, MII_ADVERTISE, anar);
 
 
3006}
3007
3008static void rtl8152_disable(struct r8152 *tp)
3009{
3010	r8152_aldps_en(tp, false);
3011	rtl_disable(tp);
3012	r8152_aldps_en(tp, true);
3013}
3014
3015static void r8152b_hw_phy_cfg(struct r8152 *tp)
3016{
3017	r8152b_enable_eee(tp);
3018	r8152_aldps_en(tp, true);
3019	r8152b_enable_fc(tp);
3020
3021	set_bit(PHY_RESET, &tp->flags);
3022}
3023
3024static void r8152b_exit_oob(struct r8152 *tp)
3025{
3026	u32 ocp_data;
3027	int i;
3028
3029	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3030	ocp_data &= ~RCR_ACPT_ALL;
3031	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3032
3033	rxdy_gated_en(tp, true);
3034	r8153_teredo_off(tp);
3035	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
3036	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00);
3037
3038	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3039	ocp_data &= ~NOW_IS_OOB;
3040	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3041
3042	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3043	ocp_data &= ~MCU_BORW_EN;
3044	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3045
3046	for (i = 0; i < 1000; i++) {
3047		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3048		if (ocp_data & LINK_LIST_READY)
3049			break;
3050		usleep_range(1000, 2000);
3051	}
3052
3053	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3054	ocp_data |= RE_INIT_LL;
3055	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3056
3057	for (i = 0; i < 1000; i++) {
3058		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3059		if (ocp_data & LINK_LIST_READY)
3060			break;
3061		usleep_range(1000, 2000);
3062	}
3063
3064	rtl8152_nic_reset(tp);
3065
3066	/* rx share fifo credit full threshold */
3067	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3068
3069	if (tp->udev->speed == USB_SPEED_FULL ||
3070	    tp->udev->speed == USB_SPEED_LOW) {
3071		/* rx share fifo credit near full threshold */
3072		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3073				RXFIFO_THR2_FULL);
3074		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3075				RXFIFO_THR3_FULL);
3076	} else {
3077		/* rx share fifo credit near full threshold */
3078		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1,
3079				RXFIFO_THR2_HIGH);
3080		ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2,
3081				RXFIFO_THR3_HIGH);
3082	}
3083
3084	/* TX share fifo free credit full threshold */
3085	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
3086
3087	ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
3088	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
3089	ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA,
3090			TEST_MODE_DISABLE | TX_SIZE_ADJUST1);
3091
3092	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3093
3094	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3095
3096	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3097	ocp_data |= TCR0_AUTO_FIFO;
3098	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3099}
3100
3101static void r8152b_enter_oob(struct r8152 *tp)
3102{
3103	u32 ocp_data;
3104	int i;
3105
3106	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3107	ocp_data &= ~NOW_IS_OOB;
3108	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3109
3110	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB);
3111	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB);
3112	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB);
3113
3114	rtl_disable(tp);
3115
3116	for (i = 0; i < 1000; i++) {
3117		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3118		if (ocp_data & LINK_LIST_READY)
3119			break;
3120		usleep_range(1000, 2000);
3121	}
3122
3123	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3124	ocp_data |= RE_INIT_LL;
3125	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3126
3127	for (i = 0; i < 1000; i++) {
3128		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3129		if (ocp_data & LINK_LIST_READY)
3130			break;
3131		usleep_range(1000, 2000);
3132	}
3133
3134	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS);
3135
3136	rtl_rx_vlan_en(tp, true);
3137
3138	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3139	ocp_data |= ALDPS_PROXY_MODE;
3140	ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3141
3142	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3143	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3144	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3145
3146	rxdy_gated_en(tp, false);
3147
3148	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3149	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3150	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3151}
3152
3153static int r8153_patch_request(struct r8152 *tp, bool request)
3154{
3155	u16 data;
3156	int i;
3157
3158	data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD);
3159	if (request)
3160		data |= PATCH_REQUEST;
3161	else
3162		data &= ~PATCH_REQUEST;
3163	ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data);
3164
3165	for (i = 0; request && i < 5000; i++) {
3166		usleep_range(1000, 2000);
3167		if (ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)
3168			break;
3169	}
3170
3171	if (request && !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) {
3172		netif_err(tp, drv, tp->netdev, "patch request fail\n");
3173		r8153_patch_request(tp, false);
3174		return -ETIME;
3175	} else {
3176		return 0;
3177	}
3178}
3179
3180static void r8153_aldps_en(struct r8152 *tp, bool enable)
3181{
3182	u16 data;
3183
3184	data = ocp_reg_read(tp, OCP_POWER_CFG);
3185	if (enable) {
3186		data |= EN_ALDPS;
3187		ocp_reg_write(tp, OCP_POWER_CFG, data);
3188	} else {
3189		int i;
3190
3191		data &= ~EN_ALDPS;
3192		ocp_reg_write(tp, OCP_POWER_CFG, data);
3193		for (i = 0; i < 20; i++) {
3194			usleep_range(1000, 2000);
3195			if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100)
3196				break;
3197		}
3198	}
3199}
3200
3201static void r8153b_aldps_en(struct r8152 *tp, bool enable)
3202{
3203	r8153_aldps_en(tp, enable);
3204
3205	if (enable)
3206		r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_ALDPS, 0);
3207	else
3208		r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_ALDPS);
3209}
3210
3211static void r8153_eee_en(struct r8152 *tp, bool enable)
3212{
3213	u32 ocp_data;
3214	u16 config;
3215
3216	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
3217	config = ocp_reg_read(tp, OCP_EEE_CFG);
3218
3219	if (enable) {
3220		ocp_data |= EEE_RX_EN | EEE_TX_EN;
3221		config |= EEE10_EN;
3222	} else {
3223		ocp_data &= ~(EEE_RX_EN | EEE_TX_EN);
3224		config &= ~EEE10_EN;
3225	}
3226
3227	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data);
3228	ocp_reg_write(tp, OCP_EEE_CFG, config);
3229}
3230
3231static void r8153b_eee_en(struct r8152 *tp, bool enable)
3232{
3233	r8153_eee_en(tp, enable);
3234
3235	if (enable)
3236		r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_EEE, 0);
3237	else
3238		r8153b_ups_flags_w1w0(tp, 0, UPS_FLAGS_EN_EEE);
3239}
3240
3241static void r8153b_enable_fc(struct r8152 *tp)
3242{
3243	r8152b_enable_fc(tp);
3244	r8153b_ups_flags_w1w0(tp, UPS_FLAGS_EN_FLOW_CTR, 0);
3245}
3246
3247static void r8153_hw_phy_cfg(struct r8152 *tp)
3248{
3249	u32 ocp_data;
3250	u16 data;
3251
3252	/* disable ALDPS before updating the PHY parameters */
3253	r8153_aldps_en(tp, false);
3254
3255	/* disable EEE before updating the PHY parameters */
3256	r8153_eee_en(tp, false);
3257	ocp_reg_write(tp, OCP_EEE_ADV, 0);
3258
3259	if (tp->version == RTL_VER_03) {
3260		data = ocp_reg_read(tp, OCP_EEE_CFG);
3261		data &= ~CTAP_SHORT_EN;
3262		ocp_reg_write(tp, OCP_EEE_CFG, data);
3263	}
3264
3265	data = ocp_reg_read(tp, OCP_POWER_CFG);
3266	data |= EEE_CLKDIV_EN;
3267	ocp_reg_write(tp, OCP_POWER_CFG, data);
3268
3269	data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3270	data |= EN_10M_BGOFF;
3271	ocp_reg_write(tp, OCP_DOWN_SPEED, data);
3272	data = ocp_reg_read(tp, OCP_POWER_CFG);
3273	data |= EN_10M_PLLOFF;
3274	ocp_reg_write(tp, OCP_POWER_CFG, data);
3275	sram_write(tp, SRAM_IMPEDANCE, 0x0b13);
3276
3277	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3278	ocp_data |= PFM_PWM_SWITCH;
3279	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3280
3281	/* Enable LPF corner auto tune */
3282	sram_write(tp, SRAM_LPF_CFG, 0xf70f);
3283
3284	/* Adjust 10M Amplitude */
3285	sram_write(tp, SRAM_10M_AMP1, 0x00af);
3286	sram_write(tp, SRAM_10M_AMP2, 0x0208);
3287
3288	r8153_eee_en(tp, true);
3289	ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3290
3291	r8153_aldps_en(tp, true);
3292	r8152b_enable_fc(tp);
3293
3294	switch (tp->version) {
3295	case RTL_VER_03:
3296	case RTL_VER_04:
3297		break;
3298	case RTL_VER_05:
3299	case RTL_VER_06:
3300	default:
3301		r8153_u2p3en(tp, true);
3302		break;
3303	}
3304
3305	set_bit(PHY_RESET, &tp->flags);
3306}
3307
3308static u32 r8152_efuse_read(struct r8152 *tp, u8 addr)
3309{
3310	u32 ocp_data;
3311
3312	ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr);
3313	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD);
3314	ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9;	/* data of bit16 */
3315	ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA);
3316
3317	return ocp_data;
3318}
3319
3320static void r8153b_hw_phy_cfg(struct r8152 *tp)
3321{
3322	u32 ocp_data, ups_flags = 0;
3323	u16 data;
3324
3325	/* disable ALDPS before updating the PHY parameters */
3326	r8153b_aldps_en(tp, false);
3327
3328	/* disable EEE before updating the PHY parameters */
3329	r8153b_eee_en(tp, false);
3330	ocp_reg_write(tp, OCP_EEE_ADV, 0);
3331
3332	r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
3333
3334	data = sram_read(tp, SRAM_GREEN_CFG);
3335	data |= R_TUNE_EN;
3336	sram_write(tp, SRAM_GREEN_CFG, data);
3337	data = ocp_reg_read(tp, OCP_NCTL_CFG);
3338	data |= PGA_RETURN_EN;
3339	ocp_reg_write(tp, OCP_NCTL_CFG, data);
3340
3341	/* ADC Bias Calibration:
3342	 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake
3343	 * bit (bit3) to rebuild the real 16-bit data. Write the data to the
3344	 * ADC ioffset.
3345	 */
3346	ocp_data = r8152_efuse_read(tp, 0x7d);
3347	data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7));
3348	if (data != 0xffff)
3349		ocp_reg_write(tp, OCP_ADC_IOFFSET, data);
3350
3351	/* ups mode tx-link-pulse timing adjustment:
3352	 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0]
3353	 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt
3354	 */
3355	ocp_data = ocp_reg_read(tp, 0xc426);
3356	ocp_data &= 0x3fff;
3357	if (ocp_data) {
3358		u32 swr_cnt_1ms_ini;
3359
3360		swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK;
3361		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG);
3362		ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini;
3363		ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data);
3364	}
3365
3366	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
3367	ocp_data |= PFM_PWM_SWITCH;
3368	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
3369
3370	/* Advnace EEE */
3371	if (!r8153_patch_request(tp, true)) {
3372		data = ocp_reg_read(tp, OCP_POWER_CFG);
3373		data |= EEE_CLKDIV_EN;
3374		ocp_reg_write(tp, OCP_POWER_CFG, data);
 
3375
3376		data = ocp_reg_read(tp, OCP_DOWN_SPEED);
3377		data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV;
3378		ocp_reg_write(tp, OCP_DOWN_SPEED, data);
 
 
 
3379
3380		ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
3381		ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5));
3382
3383		ups_flags |= UPS_FLAGS_EN_10M_CKDIV | UPS_FLAGS_250M_CKDIV |
3384			     UPS_FLAGS_EN_EEE_CKDIV | UPS_FLAGS_EEE_CMOD_LV_EN |
3385			     UPS_FLAGS_EEE_PLLOFF_GIGA;
3386
3387		r8153_patch_request(tp, false);
3388	}
3389
3390	r8153b_ups_flags_w1w0(tp, ups_flags, 0);
 
3391
3392	r8153b_eee_en(tp, true);
3393	ocp_reg_write(tp, OCP_EEE_ADV, MDIO_EEE_1000T | MDIO_EEE_100TX);
3394
3395	r8153b_aldps_en(tp, true);
3396	r8153b_enable_fc(tp);
3397	r8153_u2p3en(tp, true);
3398
3399	set_bit(PHY_RESET, &tp->flags);
3400}
3401
3402static void r8153_first_init(struct r8152 *tp)
3403{
3404	u32 ocp_data;
3405	int i;
3406
3407	r8153_mac_clk_spd(tp, false);
3408	rxdy_gated_en(tp, true);
3409	r8153_teredo_off(tp);
3410
3411	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3412	ocp_data &= ~RCR_ACPT_ALL;
3413	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3414
3415	rtl8152_nic_reset(tp);
3416	rtl_reset_bmu(tp);
3417
3418	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3419	ocp_data &= ~NOW_IS_OOB;
3420	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3421
3422	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3423	ocp_data &= ~MCU_BORW_EN;
3424	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3425
3426	for (i = 0; i < 1000; i++) {
3427		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3428		if (ocp_data & LINK_LIST_READY)
3429			break;
3430		usleep_range(1000, 2000);
3431	}
3432
3433	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3434	ocp_data |= RE_INIT_LL;
3435	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3436
3437	for (i = 0; i < 1000; i++) {
3438		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3439		if (ocp_data & LINK_LIST_READY)
3440			break;
3441		usleep_range(1000, 2000);
3442	}
3443
3444	rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
3445
3446	ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3447	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3448	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
3449
3450	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0);
3451	ocp_data |= TCR0_AUTO_FIFO;
3452	ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data);
3453
3454	rtl8152_nic_reset(tp);
3455
3456	/* rx share fifo credit full threshold */
3457	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL);
3458	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
3459	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
3460	/* TX share fifo free credit full threshold */
3461	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
3462}
3463
3464static void r8153_enter_oob(struct r8152 *tp)
3465{
3466	u32 ocp_data;
3467	int i;
3468
3469	r8153_mac_clk_spd(tp, true);
3470
3471	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3472	ocp_data &= ~NOW_IS_OOB;
3473	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3474
3475	rtl_disable(tp);
3476	rtl_reset_bmu(tp);
3477
3478	for (i = 0; i < 1000; i++) {
3479		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3480		if (ocp_data & LINK_LIST_READY)
3481			break;
3482		usleep_range(1000, 2000);
3483	}
3484
3485	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
3486	ocp_data |= RE_INIT_LL;
3487	ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
3488
3489	for (i = 0; i < 1000; i++) {
3490		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3491		if (ocp_data & LINK_LIST_READY)
3492			break;
3493		usleep_range(1000, 2000);
3494	}
3495
3496	ocp_data = tp->netdev->mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
3497	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, ocp_data);
3498
3499	switch (tp->version) {
3500	case RTL_VER_03:
3501	case RTL_VER_04:
3502	case RTL_VER_05:
3503	case RTL_VER_06:
3504		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG);
3505		ocp_data &= ~TEREDO_WAKE_MASK;
3506		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data);
3507		break;
3508
3509	case RTL_VER_08:
3510	case RTL_VER_09:
3511		/* Clear teredo wake event. bit[15:8] is the teredo wakeup
3512		 * type. Set it to zero. bits[7:0] are the W1C bits about
3513		 * the events. Set them to all 1 to clear them.
3514		 */
3515		ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
3516		break;
3517
3518	default:
3519		break;
3520	}
3521
3522	rtl_rx_vlan_en(tp, true);
3523
3524	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PAL_BDC_CR);
3525	ocp_data |= ALDPS_PROXY_MODE;
3526	ocp_write_word(tp, MCU_TYPE_PLA, PAL_BDC_CR, ocp_data);
3527
3528	ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
3529	ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB;
3530	ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
3531
3532	rxdy_gated_en(tp, false);
3533
3534	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
3535	ocp_data |= RCR_APM | RCR_AM | RCR_AB;
3536	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
3537}
3538
3539static void rtl8153_disable(struct r8152 *tp)
3540{
3541	r8153_aldps_en(tp, false);
3542	rtl_disable(tp);
3543	rtl_reset_bmu(tp);
3544	r8153_aldps_en(tp, true);
3545}
3546
3547static void rtl8153b_disable(struct r8152 *tp)
 
3548{
3549	r8153b_aldps_en(tp, false);
3550	rtl_disable(tp);
3551	rtl_reset_bmu(tp);
3552	r8153b_aldps_en(tp, true);
3553}
3554
3555static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u16 speed, u8 duplex)
3556{
3557	u16 bmcr, anar, gbcr;
3558	enum spd_duplex speed_duplex;
3559	int ret = 0;
3560
3561	anar = r8152_mdio_read(tp, MII_ADVERTISE);
3562	anar &= ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
3563		  ADVERTISE_100HALF | ADVERTISE_100FULL);
3564	if (tp->mii.supports_gmii) {
3565		gbcr = r8152_mdio_read(tp, MII_CTRL1000);
3566		gbcr &= ~(ADVERTISE_1000FULL | ADVERTISE_1000HALF);
3567	} else {
3568		gbcr = 0;
3569	}
3570
3571	if (autoneg == AUTONEG_DISABLE) {
3572		if (speed == SPEED_10) {
3573			bmcr = 0;
3574			anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3575			speed_duplex = FORCE_10M_HALF;
3576		} else if (speed == SPEED_100) {
3577			bmcr = BMCR_SPEED100;
3578			anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3579			speed_duplex = FORCE_100M_HALF;
3580		} else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3581			bmcr = BMCR_SPEED1000;
3582			gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3583			speed_duplex = NWAY_1000M_FULL;
3584		} else {
3585			ret = -EINVAL;
3586			goto out;
3587		}
3588
3589		if (duplex == DUPLEX_FULL) {
3590			bmcr |= BMCR_FULLDPLX;
3591			if (speed != SPEED_1000)
3592				speed_duplex++;
3593		}
3594	} else {
3595		if (speed == SPEED_10) {
3596			if (duplex == DUPLEX_FULL) {
3597				anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3598				speed_duplex = NWAY_10M_FULL;
3599			} else {
3600				anar |= ADVERTISE_10HALF;
3601				speed_duplex = NWAY_10M_HALF;
3602			}
3603		} else if (speed == SPEED_100) {
 
 
3604			if (duplex == DUPLEX_FULL) {
3605				anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3606				anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3607				speed_duplex = NWAY_100M_FULL;
3608			} else {
3609				anar |= ADVERTISE_10HALF;
3610				anar |= ADVERTISE_100HALF;
3611				speed_duplex = NWAY_100M_HALF;
3612			}
3613		} else if (speed == SPEED_1000 && tp->mii.supports_gmii) {
3614			if (duplex == DUPLEX_FULL) {
3615				anar |= ADVERTISE_10HALF | ADVERTISE_10FULL;
3616				anar |= ADVERTISE_100HALF | ADVERTISE_100FULL;
3617				gbcr |= ADVERTISE_1000FULL | ADVERTISE_1000HALF;
3618			} else {
3619				anar |= ADVERTISE_10HALF;
3620				anar |= ADVERTISE_100HALF;
3621				gbcr |= ADVERTISE_1000HALF;
3622			}
3623			speed_duplex = NWAY_1000M_FULL;
3624		} else {
3625			ret = -EINVAL;
3626			goto out;
3627		}
3628
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
3629		bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
 
 
3630	}
3631
3632	if (test_and_clear_bit(PHY_RESET, &tp->flags))
3633		bmcr |= BMCR_RESET;
3634
3635	if (tp->mii.supports_gmii)
3636		r8152_mdio_write(tp, MII_CTRL1000, gbcr);
3637
3638	r8152_mdio_write(tp, MII_ADVERTISE, anar);
3639	r8152_mdio_write(tp, MII_BMCR, bmcr);
3640
3641	switch (tp->version) {
3642	case RTL_VER_08:
3643	case RTL_VER_09:
3644		r8153b_ups_flags_w1w0(tp, ups_flags_speed(speed_duplex),
3645				      UPS_FLAGS_SPEED_MASK);
3646		break;
3647
3648	default:
3649		break;
3650	}
3651
3652	if (bmcr & BMCR_RESET) {
3653		int i;
3654
3655		for (i = 0; i < 50; i++) {
3656			msleep(20);
3657			if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0)
3658				break;
3659		}
3660	}
3661
3662out:
3663	return ret;
3664}
3665
3666static void rtl8152_up(struct r8152 *tp)
3667{
3668	if (test_bit(RTL8152_UNPLUG, &tp->flags))
3669		return;
3670
3671	r8152_aldps_en(tp, false);
3672	r8152b_exit_oob(tp);
3673	r8152_aldps_en(tp, true);
3674}
3675
3676static void rtl8152_down(struct r8152 *tp)
3677{
3678	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3679		rtl_drop_queued_tx(tp);
3680		return;
3681	}
3682
3683	r8152_power_cut_en(tp, false);
3684	r8152_aldps_en(tp, false);
3685	r8152b_enter_oob(tp);
3686	r8152_aldps_en(tp, true);
3687}
3688
3689static void rtl8153_up(struct r8152 *tp)
3690{
3691	if (test_bit(RTL8152_UNPLUG, &tp->flags))
3692		return;
3693
3694	r8153_u1u2en(tp, false);
3695	r8153_u2p3en(tp, false);
3696	r8153_aldps_en(tp, false);
3697	r8153_first_init(tp);
3698	r8153_aldps_en(tp, true);
3699
3700	switch (tp->version) {
3701	case RTL_VER_03:
3702	case RTL_VER_04:
3703		break;
3704	case RTL_VER_05:
3705	case RTL_VER_06:
3706	default:
3707		r8153_u2p3en(tp, true);
3708		break;
3709	}
3710
3711	r8153_u1u2en(tp, true);
3712}
3713
3714static void rtl8153_down(struct r8152 *tp)
3715{
3716	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3717		rtl_drop_queued_tx(tp);
3718		return;
3719	}
3720
3721	r8153_u1u2en(tp, false);
3722	r8153_u2p3en(tp, false);
3723	r8153_power_cut_en(tp, false);
3724	r8153_aldps_en(tp, false);
3725	r8153_enter_oob(tp);
3726	r8153_aldps_en(tp, true);
3727}
3728
3729static void rtl8153b_up(struct r8152 *tp)
3730{
3731	if (test_bit(RTL8152_UNPLUG, &tp->flags))
3732		return;
3733
3734	r8153b_u1u2en(tp, false);
3735	r8153_u2p3en(tp, false);
3736	r8153b_aldps_en(tp, false);
3737
3738	r8153_first_init(tp);
3739	ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
3740
3741	r8153b_aldps_en(tp, true);
3742	r8153_u2p3en(tp, true);
3743	r8153b_u1u2en(tp, true);
3744}
3745
3746static void rtl8153b_down(struct r8152 *tp)
3747{
3748	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
3749		rtl_drop_queued_tx(tp);
3750		return;
3751	}
3752
3753	r8153b_u1u2en(tp, false);
3754	r8153_u2p3en(tp, false);
3755	r8153b_power_cut_en(tp, false);
3756	r8153b_aldps_en(tp, false);
3757	r8153_enter_oob(tp);
3758	r8153b_aldps_en(tp, true);
3759}
3760
3761static bool rtl8152_in_nway(struct r8152 *tp)
3762{
3763	u16 nway_state;
3764
3765	ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000);
3766	tp->ocp_base = 0x2000;
3767	ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c);		/* phy state */
3768	nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a);
3769
3770	/* bit 15: TXDIS_STATE, bit 14: ABD_STATE */
3771	if (nway_state & 0xc000)
3772		return false;
3773	else
3774		return true;
3775}
3776
3777static bool rtl8153_in_nway(struct r8152 *tp)
3778{
3779	u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff;
3780
3781	if (phy_state == TXDIS_STATE || phy_state == ABD_STATE)
3782		return false;
3783	else
3784		return true;
3785}
3786
3787static void set_carrier(struct r8152 *tp)
3788{
3789	struct net_device *netdev = tp->netdev;
3790	struct napi_struct *napi = &tp->napi;
3791	u8 speed;
3792
3793	speed = rtl8152_get_speed(tp);
3794
3795	if (speed & LINK_STATUS) {
3796		if (!netif_carrier_ok(netdev)) {
3797			tp->rtl_ops.enable(tp);
3798			netif_stop_queue(netdev);
3799			napi_disable(napi);
3800			netif_carrier_on(netdev);
3801			rtl_start_rx(tp);
3802			clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
3803			_rtl8152_set_rx_mode(netdev);
3804			napi_enable(&tp->napi);
3805			netif_wake_queue(netdev);
3806			netif_info(tp, link, netdev, "carrier on\n");
3807		} else if (netif_queue_stopped(netdev) &&
3808			   skb_queue_len(&tp->tx_queue) < tp->tx_qlen) {
3809			netif_wake_queue(netdev);
3810		}
3811	} else {
3812		if (netif_carrier_ok(netdev)) {
3813			netif_carrier_off(netdev);
 
3814			napi_disable(napi);
3815			tp->rtl_ops.disable(tp);
3816			napi_enable(napi);
 
3817			netif_info(tp, link, netdev, "carrier off\n");
3818		}
3819	}
3820}
3821
3822static void rtl_work_func_t(struct work_struct *work)
3823{
3824	struct r8152 *tp = container_of(work, struct r8152, schedule.work);
3825
3826	/* If the device is unplugged or !netif_running(), the workqueue
3827	 * doesn't need to wake the device, and could return directly.
3828	 */
3829	if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
3830		return;
3831
3832	if (usb_autopm_get_interface(tp->intf) < 0)
3833		return;
3834
3835	if (!test_bit(WORK_ENABLE, &tp->flags))
3836		goto out1;
3837
3838	if (!mutex_trylock(&tp->control)) {
3839		schedule_delayed_work(&tp->schedule, 0);
3840		goto out1;
3841	}
3842
3843	if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags))
3844		set_carrier(tp);
3845
3846	if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags))
3847		_rtl8152_set_rx_mode(tp->netdev);
3848
3849	/* don't schedule napi before linking */
3850	if (test_and_clear_bit(SCHEDULE_NAPI, &tp->flags) &&
3851	    netif_carrier_ok(tp->netdev))
3852		napi_schedule(&tp->napi);
3853
3854	mutex_unlock(&tp->control);
3855
3856out1:
3857	usb_autopm_put_interface(tp->intf);
3858}
3859
3860static void rtl_hw_phy_work_func_t(struct work_struct *work)
3861{
3862	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
3863
3864	if (test_bit(RTL8152_UNPLUG, &tp->flags))
3865		return;
3866
3867	if (usb_autopm_get_interface(tp->intf) < 0)
3868		return;
3869
3870	mutex_lock(&tp->control);
3871
3872	tp->rtl_ops.hw_phy_cfg(tp);
3873
3874	rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex);
 
3875
3876	mutex_unlock(&tp->control);
3877
3878	usb_autopm_put_interface(tp->intf);
3879}
3880
3881#ifdef CONFIG_PM_SLEEP
3882static int rtl_notifier(struct notifier_block *nb, unsigned long action,
3883			void *data)
3884{
3885	struct r8152 *tp = container_of(nb, struct r8152, pm_notifier);
3886
3887	switch (action) {
3888	case PM_HIBERNATION_PREPARE:
3889	case PM_SUSPEND_PREPARE:
3890		usb_autopm_get_interface(tp->intf);
3891		break;
3892
3893	case PM_POST_HIBERNATION:
3894	case PM_POST_SUSPEND:
3895		usb_autopm_put_interface(tp->intf);
3896		break;
3897
3898	case PM_POST_RESTORE:
3899	case PM_RESTORE_PREPARE:
3900	default:
3901		break;
3902	}
3903
3904	return NOTIFY_DONE;
3905}
3906#endif
3907
3908static int rtl8152_open(struct net_device *netdev)
3909{
3910	struct r8152 *tp = netdev_priv(netdev);
3911	int res = 0;
3912
3913	res = alloc_all_mem(tp);
3914	if (res)
3915		goto out;
3916
3917	res = usb_autopm_get_interface(tp->intf);
3918	if (res < 0)
3919		goto out_free;
3920
3921	mutex_lock(&tp->control);
3922
3923	tp->rtl_ops.up(tp);
3924
3925	netif_carrier_off(netdev);
3926	netif_start_queue(netdev);
3927	set_bit(WORK_ENABLE, &tp->flags);
3928
3929	res = usb_submit_urb(tp->intr_urb, GFP_KERNEL);
3930	if (res) {
3931		if (res == -ENODEV)
3932			netif_device_detach(tp->netdev);
3933		netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n",
3934			   res);
3935		goto out_unlock;
3936	}
3937	napi_enable(&tp->napi);
 
3938
3939	mutex_unlock(&tp->control);
3940
3941	usb_autopm_put_interface(tp->intf);
3942#ifdef CONFIG_PM_SLEEP
3943	tp->pm_notifier.notifier_call = rtl_notifier;
3944	register_pm_notifier(&tp->pm_notifier);
3945#endif
3946	return 0;
3947
3948out_unlock:
3949	mutex_unlock(&tp->control);
3950	usb_autopm_put_interface(tp->intf);
3951out_free:
3952	free_all_mem(tp);
3953out:
3954	return res;
3955}
3956
3957static int rtl8152_close(struct net_device *netdev)
3958{
3959	struct r8152 *tp = netdev_priv(netdev);
3960	int res = 0;
3961
3962#ifdef CONFIG_PM_SLEEP
3963	unregister_pm_notifier(&tp->pm_notifier);
3964#endif
3965	napi_disable(&tp->napi);
3966	clear_bit(WORK_ENABLE, &tp->flags);
3967	usb_kill_urb(tp->intr_urb);
3968	cancel_delayed_work_sync(&tp->schedule);
 
3969	netif_stop_queue(netdev);
3970
3971	res = usb_autopm_get_interface(tp->intf);
3972	if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
3973		rtl_drop_queued_tx(tp);
3974		rtl_stop_rx(tp);
3975	} else {
3976		mutex_lock(&tp->control);
3977
3978		tp->rtl_ops.down(tp);
3979
3980		mutex_unlock(&tp->control);
3981
3982		usb_autopm_put_interface(tp->intf);
3983	}
3984
3985	free_all_mem(tp);
3986
3987	return res;
3988}
3989
3990static void rtl_tally_reset(struct r8152 *tp)
3991{
3992	u32 ocp_data;
3993
3994	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY);
3995	ocp_data |= TALLY_RESET;
3996	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
3997}
3998
3999static void r8152b_init(struct r8152 *tp)
4000{
4001	u32 ocp_data;
4002	u16 data;
4003
4004	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4005		return;
4006
4007	data = r8152_mdio_read(tp, MII_BMCR);
4008	if (data & BMCR_PDOWN) {
4009		data &= ~BMCR_PDOWN;
4010		r8152_mdio_write(tp, MII_BMCR, data);
4011	}
4012
4013	r8152_aldps_en(tp, false);
4014
4015	if (tp->version == RTL_VER_01) {
4016		ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4017		ocp_data &= ~LED_MODE_MASK;
4018		ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4019	}
4020
4021	r8152_power_cut_en(tp, false);
4022
4023	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
4024	ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH;
4025	ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
4026	ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL);
4027	ocp_data &= ~MCU_CLK_RATIO_MASK;
4028	ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN;
4029	ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data);
4030	ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK |
4031		   SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK;
4032	ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data);
4033
4034	rtl_tally_reset(tp);
4035
4036	/* enable rx aggregation */
4037	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4038	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4039	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4040}
4041
4042static void r8153_init(struct r8152 *tp)
4043{
4044	u32 ocp_data;
4045	u16 data;
4046	int i;
4047
4048	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4049		return;
4050
4051	r8153_u1u2en(tp, false);
4052
4053	for (i = 0; i < 500; i++) {
4054		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4055		    AUTOLOAD_DONE)
4056			break;
4057		msleep(20);
4058	}
4059
4060	data = r8153_phy_status(tp, 0);
4061
4062	if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 ||
4063	    tp->version == RTL_VER_05)
4064		ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L);
4065
4066	data = r8152_mdio_read(tp, MII_BMCR);
4067	if (data & BMCR_PDOWN) {
4068		data &= ~BMCR_PDOWN;
4069		r8152_mdio_write(tp, MII_BMCR, data);
4070	}
4071
4072	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4073
4074	r8153_u2p3en(tp, false);
4075
4076	if (tp->version == RTL_VER_04) {
4077		ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2);
4078		ocp_data &= ~pwd_dn_scale_mask;
4079		ocp_data |= pwd_dn_scale(96);
4080		ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data);
4081
4082		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY);
4083		ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND;
4084		ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data);
4085	} else if (tp->version == RTL_VER_05) {
4086		ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0);
4087		ocp_data &= ~ECM_ALDPS;
4088		ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data);
4089
4090		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4091		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4092			ocp_data &= ~DYNAMIC_BURST;
4093		else
4094			ocp_data |= DYNAMIC_BURST;
4095		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4096	} else if (tp->version == RTL_VER_06) {
4097		ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1);
4098		if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0)
4099			ocp_data &= ~DYNAMIC_BURST;
4100		else
4101			ocp_data |= DYNAMIC_BURST;
4102		ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data);
4103	}
4104
4105	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2);
4106	ocp_data |= EP4_FULL_FC;
4107	ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data);
4108
4109	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL);
4110	ocp_data &= ~TIMER11_EN;
4111	ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data);
4112
4113	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE);
4114	ocp_data &= ~LED_MODE_MASK;
4115	ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data);
4116
4117	ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM;
4118	if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER)
4119		ocp_data |= LPM_TIMER_500MS;
4120	else
4121		ocp_data |= LPM_TIMER_500US;
4122	ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data);
4123
4124	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2);
4125	ocp_data &= ~SEN_VAL_MASK;
4126	ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE;
4127	ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data);
4128
4129	ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
4130
4131	r8153_power_cut_en(tp, false);
4132	r8153_u1u2en(tp, true);
4133	r8153_mac_clk_spd(tp, false);
4134	usb_enable_lpm(tp->udev);
4135
4136	/* rx aggregation */
4137	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4138	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4139	if (test_bit(DELL_TB_RX_AGG_BUG, &tp->flags))
4140		ocp_data |= RX_AGG_DISABLE;
4141
4142	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4143
4144	rtl_tally_reset(tp);
4145
4146	switch (tp->udev->speed) {
4147	case USB_SPEED_SUPER:
4148	case USB_SPEED_SUPER_PLUS:
4149		tp->coalesce = COALESCE_SUPER;
4150		break;
4151	case USB_SPEED_HIGH:
4152		tp->coalesce = COALESCE_HIGH;
4153		break;
4154	default:
4155		tp->coalesce = COALESCE_SLOW;
4156		break;
4157	}
4158}
4159
4160static void r8153b_init(struct r8152 *tp)
4161{
4162	u32 ocp_data;
4163	u16 data;
4164	int i;
4165
4166	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4167		return;
4168
4169	r8153b_u1u2en(tp, false);
4170
4171	for (i = 0; i < 500; i++) {
4172		if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
4173		    AUTOLOAD_DONE)
4174			break;
4175		msleep(20);
4176	}
4177
4178	data = r8153_phy_status(tp, 0);
4179
4180	data = r8152_mdio_read(tp, MII_BMCR);
4181	if (data & BMCR_PDOWN) {
4182		data &= ~BMCR_PDOWN;
4183		r8152_mdio_write(tp, MII_BMCR, data);
4184	}
4185
4186	data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
4187
4188	r8153_u2p3en(tp, false);
4189
4190	/* MSC timer = 0xfff * 8ms = 32760 ms */
4191	ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
4192
4193	/* U1/U2/L1 idle timer. 500 us */
4194	ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
4195
4196	r8153b_power_cut_en(tp, false);
4197	r8153b_ups_en(tp, false);
4198	r8153b_queue_wake(tp, false);
4199	rtl_runtime_suspend_enable(tp, false);
4200	r8153b_u1u2en(tp, true);
4201	usb_enable_lpm(tp->udev);
4202
4203	/* MAC clock speed down */
4204	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
4205	ocp_data |= MAC_CLK_SPDWN_EN;
4206	ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
4207
4208	set_bit(GREEN_ETHERNET, &tp->flags);
4209
4210	/* rx aggregation */
4211	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
4212	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
4213	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
4214
4215	rtl_tally_reset(tp);
4216
4217	tp->coalesce = 15000;	/* 15 us */
4218}
4219
4220static int rtl8152_pre_reset(struct usb_interface *intf)
4221{
4222	struct r8152 *tp = usb_get_intfdata(intf);
4223	struct net_device *netdev;
4224
4225	if (!tp)
4226		return 0;
4227
4228	netdev = tp->netdev;
4229	if (!netif_running(netdev))
4230		return 0;
4231
4232	netif_stop_queue(netdev);
4233	napi_disable(&tp->napi);
4234	clear_bit(WORK_ENABLE, &tp->flags);
4235	usb_kill_urb(tp->intr_urb);
4236	cancel_delayed_work_sync(&tp->schedule);
 
4237	if (netif_carrier_ok(netdev)) {
4238		mutex_lock(&tp->control);
4239		tp->rtl_ops.disable(tp);
4240		mutex_unlock(&tp->control);
4241	}
4242
4243	return 0;
4244}
4245
4246static int rtl8152_post_reset(struct usb_interface *intf)
4247{
4248	struct r8152 *tp = usb_get_intfdata(intf);
4249	struct net_device *netdev;
 
4250
4251	if (!tp)
4252		return 0;
4253
 
 
 
 
 
 
 
4254	netdev = tp->netdev;
4255	if (!netif_running(netdev))
4256		return 0;
4257
4258	set_bit(WORK_ENABLE, &tp->flags);
4259	if (netif_carrier_ok(netdev)) {
4260		mutex_lock(&tp->control);
4261		tp->rtl_ops.enable(tp);
4262		rtl_start_rx(tp);
4263		_rtl8152_set_rx_mode(netdev);
4264		mutex_unlock(&tp->control);
4265	}
4266
4267	napi_enable(&tp->napi);
 
4268	netif_wake_queue(netdev);
4269	usb_submit_urb(tp->intr_urb, GFP_KERNEL);
4270
4271	if (!list_empty(&tp->rx_done))
4272		napi_schedule(&tp->napi);
4273
4274	return 0;
4275}
4276
4277static bool delay_autosuspend(struct r8152 *tp)
4278{
4279	bool sw_linking = !!netif_carrier_ok(tp->netdev);
4280	bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS);
4281
4282	/* This means a linking change occurs and the driver doesn't detect it,
4283	 * yet. If the driver has disabled tx/rx and hw is linking on, the
4284	 * device wouldn't wake up by receiving any packet.
4285	 */
4286	if (work_busy(&tp->schedule.work) || sw_linking != hw_linking)
4287		return true;
4288
4289	/* If the linking down is occurred by nway, the device may miss the
4290	 * linking change event. And it wouldn't wake when linking on.
4291	 */
4292	if (!sw_linking && tp->rtl_ops.in_nway(tp))
4293		return true;
4294	else if (!skb_queue_empty(&tp->tx_queue))
4295		return true;
4296	else
4297		return false;
4298}
4299
4300static int rtl8152_runtime_resume(struct r8152 *tp)
4301{
4302	struct net_device *netdev = tp->netdev;
4303
4304	if (netif_running(netdev) && netdev->flags & IFF_UP) {
4305		struct napi_struct *napi = &tp->napi;
4306
4307		tp->rtl_ops.autosuspend_en(tp, false);
4308		napi_disable(napi);
4309		set_bit(WORK_ENABLE, &tp->flags);
4310
4311		if (netif_carrier_ok(netdev)) {
4312			if (rtl8152_get_speed(tp) & LINK_STATUS) {
4313				rtl_start_rx(tp);
4314			} else {
4315				netif_carrier_off(netdev);
4316				tp->rtl_ops.disable(tp);
4317				netif_info(tp, link, netdev, "linking down\n");
4318			}
4319		}
4320
4321		napi_enable(napi);
4322		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4323		smp_mb__after_atomic();
4324
4325		if (!list_empty(&tp->rx_done))
4326			napi_schedule(&tp->napi);
4327
4328		usb_submit_urb(tp->intr_urb, GFP_NOIO);
4329	} else {
4330		if (netdev->flags & IFF_UP)
4331			tp->rtl_ops.autosuspend_en(tp, false);
4332
4333		clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4334	}
4335
4336	return 0;
4337}
4338
4339static int rtl8152_system_resume(struct r8152 *tp)
4340{
4341	struct net_device *netdev = tp->netdev;
4342
4343	netif_device_attach(netdev);
4344
4345	if (netif_running(netdev) && netdev->flags & IFF_UP) {
4346		tp->rtl_ops.up(tp);
4347		netif_carrier_off(netdev);
4348		set_bit(WORK_ENABLE, &tp->flags);
4349		usb_submit_urb(tp->intr_urb, GFP_NOIO);
4350	}
4351
4352	return 0;
4353}
4354
4355static int rtl8152_runtime_suspend(struct r8152 *tp)
4356{
4357	struct net_device *netdev = tp->netdev;
4358	int ret = 0;
4359
4360	set_bit(SELECTIVE_SUSPEND, &tp->flags);
4361	smp_mb__after_atomic();
4362
4363	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4364		u32 rcr = 0;
4365
4366		if (netif_carrier_ok(netdev)) {
4367			u32 ocp_data;
4368
4369			rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
4370			ocp_data = rcr & ~RCR_ACPT_ALL;
4371			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
4372			rxdy_gated_en(tp, true);
4373			ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA,
4374						 PLA_OOB_CTRL);
4375			if (!(ocp_data & RXFIFO_EMPTY)) {
4376				rxdy_gated_en(tp, false);
4377				ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4378				clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4379				smp_mb__after_atomic();
4380				ret = -EBUSY;
4381				goto out1;
4382			}
4383		}
4384
4385		clear_bit(WORK_ENABLE, &tp->flags);
4386		usb_kill_urb(tp->intr_urb);
4387
4388		tp->rtl_ops.autosuspend_en(tp, true);
4389
4390		if (netif_carrier_ok(netdev)) {
4391			struct napi_struct *napi = &tp->napi;
4392
4393			napi_disable(napi);
4394			rtl_stop_rx(tp);
4395			rxdy_gated_en(tp, false);
4396			ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr);
4397			napi_enable(napi);
4398		}
4399
4400		if (delay_autosuspend(tp)) {
4401			rtl8152_runtime_resume(tp);
4402			ret = -EBUSY;
4403		}
4404	}
4405
4406out1:
4407	return ret;
4408}
4409
4410static int rtl8152_system_suspend(struct r8152 *tp)
4411{
4412	struct net_device *netdev = tp->netdev;
4413	int ret = 0;
4414
4415	netif_device_detach(netdev);
4416
4417	if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) {
4418		struct napi_struct *napi = &tp->napi;
4419
4420		clear_bit(WORK_ENABLE, &tp->flags);
4421		usb_kill_urb(tp->intr_urb);
 
4422		napi_disable(napi);
4423		cancel_delayed_work_sync(&tp->schedule);
4424		tp->rtl_ops.down(tp);
4425		napi_enable(napi);
 
4426	}
4427
4428	return ret;
4429}
4430
4431static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message)
4432{
4433	struct r8152 *tp = usb_get_intfdata(intf);
4434	int ret;
4435
4436	mutex_lock(&tp->control);
4437
4438	if (PMSG_IS_AUTO(message))
4439		ret = rtl8152_runtime_suspend(tp);
4440	else
4441		ret = rtl8152_system_suspend(tp);
4442
4443	mutex_unlock(&tp->control);
4444
4445	return ret;
4446}
4447
4448static int rtl8152_resume(struct usb_interface *intf)
4449{
4450	struct r8152 *tp = usb_get_intfdata(intf);
4451	int ret;
4452
4453	mutex_lock(&tp->control);
4454
4455	if (test_bit(SELECTIVE_SUSPEND, &tp->flags))
4456		ret = rtl8152_runtime_resume(tp);
4457	else
4458		ret = rtl8152_system_resume(tp);
4459
4460	mutex_unlock(&tp->control);
4461
4462	return ret;
4463}
4464
4465static int rtl8152_reset_resume(struct usb_interface *intf)
4466{
4467	struct r8152 *tp = usb_get_intfdata(intf);
4468
4469	clear_bit(SELECTIVE_SUSPEND, &tp->flags);
4470	mutex_lock(&tp->control);
4471	tp->rtl_ops.init(tp);
4472	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
4473	mutex_unlock(&tp->control);
4474	return rtl8152_resume(intf);
4475}
4476
4477static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4478{
4479	struct r8152 *tp = netdev_priv(dev);
4480
4481	if (usb_autopm_get_interface(tp->intf) < 0)
4482		return;
4483
4484	if (!rtl_can_wakeup(tp)) {
4485		wol->supported = 0;
4486		wol->wolopts = 0;
4487	} else {
4488		mutex_lock(&tp->control);
4489		wol->supported = WAKE_ANY;
4490		wol->wolopts = __rtl_get_wol(tp);
4491		mutex_unlock(&tp->control);
4492	}
4493
4494	usb_autopm_put_interface(tp->intf);
4495}
4496
4497static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
4498{
4499	struct r8152 *tp = netdev_priv(dev);
4500	int ret;
4501
4502	if (!rtl_can_wakeup(tp))
4503		return -EOPNOTSUPP;
4504
 
 
 
4505	ret = usb_autopm_get_interface(tp->intf);
4506	if (ret < 0)
4507		goto out_set_wol;
4508
4509	mutex_lock(&tp->control);
4510
4511	__rtl_set_wol(tp, wol->wolopts);
4512	tp->saved_wolopts = wol->wolopts & WAKE_ANY;
4513
4514	mutex_unlock(&tp->control);
4515
4516	usb_autopm_put_interface(tp->intf);
4517
4518out_set_wol:
4519	return ret;
4520}
4521
4522static u32 rtl8152_get_msglevel(struct net_device *dev)
4523{
4524	struct r8152 *tp = netdev_priv(dev);
4525
4526	return tp->msg_enable;
4527}
4528
4529static void rtl8152_set_msglevel(struct net_device *dev, u32 value)
4530{
4531	struct r8152 *tp = netdev_priv(dev);
4532
4533	tp->msg_enable = value;
4534}
4535
4536static void rtl8152_get_drvinfo(struct net_device *netdev,
4537				struct ethtool_drvinfo *info)
4538{
4539	struct r8152 *tp = netdev_priv(netdev);
4540
4541	strlcpy(info->driver, MODULENAME, sizeof(info->driver));
4542	strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
4543	usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
4544}
4545
4546static
4547int rtl8152_get_link_ksettings(struct net_device *netdev,
4548			       struct ethtool_link_ksettings *cmd)
4549{
4550	struct r8152 *tp = netdev_priv(netdev);
4551	int ret;
4552
4553	if (!tp->mii.mdio_read)
4554		return -EOPNOTSUPP;
4555
4556	ret = usb_autopm_get_interface(tp->intf);
4557	if (ret < 0)
4558		goto out;
4559
4560	mutex_lock(&tp->control);
4561
4562	mii_ethtool_get_link_ksettings(&tp->mii, cmd);
4563
4564	mutex_unlock(&tp->control);
4565
4566	usb_autopm_put_interface(tp->intf);
4567
4568out:
4569	return ret;
4570}
4571
4572static int rtl8152_set_link_ksettings(struct net_device *dev,
4573				      const struct ethtool_link_ksettings *cmd)
4574{
4575	struct r8152 *tp = netdev_priv(dev);
 
4576	int ret;
4577
4578	ret = usb_autopm_get_interface(tp->intf);
4579	if (ret < 0)
4580		goto out;
4581
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4582	mutex_lock(&tp->control);
4583
4584	ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
4585				cmd->base.duplex);
4586	if (!ret) {
4587		tp->autoneg = cmd->base.autoneg;
4588		tp->speed = cmd->base.speed;
4589		tp->duplex = cmd->base.duplex;
 
4590	}
4591
4592	mutex_unlock(&tp->control);
4593
4594	usb_autopm_put_interface(tp->intf);
4595
4596out:
4597	return ret;
4598}
4599
4600static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = {
4601	"tx_packets",
4602	"rx_packets",
4603	"tx_errors",
4604	"rx_errors",
4605	"rx_missed",
4606	"align_errors",
4607	"tx_single_collisions",
4608	"tx_multi_collisions",
4609	"rx_unicast",
4610	"rx_broadcast",
4611	"rx_multicast",
4612	"tx_aborted",
4613	"tx_underrun",
4614};
4615
4616static int rtl8152_get_sset_count(struct net_device *dev, int sset)
4617{
4618	switch (sset) {
4619	case ETH_SS_STATS:
4620		return ARRAY_SIZE(rtl8152_gstrings);
4621	default:
4622		return -EOPNOTSUPP;
4623	}
4624}
4625
4626static void rtl8152_get_ethtool_stats(struct net_device *dev,
4627				      struct ethtool_stats *stats, u64 *data)
4628{
4629	struct r8152 *tp = netdev_priv(dev);
4630	struct tally_counter tally;
4631
4632	if (usb_autopm_get_interface(tp->intf) < 0)
4633		return;
4634
4635	generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA);
4636
4637	usb_autopm_put_interface(tp->intf);
4638
4639	data[0] = le64_to_cpu(tally.tx_packets);
4640	data[1] = le64_to_cpu(tally.rx_packets);
4641	data[2] = le64_to_cpu(tally.tx_errors);
4642	data[3] = le32_to_cpu(tally.rx_errors);
4643	data[4] = le16_to_cpu(tally.rx_missed);
4644	data[5] = le16_to_cpu(tally.align_errors);
4645	data[6] = le32_to_cpu(tally.tx_one_collision);
4646	data[7] = le32_to_cpu(tally.tx_multi_collision);
4647	data[8] = le64_to_cpu(tally.rx_unicast);
4648	data[9] = le64_to_cpu(tally.rx_broadcast);
4649	data[10] = le32_to_cpu(tally.rx_multicast);
4650	data[11] = le16_to_cpu(tally.tx_aborted);
4651	data[12] = le16_to_cpu(tally.tx_underrun);
4652}
4653
4654static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data)
4655{
4656	switch (stringset) {
4657	case ETH_SS_STATS:
4658		memcpy(data, *rtl8152_gstrings, sizeof(rtl8152_gstrings));
4659		break;
4660	}
4661}
4662
4663static int r8152_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4664{
4665	u32 ocp_data, lp, adv, supported = 0;
4666	u16 val;
4667
4668	val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE);
4669	supported = mmd_eee_cap_to_ethtool_sup_t(val);
4670
4671	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV);
4672	adv = mmd_eee_adv_to_ethtool_adv_t(val);
4673
4674	val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE);
4675	lp = mmd_eee_adv_to_ethtool_adv_t(val);
4676
4677	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4678	ocp_data &= EEE_RX_EN | EEE_TX_EN;
4679
4680	eee->eee_enabled = !!ocp_data;
4681	eee->eee_active = !!(supported & adv & lp);
4682	eee->supported = supported;
4683	eee->advertised = adv;
4684	eee->lp_advertised = lp;
4685
4686	return 0;
4687}
4688
4689static int r8152_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4690{
4691	u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4692
4693	r8152_eee_en(tp, eee->eee_enabled);
 
4694
4695	if (!eee->eee_enabled)
4696		val = 0;
4697
4698	r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, val);
4699
4700	return 0;
4701}
4702
4703static int r8153_get_eee(struct r8152 *tp, struct ethtool_eee *eee)
4704{
4705	u32 ocp_data, lp, adv, supported = 0;
4706	u16 val;
4707
4708	val = ocp_reg_read(tp, OCP_EEE_ABLE);
4709	supported = mmd_eee_cap_to_ethtool_sup_t(val);
4710
4711	val = ocp_reg_read(tp, OCP_EEE_ADV);
4712	adv = mmd_eee_adv_to_ethtool_adv_t(val);
4713
4714	val = ocp_reg_read(tp, OCP_EEE_LPABLE);
4715	lp = mmd_eee_adv_to_ethtool_adv_t(val);
4716
4717	ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR);
4718	ocp_data &= EEE_RX_EN | EEE_TX_EN;
4719
4720	eee->eee_enabled = !!ocp_data;
4721	eee->eee_active = !!(supported & adv & lp);
4722	eee->supported = supported;
4723	eee->advertised = adv;
4724	eee->lp_advertised = lp;
4725
4726	return 0;
4727}
4728
4729static int r8153_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4730{
4731	u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4732
4733	r8153_eee_en(tp, eee->eee_enabled);
4734
4735	if (!eee->eee_enabled)
4736		val = 0;
4737
4738	ocp_reg_write(tp, OCP_EEE_ADV, val);
4739
4740	return 0;
4741}
4742
4743static int r8153b_set_eee(struct r8152 *tp, struct ethtool_eee *eee)
4744{
4745	u16 val = ethtool_adv_to_mmd_eee_adv_t(eee->advertised);
4746
4747	r8153b_eee_en(tp, eee->eee_enabled);
4748
4749	if (!eee->eee_enabled)
4750		val = 0;
4751
4752	ocp_reg_write(tp, OCP_EEE_ADV, val);
4753
4754	return 0;
4755}
4756
4757static int
4758rtl_ethtool_get_eee(struct net_device *net, struct ethtool_eee *edata)
4759{
4760	struct r8152 *tp = netdev_priv(net);
4761	int ret;
4762
4763	ret = usb_autopm_get_interface(tp->intf);
4764	if (ret < 0)
4765		goto out;
4766
4767	mutex_lock(&tp->control);
4768
4769	ret = tp->rtl_ops.eee_get(tp, edata);
4770
4771	mutex_unlock(&tp->control);
4772
4773	usb_autopm_put_interface(tp->intf);
4774
4775out:
4776	return ret;
4777}
4778
4779static int
4780rtl_ethtool_set_eee(struct net_device *net, struct ethtool_eee *edata)
4781{
4782	struct r8152 *tp = netdev_priv(net);
4783	int ret;
4784
4785	ret = usb_autopm_get_interface(tp->intf);
4786	if (ret < 0)
4787		goto out;
4788
4789	mutex_lock(&tp->control);
4790
4791	ret = tp->rtl_ops.eee_set(tp, edata);
4792	if (!ret)
4793		ret = mii_nway_restart(&tp->mii);
4794
4795	mutex_unlock(&tp->control);
4796
4797	usb_autopm_put_interface(tp->intf);
4798
4799out:
4800	return ret;
4801}
4802
4803static int rtl8152_nway_reset(struct net_device *dev)
4804{
4805	struct r8152 *tp = netdev_priv(dev);
4806	int ret;
4807
4808	ret = usb_autopm_get_interface(tp->intf);
4809	if (ret < 0)
4810		goto out;
4811
4812	mutex_lock(&tp->control);
4813
4814	ret = mii_nway_restart(&tp->mii);
4815
4816	mutex_unlock(&tp->control);
4817
4818	usb_autopm_put_interface(tp->intf);
4819
4820out:
4821	return ret;
4822}
4823
4824static int rtl8152_get_coalesce(struct net_device *netdev,
4825				struct ethtool_coalesce *coalesce)
4826{
4827	struct r8152 *tp = netdev_priv(netdev);
4828
4829	switch (tp->version) {
4830	case RTL_VER_01:
4831	case RTL_VER_02:
4832	case RTL_VER_07:
4833		return -EOPNOTSUPP;
4834	default:
4835		break;
4836	}
4837
4838	coalesce->rx_coalesce_usecs = tp->coalesce;
4839
4840	return 0;
4841}
4842
4843static int rtl8152_set_coalesce(struct net_device *netdev,
4844				struct ethtool_coalesce *coalesce)
4845{
4846	struct r8152 *tp = netdev_priv(netdev);
4847	int ret;
4848
4849	switch (tp->version) {
4850	case RTL_VER_01:
4851	case RTL_VER_02:
4852	case RTL_VER_07:
4853		return -EOPNOTSUPP;
4854	default:
4855		break;
4856	}
4857
4858	if (coalesce->rx_coalesce_usecs > COALESCE_SLOW)
4859		return -EINVAL;
4860
4861	ret = usb_autopm_get_interface(tp->intf);
4862	if (ret < 0)
4863		return ret;
4864
4865	mutex_lock(&tp->control);
4866
4867	if (tp->coalesce != coalesce->rx_coalesce_usecs) {
4868		tp->coalesce = coalesce->rx_coalesce_usecs;
4869
4870		if (netif_running(tp->netdev) && netif_carrier_ok(netdev))
4871			r8153_set_rx_early_timeout(tp);
 
 
 
 
 
 
 
 
 
4872	}
4873
4874	mutex_unlock(&tp->control);
4875
4876	usb_autopm_put_interface(tp->intf);
4877
4878	return ret;
4879}
4880
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
4881static const struct ethtool_ops ops = {
4882	.get_drvinfo = rtl8152_get_drvinfo,
4883	.get_link = ethtool_op_get_link,
4884	.nway_reset = rtl8152_nway_reset,
4885	.get_msglevel = rtl8152_get_msglevel,
4886	.set_msglevel = rtl8152_set_msglevel,
4887	.get_wol = rtl8152_get_wol,
4888	.set_wol = rtl8152_set_wol,
4889	.get_strings = rtl8152_get_strings,
4890	.get_sset_count = rtl8152_get_sset_count,
4891	.get_ethtool_stats = rtl8152_get_ethtool_stats,
4892	.get_coalesce = rtl8152_get_coalesce,
4893	.set_coalesce = rtl8152_set_coalesce,
4894	.get_eee = rtl_ethtool_get_eee,
4895	.set_eee = rtl_ethtool_set_eee,
4896	.get_link_ksettings = rtl8152_get_link_ksettings,
4897	.set_link_ksettings = rtl8152_set_link_ksettings,
 
 
 
 
4898};
4899
4900static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
4901{
4902	struct r8152 *tp = netdev_priv(netdev);
4903	struct mii_ioctl_data *data = if_mii(rq);
4904	int res;
4905
4906	if (test_bit(RTL8152_UNPLUG, &tp->flags))
4907		return -ENODEV;
4908
4909	res = usb_autopm_get_interface(tp->intf);
4910	if (res < 0)
4911		goto out;
4912
4913	switch (cmd) {
4914	case SIOCGMIIPHY:
4915		data->phy_id = R8152_PHY_ID; /* Internal PHY */
4916		break;
4917
4918	case SIOCGMIIREG:
4919		mutex_lock(&tp->control);
4920		data->val_out = r8152_mdio_read(tp, data->reg_num);
4921		mutex_unlock(&tp->control);
4922		break;
4923
4924	case SIOCSMIIREG:
4925		if (!capable(CAP_NET_ADMIN)) {
4926			res = -EPERM;
4927			break;
4928		}
4929		mutex_lock(&tp->control);
4930		r8152_mdio_write(tp, data->reg_num, data->val_in);
4931		mutex_unlock(&tp->control);
4932		break;
4933
4934	default:
4935		res = -EOPNOTSUPP;
4936	}
4937
4938	usb_autopm_put_interface(tp->intf);
4939
4940out:
4941	return res;
4942}
4943
4944static int rtl8152_change_mtu(struct net_device *dev, int new_mtu)
4945{
4946	struct r8152 *tp = netdev_priv(dev);
4947	int ret;
4948
4949	switch (tp->version) {
4950	case RTL_VER_01:
4951	case RTL_VER_02:
4952	case RTL_VER_07:
4953		dev->mtu = new_mtu;
4954		return 0;
4955	default:
4956		break;
4957	}
4958
4959	ret = usb_autopm_get_interface(tp->intf);
4960	if (ret < 0)
4961		return ret;
4962
4963	mutex_lock(&tp->control);
4964
4965	dev->mtu = new_mtu;
4966
4967	if (netif_running(dev)) {
4968		u32 rms = new_mtu + VLAN_ETH_HLEN + ETH_FCS_LEN;
4969
4970		ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rms);
4971
4972		if (netif_carrier_ok(dev))
4973			r8153_set_rx_early_size(tp);
4974	}
4975
4976	mutex_unlock(&tp->control);
4977
4978	usb_autopm_put_interface(tp->intf);
4979
4980	return ret;
4981}
4982
4983static const struct net_device_ops rtl8152_netdev_ops = {
4984	.ndo_open		= rtl8152_open,
4985	.ndo_stop		= rtl8152_close,
4986	.ndo_do_ioctl		= rtl8152_ioctl,
4987	.ndo_start_xmit		= rtl8152_start_xmit,
4988	.ndo_tx_timeout		= rtl8152_tx_timeout,
4989	.ndo_set_features	= rtl8152_set_features,
4990	.ndo_set_rx_mode	= rtl8152_set_rx_mode,
4991	.ndo_set_mac_address	= rtl8152_set_mac_address,
4992	.ndo_change_mtu		= rtl8152_change_mtu,
4993	.ndo_validate_addr	= eth_validate_addr,
4994	.ndo_features_check	= rtl8152_features_check,
4995};
4996
4997static void rtl8152_unload(struct r8152 *tp)
4998{
4999	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5000		return;
5001
5002	if (tp->version != RTL_VER_01)
5003		r8152_power_cut_en(tp, true);
5004}
5005
5006static void rtl8153_unload(struct r8152 *tp)
5007{
5008	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5009		return;
5010
5011	r8153_power_cut_en(tp, false);
5012}
5013
5014static void rtl8153b_unload(struct r8152 *tp)
5015{
5016	if (test_bit(RTL8152_UNPLUG, &tp->flags))
5017		return;
5018
5019	r8153b_power_cut_en(tp, false);
5020}
5021
5022static int rtl_ops_init(struct r8152 *tp)
5023{
5024	struct rtl_ops *ops = &tp->rtl_ops;
5025	int ret = 0;
5026
5027	switch (tp->version) {
5028	case RTL_VER_01:
5029	case RTL_VER_02:
5030	case RTL_VER_07:
5031		ops->init		= r8152b_init;
5032		ops->enable		= rtl8152_enable;
5033		ops->disable		= rtl8152_disable;
5034		ops->up			= rtl8152_up;
5035		ops->down		= rtl8152_down;
5036		ops->unload		= rtl8152_unload;
5037		ops->eee_get		= r8152_get_eee;
5038		ops->eee_set		= r8152_set_eee;
5039		ops->in_nway		= rtl8152_in_nway;
5040		ops->hw_phy_cfg		= r8152b_hw_phy_cfg;
5041		ops->autosuspend_en	= rtl_runtime_suspend_enable;
 
 
 
5042		break;
5043
5044	case RTL_VER_03:
5045	case RTL_VER_04:
5046	case RTL_VER_05:
5047	case RTL_VER_06:
5048		ops->init		= r8153_init;
5049		ops->enable		= rtl8153_enable;
5050		ops->disable		= rtl8153_disable;
5051		ops->up			= rtl8153_up;
5052		ops->down		= rtl8153_down;
5053		ops->unload		= rtl8153_unload;
5054		ops->eee_get		= r8153_get_eee;
5055		ops->eee_set		= r8153_set_eee;
5056		ops->in_nway		= rtl8153_in_nway;
5057		ops->hw_phy_cfg		= r8153_hw_phy_cfg;
5058		ops->autosuspend_en	= rtl8153_runtime_enable;
 
 
 
5059		break;
5060
5061	case RTL_VER_08:
5062	case RTL_VER_09:
5063		ops->init		= r8153b_init;
5064		ops->enable		= rtl8153_enable;
5065		ops->disable		= rtl8153b_disable;
5066		ops->up			= rtl8153b_up;
5067		ops->down		= rtl8153b_down;
5068		ops->unload		= rtl8153b_unload;
5069		ops->eee_get		= r8153_get_eee;
5070		ops->eee_set		= r8153b_set_eee;
5071		ops->in_nway		= rtl8153_in_nway;
5072		ops->hw_phy_cfg		= r8153b_hw_phy_cfg;
5073		ops->autosuspend_en	= rtl8153b_runtime_enable;
 
 
 
5074		break;
5075
5076	default:
5077		ret = -ENODEV;
5078		netif_err(tp, probe, tp->netdev, "Unknown Device\n");
5079		break;
5080	}
5081
5082	return ret;
5083}
5084
5085static u8 rtl_get_version(struct usb_interface *intf)
5086{
5087	struct usb_device *udev = interface_to_usbdev(intf);
5088	u32 ocp_data = 0;
5089	__le32 *tmp;
5090	u8 version;
5091	int ret;
5092
5093	tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
5094	if (!tmp)
5095		return 0;
5096
5097	ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
5098			      RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
5099			      PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 500);
5100	if (ret > 0)
5101		ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK;
5102
5103	kfree(tmp);
5104
5105	switch (ocp_data) {
5106	case 0x4c00:
5107		version = RTL_VER_01;
5108		break;
5109	case 0x4c10:
5110		version = RTL_VER_02;
5111		break;
5112	case 0x5c00:
5113		version = RTL_VER_03;
5114		break;
5115	case 0x5c10:
5116		version = RTL_VER_04;
5117		break;
5118	case 0x5c20:
5119		version = RTL_VER_05;
5120		break;
5121	case 0x5c30:
5122		version = RTL_VER_06;
5123		break;
5124	case 0x4800:
5125		version = RTL_VER_07;
5126		break;
5127	case 0x6000:
5128		version = RTL_VER_08;
5129		break;
5130	case 0x6010:
5131		version = RTL_VER_09;
5132		break;
5133	default:
5134		version = RTL_VER_UNKNOWN;
5135		dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
5136		break;
5137	}
5138
5139	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
5140
5141	return version;
5142}
5143
5144static int rtl8152_probe(struct usb_interface *intf,
5145			 const struct usb_device_id *id)
5146{
5147	struct usb_device *udev = interface_to_usbdev(intf);
5148	u8 version = rtl_get_version(intf);
5149	struct r8152 *tp;
5150	struct net_device *netdev;
5151	int ret;
5152
5153	if (version == RTL_VER_UNKNOWN)
5154		return -ENODEV;
5155
5156	if (udev->actconfig->desc.bConfigurationValue != 1) {
5157		usb_driver_set_configuration(udev, 1);
5158		return -ENODEV;
5159	}
5160
5161	usb_reset_device(udev);
5162	netdev = alloc_etherdev(sizeof(struct r8152));
5163	if (!netdev) {
5164		dev_err(&intf->dev, "Out of memory\n");
5165		return -ENOMEM;
5166	}
5167
5168	SET_NETDEV_DEV(netdev, &intf->dev);
5169	tp = netdev_priv(netdev);
5170	tp->msg_enable = 0x7FFF;
5171
5172	tp->udev = udev;
5173	tp->netdev = netdev;
5174	tp->intf = intf;
5175	tp->version = version;
5176
5177	switch (version) {
5178	case RTL_VER_01:
5179	case RTL_VER_02:
5180	case RTL_VER_07:
5181		tp->mii.supports_gmii = 0;
5182		break;
5183	default:
5184		tp->mii.supports_gmii = 1;
5185		break;
5186	}
5187
5188	ret = rtl_ops_init(tp);
5189	if (ret)
5190		goto out;
5191
5192	mutex_init(&tp->control);
5193	INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t);
5194	INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t);
 
 
5195
5196	netdev->netdev_ops = &rtl8152_netdev_ops;
5197	netdev->watchdog_timeo = RTL8152_TX_TIMEOUT;
5198
5199	netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5200			    NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM |
5201			    NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX |
5202			    NETIF_F_HW_VLAN_CTAG_TX;
5203	netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG |
5204			      NETIF_F_TSO | NETIF_F_FRAGLIST |
5205			      NETIF_F_IPV6_CSUM | NETIF_F_TSO6 |
5206			      NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX;
5207	netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
5208				NETIF_F_HIGHDMA | NETIF_F_FRAGLIST |
5209				NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
5210
5211	if (tp->version == RTL_VER_01) {
5212		netdev->features &= ~NETIF_F_RXCSUM;
5213		netdev->hw_features &= ~NETIF_F_RXCSUM;
5214	}
5215
5216	if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 &&
5217	    udev->serial && !strcmp(udev->serial, "000001000000")) {
5218		dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation");
5219		set_bit(DELL_TB_RX_AGG_BUG, &tp->flags);
5220	}
5221
5222	netdev->ethtool_ops = &ops;
5223	netif_set_gso_max_size(netdev, RTL_LIMITED_TSO_SIZE);
5224
5225	/* MTU range: 68 - 1500 or 9194 */
5226	netdev->min_mtu = ETH_MIN_MTU;
5227	switch (tp->version) {
5228	case RTL_VER_01:
5229	case RTL_VER_02:
5230		netdev->max_mtu = ETH_DATA_LEN;
5231		break;
5232	default:
5233		netdev->max_mtu = RTL8153_MAX_MTU;
5234		break;
5235	}
5236
5237	tp->mii.dev = netdev;
5238	tp->mii.mdio_read = read_mii_word;
5239	tp->mii.mdio_write = write_mii_word;
5240	tp->mii.phy_id_mask = 0x3f;
5241	tp->mii.reg_num_mask = 0x1f;
5242	tp->mii.phy_id = R8152_PHY_ID;
5243
5244	tp->autoneg = AUTONEG_ENABLE;
5245	tp->speed = tp->mii.supports_gmii ? SPEED_1000 : SPEED_100;
 
 
 
 
 
 
5246	tp->duplex = DUPLEX_FULL;
5247
 
 
 
5248	intf->needs_remote_wakeup = 1;
5249
5250	tp->rtl_ops.init(tp);
5251	queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0);
5252	set_ethernet_addr(tp);
5253
5254	usb_set_intfdata(intf, tp);
5255	netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
5256
5257	ret = register_netdev(netdev);
5258	if (ret != 0) {
5259		netif_err(tp, probe, netdev, "couldn't register the device\n");
5260		goto out1;
5261	}
5262
5263	if (!rtl_can_wakeup(tp))
5264		__rtl_set_wol(tp, 0);
5265
5266	tp->saved_wolopts = __rtl_get_wol(tp);
5267	if (tp->saved_wolopts)
5268		device_set_wakeup_enable(&udev->dev, true);
5269	else
5270		device_set_wakeup_enable(&udev->dev, false);
5271
5272	netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION);
5273
5274	return 0;
5275
5276out1:
5277	netif_napi_del(&tp->napi);
5278	usb_set_intfdata(intf, NULL);
5279out:
5280	free_netdev(netdev);
5281	return ret;
5282}
5283
5284static void rtl8152_disconnect(struct usb_interface *intf)
5285{
5286	struct r8152 *tp = usb_get_intfdata(intf);
5287
5288	usb_set_intfdata(intf, NULL);
5289	if (tp) {
5290		struct usb_device *udev = tp->udev;
5291
5292		if (udev->state == USB_STATE_NOTATTACHED)
5293			set_bit(RTL8152_UNPLUG, &tp->flags);
5294
5295		netif_napi_del(&tp->napi);
5296		unregister_netdev(tp->netdev);
 
5297		cancel_delayed_work_sync(&tp->hw_phy_work);
5298		tp->rtl_ops.unload(tp);
5299		free_netdev(tp->netdev);
5300	}
5301}
5302
5303#define REALTEK_USB_DEVICE(vend, prod)	\
5304	.match_flags = USB_DEVICE_ID_MATCH_DEVICE | \
5305		       USB_DEVICE_ID_MATCH_INT_CLASS, \
5306	.idVendor = (vend), \
5307	.idProduct = (prod), \
5308	.bInterfaceClass = USB_CLASS_VENDOR_SPEC \
5309}, \
5310{ \
5311	.match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
5312		       USB_DEVICE_ID_MATCH_DEVICE, \
5313	.idVendor = (vend), \
5314	.idProduct = (prod), \
5315	.bInterfaceClass = USB_CLASS_COMM, \
5316	.bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
5317	.bInterfaceProtocol = USB_CDC_PROTO_NONE
5318
5319/* table of devices that work with this driver */
5320static const struct usb_device_id rtl8152_table[] = {
5321	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
5322	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
5323	{REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
5324	{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
5325	{REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
5326	{REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101)},
5327	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f)},
5328	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062)},
5329	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069)},
5330	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205)},
5331	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c)},
5332	{REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214)},
 
5333	{REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041)},
5334	{REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff)},
5335	{REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601)},
5336	{}
5337};
5338
5339MODULE_DEVICE_TABLE(usb, rtl8152_table);
5340
5341static struct usb_driver rtl8152_driver = {
5342	.name =		MODULENAME,
5343	.id_table =	rtl8152_table,
5344	.probe =	rtl8152_probe,
5345	.disconnect =	rtl8152_disconnect,
5346	.suspend =	rtl8152_suspend,
5347	.resume =	rtl8152_resume,
5348	.reset_resume =	rtl8152_reset_resume,
5349	.pre_reset =	rtl8152_pre_reset,
5350	.post_reset =	rtl8152_post_reset,
5351	.supports_autosuspend = 1,
5352	.disable_hub_initiated_lpm = 1,
5353};
5354
5355module_usb_driver(rtl8152_driver);
5356
5357MODULE_AUTHOR(DRIVER_AUTHOR);
5358MODULE_DESCRIPTION(DRIVER_DESC);
5359MODULE_LICENSE("GPL");
5360MODULE_VERSION(DRIVER_VERSION);