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1/*
2 * Driver for the Texas Instruments DP83867 PHY
3 *
4 * Copyright (C) 2015 Texas Instruments Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/ethtool.h>
17#include <linux/kernel.h>
18#include <linux/mii.h>
19#include <linux/module.h>
20#include <linux/of.h>
21#include <linux/phy.h>
22
23#include <dt-bindings/net/ti-dp83867.h>
24
25#define DP83867_PHY_ID 0x2000a231
26#define DP83867_DEVADDR 0x1f
27
28#define MII_DP83867_PHYCTRL 0x10
29#define MII_DP83867_MICR 0x12
30#define MII_DP83867_ISR 0x13
31#define DP83867_CTRL 0x1f
32#define DP83867_CFG3 0x1e
33
34/* Extended Registers */
35#define DP83867_CFG4 0x0031
36#define DP83867_RGMIICTL 0x0032
37#define DP83867_STRAP_STS1 0x006E
38#define DP83867_RGMIIDCTL 0x0086
39#define DP83867_IO_MUX_CFG 0x0170
40
41#define DP83867_SW_RESET BIT(15)
42#define DP83867_SW_RESTART BIT(14)
43
44/* MICR Interrupt bits */
45#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
46#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
47#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
48#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
49#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
50#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
51#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
52#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
53#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
54#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
55#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
56#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
57
58/* RGMIICTL bits */
59#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
60#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
61
62/* STRAP_STS1 bits */
63#define DP83867_STRAP_STS1_RESERVED BIT(11)
64
65/* PHY CTRL bits */
66#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
67#define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14)
68#define DP83867_PHYCR_RESERVED_MASK BIT(11)
69
70/* RGMIIDCTL bits */
71#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
72
73/* IO_MUX_CFG bits */
74#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL 0x1f
75
76#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
77#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
78#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
79#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
80
81/* CFG4 bits */
82#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
83
84enum {
85 DP83867_PORT_MIRROING_KEEP,
86 DP83867_PORT_MIRROING_EN,
87 DP83867_PORT_MIRROING_DIS,
88};
89
90struct dp83867_private {
91 int rx_id_delay;
92 int tx_id_delay;
93 int fifo_depth;
94 int io_impedance;
95 int port_mirroring;
96 bool rxctrl_strap_quirk;
97 int clk_output_sel;
98};
99
100static int dp83867_ack_interrupt(struct phy_device *phydev)
101{
102 int err = phy_read(phydev, MII_DP83867_ISR);
103
104 if (err < 0)
105 return err;
106
107 return 0;
108}
109
110static int dp83867_config_intr(struct phy_device *phydev)
111{
112 int micr_status;
113
114 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
115 micr_status = phy_read(phydev, MII_DP83867_MICR);
116 if (micr_status < 0)
117 return micr_status;
118
119 micr_status |=
120 (MII_DP83867_MICR_AN_ERR_INT_EN |
121 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
122 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
123 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
124 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
125 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
126
127 return phy_write(phydev, MII_DP83867_MICR, micr_status);
128 }
129
130 micr_status = 0x0;
131 return phy_write(phydev, MII_DP83867_MICR, micr_status);
132}
133
134static int dp83867_config_port_mirroring(struct phy_device *phydev)
135{
136 struct dp83867_private *dp83867 =
137 (struct dp83867_private *)phydev->priv;
138 u16 val;
139
140 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
141
142 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
143 val |= DP83867_CFG4_PORT_MIRROR_EN;
144 else
145 val &= ~DP83867_CFG4_PORT_MIRROR_EN;
146
147 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
148
149 return 0;
150}
151
152#ifdef CONFIG_OF_MDIO
153static int dp83867_of_init(struct phy_device *phydev)
154{
155 struct dp83867_private *dp83867 = phydev->priv;
156 struct device *dev = &phydev->mdio.dev;
157 struct device_node *of_node = dev->of_node;
158 int ret;
159
160 if (!of_node)
161 return -ENODEV;
162
163 dp83867->io_impedance = -EINVAL;
164
165 /* Optional configuration */
166 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
167 &dp83867->clk_output_sel);
168 if (ret || dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK)
169 /* Keep the default value if ti,clk-output-sel is not set
170 * or too high
171 */
172 dp83867->clk_output_sel = DP83867_CLK_O_SEL_REF_CLK;
173
174 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
175 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
176 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
177 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
178
179 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
180 "ti,dp83867-rxctrl-strap-quirk");
181
182 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
183 &dp83867->rx_id_delay);
184 if (ret &&
185 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
186 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID))
187 return ret;
188
189 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
190 &dp83867->tx_id_delay);
191 if (ret &&
192 (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
193 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID))
194 return ret;
195
196 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
197 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
198
199 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
200 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
201
202 return of_property_read_u32(of_node, "ti,fifo-depth",
203 &dp83867->fifo_depth);
204}
205#else
206static int dp83867_of_init(struct phy_device *phydev)
207{
208 return 0;
209}
210#endif /* CONFIG_OF_MDIO */
211
212static int dp83867_config_init(struct phy_device *phydev)
213{
214 struct dp83867_private *dp83867;
215 int ret, val, bs;
216 u16 delay;
217
218 if (!phydev->priv) {
219 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
220 GFP_KERNEL);
221 if (!dp83867)
222 return -ENOMEM;
223
224 phydev->priv = dp83867;
225 ret = dp83867_of_init(phydev);
226 if (ret)
227 return ret;
228 } else {
229 dp83867 = (struct dp83867_private *)phydev->priv;
230 }
231
232 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
233 if (dp83867->rxctrl_strap_quirk) {
234 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4);
235 val &= ~BIT(7);
236 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4, val);
237 }
238
239 if (phy_interface_is_rgmii(phydev)) {
240 val = phy_read(phydev, MII_DP83867_PHYCTRL);
241 if (val < 0)
242 return val;
243 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
244 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
245
246 /* The code below checks if "port mirroring" N/A MODE4 has been
247 * enabled during power on bootstrap.
248 *
249 * Such N/A mode enabled by mistake can put PHY IC in some
250 * internal testing mode and disable RGMII transmission.
251 *
252 * In this particular case one needs to check STRAP_STS1
253 * register's bit 11 (marked as RESERVED).
254 */
255
256 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
257 if (bs & DP83867_STRAP_STS1_RESERVED)
258 val &= ~DP83867_PHYCR_RESERVED_MASK;
259
260 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
261 if (ret)
262 return ret;
263 }
264
265 if ((phydev->interface >= PHY_INTERFACE_MODE_RGMII_ID) &&
266 (phydev->interface <= PHY_INTERFACE_MODE_RGMII_RXID)) {
267 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
268
269 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
270 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
271
272 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
273 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
274
275 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
276 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
277
278 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
279
280 delay = (dp83867->rx_id_delay |
281 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
282
283 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
284 delay);
285
286 if (dp83867->io_impedance >= 0) {
287 val = phy_read_mmd(phydev, DP83867_DEVADDR,
288 DP83867_IO_MUX_CFG);
289
290 val &= ~DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
291 val |= dp83867->io_impedance &
292 DP83867_IO_MUX_CFG_IO_IMPEDANCE_CTRL;
293
294 phy_write_mmd(phydev, DP83867_DEVADDR,
295 DP83867_IO_MUX_CFG, val);
296 }
297 }
298
299 /* Enable Interrupt output INT_OE in CFG3 register */
300 if (phy_interrupt_is_valid(phydev)) {
301 val = phy_read(phydev, DP83867_CFG3);
302 val |= BIT(7);
303 phy_write(phydev, DP83867_CFG3, val);
304 }
305
306 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
307 dp83867_config_port_mirroring(phydev);
308
309 /* Clock output selection if muxing property is set */
310 if (dp83867->clk_output_sel != DP83867_CLK_O_SEL_REF_CLK) {
311 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG);
312 val &= ~DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
313 val |= (dp83867->clk_output_sel << DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT);
314 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG, val);
315 }
316
317 return 0;
318}
319
320static int dp83867_phy_reset(struct phy_device *phydev)
321{
322 int err;
323
324 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
325 if (err < 0)
326 return err;
327
328 return dp83867_config_init(phydev);
329}
330
331static struct phy_driver dp83867_driver[] = {
332 {
333 .phy_id = DP83867_PHY_ID,
334 .phy_id_mask = 0xfffffff0,
335 .name = "TI DP83867",
336 .features = PHY_GBIT_FEATURES,
337 .flags = PHY_HAS_INTERRUPT,
338
339 .config_init = dp83867_config_init,
340 .soft_reset = dp83867_phy_reset,
341
342 /* IRQ related */
343 .ack_interrupt = dp83867_ack_interrupt,
344 .config_intr = dp83867_config_intr,
345
346 .suspend = genphy_suspend,
347 .resume = genphy_resume,
348 },
349};
350module_phy_driver(dp83867_driver);
351
352static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
353 { DP83867_PHY_ID, 0xfffffff0 },
354 { }
355};
356
357MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
358
359MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
360MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
361MODULE_LICENSE("GPL");
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Driver for the Texas Instruments DP83867 PHY
4 *
5 * Copyright (C) 2015 Texas Instruments Inc.
6 */
7
8#include <linux/ethtool.h>
9#include <linux/kernel.h>
10#include <linux/mii.h>
11#include <linux/module.h>
12#include <linux/of.h>
13#include <linux/phy.h>
14#include <linux/delay.h>
15
16#include <dt-bindings/net/ti-dp83867.h>
17
18#define DP83867_PHY_ID 0x2000a231
19#define DP83867_DEVADDR 0x1f
20
21#define MII_DP83867_PHYCTRL 0x10
22#define MII_DP83867_MICR 0x12
23#define MII_DP83867_ISR 0x13
24#define DP83867_CTRL 0x1f
25#define DP83867_CFG3 0x1e
26
27/* Extended Registers */
28#define DP83867_CFG4 0x0031
29#define DP83867_CFG4_SGMII_ANEG_MASK (BIT(5) | BIT(6))
30#define DP83867_CFG4_SGMII_ANEG_TIMER_11MS (3 << 5)
31#define DP83867_CFG4_SGMII_ANEG_TIMER_800US (2 << 5)
32#define DP83867_CFG4_SGMII_ANEG_TIMER_2US (1 << 5)
33#define DP83867_CFG4_SGMII_ANEG_TIMER_16MS (0 << 5)
34
35#define DP83867_RGMIICTL 0x0032
36#define DP83867_STRAP_STS1 0x006E
37#define DP83867_STRAP_STS2 0x006f
38#define DP83867_RGMIIDCTL 0x0086
39#define DP83867_IO_MUX_CFG 0x0170
40#define DP83867_SGMIICTL 0x00D3
41#define DP83867_10M_SGMII_CFG 0x016F
42#define DP83867_10M_SGMII_RATE_ADAPT_MASK BIT(7)
43
44#define DP83867_SW_RESET BIT(15)
45#define DP83867_SW_RESTART BIT(14)
46
47/* MICR Interrupt bits */
48#define MII_DP83867_MICR_AN_ERR_INT_EN BIT(15)
49#define MII_DP83867_MICR_SPEED_CHNG_INT_EN BIT(14)
50#define MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN BIT(13)
51#define MII_DP83867_MICR_PAGE_RXD_INT_EN BIT(12)
52#define MII_DP83867_MICR_AUTONEG_COMP_INT_EN BIT(11)
53#define MII_DP83867_MICR_LINK_STS_CHNG_INT_EN BIT(10)
54#define MII_DP83867_MICR_FALSE_CARRIER_INT_EN BIT(8)
55#define MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN BIT(4)
56#define MII_DP83867_MICR_WOL_INT_EN BIT(3)
57#define MII_DP83867_MICR_XGMII_ERR_INT_EN BIT(2)
58#define MII_DP83867_MICR_POL_CHNG_INT_EN BIT(1)
59#define MII_DP83867_MICR_JABBER_INT_EN BIT(0)
60
61/* RGMIICTL bits */
62#define DP83867_RGMII_TX_CLK_DELAY_EN BIT(1)
63#define DP83867_RGMII_RX_CLK_DELAY_EN BIT(0)
64
65/* SGMIICTL bits */
66#define DP83867_SGMII_TYPE BIT(14)
67
68/* STRAP_STS1 bits */
69#define DP83867_STRAP_STS1_RESERVED BIT(11)
70
71/* STRAP_STS2 bits */
72#define DP83867_STRAP_STS2_CLK_SKEW_TX_MASK GENMASK(6, 4)
73#define DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT 4
74#define DP83867_STRAP_STS2_CLK_SKEW_RX_MASK GENMASK(2, 0)
75#define DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT 0
76#define DP83867_STRAP_STS2_CLK_SKEW_NONE BIT(2)
77
78/* PHY CTRL bits */
79#define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14
80#define DP83867_PHYCR_FIFO_DEPTH_MAX 0x03
81#define DP83867_PHYCR_FIFO_DEPTH_MASK GENMASK(15, 14)
82#define DP83867_PHYCR_RESERVED_MASK BIT(11)
83
84/* RGMIIDCTL bits */
85#define DP83867_RGMII_TX_CLK_DELAY_MAX 0xf
86#define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4
87#define DP83867_RGMII_RX_CLK_DELAY_MAX 0xf
88#define DP83867_RGMII_RX_CLK_DELAY_SHIFT 0
89
90/* IO_MUX_CFG bits */
91#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK 0x1f
92#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX 0x0
93#define DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN 0x1f
94#define DP83867_IO_MUX_CFG_CLK_O_DISABLE BIT(6)
95#define DP83867_IO_MUX_CFG_CLK_O_SEL_MASK (0x1f << 8)
96#define DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT 8
97
98/* CFG4 bits */
99#define DP83867_CFG4_PORT_MIRROR_EN BIT(0)
100
101enum {
102 DP83867_PORT_MIRROING_KEEP,
103 DP83867_PORT_MIRROING_EN,
104 DP83867_PORT_MIRROING_DIS,
105};
106
107struct dp83867_private {
108 u32 rx_id_delay;
109 u32 tx_id_delay;
110 u32 fifo_depth;
111 int io_impedance;
112 int port_mirroring;
113 bool rxctrl_strap_quirk;
114 bool set_clk_output;
115 u32 clk_output_sel;
116 bool sgmii_ref_clk_en;
117};
118
119static int dp83867_ack_interrupt(struct phy_device *phydev)
120{
121 int err = phy_read(phydev, MII_DP83867_ISR);
122
123 if (err < 0)
124 return err;
125
126 return 0;
127}
128
129static int dp83867_config_intr(struct phy_device *phydev)
130{
131 int micr_status;
132
133 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
134 micr_status = phy_read(phydev, MII_DP83867_MICR);
135 if (micr_status < 0)
136 return micr_status;
137
138 micr_status |=
139 (MII_DP83867_MICR_AN_ERR_INT_EN |
140 MII_DP83867_MICR_SPEED_CHNG_INT_EN |
141 MII_DP83867_MICR_AUTONEG_COMP_INT_EN |
142 MII_DP83867_MICR_LINK_STS_CHNG_INT_EN |
143 MII_DP83867_MICR_DUP_MODE_CHNG_INT_EN |
144 MII_DP83867_MICR_SLEEP_MODE_CHNG_INT_EN);
145
146 return phy_write(phydev, MII_DP83867_MICR, micr_status);
147 }
148
149 micr_status = 0x0;
150 return phy_write(phydev, MII_DP83867_MICR, micr_status);
151}
152
153static int dp83867_config_port_mirroring(struct phy_device *phydev)
154{
155 struct dp83867_private *dp83867 =
156 (struct dp83867_private *)phydev->priv;
157
158 if (dp83867->port_mirroring == DP83867_PORT_MIRROING_EN)
159 phy_set_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
160 DP83867_CFG4_PORT_MIRROR_EN);
161 else
162 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
163 DP83867_CFG4_PORT_MIRROR_EN);
164 return 0;
165}
166
167#ifdef CONFIG_OF_MDIO
168static int dp83867_of_init(struct phy_device *phydev)
169{
170 struct dp83867_private *dp83867 = phydev->priv;
171 struct device *dev = &phydev->mdio.dev;
172 struct device_node *of_node = dev->of_node;
173 int ret;
174
175 if (!of_node)
176 return -ENODEV;
177
178 /* Optional configuration */
179 ret = of_property_read_u32(of_node, "ti,clk-output-sel",
180 &dp83867->clk_output_sel);
181 /* If not set, keep default */
182 if (!ret) {
183 dp83867->set_clk_output = true;
184 /* Valid values are 0 to DP83867_CLK_O_SEL_REF_CLK or
185 * DP83867_CLK_O_SEL_OFF.
186 */
187 if (dp83867->clk_output_sel > DP83867_CLK_O_SEL_REF_CLK &&
188 dp83867->clk_output_sel != DP83867_CLK_O_SEL_OFF) {
189 phydev_err(phydev, "ti,clk-output-sel value %u out of range\n",
190 dp83867->clk_output_sel);
191 return -EINVAL;
192 }
193 }
194
195 if (of_property_read_bool(of_node, "ti,max-output-impedance"))
196 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MAX;
197 else if (of_property_read_bool(of_node, "ti,min-output-impedance"))
198 dp83867->io_impedance = DP83867_IO_MUX_CFG_IO_IMPEDANCE_MIN;
199 else
200 dp83867->io_impedance = -1; /* leave at default */
201
202 dp83867->rxctrl_strap_quirk = of_property_read_bool(of_node,
203 "ti,dp83867-rxctrl-strap-quirk");
204
205 dp83867->sgmii_ref_clk_en = of_property_read_bool(of_node,
206 "ti,sgmii-ref-clock-output-enable");
207
208 /* Existing behavior was to use default pin strapping delay in rgmii
209 * mode, but rgmii should have meant no delay. Warn existing users.
210 */
211 if (phydev->interface == PHY_INTERFACE_MODE_RGMII) {
212 const u16 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS2);
213 const u16 txskew = (val & DP83867_STRAP_STS2_CLK_SKEW_TX_MASK) >>
214 DP83867_STRAP_STS2_CLK_SKEW_TX_SHIFT;
215 const u16 rxskew = (val & DP83867_STRAP_STS2_CLK_SKEW_RX_MASK) >>
216 DP83867_STRAP_STS2_CLK_SKEW_RX_SHIFT;
217
218 if (txskew != DP83867_STRAP_STS2_CLK_SKEW_NONE ||
219 rxskew != DP83867_STRAP_STS2_CLK_SKEW_NONE)
220 phydev_warn(phydev,
221 "PHY has delays via pin strapping, but phy-mode = 'rgmii'\n"
222 "Should be 'rgmii-id' to use internal delays\n");
223 }
224
225 /* RX delay *must* be specified if internal delay of RX is used. */
226 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
227 phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) {
228 ret = of_property_read_u32(of_node, "ti,rx-internal-delay",
229 &dp83867->rx_id_delay);
230 if (ret) {
231 phydev_err(phydev, "ti,rx-internal-delay must be specified\n");
232 return ret;
233 }
234 if (dp83867->rx_id_delay > DP83867_RGMII_RX_CLK_DELAY_MAX) {
235 phydev_err(phydev,
236 "ti,rx-internal-delay value of %u out of range\n",
237 dp83867->rx_id_delay);
238 return -EINVAL;
239 }
240 }
241
242 /* TX delay *must* be specified if internal delay of RX is used. */
243 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
244 phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) {
245 ret = of_property_read_u32(of_node, "ti,tx-internal-delay",
246 &dp83867->tx_id_delay);
247 if (ret) {
248 phydev_err(phydev, "ti,tx-internal-delay must be specified\n");
249 return ret;
250 }
251 if (dp83867->tx_id_delay > DP83867_RGMII_TX_CLK_DELAY_MAX) {
252 phydev_err(phydev,
253 "ti,tx-internal-delay value of %u out of range\n",
254 dp83867->tx_id_delay);
255 return -EINVAL;
256 }
257 }
258
259 if (of_property_read_bool(of_node, "enet-phy-lane-swap"))
260 dp83867->port_mirroring = DP83867_PORT_MIRROING_EN;
261
262 if (of_property_read_bool(of_node, "enet-phy-lane-no-swap"))
263 dp83867->port_mirroring = DP83867_PORT_MIRROING_DIS;
264
265 ret = of_property_read_u32(of_node, "ti,fifo-depth",
266 &dp83867->fifo_depth);
267 if (ret) {
268 phydev_err(phydev,
269 "ti,fifo-depth property is required\n");
270 return ret;
271 }
272 if (dp83867->fifo_depth > DP83867_PHYCR_FIFO_DEPTH_MAX) {
273 phydev_err(phydev,
274 "ti,fifo-depth value %u out of range\n",
275 dp83867->fifo_depth);
276 return -EINVAL;
277 }
278 return 0;
279}
280#else
281static int dp83867_of_init(struct phy_device *phydev)
282{
283 return 0;
284}
285#endif /* CONFIG_OF_MDIO */
286
287static int dp83867_probe(struct phy_device *phydev)
288{
289 struct dp83867_private *dp83867;
290
291 dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867),
292 GFP_KERNEL);
293 if (!dp83867)
294 return -ENOMEM;
295
296 phydev->priv = dp83867;
297
298 return 0;
299}
300
301static int dp83867_config_init(struct phy_device *phydev)
302{
303 struct dp83867_private *dp83867 = phydev->priv;
304 int ret, val, bs;
305 u16 delay;
306
307 ret = dp83867_of_init(phydev);
308 if (ret)
309 return ret;
310
311 /* RX_DV/RX_CTRL strapped in mode 1 or mode 2 workaround */
312 if (dp83867->rxctrl_strap_quirk)
313 phy_clear_bits_mmd(phydev, DP83867_DEVADDR, DP83867_CFG4,
314 BIT(7));
315
316 if (phy_interface_is_rgmii(phydev)) {
317 val = phy_read(phydev, MII_DP83867_PHYCTRL);
318 if (val < 0)
319 return val;
320 val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK;
321 val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT);
322
323 /* The code below checks if "port mirroring" N/A MODE4 has been
324 * enabled during power on bootstrap.
325 *
326 * Such N/A mode enabled by mistake can put PHY IC in some
327 * internal testing mode and disable RGMII transmission.
328 *
329 * In this particular case one needs to check STRAP_STS1
330 * register's bit 11 (marked as RESERVED).
331 */
332
333 bs = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_STRAP_STS1);
334 if (bs & DP83867_STRAP_STS1_RESERVED)
335 val &= ~DP83867_PHYCR_RESERVED_MASK;
336
337 ret = phy_write(phydev, MII_DP83867_PHYCTRL, val);
338 if (ret)
339 return ret;
340
341 /* If rgmii mode with no internal delay is selected, we do NOT use
342 * aligned mode as one might expect. Instead we use the PHY's default
343 * based on pin strapping. And the "mode 0" default is to *use*
344 * internal delay with a value of 7 (2.00 ns).
345 *
346 * Set up RGMII delays
347 */
348 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL);
349
350 val &= ~(DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
351 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID)
352 val |= (DP83867_RGMII_TX_CLK_DELAY_EN | DP83867_RGMII_RX_CLK_DELAY_EN);
353
354 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
355 val |= DP83867_RGMII_TX_CLK_DELAY_EN;
356
357 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
358 val |= DP83867_RGMII_RX_CLK_DELAY_EN;
359
360 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIICTL, val);
361
362 delay = (dp83867->rx_id_delay |
363 (dp83867->tx_id_delay << DP83867_RGMII_TX_CLK_DELAY_SHIFT));
364
365 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_RGMIIDCTL,
366 delay);
367 }
368
369 /* If specified, set io impedance */
370 if (dp83867->io_impedance >= 0)
371 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
372 DP83867_IO_MUX_CFG_IO_IMPEDANCE_MASK,
373 dp83867->io_impedance);
374
375 if (phydev->interface == PHY_INTERFACE_MODE_SGMII) {
376 /* For support SPEED_10 in SGMII mode
377 * DP83867_10M_SGMII_RATE_ADAPT bit
378 * has to be cleared by software. That
379 * does not affect SPEED_100 and
380 * SPEED_1000.
381 */
382 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
383 DP83867_10M_SGMII_CFG,
384 DP83867_10M_SGMII_RATE_ADAPT_MASK,
385 0);
386 if (ret)
387 return ret;
388
389 /* After reset SGMII Autoneg timer is set to 2us (bits 6 and 5
390 * are 01). That is not enough to finalize autoneg on some
391 * devices. Increase this timer duration to maximum 16ms.
392 */
393 ret = phy_modify_mmd(phydev, DP83867_DEVADDR,
394 DP83867_CFG4,
395 DP83867_CFG4_SGMII_ANEG_MASK,
396 DP83867_CFG4_SGMII_ANEG_TIMER_16MS);
397
398 if (ret)
399 return ret;
400
401 val = phy_read_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL);
402 /* SGMII type is set to 4-wire mode by default.
403 * If we place appropriate property in dts (see above)
404 * switch on 6-wire mode.
405 */
406 if (dp83867->sgmii_ref_clk_en)
407 val |= DP83867_SGMII_TYPE;
408 else
409 val &= ~DP83867_SGMII_TYPE;
410 phy_write_mmd(phydev, DP83867_DEVADDR, DP83867_SGMIICTL, val);
411 }
412
413 /* Enable Interrupt output INT_OE in CFG3 register */
414 if (phy_interrupt_is_valid(phydev)) {
415 val = phy_read(phydev, DP83867_CFG3);
416 val |= BIT(7);
417 phy_write(phydev, DP83867_CFG3, val);
418 }
419
420 if (dp83867->port_mirroring != DP83867_PORT_MIRROING_KEEP)
421 dp83867_config_port_mirroring(phydev);
422
423 /* Clock output selection if muxing property is set */
424 if (dp83867->set_clk_output) {
425 u16 mask = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
426
427 if (dp83867->clk_output_sel == DP83867_CLK_O_SEL_OFF) {
428 val = DP83867_IO_MUX_CFG_CLK_O_DISABLE;
429 } else {
430 mask |= DP83867_IO_MUX_CFG_CLK_O_SEL_MASK;
431 val = dp83867->clk_output_sel <<
432 DP83867_IO_MUX_CFG_CLK_O_SEL_SHIFT;
433 }
434
435 phy_modify_mmd(phydev, DP83867_DEVADDR, DP83867_IO_MUX_CFG,
436 mask, val);
437 }
438
439 return 0;
440}
441
442static int dp83867_phy_reset(struct phy_device *phydev)
443{
444 int err;
445
446 err = phy_write(phydev, DP83867_CTRL, DP83867_SW_RESET);
447 if (err < 0)
448 return err;
449
450 usleep_range(10, 20);
451
452 return 0;
453}
454
455static struct phy_driver dp83867_driver[] = {
456 {
457 .phy_id = DP83867_PHY_ID,
458 .phy_id_mask = 0xfffffff0,
459 .name = "TI DP83867",
460 /* PHY_GBIT_FEATURES */
461
462 .probe = dp83867_probe,
463 .config_init = dp83867_config_init,
464 .soft_reset = dp83867_phy_reset,
465
466 /* IRQ related */
467 .ack_interrupt = dp83867_ack_interrupt,
468 .config_intr = dp83867_config_intr,
469
470 .suspend = genphy_suspend,
471 .resume = genphy_resume,
472 },
473};
474module_phy_driver(dp83867_driver);
475
476static struct mdio_device_id __maybe_unused dp83867_tbl[] = {
477 { DP83867_PHY_ID, 0xfffffff0 },
478 { }
479};
480
481MODULE_DEVICE_TABLE(mdio, dp83867_tbl);
482
483MODULE_DESCRIPTION("Texas Instruments DP83867 PHY driver");
484MODULE_AUTHOR("Dan Murphy <dmurphy@ti.com");
485MODULE_LICENSE("GPL v2");