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1/* SuperH Ethernet device driver
2 *
3 * Copyright (C) 2014 Renesas Electronics Corporation
4 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
5 * Copyright (C) 2008-2014 Renesas Solutions Corp.
6 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
7 * Copyright (C) 2014 Codethink Limited
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms and conditions of the GNU General Public License,
11 * version 2, as published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope it will be useful, but WITHOUT
14 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 * more details.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 */
21
22#include <linux/module.h>
23#include <linux/kernel.h>
24#include <linux/spinlock.h>
25#include <linux/interrupt.h>
26#include <linux/dma-mapping.h>
27#include <linux/etherdevice.h>
28#include <linux/delay.h>
29#include <linux/platform_device.h>
30#include <linux/mdio-bitbang.h>
31#include <linux/netdevice.h>
32#include <linux/of.h>
33#include <linux/of_device.h>
34#include <linux/of_irq.h>
35#include <linux/of_net.h>
36#include <linux/phy.h>
37#include <linux/cache.h>
38#include <linux/io.h>
39#include <linux/pm_runtime.h>
40#include <linux/slab.h>
41#include <linux/ethtool.h>
42#include <linux/if_vlan.h>
43#include <linux/sh_eth.h>
44#include <linux/of_mdio.h>
45
46#include "sh_eth.h"
47
48#define SH_ETH_DEF_MSG_ENABLE \
49 (NETIF_MSG_LINK | \
50 NETIF_MSG_TIMER | \
51 NETIF_MSG_RX_ERR| \
52 NETIF_MSG_TX_ERR)
53
54#define SH_ETH_OFFSET_INVALID ((u16)~0)
55
56#define SH_ETH_OFFSET_DEFAULTS \
57 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
58
59static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
60 SH_ETH_OFFSET_DEFAULTS,
61
62 [EDSR] = 0x0000,
63 [EDMR] = 0x0400,
64 [EDTRR] = 0x0408,
65 [EDRRR] = 0x0410,
66 [EESR] = 0x0428,
67 [EESIPR] = 0x0430,
68 [TDLAR] = 0x0010,
69 [TDFAR] = 0x0014,
70 [TDFXR] = 0x0018,
71 [TDFFR] = 0x001c,
72 [RDLAR] = 0x0030,
73 [RDFAR] = 0x0034,
74 [RDFXR] = 0x0038,
75 [RDFFR] = 0x003c,
76 [TRSCER] = 0x0438,
77 [RMFCR] = 0x0440,
78 [TFTR] = 0x0448,
79 [FDR] = 0x0450,
80 [RMCR] = 0x0458,
81 [RPADIR] = 0x0460,
82 [FCFTR] = 0x0468,
83 [CSMR] = 0x04E4,
84
85 [ECMR] = 0x0500,
86 [ECSR] = 0x0510,
87 [ECSIPR] = 0x0518,
88 [PIR] = 0x0520,
89 [PSR] = 0x0528,
90 [PIPR] = 0x052c,
91 [RFLR] = 0x0508,
92 [APR] = 0x0554,
93 [MPR] = 0x0558,
94 [PFTCR] = 0x055c,
95 [PFRCR] = 0x0560,
96 [TPAUSER] = 0x0564,
97 [GECMR] = 0x05b0,
98 [BCULR] = 0x05b4,
99 [MAHR] = 0x05c0,
100 [MALR] = 0x05c8,
101 [TROCR] = 0x0700,
102 [CDCR] = 0x0708,
103 [LCCR] = 0x0710,
104 [CEFCR] = 0x0740,
105 [FRECR] = 0x0748,
106 [TSFRCR] = 0x0750,
107 [TLFRCR] = 0x0758,
108 [RFCR] = 0x0760,
109 [CERCR] = 0x0768,
110 [CEECR] = 0x0770,
111 [MAFCR] = 0x0778,
112 [RMII_MII] = 0x0790,
113
114 [ARSTR] = 0x0000,
115 [TSU_CTRST] = 0x0004,
116 [TSU_FWEN0] = 0x0010,
117 [TSU_FWEN1] = 0x0014,
118 [TSU_FCM] = 0x0018,
119 [TSU_BSYSL0] = 0x0020,
120 [TSU_BSYSL1] = 0x0024,
121 [TSU_PRISL0] = 0x0028,
122 [TSU_PRISL1] = 0x002c,
123 [TSU_FWSL0] = 0x0030,
124 [TSU_FWSL1] = 0x0034,
125 [TSU_FWSLC] = 0x0038,
126 [TSU_QTAGM0] = 0x0040,
127 [TSU_QTAGM1] = 0x0044,
128 [TSU_FWSR] = 0x0050,
129 [TSU_FWINMK] = 0x0054,
130 [TSU_ADQT0] = 0x0048,
131 [TSU_ADQT1] = 0x004c,
132 [TSU_VTAG0] = 0x0058,
133 [TSU_VTAG1] = 0x005c,
134 [TSU_ADSBSY] = 0x0060,
135 [TSU_TEN] = 0x0064,
136 [TSU_POST1] = 0x0070,
137 [TSU_POST2] = 0x0074,
138 [TSU_POST3] = 0x0078,
139 [TSU_POST4] = 0x007c,
140 [TSU_ADRH0] = 0x0100,
141
142 [TXNLCR0] = 0x0080,
143 [TXALCR0] = 0x0084,
144 [RXNLCR0] = 0x0088,
145 [RXALCR0] = 0x008c,
146 [FWNLCR0] = 0x0090,
147 [FWALCR0] = 0x0094,
148 [TXNLCR1] = 0x00a0,
149 [TXALCR1] = 0x00a4,
150 [RXNLCR1] = 0x00a8,
151 [RXALCR1] = 0x00ac,
152 [FWNLCR1] = 0x00b0,
153 [FWALCR1] = 0x00b4,
154};
155
156static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
157 SH_ETH_OFFSET_DEFAULTS,
158
159 [EDSR] = 0x0000,
160 [EDMR] = 0x0400,
161 [EDTRR] = 0x0408,
162 [EDRRR] = 0x0410,
163 [EESR] = 0x0428,
164 [EESIPR] = 0x0430,
165 [TDLAR] = 0x0010,
166 [TDFAR] = 0x0014,
167 [TDFXR] = 0x0018,
168 [TDFFR] = 0x001c,
169 [RDLAR] = 0x0030,
170 [RDFAR] = 0x0034,
171 [RDFXR] = 0x0038,
172 [RDFFR] = 0x003c,
173 [TRSCER] = 0x0438,
174 [RMFCR] = 0x0440,
175 [TFTR] = 0x0448,
176 [FDR] = 0x0450,
177 [RMCR] = 0x0458,
178 [RPADIR] = 0x0460,
179 [FCFTR] = 0x0468,
180 [CSMR] = 0x04E4,
181
182 [ECMR] = 0x0500,
183 [RFLR] = 0x0508,
184 [ECSR] = 0x0510,
185 [ECSIPR] = 0x0518,
186 [PIR] = 0x0520,
187 [APR] = 0x0554,
188 [MPR] = 0x0558,
189 [PFTCR] = 0x055c,
190 [PFRCR] = 0x0560,
191 [TPAUSER] = 0x0564,
192 [MAHR] = 0x05c0,
193 [MALR] = 0x05c8,
194 [CEFCR] = 0x0740,
195 [FRECR] = 0x0748,
196 [TSFRCR] = 0x0750,
197 [TLFRCR] = 0x0758,
198 [RFCR] = 0x0760,
199 [MAFCR] = 0x0778,
200
201 [ARSTR] = 0x0000,
202 [TSU_CTRST] = 0x0004,
203 [TSU_FWSLC] = 0x0038,
204 [TSU_VTAG0] = 0x0058,
205 [TSU_ADSBSY] = 0x0060,
206 [TSU_TEN] = 0x0064,
207 [TSU_POST1] = 0x0070,
208 [TSU_POST2] = 0x0074,
209 [TSU_POST3] = 0x0078,
210 [TSU_POST4] = 0x007c,
211 [TSU_ADRH0] = 0x0100,
212
213 [TXNLCR0] = 0x0080,
214 [TXALCR0] = 0x0084,
215 [RXNLCR0] = 0x0088,
216 [RXALCR0] = 0x008C,
217};
218
219static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
220 SH_ETH_OFFSET_DEFAULTS,
221
222 [ECMR] = 0x0300,
223 [RFLR] = 0x0308,
224 [ECSR] = 0x0310,
225 [ECSIPR] = 0x0318,
226 [PIR] = 0x0320,
227 [PSR] = 0x0328,
228 [RDMLR] = 0x0340,
229 [IPGR] = 0x0350,
230 [APR] = 0x0354,
231 [MPR] = 0x0358,
232 [RFCF] = 0x0360,
233 [TPAUSER] = 0x0364,
234 [TPAUSECR] = 0x0368,
235 [MAHR] = 0x03c0,
236 [MALR] = 0x03c8,
237 [TROCR] = 0x03d0,
238 [CDCR] = 0x03d4,
239 [LCCR] = 0x03d8,
240 [CNDCR] = 0x03dc,
241 [CEFCR] = 0x03e4,
242 [FRECR] = 0x03e8,
243 [TSFRCR] = 0x03ec,
244 [TLFRCR] = 0x03f0,
245 [RFCR] = 0x03f4,
246 [MAFCR] = 0x03f8,
247
248 [EDMR] = 0x0200,
249 [EDTRR] = 0x0208,
250 [EDRRR] = 0x0210,
251 [TDLAR] = 0x0218,
252 [RDLAR] = 0x0220,
253 [EESR] = 0x0228,
254 [EESIPR] = 0x0230,
255 [TRSCER] = 0x0238,
256 [RMFCR] = 0x0240,
257 [TFTR] = 0x0248,
258 [FDR] = 0x0250,
259 [RMCR] = 0x0258,
260 [TFUCR] = 0x0264,
261 [RFOCR] = 0x0268,
262 [RMIIMODE] = 0x026c,
263 [FCFTR] = 0x0270,
264 [TRIMD] = 0x027c,
265};
266
267static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
268 SH_ETH_OFFSET_DEFAULTS,
269
270 [ECMR] = 0x0100,
271 [RFLR] = 0x0108,
272 [ECSR] = 0x0110,
273 [ECSIPR] = 0x0118,
274 [PIR] = 0x0120,
275 [PSR] = 0x0128,
276 [RDMLR] = 0x0140,
277 [IPGR] = 0x0150,
278 [APR] = 0x0154,
279 [MPR] = 0x0158,
280 [TPAUSER] = 0x0164,
281 [RFCF] = 0x0160,
282 [TPAUSECR] = 0x0168,
283 [BCFRR] = 0x016c,
284 [MAHR] = 0x01c0,
285 [MALR] = 0x01c8,
286 [TROCR] = 0x01d0,
287 [CDCR] = 0x01d4,
288 [LCCR] = 0x01d8,
289 [CNDCR] = 0x01dc,
290 [CEFCR] = 0x01e4,
291 [FRECR] = 0x01e8,
292 [TSFRCR] = 0x01ec,
293 [TLFRCR] = 0x01f0,
294 [RFCR] = 0x01f4,
295 [MAFCR] = 0x01f8,
296 [RTRATE] = 0x01fc,
297
298 [EDMR] = 0x0000,
299 [EDTRR] = 0x0008,
300 [EDRRR] = 0x0010,
301 [TDLAR] = 0x0018,
302 [RDLAR] = 0x0020,
303 [EESR] = 0x0028,
304 [EESIPR] = 0x0030,
305 [TRSCER] = 0x0038,
306 [RMFCR] = 0x0040,
307 [TFTR] = 0x0048,
308 [FDR] = 0x0050,
309 [RMCR] = 0x0058,
310 [TFUCR] = 0x0064,
311 [RFOCR] = 0x0068,
312 [FCFTR] = 0x0070,
313 [RPADIR] = 0x0078,
314 [TRIMD] = 0x007c,
315 [RBWAR] = 0x00c8,
316 [RDFAR] = 0x00cc,
317 [TBRAR] = 0x00d4,
318 [TDFAR] = 0x00d8,
319};
320
321static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
322 SH_ETH_OFFSET_DEFAULTS,
323
324 [EDMR] = 0x0000,
325 [EDTRR] = 0x0004,
326 [EDRRR] = 0x0008,
327 [TDLAR] = 0x000c,
328 [RDLAR] = 0x0010,
329 [EESR] = 0x0014,
330 [EESIPR] = 0x0018,
331 [TRSCER] = 0x001c,
332 [RMFCR] = 0x0020,
333 [TFTR] = 0x0024,
334 [FDR] = 0x0028,
335 [RMCR] = 0x002c,
336 [EDOCR] = 0x0030,
337 [FCFTR] = 0x0034,
338 [RPADIR] = 0x0038,
339 [TRIMD] = 0x003c,
340 [RBWAR] = 0x0040,
341 [RDFAR] = 0x0044,
342 [TBRAR] = 0x004c,
343 [TDFAR] = 0x0050,
344
345 [ECMR] = 0x0160,
346 [ECSR] = 0x0164,
347 [ECSIPR] = 0x0168,
348 [PIR] = 0x016c,
349 [MAHR] = 0x0170,
350 [MALR] = 0x0174,
351 [RFLR] = 0x0178,
352 [PSR] = 0x017c,
353 [TROCR] = 0x0180,
354 [CDCR] = 0x0184,
355 [LCCR] = 0x0188,
356 [CNDCR] = 0x018c,
357 [CEFCR] = 0x0194,
358 [FRECR] = 0x0198,
359 [TSFRCR] = 0x019c,
360 [TLFRCR] = 0x01a0,
361 [RFCR] = 0x01a4,
362 [MAFCR] = 0x01a8,
363 [IPGR] = 0x01b4,
364 [APR] = 0x01b8,
365 [MPR] = 0x01bc,
366 [TPAUSER] = 0x01c4,
367 [BCFR] = 0x01cc,
368
369 [ARSTR] = 0x0000,
370 [TSU_CTRST] = 0x0004,
371 [TSU_FWEN0] = 0x0010,
372 [TSU_FWEN1] = 0x0014,
373 [TSU_FCM] = 0x0018,
374 [TSU_BSYSL0] = 0x0020,
375 [TSU_BSYSL1] = 0x0024,
376 [TSU_PRISL0] = 0x0028,
377 [TSU_PRISL1] = 0x002c,
378 [TSU_FWSL0] = 0x0030,
379 [TSU_FWSL1] = 0x0034,
380 [TSU_FWSLC] = 0x0038,
381 [TSU_QTAGM0] = 0x0040,
382 [TSU_QTAGM1] = 0x0044,
383 [TSU_ADQT0] = 0x0048,
384 [TSU_ADQT1] = 0x004c,
385 [TSU_FWSR] = 0x0050,
386 [TSU_FWINMK] = 0x0054,
387 [TSU_ADSBSY] = 0x0060,
388 [TSU_TEN] = 0x0064,
389 [TSU_POST1] = 0x0070,
390 [TSU_POST2] = 0x0074,
391 [TSU_POST3] = 0x0078,
392 [TSU_POST4] = 0x007c,
393
394 [TXNLCR0] = 0x0080,
395 [TXALCR0] = 0x0084,
396 [RXNLCR0] = 0x0088,
397 [RXALCR0] = 0x008c,
398 [FWNLCR0] = 0x0090,
399 [FWALCR0] = 0x0094,
400 [TXNLCR1] = 0x00a0,
401 [TXALCR1] = 0x00a4,
402 [RXNLCR1] = 0x00a8,
403 [RXALCR1] = 0x00ac,
404 [FWNLCR1] = 0x00b0,
405 [FWALCR1] = 0x00b4,
406
407 [TSU_ADRH0] = 0x0100,
408};
409
410static void sh_eth_rcv_snd_disable(struct net_device *ndev);
411static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
412
413static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
414{
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416 u16 offset = mdp->reg_offset[enum_index];
417
418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
419 return;
420
421 iowrite32(data, mdp->addr + offset);
422}
423
424static u32 sh_eth_read(struct net_device *ndev, int enum_index)
425{
426 struct sh_eth_private *mdp = netdev_priv(ndev);
427 u16 offset = mdp->reg_offset[enum_index];
428
429 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
430 return ~0U;
431
432 return ioread32(mdp->addr + offset);
433}
434
435static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
436 u32 set)
437{
438 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
439 enum_index);
440}
441
442static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
443 int enum_index)
444{
445 iowrite32(data, mdp->tsu_addr + mdp->reg_offset[enum_index]);
446}
447
448static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
449{
450 return ioread32(mdp->tsu_addr + mdp->reg_offset[enum_index]);
451}
452
453static void sh_eth_select_mii(struct net_device *ndev)
454{
455 struct sh_eth_private *mdp = netdev_priv(ndev);
456 u32 value;
457
458 switch (mdp->phy_interface) {
459 case PHY_INTERFACE_MODE_GMII:
460 value = 0x2;
461 break;
462 case PHY_INTERFACE_MODE_MII:
463 value = 0x1;
464 break;
465 case PHY_INTERFACE_MODE_RMII:
466 value = 0x0;
467 break;
468 default:
469 netdev_warn(ndev,
470 "PHY interface mode was not setup. Set to MII.\n");
471 value = 0x1;
472 break;
473 }
474
475 sh_eth_write(ndev, value, RMII_MII);
476}
477
478static void sh_eth_set_duplex(struct net_device *ndev)
479{
480 struct sh_eth_private *mdp = netdev_priv(ndev);
481
482 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
483}
484
485static void sh_eth_chip_reset(struct net_device *ndev)
486{
487 struct sh_eth_private *mdp = netdev_priv(ndev);
488
489 /* reset device */
490 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
491 mdelay(1);
492}
493
494static int sh_eth_soft_reset(struct net_device *ndev)
495{
496 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
497 mdelay(3);
498 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
499
500 return 0;
501}
502
503static int sh_eth_check_soft_reset(struct net_device *ndev)
504{
505 int cnt;
506
507 for (cnt = 100; cnt > 0; cnt--) {
508 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
509 return 0;
510 mdelay(1);
511 }
512
513 netdev_err(ndev, "Device reset failed\n");
514 return -ETIMEDOUT;
515}
516
517static int sh_eth_soft_reset_gether(struct net_device *ndev)
518{
519 struct sh_eth_private *mdp = netdev_priv(ndev);
520 int ret;
521
522 sh_eth_write(ndev, EDSR_ENALL, EDSR);
523 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
524
525 ret = sh_eth_check_soft_reset(ndev);
526 if (ret)
527 return ret;
528
529 /* Table Init */
530 sh_eth_write(ndev, 0, TDLAR);
531 sh_eth_write(ndev, 0, TDFAR);
532 sh_eth_write(ndev, 0, TDFXR);
533 sh_eth_write(ndev, 0, TDFFR);
534 sh_eth_write(ndev, 0, RDLAR);
535 sh_eth_write(ndev, 0, RDFAR);
536 sh_eth_write(ndev, 0, RDFXR);
537 sh_eth_write(ndev, 0, RDFFR);
538
539 /* Reset HW CRC register */
540 if (mdp->cd->hw_checksum)
541 sh_eth_write(ndev, 0, CSMR);
542
543 /* Select MII mode */
544 if (mdp->cd->select_mii)
545 sh_eth_select_mii(ndev);
546
547 return ret;
548}
549
550static void sh_eth_set_rate_gether(struct net_device *ndev)
551{
552 struct sh_eth_private *mdp = netdev_priv(ndev);
553
554 switch (mdp->speed) {
555 case 10: /* 10BASE */
556 sh_eth_write(ndev, GECMR_10, GECMR);
557 break;
558 case 100:/* 100BASE */
559 sh_eth_write(ndev, GECMR_100, GECMR);
560 break;
561 case 1000: /* 1000BASE */
562 sh_eth_write(ndev, GECMR_1000, GECMR);
563 break;
564 }
565}
566
567#ifdef CONFIG_OF
568/* R7S72100 */
569static struct sh_eth_cpu_data r7s72100_data = {
570 .soft_reset = sh_eth_soft_reset_gether,
571
572 .chip_reset = sh_eth_chip_reset,
573 .set_duplex = sh_eth_set_duplex,
574
575 .register_type = SH_ETH_REG_FAST_RZ,
576
577 .edtrr_trns = EDTRR_TRNS_GETHER,
578 .ecsr_value = ECSR_ICD,
579 .ecsipr_value = ECSIPR_ICDIP,
580 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
581 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
582 EESIPR_ECIIP |
583 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
584 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
585 EESIPR_RMAFIP | EESIPR_RRFIP |
586 EESIPR_RTLFIP | EESIPR_RTSFIP |
587 EESIPR_PREIP | EESIPR_CERFIP,
588
589 .tx_check = EESR_TC1 | EESR_FTC,
590 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
591 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
592 EESR_TDE,
593 .fdr_value = 0x0000070f,
594
595 .no_psr = 1,
596 .apr = 1,
597 .mpr = 1,
598 .tpauser = 1,
599 .hw_swap = 1,
600 .rpadir = 1,
601 .rpadir_value = 2 << 16,
602 .no_trimd = 1,
603 .no_ade = 1,
604 .xdfar_rw = 1,
605 .hw_checksum = 1,
606 .tsu = 1,
607 .no_tx_cntrs = 1,
608};
609
610static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
611{
612 sh_eth_chip_reset(ndev);
613
614 sh_eth_select_mii(ndev);
615}
616
617/* R8A7740 */
618static struct sh_eth_cpu_data r8a7740_data = {
619 .soft_reset = sh_eth_soft_reset_gether,
620
621 .chip_reset = sh_eth_chip_reset_r8a7740,
622 .set_duplex = sh_eth_set_duplex,
623 .set_rate = sh_eth_set_rate_gether,
624
625 .register_type = SH_ETH_REG_GIGABIT,
626
627 .edtrr_trns = EDTRR_TRNS_GETHER,
628 .ecsr_value = ECSR_ICD | ECSR_MPD,
629 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
630 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
631 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
632 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
633 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
634 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
635 EESIPR_CEEFIP | EESIPR_CELFIP |
636 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
637 EESIPR_PREIP | EESIPR_CERFIP,
638
639 .tx_check = EESR_TC1 | EESR_FTC,
640 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
641 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
642 EESR_TDE,
643 .fdr_value = 0x0000070f,
644
645 .apr = 1,
646 .mpr = 1,
647 .tpauser = 1,
648 .bculr = 1,
649 .hw_swap = 1,
650 .rpadir = 1,
651 .rpadir_value = 2 << 16,
652 .no_trimd = 1,
653 .no_ade = 1,
654 .xdfar_rw = 1,
655 .hw_checksum = 1,
656 .tsu = 1,
657 .select_mii = 1,
658 .magic = 1,
659 .cexcr = 1,
660};
661
662/* There is CPU dependent code */
663static void sh_eth_set_rate_rcar(struct net_device *ndev)
664{
665 struct sh_eth_private *mdp = netdev_priv(ndev);
666
667 switch (mdp->speed) {
668 case 10: /* 10BASE */
669 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
670 break;
671 case 100:/* 100BASE */
672 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
673 break;
674 }
675}
676
677/* R-Car Gen1 */
678static struct sh_eth_cpu_data rcar_gen1_data = {
679 .soft_reset = sh_eth_soft_reset,
680
681 .set_duplex = sh_eth_set_duplex,
682 .set_rate = sh_eth_set_rate_rcar,
683
684 .register_type = SH_ETH_REG_FAST_RCAR,
685
686 .edtrr_trns = EDTRR_TRNS_ETHER,
687 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
688 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
689 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
690 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
691 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
692 EESIPR_RMAFIP | EESIPR_RRFIP |
693 EESIPR_RTLFIP | EESIPR_RTSFIP |
694 EESIPR_PREIP | EESIPR_CERFIP,
695
696 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
697 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
698 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
699 .fdr_value = 0x00000f0f,
700
701 .apr = 1,
702 .mpr = 1,
703 .tpauser = 1,
704 .hw_swap = 1,
705 .no_xdfar = 1,
706};
707
708/* R-Car Gen2 and RZ/G1 */
709static struct sh_eth_cpu_data rcar_gen2_data = {
710 .soft_reset = sh_eth_soft_reset,
711
712 .set_duplex = sh_eth_set_duplex,
713 .set_rate = sh_eth_set_rate_rcar,
714
715 .register_type = SH_ETH_REG_FAST_RCAR,
716
717 .edtrr_trns = EDTRR_TRNS_ETHER,
718 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
719 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
720 ECSIPR_MPDIP,
721 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
722 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
723 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
724 EESIPR_RMAFIP | EESIPR_RRFIP |
725 EESIPR_RTLFIP | EESIPR_RTSFIP |
726 EESIPR_PREIP | EESIPR_CERFIP,
727
728 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
729 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
730 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
731 .fdr_value = 0x00000f0f,
732
733 .trscer_err_mask = DESC_I_RINT8,
734
735 .apr = 1,
736 .mpr = 1,
737 .tpauser = 1,
738 .hw_swap = 1,
739 .no_xdfar = 1,
740 .rmiimode = 1,
741 .magic = 1,
742};
743#endif /* CONFIG_OF */
744
745static void sh_eth_set_rate_sh7724(struct net_device *ndev)
746{
747 struct sh_eth_private *mdp = netdev_priv(ndev);
748
749 switch (mdp->speed) {
750 case 10: /* 10BASE */
751 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
752 break;
753 case 100:/* 100BASE */
754 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
755 break;
756 }
757}
758
759/* SH7724 */
760static struct sh_eth_cpu_data sh7724_data = {
761 .soft_reset = sh_eth_soft_reset,
762
763 .set_duplex = sh_eth_set_duplex,
764 .set_rate = sh_eth_set_rate_sh7724,
765
766 .register_type = SH_ETH_REG_FAST_SH4,
767
768 .edtrr_trns = EDTRR_TRNS_ETHER,
769 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
770 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
771 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
772 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
773 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
774 EESIPR_RMAFIP | EESIPR_RRFIP |
775 EESIPR_RTLFIP | EESIPR_RTSFIP |
776 EESIPR_PREIP | EESIPR_CERFIP,
777
778 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
779 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
780 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
781
782 .apr = 1,
783 .mpr = 1,
784 .tpauser = 1,
785 .hw_swap = 1,
786 .rpadir = 1,
787 .rpadir_value = 0x00020000, /* NET_IP_ALIGN assumed to be 2 */
788};
789
790static void sh_eth_set_rate_sh7757(struct net_device *ndev)
791{
792 struct sh_eth_private *mdp = netdev_priv(ndev);
793
794 switch (mdp->speed) {
795 case 10: /* 10BASE */
796 sh_eth_write(ndev, 0, RTRATE);
797 break;
798 case 100:/* 100BASE */
799 sh_eth_write(ndev, 1, RTRATE);
800 break;
801 }
802}
803
804/* SH7757 */
805static struct sh_eth_cpu_data sh7757_data = {
806 .soft_reset = sh_eth_soft_reset,
807
808 .set_duplex = sh_eth_set_duplex,
809 .set_rate = sh_eth_set_rate_sh7757,
810
811 .register_type = SH_ETH_REG_FAST_SH4,
812
813 .edtrr_trns = EDTRR_TRNS_ETHER,
814 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
815 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
816 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
817 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
818 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
819 EESIPR_CEEFIP | EESIPR_CELFIP |
820 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
821 EESIPR_PREIP | EESIPR_CERFIP,
822
823 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_RTO,
824 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
825 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
826
827 .irq_flags = IRQF_SHARED,
828 .apr = 1,
829 .mpr = 1,
830 .tpauser = 1,
831 .hw_swap = 1,
832 .no_ade = 1,
833 .rpadir = 1,
834 .rpadir_value = 2 << 16,
835 .rtrate = 1,
836 .dual_port = 1,
837};
838
839#define SH_GIGA_ETH_BASE 0xfee00000UL
840#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
841#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
842static void sh_eth_chip_reset_giga(struct net_device *ndev)
843{
844 u32 mahr[2], malr[2];
845 int i;
846
847 /* save MAHR and MALR */
848 for (i = 0; i < 2; i++) {
849 malr[i] = ioread32((void *)GIGA_MALR(i));
850 mahr[i] = ioread32((void *)GIGA_MAHR(i));
851 }
852
853 sh_eth_chip_reset(ndev);
854
855 /* restore MAHR and MALR */
856 for (i = 0; i < 2; i++) {
857 iowrite32(malr[i], (void *)GIGA_MALR(i));
858 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
859 }
860}
861
862static void sh_eth_set_rate_giga(struct net_device *ndev)
863{
864 struct sh_eth_private *mdp = netdev_priv(ndev);
865
866 switch (mdp->speed) {
867 case 10: /* 10BASE */
868 sh_eth_write(ndev, 0x00000000, GECMR);
869 break;
870 case 100:/* 100BASE */
871 sh_eth_write(ndev, 0x00000010, GECMR);
872 break;
873 case 1000: /* 1000BASE */
874 sh_eth_write(ndev, 0x00000020, GECMR);
875 break;
876 }
877}
878
879/* SH7757(GETHERC) */
880static struct sh_eth_cpu_data sh7757_data_giga = {
881 .soft_reset = sh_eth_soft_reset_gether,
882
883 .chip_reset = sh_eth_chip_reset_giga,
884 .set_duplex = sh_eth_set_duplex,
885 .set_rate = sh_eth_set_rate_giga,
886
887 .register_type = SH_ETH_REG_GIGABIT,
888
889 .edtrr_trns = EDTRR_TRNS_GETHER,
890 .ecsr_value = ECSR_ICD | ECSR_MPD,
891 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
892 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
893 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
894 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
895 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
896 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
897 EESIPR_CEEFIP | EESIPR_CELFIP |
898 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
899 EESIPR_PREIP | EESIPR_CERFIP,
900
901 .tx_check = EESR_TC1 | EESR_FTC,
902 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
903 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
904 EESR_TDE,
905 .fdr_value = 0x0000072f,
906
907 .irq_flags = IRQF_SHARED,
908 .apr = 1,
909 .mpr = 1,
910 .tpauser = 1,
911 .bculr = 1,
912 .hw_swap = 1,
913 .rpadir = 1,
914 .rpadir_value = 2 << 16,
915 .no_trimd = 1,
916 .no_ade = 1,
917 .xdfar_rw = 1,
918 .tsu = 1,
919 .cexcr = 1,
920 .dual_port = 1,
921};
922
923/* SH7734 */
924static struct sh_eth_cpu_data sh7734_data = {
925 .soft_reset = sh_eth_soft_reset_gether,
926
927 .chip_reset = sh_eth_chip_reset,
928 .set_duplex = sh_eth_set_duplex,
929 .set_rate = sh_eth_set_rate_gether,
930
931 .register_type = SH_ETH_REG_GIGABIT,
932
933 .edtrr_trns = EDTRR_TRNS_GETHER,
934 .ecsr_value = ECSR_ICD | ECSR_MPD,
935 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
936 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
937 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
938 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
939 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
940 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
941 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
942 EESIPR_PREIP | EESIPR_CERFIP,
943
944 .tx_check = EESR_TC1 | EESR_FTC,
945 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
946 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
947 EESR_TDE,
948
949 .apr = 1,
950 .mpr = 1,
951 .tpauser = 1,
952 .bculr = 1,
953 .hw_swap = 1,
954 .no_trimd = 1,
955 .no_ade = 1,
956 .xdfar_rw = 1,
957 .tsu = 1,
958 .hw_checksum = 1,
959 .select_mii = 1,
960 .magic = 1,
961 .cexcr = 1,
962};
963
964/* SH7763 */
965static struct sh_eth_cpu_data sh7763_data = {
966 .soft_reset = sh_eth_soft_reset_gether,
967
968 .chip_reset = sh_eth_chip_reset,
969 .set_duplex = sh_eth_set_duplex,
970 .set_rate = sh_eth_set_rate_gether,
971
972 .register_type = SH_ETH_REG_GIGABIT,
973
974 .edtrr_trns = EDTRR_TRNS_GETHER,
975 .ecsr_value = ECSR_ICD | ECSR_MPD,
976 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
977 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
978 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
979 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
980 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
981 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
982 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
983 EESIPR_PREIP | EESIPR_CERFIP,
984
985 .tx_check = EESR_TC1 | EESR_FTC,
986 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
987 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
988
989 .apr = 1,
990 .mpr = 1,
991 .tpauser = 1,
992 .bculr = 1,
993 .hw_swap = 1,
994 .no_trimd = 1,
995 .no_ade = 1,
996 .xdfar_rw = 1,
997 .tsu = 1,
998 .irq_flags = IRQF_SHARED,
999 .magic = 1,
1000 .cexcr = 1,
1001 .dual_port = 1,
1002};
1003
1004static struct sh_eth_cpu_data sh7619_data = {
1005 .soft_reset = sh_eth_soft_reset,
1006
1007 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1008
1009 .edtrr_trns = EDTRR_TRNS_ETHER,
1010 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1011 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1012 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1013 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1014 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1015 EESIPR_CEEFIP | EESIPR_CELFIP |
1016 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1017 EESIPR_PREIP | EESIPR_CERFIP,
1018
1019 .apr = 1,
1020 .mpr = 1,
1021 .tpauser = 1,
1022 .hw_swap = 1,
1023};
1024
1025static struct sh_eth_cpu_data sh771x_data = {
1026 .soft_reset = sh_eth_soft_reset,
1027
1028 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1029
1030 .edtrr_trns = EDTRR_TRNS_ETHER,
1031 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1032 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1033 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1034 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1035 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1036 EESIPR_CEEFIP | EESIPR_CELFIP |
1037 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1038 EESIPR_PREIP | EESIPR_CERFIP,
1039 .tsu = 1,
1040 .dual_port = 1,
1041};
1042
1043static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1044{
1045 if (!cd->ecsr_value)
1046 cd->ecsr_value = DEFAULT_ECSR_INIT;
1047
1048 if (!cd->ecsipr_value)
1049 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1050
1051 if (!cd->fcftr_value)
1052 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1053 DEFAULT_FIFO_F_D_RFD;
1054
1055 if (!cd->fdr_value)
1056 cd->fdr_value = DEFAULT_FDR_INIT;
1057
1058 if (!cd->tx_check)
1059 cd->tx_check = DEFAULT_TX_CHECK;
1060
1061 if (!cd->eesr_err_check)
1062 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1063
1064 if (!cd->trscer_err_mask)
1065 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1066}
1067
1068static void sh_eth_set_receive_align(struct sk_buff *skb)
1069{
1070 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1071
1072 if (reserve)
1073 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1074}
1075
1076/* Program the hardware MAC address from dev->dev_addr. */
1077static void update_mac_address(struct net_device *ndev)
1078{
1079 sh_eth_write(ndev,
1080 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1081 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1082 sh_eth_write(ndev,
1083 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1084}
1085
1086/* Get MAC address from SuperH MAC address register
1087 *
1088 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1089 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1090 * When you want use this device, you must set MAC address in bootloader.
1091 *
1092 */
1093static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1094{
1095 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1096 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1097 } else {
1098 u32 mahr = sh_eth_read(ndev, MAHR);
1099 u32 malr = sh_eth_read(ndev, MALR);
1100
1101 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1102 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1103 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1104 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1105 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1106 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1107 }
1108}
1109
1110struct bb_info {
1111 void (*set_gate)(void *addr);
1112 struct mdiobb_ctrl ctrl;
1113 void *addr;
1114};
1115
1116static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1117{
1118 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1119 u32 pir;
1120
1121 if (bitbang->set_gate)
1122 bitbang->set_gate(bitbang->addr);
1123
1124 pir = ioread32(bitbang->addr);
1125 if (set)
1126 pir |= mask;
1127 else
1128 pir &= ~mask;
1129 iowrite32(pir, bitbang->addr);
1130}
1131
1132/* Data I/O pin control */
1133static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1134{
1135 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1136}
1137
1138/* Set bit data*/
1139static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1140{
1141 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1142}
1143
1144/* Get bit data*/
1145static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1146{
1147 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1148
1149 if (bitbang->set_gate)
1150 bitbang->set_gate(bitbang->addr);
1151
1152 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1153}
1154
1155/* MDC pin control */
1156static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1157{
1158 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1159}
1160
1161/* mdio bus control struct */
1162static struct mdiobb_ops bb_ops = {
1163 .owner = THIS_MODULE,
1164 .set_mdc = sh_mdc_ctrl,
1165 .set_mdio_dir = sh_mmd_ctrl,
1166 .set_mdio_data = sh_set_mdio,
1167 .get_mdio_data = sh_get_mdio,
1168};
1169
1170/* free Tx skb function */
1171static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1172{
1173 struct sh_eth_private *mdp = netdev_priv(ndev);
1174 struct sh_eth_txdesc *txdesc;
1175 int free_num = 0;
1176 int entry;
1177 bool sent;
1178
1179 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1180 entry = mdp->dirty_tx % mdp->num_tx_ring;
1181 txdesc = &mdp->tx_ring[entry];
1182 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1183 if (sent_only && !sent)
1184 break;
1185 /* TACT bit must be checked before all the following reads */
1186 dma_rmb();
1187 netif_info(mdp, tx_done, ndev,
1188 "tx entry %d status 0x%08x\n",
1189 entry, le32_to_cpu(txdesc->status));
1190 /* Free the original skb. */
1191 if (mdp->tx_skbuff[entry]) {
1192 dma_unmap_single(&mdp->pdev->dev,
1193 le32_to_cpu(txdesc->addr),
1194 le32_to_cpu(txdesc->len) >> 16,
1195 DMA_TO_DEVICE);
1196 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1197 mdp->tx_skbuff[entry] = NULL;
1198 free_num++;
1199 }
1200 txdesc->status = cpu_to_le32(TD_TFP);
1201 if (entry >= mdp->num_tx_ring - 1)
1202 txdesc->status |= cpu_to_le32(TD_TDLE);
1203
1204 if (sent) {
1205 ndev->stats.tx_packets++;
1206 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1207 }
1208 }
1209 return free_num;
1210}
1211
1212/* free skb and descriptor buffer */
1213static void sh_eth_ring_free(struct net_device *ndev)
1214{
1215 struct sh_eth_private *mdp = netdev_priv(ndev);
1216 int ringsize, i;
1217
1218 if (mdp->rx_ring) {
1219 for (i = 0; i < mdp->num_rx_ring; i++) {
1220 if (mdp->rx_skbuff[i]) {
1221 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1222
1223 dma_unmap_single(&mdp->pdev->dev,
1224 le32_to_cpu(rxdesc->addr),
1225 ALIGN(mdp->rx_buf_sz, 32),
1226 DMA_FROM_DEVICE);
1227 }
1228 }
1229 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1230 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1231 mdp->rx_desc_dma);
1232 mdp->rx_ring = NULL;
1233 }
1234
1235 /* Free Rx skb ringbuffer */
1236 if (mdp->rx_skbuff) {
1237 for (i = 0; i < mdp->num_rx_ring; i++)
1238 dev_kfree_skb(mdp->rx_skbuff[i]);
1239 }
1240 kfree(mdp->rx_skbuff);
1241 mdp->rx_skbuff = NULL;
1242
1243 if (mdp->tx_ring) {
1244 sh_eth_tx_free(ndev, false);
1245
1246 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1247 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1248 mdp->tx_desc_dma);
1249 mdp->tx_ring = NULL;
1250 }
1251
1252 /* Free Tx skb ringbuffer */
1253 kfree(mdp->tx_skbuff);
1254 mdp->tx_skbuff = NULL;
1255}
1256
1257/* format skb and descriptor buffer */
1258static void sh_eth_ring_format(struct net_device *ndev)
1259{
1260 struct sh_eth_private *mdp = netdev_priv(ndev);
1261 int i;
1262 struct sk_buff *skb;
1263 struct sh_eth_rxdesc *rxdesc = NULL;
1264 struct sh_eth_txdesc *txdesc = NULL;
1265 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1266 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1267 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1268 dma_addr_t dma_addr;
1269 u32 buf_len;
1270
1271 mdp->cur_rx = 0;
1272 mdp->cur_tx = 0;
1273 mdp->dirty_rx = 0;
1274 mdp->dirty_tx = 0;
1275
1276 memset(mdp->rx_ring, 0, rx_ringsize);
1277
1278 /* build Rx ring buffer */
1279 for (i = 0; i < mdp->num_rx_ring; i++) {
1280 /* skb */
1281 mdp->rx_skbuff[i] = NULL;
1282 skb = netdev_alloc_skb(ndev, skbuff_size);
1283 if (skb == NULL)
1284 break;
1285 sh_eth_set_receive_align(skb);
1286
1287 /* The size of the buffer is a multiple of 32 bytes. */
1288 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1289 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1290 DMA_FROM_DEVICE);
1291 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1292 kfree_skb(skb);
1293 break;
1294 }
1295 mdp->rx_skbuff[i] = skb;
1296
1297 /* RX descriptor */
1298 rxdesc = &mdp->rx_ring[i];
1299 rxdesc->len = cpu_to_le32(buf_len << 16);
1300 rxdesc->addr = cpu_to_le32(dma_addr);
1301 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1302
1303 /* Rx descriptor address set */
1304 if (i == 0) {
1305 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1306 if (mdp->cd->xdfar_rw)
1307 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1308 }
1309 }
1310
1311 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1312
1313 /* Mark the last entry as wrapping the ring. */
1314 if (rxdesc)
1315 rxdesc->status |= cpu_to_le32(RD_RDLE);
1316
1317 memset(mdp->tx_ring, 0, tx_ringsize);
1318
1319 /* build Tx ring buffer */
1320 for (i = 0; i < mdp->num_tx_ring; i++) {
1321 mdp->tx_skbuff[i] = NULL;
1322 txdesc = &mdp->tx_ring[i];
1323 txdesc->status = cpu_to_le32(TD_TFP);
1324 txdesc->len = cpu_to_le32(0);
1325 if (i == 0) {
1326 /* Tx descriptor address set */
1327 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1328 if (mdp->cd->xdfar_rw)
1329 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1330 }
1331 }
1332
1333 txdesc->status |= cpu_to_le32(TD_TDLE);
1334}
1335
1336/* Get skb and descriptor buffer */
1337static int sh_eth_ring_init(struct net_device *ndev)
1338{
1339 struct sh_eth_private *mdp = netdev_priv(ndev);
1340 int rx_ringsize, tx_ringsize;
1341
1342 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1343 * card needs room to do 8 byte alignment, +2 so we can reserve
1344 * the first 2 bytes, and +16 gets room for the status word from the
1345 * card.
1346 */
1347 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1348 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1349 if (mdp->cd->rpadir)
1350 mdp->rx_buf_sz += NET_IP_ALIGN;
1351
1352 /* Allocate RX and TX skb rings */
1353 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1354 GFP_KERNEL);
1355 if (!mdp->rx_skbuff)
1356 return -ENOMEM;
1357
1358 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1359 GFP_KERNEL);
1360 if (!mdp->tx_skbuff)
1361 goto ring_free;
1362
1363 /* Allocate all Rx descriptors. */
1364 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1365 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1366 &mdp->rx_desc_dma, GFP_KERNEL);
1367 if (!mdp->rx_ring)
1368 goto ring_free;
1369
1370 mdp->dirty_rx = 0;
1371
1372 /* Allocate all Tx descriptors. */
1373 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1374 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1375 &mdp->tx_desc_dma, GFP_KERNEL);
1376 if (!mdp->tx_ring)
1377 goto ring_free;
1378 return 0;
1379
1380ring_free:
1381 /* Free Rx and Tx skb ring buffer and DMA buffer */
1382 sh_eth_ring_free(ndev);
1383
1384 return -ENOMEM;
1385}
1386
1387static int sh_eth_dev_init(struct net_device *ndev)
1388{
1389 struct sh_eth_private *mdp = netdev_priv(ndev);
1390 int ret;
1391
1392 /* Soft Reset */
1393 ret = mdp->cd->soft_reset(ndev);
1394 if (ret)
1395 return ret;
1396
1397 if (mdp->cd->rmiimode)
1398 sh_eth_write(ndev, 0x1, RMIIMODE);
1399
1400 /* Descriptor format */
1401 sh_eth_ring_format(ndev);
1402 if (mdp->cd->rpadir)
1403 sh_eth_write(ndev, mdp->cd->rpadir_value, RPADIR);
1404
1405 /* all sh_eth int mask */
1406 sh_eth_write(ndev, 0, EESIPR);
1407
1408#if defined(__LITTLE_ENDIAN)
1409 if (mdp->cd->hw_swap)
1410 sh_eth_write(ndev, EDMR_EL, EDMR);
1411 else
1412#endif
1413 sh_eth_write(ndev, 0, EDMR);
1414
1415 /* FIFO size set */
1416 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1417 sh_eth_write(ndev, 0, TFTR);
1418
1419 /* Frame recv control (enable multiple-packets per rx irq) */
1420 sh_eth_write(ndev, RMCR_RNC, RMCR);
1421
1422 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1423
1424 if (mdp->cd->bculr)
1425 sh_eth_write(ndev, 0x800, BCULR); /* Burst sycle set */
1426
1427 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1428
1429 if (!mdp->cd->no_trimd)
1430 sh_eth_write(ndev, 0, TRIMD);
1431
1432 /* Recv frame limit set register */
1433 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1434 RFLR);
1435
1436 sh_eth_modify(ndev, EESR, 0, 0);
1437 mdp->irq_enabled = true;
1438 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1439
1440 /* PAUSE Prohibition */
1441 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1442 ECMR_TE | ECMR_RE, ECMR);
1443
1444 if (mdp->cd->set_rate)
1445 mdp->cd->set_rate(ndev);
1446
1447 /* E-MAC Status Register clear */
1448 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1449
1450 /* E-MAC Interrupt Enable register */
1451 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1452
1453 /* Set MAC address */
1454 update_mac_address(ndev);
1455
1456 /* mask reset */
1457 if (mdp->cd->apr)
1458 sh_eth_write(ndev, APR_AP, APR);
1459 if (mdp->cd->mpr)
1460 sh_eth_write(ndev, MPR_MP, MPR);
1461 if (mdp->cd->tpauser)
1462 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1463
1464 /* Setting the Rx mode will start the Rx process. */
1465 sh_eth_write(ndev, EDRRR_R, EDRRR);
1466
1467 return ret;
1468}
1469
1470static void sh_eth_dev_exit(struct net_device *ndev)
1471{
1472 struct sh_eth_private *mdp = netdev_priv(ndev);
1473 int i;
1474
1475 /* Deactivate all TX descriptors, so DMA should stop at next
1476 * packet boundary if it's currently running
1477 */
1478 for (i = 0; i < mdp->num_tx_ring; i++)
1479 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1480
1481 /* Disable TX FIFO egress to MAC */
1482 sh_eth_rcv_snd_disable(ndev);
1483
1484 /* Stop RX DMA at next packet boundary */
1485 sh_eth_write(ndev, 0, EDRRR);
1486
1487 /* Aside from TX DMA, we can't tell when the hardware is
1488 * really stopped, so we need to reset to make sure.
1489 * Before doing that, wait for long enough to *probably*
1490 * finish transmitting the last packet and poll stats.
1491 */
1492 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1493 sh_eth_get_stats(ndev);
1494 mdp->cd->soft_reset(ndev);
1495
1496 /* Set MAC address again */
1497 update_mac_address(ndev);
1498}
1499
1500/* Packet receive function */
1501static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1502{
1503 struct sh_eth_private *mdp = netdev_priv(ndev);
1504 struct sh_eth_rxdesc *rxdesc;
1505
1506 int entry = mdp->cur_rx % mdp->num_rx_ring;
1507 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1508 int limit;
1509 struct sk_buff *skb;
1510 u32 desc_status;
1511 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1512 dma_addr_t dma_addr;
1513 u16 pkt_len;
1514 u32 buf_len;
1515
1516 boguscnt = min(boguscnt, *quota);
1517 limit = boguscnt;
1518 rxdesc = &mdp->rx_ring[entry];
1519 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1520 /* RACT bit must be checked before all the following reads */
1521 dma_rmb();
1522 desc_status = le32_to_cpu(rxdesc->status);
1523 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1524
1525 if (--boguscnt < 0)
1526 break;
1527
1528 netif_info(mdp, rx_status, ndev,
1529 "rx entry %d status 0x%08x len %d\n",
1530 entry, desc_status, pkt_len);
1531
1532 if (!(desc_status & RDFEND))
1533 ndev->stats.rx_length_errors++;
1534
1535 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1536 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1537 * bit 0. However, in case of the R8A7740 and R7S72100
1538 * the RFS bits are from bit 25 to bit 16. So, the
1539 * driver needs right shifting by 16.
1540 */
1541 if (mdp->cd->hw_checksum)
1542 desc_status >>= 16;
1543
1544 skb = mdp->rx_skbuff[entry];
1545 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1546 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1547 ndev->stats.rx_errors++;
1548 if (desc_status & RD_RFS1)
1549 ndev->stats.rx_crc_errors++;
1550 if (desc_status & RD_RFS2)
1551 ndev->stats.rx_frame_errors++;
1552 if (desc_status & RD_RFS3)
1553 ndev->stats.rx_length_errors++;
1554 if (desc_status & RD_RFS4)
1555 ndev->stats.rx_length_errors++;
1556 if (desc_status & RD_RFS6)
1557 ndev->stats.rx_missed_errors++;
1558 if (desc_status & RD_RFS10)
1559 ndev->stats.rx_over_errors++;
1560 } else if (skb) {
1561 dma_addr = le32_to_cpu(rxdesc->addr);
1562 if (!mdp->cd->hw_swap)
1563 sh_eth_soft_swap(
1564 phys_to_virt(ALIGN(dma_addr, 4)),
1565 pkt_len + 2);
1566 mdp->rx_skbuff[entry] = NULL;
1567 if (mdp->cd->rpadir)
1568 skb_reserve(skb, NET_IP_ALIGN);
1569 dma_unmap_single(&mdp->pdev->dev, dma_addr,
1570 ALIGN(mdp->rx_buf_sz, 32),
1571 DMA_FROM_DEVICE);
1572 skb_put(skb, pkt_len);
1573 skb->protocol = eth_type_trans(skb, ndev);
1574 netif_receive_skb(skb);
1575 ndev->stats.rx_packets++;
1576 ndev->stats.rx_bytes += pkt_len;
1577 if (desc_status & RD_RFS8)
1578 ndev->stats.multicast++;
1579 }
1580 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1581 rxdesc = &mdp->rx_ring[entry];
1582 }
1583
1584 /* Refill the Rx ring buffers. */
1585 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1586 entry = mdp->dirty_rx % mdp->num_rx_ring;
1587 rxdesc = &mdp->rx_ring[entry];
1588 /* The size of the buffer is 32 byte boundary. */
1589 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1590 rxdesc->len = cpu_to_le32(buf_len << 16);
1591
1592 if (mdp->rx_skbuff[entry] == NULL) {
1593 skb = netdev_alloc_skb(ndev, skbuff_size);
1594 if (skb == NULL)
1595 break; /* Better luck next round. */
1596 sh_eth_set_receive_align(skb);
1597 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1598 buf_len, DMA_FROM_DEVICE);
1599 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1600 kfree_skb(skb);
1601 break;
1602 }
1603 mdp->rx_skbuff[entry] = skb;
1604
1605 skb_checksum_none_assert(skb);
1606 rxdesc->addr = cpu_to_le32(dma_addr);
1607 }
1608 dma_wmb(); /* RACT bit must be set after all the above writes */
1609 if (entry >= mdp->num_rx_ring - 1)
1610 rxdesc->status |=
1611 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1612 else
1613 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1614 }
1615
1616 /* Restart Rx engine if stopped. */
1617 /* If we don't need to check status, don't. -KDU */
1618 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1619 /* fix the values for the next receiving if RDE is set */
1620 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1621 u32 count = (sh_eth_read(ndev, RDFAR) -
1622 sh_eth_read(ndev, RDLAR)) >> 4;
1623
1624 mdp->cur_rx = count;
1625 mdp->dirty_rx = count;
1626 }
1627 sh_eth_write(ndev, EDRRR_R, EDRRR);
1628 }
1629
1630 *quota -= limit - boguscnt - 1;
1631
1632 return *quota <= 0;
1633}
1634
1635static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1636{
1637 /* disable tx and rx */
1638 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1639}
1640
1641static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1642{
1643 /* enable tx and rx */
1644 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1645}
1646
1647/* E-MAC interrupt handler */
1648static void sh_eth_emac_interrupt(struct net_device *ndev)
1649{
1650 struct sh_eth_private *mdp = netdev_priv(ndev);
1651 u32 felic_stat;
1652 u32 link_stat;
1653
1654 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1655 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1656 if (felic_stat & ECSR_ICD)
1657 ndev->stats.tx_carrier_errors++;
1658 if (felic_stat & ECSR_MPD)
1659 pm_wakeup_event(&mdp->pdev->dev, 0);
1660 if (felic_stat & ECSR_LCHNG) {
1661 /* Link Changed */
1662 if (mdp->cd->no_psr || mdp->no_ether_link)
1663 return;
1664 link_stat = sh_eth_read(ndev, PSR);
1665 if (mdp->ether_link_active_low)
1666 link_stat = ~link_stat;
1667 if (!(link_stat & PHY_ST_LINK)) {
1668 sh_eth_rcv_snd_disable(ndev);
1669 } else {
1670 /* Link Up */
1671 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1672 /* clear int */
1673 sh_eth_modify(ndev, ECSR, 0, 0);
1674 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1675 /* enable tx and rx */
1676 sh_eth_rcv_snd_enable(ndev);
1677 }
1678 }
1679}
1680
1681/* error control function */
1682static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1683{
1684 struct sh_eth_private *mdp = netdev_priv(ndev);
1685 u32 mask;
1686
1687 if (intr_status & EESR_TWB) {
1688 /* Unused write back interrupt */
1689 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1690 ndev->stats.tx_aborted_errors++;
1691 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1692 }
1693 }
1694
1695 if (intr_status & EESR_RABT) {
1696 /* Receive Abort int */
1697 if (intr_status & EESR_RFRMER) {
1698 /* Receive Frame Overflow int */
1699 ndev->stats.rx_frame_errors++;
1700 }
1701 }
1702
1703 if (intr_status & EESR_TDE) {
1704 /* Transmit Descriptor Empty int */
1705 ndev->stats.tx_fifo_errors++;
1706 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1707 }
1708
1709 if (intr_status & EESR_TFE) {
1710 /* FIFO under flow */
1711 ndev->stats.tx_fifo_errors++;
1712 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1713 }
1714
1715 if (intr_status & EESR_RDE) {
1716 /* Receive Descriptor Empty int */
1717 ndev->stats.rx_over_errors++;
1718 }
1719
1720 if (intr_status & EESR_RFE) {
1721 /* Receive FIFO Overflow int */
1722 ndev->stats.rx_fifo_errors++;
1723 }
1724
1725 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1726 /* Address Error */
1727 ndev->stats.tx_fifo_errors++;
1728 netif_err(mdp, tx_err, ndev, "Address Error\n");
1729 }
1730
1731 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1732 if (mdp->cd->no_ade)
1733 mask &= ~EESR_ADE;
1734 if (intr_status & mask) {
1735 /* Tx error */
1736 u32 edtrr = sh_eth_read(ndev, EDTRR);
1737
1738 /* dmesg */
1739 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1740 intr_status, mdp->cur_tx, mdp->dirty_tx,
1741 (u32)ndev->state, edtrr);
1742 /* dirty buffer free */
1743 sh_eth_tx_free(ndev, true);
1744
1745 /* SH7712 BUG */
1746 if (edtrr ^ mdp->cd->edtrr_trns) {
1747 /* tx dma start */
1748 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1749 }
1750 /* wakeup */
1751 netif_wake_queue(ndev);
1752 }
1753}
1754
1755static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1756{
1757 struct net_device *ndev = netdev;
1758 struct sh_eth_private *mdp = netdev_priv(ndev);
1759 struct sh_eth_cpu_data *cd = mdp->cd;
1760 irqreturn_t ret = IRQ_NONE;
1761 u32 intr_status, intr_enable;
1762
1763 spin_lock(&mdp->lock);
1764
1765 /* Get interrupt status */
1766 intr_status = sh_eth_read(ndev, EESR);
1767 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1768 * enabled since it's the one that comes thru regardless of the mask,
1769 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1770 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1771 * bit...
1772 */
1773 intr_enable = sh_eth_read(ndev, EESIPR);
1774 intr_status &= intr_enable | EESIPR_ECIIP;
1775 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1776 cd->eesr_err_check))
1777 ret = IRQ_HANDLED;
1778 else
1779 goto out;
1780
1781 if (unlikely(!mdp->irq_enabled)) {
1782 sh_eth_write(ndev, 0, EESIPR);
1783 goto out;
1784 }
1785
1786 if (intr_status & EESR_RX_CHECK) {
1787 if (napi_schedule_prep(&mdp->napi)) {
1788 /* Mask Rx interrupts */
1789 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1790 EESIPR);
1791 __napi_schedule(&mdp->napi);
1792 } else {
1793 netdev_warn(ndev,
1794 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1795 intr_status, intr_enable);
1796 }
1797 }
1798
1799 /* Tx Check */
1800 if (intr_status & cd->tx_check) {
1801 /* Clear Tx interrupts */
1802 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1803
1804 sh_eth_tx_free(ndev, true);
1805 netif_wake_queue(ndev);
1806 }
1807
1808 /* E-MAC interrupt */
1809 if (intr_status & EESR_ECI)
1810 sh_eth_emac_interrupt(ndev);
1811
1812 if (intr_status & cd->eesr_err_check) {
1813 /* Clear error interrupts */
1814 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1815
1816 sh_eth_error(ndev, intr_status);
1817 }
1818
1819out:
1820 spin_unlock(&mdp->lock);
1821
1822 return ret;
1823}
1824
1825static int sh_eth_poll(struct napi_struct *napi, int budget)
1826{
1827 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1828 napi);
1829 struct net_device *ndev = napi->dev;
1830 int quota = budget;
1831 u32 intr_status;
1832
1833 for (;;) {
1834 intr_status = sh_eth_read(ndev, EESR);
1835 if (!(intr_status & EESR_RX_CHECK))
1836 break;
1837 /* Clear Rx interrupts */
1838 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1839
1840 if (sh_eth_rx(ndev, intr_status, "a))
1841 goto out;
1842 }
1843
1844 napi_complete(napi);
1845
1846 /* Reenable Rx interrupts */
1847 if (mdp->irq_enabled)
1848 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1849out:
1850 return budget - quota;
1851}
1852
1853/* PHY state control function */
1854static void sh_eth_adjust_link(struct net_device *ndev)
1855{
1856 struct sh_eth_private *mdp = netdev_priv(ndev);
1857 struct phy_device *phydev = ndev->phydev;
1858 int new_state = 0;
1859
1860 if (phydev->link) {
1861 if (phydev->duplex != mdp->duplex) {
1862 new_state = 1;
1863 mdp->duplex = phydev->duplex;
1864 if (mdp->cd->set_duplex)
1865 mdp->cd->set_duplex(ndev);
1866 }
1867
1868 if (phydev->speed != mdp->speed) {
1869 new_state = 1;
1870 mdp->speed = phydev->speed;
1871 if (mdp->cd->set_rate)
1872 mdp->cd->set_rate(ndev);
1873 }
1874 if (!mdp->link) {
1875 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
1876 new_state = 1;
1877 mdp->link = phydev->link;
1878 if (mdp->cd->no_psr || mdp->no_ether_link)
1879 sh_eth_rcv_snd_enable(ndev);
1880 }
1881 } else if (mdp->link) {
1882 new_state = 1;
1883 mdp->link = 0;
1884 mdp->speed = 0;
1885 mdp->duplex = -1;
1886 if (mdp->cd->no_psr || mdp->no_ether_link)
1887 sh_eth_rcv_snd_disable(ndev);
1888 }
1889
1890 if (new_state && netif_msg_link(mdp))
1891 phy_print_status(phydev);
1892}
1893
1894/* PHY init function */
1895static int sh_eth_phy_init(struct net_device *ndev)
1896{
1897 struct device_node *np = ndev->dev.parent->of_node;
1898 struct sh_eth_private *mdp = netdev_priv(ndev);
1899 struct phy_device *phydev;
1900
1901 mdp->link = 0;
1902 mdp->speed = 0;
1903 mdp->duplex = -1;
1904
1905 /* Try connect to PHY */
1906 if (np) {
1907 struct device_node *pn;
1908
1909 pn = of_parse_phandle(np, "phy-handle", 0);
1910 phydev = of_phy_connect(ndev, pn,
1911 sh_eth_adjust_link, 0,
1912 mdp->phy_interface);
1913
1914 of_node_put(pn);
1915 if (!phydev)
1916 phydev = ERR_PTR(-ENOENT);
1917 } else {
1918 char phy_id[MII_BUS_ID_SIZE + 3];
1919
1920 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
1921 mdp->mii_bus->id, mdp->phy_id);
1922
1923 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
1924 mdp->phy_interface);
1925 }
1926
1927 if (IS_ERR(phydev)) {
1928 netdev_err(ndev, "failed to connect PHY\n");
1929 return PTR_ERR(phydev);
1930 }
1931
1932 /* mask with MAC supported features */
1933 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
1934 int err = phy_set_max_speed(phydev, SPEED_100);
1935 if (err) {
1936 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
1937 phy_disconnect(phydev);
1938 return err;
1939 }
1940 }
1941
1942 phy_attached_info(phydev);
1943
1944 return 0;
1945}
1946
1947/* PHY control start function */
1948static int sh_eth_phy_start(struct net_device *ndev)
1949{
1950 int ret;
1951
1952 ret = sh_eth_phy_init(ndev);
1953 if (ret)
1954 return ret;
1955
1956 phy_start(ndev->phydev);
1957
1958 return 0;
1959}
1960
1961static int sh_eth_get_link_ksettings(struct net_device *ndev,
1962 struct ethtool_link_ksettings *cmd)
1963{
1964 struct sh_eth_private *mdp = netdev_priv(ndev);
1965 unsigned long flags;
1966
1967 if (!ndev->phydev)
1968 return -ENODEV;
1969
1970 spin_lock_irqsave(&mdp->lock, flags);
1971 phy_ethtool_ksettings_get(ndev->phydev, cmd);
1972 spin_unlock_irqrestore(&mdp->lock, flags);
1973
1974 return 0;
1975}
1976
1977static int sh_eth_set_link_ksettings(struct net_device *ndev,
1978 const struct ethtool_link_ksettings *cmd)
1979{
1980 struct sh_eth_private *mdp = netdev_priv(ndev);
1981 unsigned long flags;
1982 int ret;
1983
1984 if (!ndev->phydev)
1985 return -ENODEV;
1986
1987 spin_lock_irqsave(&mdp->lock, flags);
1988
1989 /* disable tx and rx */
1990 sh_eth_rcv_snd_disable(ndev);
1991
1992 ret = phy_ethtool_ksettings_set(ndev->phydev, cmd);
1993 if (ret)
1994 goto error_exit;
1995
1996 if (cmd->base.duplex == DUPLEX_FULL)
1997 mdp->duplex = 1;
1998 else
1999 mdp->duplex = 0;
2000
2001 if (mdp->cd->set_duplex)
2002 mdp->cd->set_duplex(ndev);
2003
2004error_exit:
2005 mdelay(1);
2006
2007 /* enable tx and rx */
2008 sh_eth_rcv_snd_enable(ndev);
2009
2010 spin_unlock_irqrestore(&mdp->lock, flags);
2011
2012 return ret;
2013}
2014
2015/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2016 * version must be bumped as well. Just adding registers up to that
2017 * limit is fine, as long as the existing register indices don't
2018 * change.
2019 */
2020#define SH_ETH_REG_DUMP_VERSION 1
2021#define SH_ETH_REG_DUMP_MAX_REGS 256
2022
2023static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2024{
2025 struct sh_eth_private *mdp = netdev_priv(ndev);
2026 struct sh_eth_cpu_data *cd = mdp->cd;
2027 u32 *valid_map;
2028 size_t len;
2029
2030 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2031
2032 /* Dump starts with a bitmap that tells ethtool which
2033 * registers are defined for this chip.
2034 */
2035 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2036 if (buf) {
2037 valid_map = buf;
2038 buf += len;
2039 } else {
2040 valid_map = NULL;
2041 }
2042
2043 /* Add a register to the dump, if it has a defined offset.
2044 * This automatically skips most undefined registers, but for
2045 * some it is also necessary to check a capability flag in
2046 * struct sh_eth_cpu_data.
2047 */
2048#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2049#define add_reg_from(reg, read_expr) do { \
2050 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2051 if (buf) { \
2052 mark_reg_valid(reg); \
2053 *buf++ = read_expr; \
2054 } \
2055 ++len; \
2056 } \
2057 } while (0)
2058#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2059#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2060
2061 add_reg(EDSR);
2062 add_reg(EDMR);
2063 add_reg(EDTRR);
2064 add_reg(EDRRR);
2065 add_reg(EESR);
2066 add_reg(EESIPR);
2067 add_reg(TDLAR);
2068 add_reg(TDFAR);
2069 add_reg(TDFXR);
2070 add_reg(TDFFR);
2071 add_reg(RDLAR);
2072 add_reg(RDFAR);
2073 add_reg(RDFXR);
2074 add_reg(RDFFR);
2075 add_reg(TRSCER);
2076 add_reg(RMFCR);
2077 add_reg(TFTR);
2078 add_reg(FDR);
2079 add_reg(RMCR);
2080 add_reg(TFUCR);
2081 add_reg(RFOCR);
2082 if (cd->rmiimode)
2083 add_reg(RMIIMODE);
2084 add_reg(FCFTR);
2085 if (cd->rpadir)
2086 add_reg(RPADIR);
2087 if (!cd->no_trimd)
2088 add_reg(TRIMD);
2089 add_reg(ECMR);
2090 add_reg(ECSR);
2091 add_reg(ECSIPR);
2092 add_reg(PIR);
2093 if (!cd->no_psr)
2094 add_reg(PSR);
2095 add_reg(RDMLR);
2096 add_reg(RFLR);
2097 add_reg(IPGR);
2098 if (cd->apr)
2099 add_reg(APR);
2100 if (cd->mpr)
2101 add_reg(MPR);
2102 add_reg(RFCR);
2103 add_reg(RFCF);
2104 if (cd->tpauser)
2105 add_reg(TPAUSER);
2106 add_reg(TPAUSECR);
2107 add_reg(GECMR);
2108 if (cd->bculr)
2109 add_reg(BCULR);
2110 add_reg(MAHR);
2111 add_reg(MALR);
2112 add_reg(TROCR);
2113 add_reg(CDCR);
2114 add_reg(LCCR);
2115 add_reg(CNDCR);
2116 add_reg(CEFCR);
2117 add_reg(FRECR);
2118 add_reg(TSFRCR);
2119 add_reg(TLFRCR);
2120 add_reg(CERCR);
2121 add_reg(CEECR);
2122 add_reg(MAFCR);
2123 if (cd->rtrate)
2124 add_reg(RTRATE);
2125 if (cd->hw_checksum)
2126 add_reg(CSMR);
2127 if (cd->select_mii)
2128 add_reg(RMII_MII);
2129 if (cd->tsu) {
2130 add_tsu_reg(ARSTR);
2131 add_tsu_reg(TSU_CTRST);
2132 add_tsu_reg(TSU_FWEN0);
2133 add_tsu_reg(TSU_FWEN1);
2134 add_tsu_reg(TSU_FCM);
2135 add_tsu_reg(TSU_BSYSL0);
2136 add_tsu_reg(TSU_BSYSL1);
2137 add_tsu_reg(TSU_PRISL0);
2138 add_tsu_reg(TSU_PRISL1);
2139 add_tsu_reg(TSU_FWSL0);
2140 add_tsu_reg(TSU_FWSL1);
2141 add_tsu_reg(TSU_FWSLC);
2142 add_tsu_reg(TSU_QTAGM0);
2143 add_tsu_reg(TSU_QTAGM1);
2144 add_tsu_reg(TSU_FWSR);
2145 add_tsu_reg(TSU_FWINMK);
2146 add_tsu_reg(TSU_ADQT0);
2147 add_tsu_reg(TSU_ADQT1);
2148 add_tsu_reg(TSU_VTAG0);
2149 add_tsu_reg(TSU_VTAG1);
2150 add_tsu_reg(TSU_ADSBSY);
2151 add_tsu_reg(TSU_TEN);
2152 add_tsu_reg(TSU_POST1);
2153 add_tsu_reg(TSU_POST2);
2154 add_tsu_reg(TSU_POST3);
2155 add_tsu_reg(TSU_POST4);
2156 /* This is the start of a table, not just a single register. */
2157 if (buf) {
2158 unsigned int i;
2159
2160 mark_reg_valid(TSU_ADRH0);
2161 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2162 *buf++ = ioread32(mdp->tsu_addr +
2163 mdp->reg_offset[TSU_ADRH0] +
2164 i * 4);
2165 }
2166 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2167 }
2168
2169#undef mark_reg_valid
2170#undef add_reg_from
2171#undef add_reg
2172#undef add_tsu_reg
2173
2174 return len * 4;
2175}
2176
2177static int sh_eth_get_regs_len(struct net_device *ndev)
2178{
2179 return __sh_eth_get_regs(ndev, NULL);
2180}
2181
2182static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2183 void *buf)
2184{
2185 struct sh_eth_private *mdp = netdev_priv(ndev);
2186
2187 regs->version = SH_ETH_REG_DUMP_VERSION;
2188
2189 pm_runtime_get_sync(&mdp->pdev->dev);
2190 __sh_eth_get_regs(ndev, buf);
2191 pm_runtime_put_sync(&mdp->pdev->dev);
2192}
2193
2194static int sh_eth_nway_reset(struct net_device *ndev)
2195{
2196 struct sh_eth_private *mdp = netdev_priv(ndev);
2197 unsigned long flags;
2198 int ret;
2199
2200 if (!ndev->phydev)
2201 return -ENODEV;
2202
2203 spin_lock_irqsave(&mdp->lock, flags);
2204 ret = phy_start_aneg(ndev->phydev);
2205 spin_unlock_irqrestore(&mdp->lock, flags);
2206
2207 return ret;
2208}
2209
2210static u32 sh_eth_get_msglevel(struct net_device *ndev)
2211{
2212 struct sh_eth_private *mdp = netdev_priv(ndev);
2213 return mdp->msg_enable;
2214}
2215
2216static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2217{
2218 struct sh_eth_private *mdp = netdev_priv(ndev);
2219 mdp->msg_enable = value;
2220}
2221
2222static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2223 "rx_current", "tx_current",
2224 "rx_dirty", "tx_dirty",
2225};
2226#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2227
2228static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2229{
2230 switch (sset) {
2231 case ETH_SS_STATS:
2232 return SH_ETH_STATS_LEN;
2233 default:
2234 return -EOPNOTSUPP;
2235 }
2236}
2237
2238static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2239 struct ethtool_stats *stats, u64 *data)
2240{
2241 struct sh_eth_private *mdp = netdev_priv(ndev);
2242 int i = 0;
2243
2244 /* device-specific stats */
2245 data[i++] = mdp->cur_rx;
2246 data[i++] = mdp->cur_tx;
2247 data[i++] = mdp->dirty_rx;
2248 data[i++] = mdp->dirty_tx;
2249}
2250
2251static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2252{
2253 switch (stringset) {
2254 case ETH_SS_STATS:
2255 memcpy(data, *sh_eth_gstrings_stats,
2256 sizeof(sh_eth_gstrings_stats));
2257 break;
2258 }
2259}
2260
2261static void sh_eth_get_ringparam(struct net_device *ndev,
2262 struct ethtool_ringparam *ring)
2263{
2264 struct sh_eth_private *mdp = netdev_priv(ndev);
2265
2266 ring->rx_max_pending = RX_RING_MAX;
2267 ring->tx_max_pending = TX_RING_MAX;
2268 ring->rx_pending = mdp->num_rx_ring;
2269 ring->tx_pending = mdp->num_tx_ring;
2270}
2271
2272static int sh_eth_set_ringparam(struct net_device *ndev,
2273 struct ethtool_ringparam *ring)
2274{
2275 struct sh_eth_private *mdp = netdev_priv(ndev);
2276 int ret;
2277
2278 if (ring->tx_pending > TX_RING_MAX ||
2279 ring->rx_pending > RX_RING_MAX ||
2280 ring->tx_pending < TX_RING_MIN ||
2281 ring->rx_pending < RX_RING_MIN)
2282 return -EINVAL;
2283 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2284 return -EINVAL;
2285
2286 if (netif_running(ndev)) {
2287 netif_device_detach(ndev);
2288 netif_tx_disable(ndev);
2289
2290 /* Serialise with the interrupt handler and NAPI, then
2291 * disable interrupts. We have to clear the
2292 * irq_enabled flag first to ensure that interrupts
2293 * won't be re-enabled.
2294 */
2295 mdp->irq_enabled = false;
2296 synchronize_irq(ndev->irq);
2297 napi_synchronize(&mdp->napi);
2298 sh_eth_write(ndev, 0x0000, EESIPR);
2299
2300 sh_eth_dev_exit(ndev);
2301
2302 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2303 sh_eth_ring_free(ndev);
2304 }
2305
2306 /* Set new parameters */
2307 mdp->num_rx_ring = ring->rx_pending;
2308 mdp->num_tx_ring = ring->tx_pending;
2309
2310 if (netif_running(ndev)) {
2311 ret = sh_eth_ring_init(ndev);
2312 if (ret < 0) {
2313 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2314 __func__);
2315 return ret;
2316 }
2317 ret = sh_eth_dev_init(ndev);
2318 if (ret < 0) {
2319 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2320 __func__);
2321 return ret;
2322 }
2323
2324 netif_device_attach(ndev);
2325 }
2326
2327 return 0;
2328}
2329
2330static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2331{
2332 struct sh_eth_private *mdp = netdev_priv(ndev);
2333
2334 wol->supported = 0;
2335 wol->wolopts = 0;
2336
2337 if (mdp->cd->magic) {
2338 wol->supported = WAKE_MAGIC;
2339 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2340 }
2341}
2342
2343static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2344{
2345 struct sh_eth_private *mdp = netdev_priv(ndev);
2346
2347 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2348 return -EOPNOTSUPP;
2349
2350 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2351
2352 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2353
2354 return 0;
2355}
2356
2357static const struct ethtool_ops sh_eth_ethtool_ops = {
2358 .get_regs_len = sh_eth_get_regs_len,
2359 .get_regs = sh_eth_get_regs,
2360 .nway_reset = sh_eth_nway_reset,
2361 .get_msglevel = sh_eth_get_msglevel,
2362 .set_msglevel = sh_eth_set_msglevel,
2363 .get_link = ethtool_op_get_link,
2364 .get_strings = sh_eth_get_strings,
2365 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2366 .get_sset_count = sh_eth_get_sset_count,
2367 .get_ringparam = sh_eth_get_ringparam,
2368 .set_ringparam = sh_eth_set_ringparam,
2369 .get_link_ksettings = sh_eth_get_link_ksettings,
2370 .set_link_ksettings = sh_eth_set_link_ksettings,
2371 .get_wol = sh_eth_get_wol,
2372 .set_wol = sh_eth_set_wol,
2373};
2374
2375/* network device open function */
2376static int sh_eth_open(struct net_device *ndev)
2377{
2378 struct sh_eth_private *mdp = netdev_priv(ndev);
2379 int ret;
2380
2381 pm_runtime_get_sync(&mdp->pdev->dev);
2382
2383 napi_enable(&mdp->napi);
2384
2385 ret = request_irq(ndev->irq, sh_eth_interrupt,
2386 mdp->cd->irq_flags, ndev->name, ndev);
2387 if (ret) {
2388 netdev_err(ndev, "Can not assign IRQ number\n");
2389 goto out_napi_off;
2390 }
2391
2392 /* Descriptor set */
2393 ret = sh_eth_ring_init(ndev);
2394 if (ret)
2395 goto out_free_irq;
2396
2397 /* device init */
2398 ret = sh_eth_dev_init(ndev);
2399 if (ret)
2400 goto out_free_irq;
2401
2402 /* PHY control start*/
2403 ret = sh_eth_phy_start(ndev);
2404 if (ret)
2405 goto out_free_irq;
2406
2407 netif_start_queue(ndev);
2408
2409 mdp->is_opened = 1;
2410
2411 return ret;
2412
2413out_free_irq:
2414 free_irq(ndev->irq, ndev);
2415out_napi_off:
2416 napi_disable(&mdp->napi);
2417 pm_runtime_put_sync(&mdp->pdev->dev);
2418 return ret;
2419}
2420
2421/* Timeout function */
2422static void sh_eth_tx_timeout(struct net_device *ndev)
2423{
2424 struct sh_eth_private *mdp = netdev_priv(ndev);
2425 struct sh_eth_rxdesc *rxdesc;
2426 int i;
2427
2428 netif_stop_queue(ndev);
2429
2430 netif_err(mdp, timer, ndev,
2431 "transmit timed out, status %8.8x, resetting...\n",
2432 sh_eth_read(ndev, EESR));
2433
2434 /* tx_errors count up */
2435 ndev->stats.tx_errors++;
2436
2437 /* Free all the skbuffs in the Rx queue. */
2438 for (i = 0; i < mdp->num_rx_ring; i++) {
2439 rxdesc = &mdp->rx_ring[i];
2440 rxdesc->status = cpu_to_le32(0);
2441 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2442 dev_kfree_skb(mdp->rx_skbuff[i]);
2443 mdp->rx_skbuff[i] = NULL;
2444 }
2445 for (i = 0; i < mdp->num_tx_ring; i++) {
2446 dev_kfree_skb(mdp->tx_skbuff[i]);
2447 mdp->tx_skbuff[i] = NULL;
2448 }
2449
2450 /* device init */
2451 sh_eth_dev_init(ndev);
2452
2453 netif_start_queue(ndev);
2454}
2455
2456/* Packet transmit function */
2457static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2458{
2459 struct sh_eth_private *mdp = netdev_priv(ndev);
2460 struct sh_eth_txdesc *txdesc;
2461 dma_addr_t dma_addr;
2462 u32 entry;
2463 unsigned long flags;
2464
2465 spin_lock_irqsave(&mdp->lock, flags);
2466 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2467 if (!sh_eth_tx_free(ndev, true)) {
2468 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2469 netif_stop_queue(ndev);
2470 spin_unlock_irqrestore(&mdp->lock, flags);
2471 return NETDEV_TX_BUSY;
2472 }
2473 }
2474 spin_unlock_irqrestore(&mdp->lock, flags);
2475
2476 if (skb_put_padto(skb, ETH_ZLEN))
2477 return NETDEV_TX_OK;
2478
2479 entry = mdp->cur_tx % mdp->num_tx_ring;
2480 mdp->tx_skbuff[entry] = skb;
2481 txdesc = &mdp->tx_ring[entry];
2482 /* soft swap. */
2483 if (!mdp->cd->hw_swap)
2484 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2485 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2486 DMA_TO_DEVICE);
2487 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2488 kfree_skb(skb);
2489 return NETDEV_TX_OK;
2490 }
2491 txdesc->addr = cpu_to_le32(dma_addr);
2492 txdesc->len = cpu_to_le32(skb->len << 16);
2493
2494 dma_wmb(); /* TACT bit must be set after all the above writes */
2495 if (entry >= mdp->num_tx_ring - 1)
2496 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2497 else
2498 txdesc->status |= cpu_to_le32(TD_TACT);
2499
2500 mdp->cur_tx++;
2501
2502 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2503 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2504
2505 return NETDEV_TX_OK;
2506}
2507
2508/* The statistics registers have write-clear behaviour, which means we
2509 * will lose any increment between the read and write. We mitigate
2510 * this by only clearing when we read a non-zero value, so we will
2511 * never falsely report a total of zero.
2512 */
2513static void
2514sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2515{
2516 u32 delta = sh_eth_read(ndev, reg);
2517
2518 if (delta) {
2519 *stat += delta;
2520 sh_eth_write(ndev, 0, reg);
2521 }
2522}
2523
2524static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2525{
2526 struct sh_eth_private *mdp = netdev_priv(ndev);
2527
2528 if (mdp->cd->no_tx_cntrs)
2529 return &ndev->stats;
2530
2531 if (!mdp->is_opened)
2532 return &ndev->stats;
2533
2534 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2535 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2536 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2537
2538 if (mdp->cd->cexcr) {
2539 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2540 CERCR);
2541 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2542 CEECR);
2543 } else {
2544 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2545 CNDCR);
2546 }
2547
2548 return &ndev->stats;
2549}
2550
2551/* device close function */
2552static int sh_eth_close(struct net_device *ndev)
2553{
2554 struct sh_eth_private *mdp = netdev_priv(ndev);
2555
2556 netif_stop_queue(ndev);
2557
2558 /* Serialise with the interrupt handler and NAPI, then disable
2559 * interrupts. We have to clear the irq_enabled flag first to
2560 * ensure that interrupts won't be re-enabled.
2561 */
2562 mdp->irq_enabled = false;
2563 synchronize_irq(ndev->irq);
2564 napi_disable(&mdp->napi);
2565 sh_eth_write(ndev, 0x0000, EESIPR);
2566
2567 sh_eth_dev_exit(ndev);
2568
2569 /* PHY Disconnect */
2570 if (ndev->phydev) {
2571 phy_stop(ndev->phydev);
2572 phy_disconnect(ndev->phydev);
2573 }
2574
2575 free_irq(ndev->irq, ndev);
2576
2577 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2578 sh_eth_ring_free(ndev);
2579
2580 pm_runtime_put_sync(&mdp->pdev->dev);
2581
2582 mdp->is_opened = 0;
2583
2584 return 0;
2585}
2586
2587/* ioctl to device function */
2588static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2589{
2590 struct phy_device *phydev = ndev->phydev;
2591
2592 if (!netif_running(ndev))
2593 return -EINVAL;
2594
2595 if (!phydev)
2596 return -ENODEV;
2597
2598 return phy_mii_ioctl(phydev, rq, cmd);
2599}
2600
2601static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2602{
2603 if (netif_running(ndev))
2604 return -EBUSY;
2605
2606 ndev->mtu = new_mtu;
2607 netdev_update_features(ndev);
2608
2609 return 0;
2610}
2611
2612/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2613static void *sh_eth_tsu_get_post_reg_offset(struct sh_eth_private *mdp,
2614 int entry)
2615{
2616 return sh_eth_tsu_get_offset(mdp, TSU_POST1) + (entry / 8 * 4);
2617}
2618
2619static u32 sh_eth_tsu_get_post_mask(int entry)
2620{
2621 return 0x0f << (28 - ((entry % 8) * 4));
2622}
2623
2624static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2625{
2626 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2627}
2628
2629static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2630 int entry)
2631{
2632 struct sh_eth_private *mdp = netdev_priv(ndev);
2633 u32 tmp;
2634 void *reg_offset;
2635
2636 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2637 tmp = ioread32(reg_offset);
2638 iowrite32(tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg_offset);
2639}
2640
2641static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2642 int entry)
2643{
2644 struct sh_eth_private *mdp = netdev_priv(ndev);
2645 u32 post_mask, ref_mask, tmp;
2646 void *reg_offset;
2647
2648 reg_offset = sh_eth_tsu_get_post_reg_offset(mdp, entry);
2649 post_mask = sh_eth_tsu_get_post_mask(entry);
2650 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2651
2652 tmp = ioread32(reg_offset);
2653 iowrite32(tmp & ~post_mask, reg_offset);
2654
2655 /* If other port enables, the function returns "true" */
2656 return tmp & ref_mask;
2657}
2658
2659static int sh_eth_tsu_busy(struct net_device *ndev)
2660{
2661 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2662 struct sh_eth_private *mdp = netdev_priv(ndev);
2663
2664 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2665 udelay(10);
2666 timeout--;
2667 if (timeout <= 0) {
2668 netdev_err(ndev, "%s: timeout\n", __func__);
2669 return -ETIMEDOUT;
2670 }
2671 }
2672
2673 return 0;
2674}
2675
2676static int sh_eth_tsu_write_entry(struct net_device *ndev, void *reg,
2677 const u8 *addr)
2678{
2679 u32 val;
2680
2681 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2682 iowrite32(val, reg);
2683 if (sh_eth_tsu_busy(ndev) < 0)
2684 return -EBUSY;
2685
2686 val = addr[4] << 8 | addr[5];
2687 iowrite32(val, reg + 4);
2688 if (sh_eth_tsu_busy(ndev) < 0)
2689 return -EBUSY;
2690
2691 return 0;
2692}
2693
2694static void sh_eth_tsu_read_entry(void *reg, u8 *addr)
2695{
2696 u32 val;
2697
2698 val = ioread32(reg);
2699 addr[0] = (val >> 24) & 0xff;
2700 addr[1] = (val >> 16) & 0xff;
2701 addr[2] = (val >> 8) & 0xff;
2702 addr[3] = val & 0xff;
2703 val = ioread32(reg + 4);
2704 addr[4] = (val >> 8) & 0xff;
2705 addr[5] = val & 0xff;
2706}
2707
2708
2709static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2710{
2711 struct sh_eth_private *mdp = netdev_priv(ndev);
2712 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2713 int i;
2714 u8 c_addr[ETH_ALEN];
2715
2716 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2717 sh_eth_tsu_read_entry(reg_offset, c_addr);
2718 if (ether_addr_equal(addr, c_addr))
2719 return i;
2720 }
2721
2722 return -ENOENT;
2723}
2724
2725static int sh_eth_tsu_find_empty(struct net_device *ndev)
2726{
2727 u8 blank[ETH_ALEN];
2728 int entry;
2729
2730 memset(blank, 0, sizeof(blank));
2731 entry = sh_eth_tsu_find_entry(ndev, blank);
2732 return (entry < 0) ? -ENOMEM : entry;
2733}
2734
2735static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2736 int entry)
2737{
2738 struct sh_eth_private *mdp = netdev_priv(ndev);
2739 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2740 int ret;
2741 u8 blank[ETH_ALEN];
2742
2743 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2744 ~(1 << (31 - entry)), TSU_TEN);
2745
2746 memset(blank, 0, sizeof(blank));
2747 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2748 if (ret < 0)
2749 return ret;
2750 return 0;
2751}
2752
2753static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2754{
2755 struct sh_eth_private *mdp = netdev_priv(ndev);
2756 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2757 int i, ret;
2758
2759 if (!mdp->cd->tsu)
2760 return 0;
2761
2762 i = sh_eth_tsu_find_entry(ndev, addr);
2763 if (i < 0) {
2764 /* No entry found, create one */
2765 i = sh_eth_tsu_find_empty(ndev);
2766 if (i < 0)
2767 return -ENOMEM;
2768 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2769 if (ret < 0)
2770 return ret;
2771
2772 /* Enable the entry */
2773 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2774 (1 << (31 - i)), TSU_TEN);
2775 }
2776
2777 /* Entry found or created, enable POST */
2778 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2779
2780 return 0;
2781}
2782
2783static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2784{
2785 struct sh_eth_private *mdp = netdev_priv(ndev);
2786 int i, ret;
2787
2788 if (!mdp->cd->tsu)
2789 return 0;
2790
2791 i = sh_eth_tsu_find_entry(ndev, addr);
2792 if (i) {
2793 /* Entry found */
2794 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2795 goto done;
2796
2797 /* Disable the entry if both ports was disabled */
2798 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2799 if (ret < 0)
2800 return ret;
2801 }
2802done:
2803 return 0;
2804}
2805
2806static int sh_eth_tsu_purge_all(struct net_device *ndev)
2807{
2808 struct sh_eth_private *mdp = netdev_priv(ndev);
2809 int i, ret;
2810
2811 if (!mdp->cd->tsu)
2812 return 0;
2813
2814 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2815 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2816 continue;
2817
2818 /* Disable the entry if both ports was disabled */
2819 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2820 if (ret < 0)
2821 return ret;
2822 }
2823
2824 return 0;
2825}
2826
2827static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2828{
2829 struct sh_eth_private *mdp = netdev_priv(ndev);
2830 u8 addr[ETH_ALEN];
2831 void *reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2832 int i;
2833
2834 if (!mdp->cd->tsu)
2835 return;
2836
2837 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2838 sh_eth_tsu_read_entry(reg_offset, addr);
2839 if (is_multicast_ether_addr(addr))
2840 sh_eth_tsu_del_entry(ndev, addr);
2841 }
2842}
2843
2844/* Update promiscuous flag and multicast filter */
2845static void sh_eth_set_rx_mode(struct net_device *ndev)
2846{
2847 struct sh_eth_private *mdp = netdev_priv(ndev);
2848 u32 ecmr_bits;
2849 int mcast_all = 0;
2850 unsigned long flags;
2851
2852 spin_lock_irqsave(&mdp->lock, flags);
2853 /* Initial condition is MCT = 1, PRM = 0.
2854 * Depending on ndev->flags, set PRM or clear MCT
2855 */
2856 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2857 if (mdp->cd->tsu)
2858 ecmr_bits |= ECMR_MCT;
2859
2860 if (!(ndev->flags & IFF_MULTICAST)) {
2861 sh_eth_tsu_purge_mcast(ndev);
2862 mcast_all = 1;
2863 }
2864 if (ndev->flags & IFF_ALLMULTI) {
2865 sh_eth_tsu_purge_mcast(ndev);
2866 ecmr_bits &= ~ECMR_MCT;
2867 mcast_all = 1;
2868 }
2869
2870 if (ndev->flags & IFF_PROMISC) {
2871 sh_eth_tsu_purge_all(ndev);
2872 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2873 } else if (mdp->cd->tsu) {
2874 struct netdev_hw_addr *ha;
2875 netdev_for_each_mc_addr(ha, ndev) {
2876 if (mcast_all && is_multicast_ether_addr(ha->addr))
2877 continue;
2878
2879 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2880 if (!mcast_all) {
2881 sh_eth_tsu_purge_mcast(ndev);
2882 ecmr_bits &= ~ECMR_MCT;
2883 mcast_all = 1;
2884 }
2885 }
2886 }
2887 }
2888
2889 /* update the ethernet mode */
2890 sh_eth_write(ndev, ecmr_bits, ECMR);
2891
2892 spin_unlock_irqrestore(&mdp->lock, flags);
2893}
2894
2895static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2896{
2897 if (!mdp->port)
2898 return TSU_VTAG0;
2899 else
2900 return TSU_VTAG1;
2901}
2902
2903static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2904 __be16 proto, u16 vid)
2905{
2906 struct sh_eth_private *mdp = netdev_priv(ndev);
2907 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2908
2909 if (unlikely(!mdp->cd->tsu))
2910 return -EPERM;
2911
2912 /* No filtering if vid = 0 */
2913 if (!vid)
2914 return 0;
2915
2916 mdp->vlan_num_ids++;
2917
2918 /* The controller has one VLAN tag HW filter. So, if the filter is
2919 * already enabled, the driver disables it and the filte
2920 */
2921 if (mdp->vlan_num_ids > 1) {
2922 /* disable VLAN filter */
2923 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2924 return 0;
2925 }
2926
2927 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
2928 vtag_reg_index);
2929
2930 return 0;
2931}
2932
2933static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
2934 __be16 proto, u16 vid)
2935{
2936 struct sh_eth_private *mdp = netdev_priv(ndev);
2937 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2938
2939 if (unlikely(!mdp->cd->tsu))
2940 return -EPERM;
2941
2942 /* No filtering if vid = 0 */
2943 if (!vid)
2944 return 0;
2945
2946 mdp->vlan_num_ids--;
2947 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
2948
2949 return 0;
2950}
2951
2952/* SuperH's TSU register init function */
2953static void sh_eth_tsu_init(struct sh_eth_private *mdp)
2954{
2955 if (!mdp->cd->dual_port) {
2956 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2957 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
2958 TSU_FWSLC); /* Enable POST registers */
2959 return;
2960 }
2961
2962 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
2963 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
2964 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
2965 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
2966 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
2967 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
2968 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
2969 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
2970 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
2971 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
2972 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
2973 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
2974 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
2975 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
2976 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
2977 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
2978 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
2979 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
2980 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
2981}
2982
2983/* MDIO bus release function */
2984static int sh_mdio_release(struct sh_eth_private *mdp)
2985{
2986 /* unregister mdio bus */
2987 mdiobus_unregister(mdp->mii_bus);
2988
2989 /* free bitbang info */
2990 free_mdio_bitbang(mdp->mii_bus);
2991
2992 return 0;
2993}
2994
2995/* MDIO bus init function */
2996static int sh_mdio_init(struct sh_eth_private *mdp,
2997 struct sh_eth_plat_data *pd)
2998{
2999 int ret;
3000 struct bb_info *bitbang;
3001 struct platform_device *pdev = mdp->pdev;
3002 struct device *dev = &mdp->pdev->dev;
3003
3004 /* create bit control struct for PHY */
3005 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3006 if (!bitbang)
3007 return -ENOMEM;
3008
3009 /* bitbang init */
3010 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3011 bitbang->set_gate = pd->set_mdio_gate;
3012 bitbang->ctrl.ops = &bb_ops;
3013
3014 /* MII controller setting */
3015 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3016 if (!mdp->mii_bus)
3017 return -ENOMEM;
3018
3019 /* Hook up MII support for ethtool */
3020 mdp->mii_bus->name = "sh_mii";
3021 mdp->mii_bus->parent = dev;
3022 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3023 pdev->name, pdev->id);
3024
3025 /* register MDIO bus */
3026 if (dev->of_node) {
3027 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3028 } else {
3029 if (pd->phy_irq > 0)
3030 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3031
3032 ret = mdiobus_register(mdp->mii_bus);
3033 }
3034
3035 if (ret)
3036 goto out_free_bus;
3037
3038 return 0;
3039
3040out_free_bus:
3041 free_mdio_bitbang(mdp->mii_bus);
3042 return ret;
3043}
3044
3045static const u16 *sh_eth_get_register_offset(int register_type)
3046{
3047 const u16 *reg_offset = NULL;
3048
3049 switch (register_type) {
3050 case SH_ETH_REG_GIGABIT:
3051 reg_offset = sh_eth_offset_gigabit;
3052 break;
3053 case SH_ETH_REG_FAST_RZ:
3054 reg_offset = sh_eth_offset_fast_rz;
3055 break;
3056 case SH_ETH_REG_FAST_RCAR:
3057 reg_offset = sh_eth_offset_fast_rcar;
3058 break;
3059 case SH_ETH_REG_FAST_SH4:
3060 reg_offset = sh_eth_offset_fast_sh4;
3061 break;
3062 case SH_ETH_REG_FAST_SH3_SH2:
3063 reg_offset = sh_eth_offset_fast_sh3_sh2;
3064 break;
3065 }
3066
3067 return reg_offset;
3068}
3069
3070static const struct net_device_ops sh_eth_netdev_ops = {
3071 .ndo_open = sh_eth_open,
3072 .ndo_stop = sh_eth_close,
3073 .ndo_start_xmit = sh_eth_start_xmit,
3074 .ndo_get_stats = sh_eth_get_stats,
3075 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3076 .ndo_tx_timeout = sh_eth_tx_timeout,
3077 .ndo_do_ioctl = sh_eth_do_ioctl,
3078 .ndo_change_mtu = sh_eth_change_mtu,
3079 .ndo_validate_addr = eth_validate_addr,
3080 .ndo_set_mac_address = eth_mac_addr,
3081};
3082
3083static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3084 .ndo_open = sh_eth_open,
3085 .ndo_stop = sh_eth_close,
3086 .ndo_start_xmit = sh_eth_start_xmit,
3087 .ndo_get_stats = sh_eth_get_stats,
3088 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3089 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3090 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3091 .ndo_tx_timeout = sh_eth_tx_timeout,
3092 .ndo_do_ioctl = sh_eth_do_ioctl,
3093 .ndo_change_mtu = sh_eth_change_mtu,
3094 .ndo_validate_addr = eth_validate_addr,
3095 .ndo_set_mac_address = eth_mac_addr,
3096};
3097
3098#ifdef CONFIG_OF
3099static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3100{
3101 struct device_node *np = dev->of_node;
3102 struct sh_eth_plat_data *pdata;
3103 const char *mac_addr;
3104
3105 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3106 if (!pdata)
3107 return NULL;
3108
3109 pdata->phy_interface = of_get_phy_mode(np);
3110
3111 mac_addr = of_get_mac_address(np);
3112 if (mac_addr)
3113 memcpy(pdata->mac_addr, mac_addr, ETH_ALEN);
3114
3115 pdata->no_ether_link =
3116 of_property_read_bool(np, "renesas,no-ether-link");
3117 pdata->ether_link_active_low =
3118 of_property_read_bool(np, "renesas,ether-link-active-low");
3119
3120 return pdata;
3121}
3122
3123static const struct of_device_id sh_eth_match_table[] = {
3124 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3125 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3126 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3127 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3128 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3129 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3130 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3131 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3132 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3133 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3134 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3135 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3136 { }
3137};
3138MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3139#else
3140static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3141{
3142 return NULL;
3143}
3144#endif
3145
3146static int sh_eth_drv_probe(struct platform_device *pdev)
3147{
3148 struct resource *res;
3149 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3150 const struct platform_device_id *id = platform_get_device_id(pdev);
3151 struct sh_eth_private *mdp;
3152 struct net_device *ndev;
3153 int ret;
3154
3155 /* get base addr */
3156 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3157
3158 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3159 if (!ndev)
3160 return -ENOMEM;
3161
3162 pm_runtime_enable(&pdev->dev);
3163 pm_runtime_get_sync(&pdev->dev);
3164
3165 ret = platform_get_irq(pdev, 0);
3166 if (ret < 0)
3167 goto out_release;
3168 ndev->irq = ret;
3169
3170 SET_NETDEV_DEV(ndev, &pdev->dev);
3171
3172 mdp = netdev_priv(ndev);
3173 mdp->num_tx_ring = TX_RING_SIZE;
3174 mdp->num_rx_ring = RX_RING_SIZE;
3175 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3176 if (IS_ERR(mdp->addr)) {
3177 ret = PTR_ERR(mdp->addr);
3178 goto out_release;
3179 }
3180
3181 ndev->base_addr = res->start;
3182
3183 spin_lock_init(&mdp->lock);
3184 mdp->pdev = pdev;
3185
3186 if (pdev->dev.of_node)
3187 pd = sh_eth_parse_dt(&pdev->dev);
3188 if (!pd) {
3189 dev_err(&pdev->dev, "no platform data\n");
3190 ret = -EINVAL;
3191 goto out_release;
3192 }
3193
3194 /* get PHY ID */
3195 mdp->phy_id = pd->phy;
3196 mdp->phy_interface = pd->phy_interface;
3197 mdp->no_ether_link = pd->no_ether_link;
3198 mdp->ether_link_active_low = pd->ether_link_active_low;
3199
3200 /* set cpu data */
3201 if (id)
3202 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3203 else
3204 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3205
3206 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3207 if (!mdp->reg_offset) {
3208 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3209 mdp->cd->register_type);
3210 ret = -EINVAL;
3211 goto out_release;
3212 }
3213 sh_eth_set_default_cpu_data(mdp->cd);
3214
3215 /* User's manual states max MTU should be 2048 but due to the
3216 * alignment calculations in sh_eth_ring_init() the practical
3217 * MTU is a bit less. Maybe this can be optimized some more.
3218 */
3219 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3220 ndev->min_mtu = ETH_MIN_MTU;
3221
3222 /* set function */
3223 if (mdp->cd->tsu)
3224 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3225 else
3226 ndev->netdev_ops = &sh_eth_netdev_ops;
3227 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3228 ndev->watchdog_timeo = TX_TIMEOUT;
3229
3230 /* debug message level */
3231 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3232
3233 /* read and set MAC address */
3234 read_mac_address(ndev, pd->mac_addr);
3235 if (!is_valid_ether_addr(ndev->dev_addr)) {
3236 dev_warn(&pdev->dev,
3237 "no valid MAC address supplied, using a random one.\n");
3238 eth_hw_addr_random(ndev);
3239 }
3240
3241 if (mdp->cd->tsu) {
3242 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3243 struct resource *rtsu;
3244
3245 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3246 if (!rtsu) {
3247 dev_err(&pdev->dev, "no TSU resource\n");
3248 ret = -ENODEV;
3249 goto out_release;
3250 }
3251 /* We can only request the TSU region for the first port
3252 * of the two sharing this TSU for the probe to succeed...
3253 */
3254 if (port == 0 &&
3255 !devm_request_mem_region(&pdev->dev, rtsu->start,
3256 resource_size(rtsu),
3257 dev_name(&pdev->dev))) {
3258 dev_err(&pdev->dev, "can't request TSU resource.\n");
3259 ret = -EBUSY;
3260 goto out_release;
3261 }
3262 /* ioremap the TSU registers */
3263 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3264 resource_size(rtsu));
3265 if (!mdp->tsu_addr) {
3266 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3267 ret = -ENOMEM;
3268 goto out_release;
3269 }
3270 mdp->port = port;
3271 ndev->features = NETIF_F_HW_VLAN_CTAG_FILTER;
3272
3273 /* Need to init only the first port of the two sharing a TSU */
3274 if (port == 0) {
3275 if (mdp->cd->chip_reset)
3276 mdp->cd->chip_reset(ndev);
3277
3278 /* TSU init (Init only)*/
3279 sh_eth_tsu_init(mdp);
3280 }
3281 }
3282
3283 if (mdp->cd->rmiimode)
3284 sh_eth_write(ndev, 0x1, RMIIMODE);
3285
3286 /* MDIO bus init */
3287 ret = sh_mdio_init(mdp, pd);
3288 if (ret) {
3289 if (ret != -EPROBE_DEFER)
3290 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3291 goto out_release;
3292 }
3293
3294 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3295
3296 /* network device register */
3297 ret = register_netdev(ndev);
3298 if (ret)
3299 goto out_napi_del;
3300
3301 if (mdp->cd->magic)
3302 device_set_wakeup_capable(&pdev->dev, 1);
3303
3304 /* print device information */
3305 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3306 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3307
3308 pm_runtime_put(&pdev->dev);
3309 platform_set_drvdata(pdev, ndev);
3310
3311 return ret;
3312
3313out_napi_del:
3314 netif_napi_del(&mdp->napi);
3315 sh_mdio_release(mdp);
3316
3317out_release:
3318 /* net_dev free */
3319 free_netdev(ndev);
3320
3321 pm_runtime_put(&pdev->dev);
3322 pm_runtime_disable(&pdev->dev);
3323 return ret;
3324}
3325
3326static int sh_eth_drv_remove(struct platform_device *pdev)
3327{
3328 struct net_device *ndev = platform_get_drvdata(pdev);
3329 struct sh_eth_private *mdp = netdev_priv(ndev);
3330
3331 unregister_netdev(ndev);
3332 netif_napi_del(&mdp->napi);
3333 sh_mdio_release(mdp);
3334 pm_runtime_disable(&pdev->dev);
3335 free_netdev(ndev);
3336
3337 return 0;
3338}
3339
3340#ifdef CONFIG_PM
3341#ifdef CONFIG_PM_SLEEP
3342static int sh_eth_wol_setup(struct net_device *ndev)
3343{
3344 struct sh_eth_private *mdp = netdev_priv(ndev);
3345
3346 /* Only allow ECI interrupts */
3347 synchronize_irq(ndev->irq);
3348 napi_disable(&mdp->napi);
3349 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3350
3351 /* Enable MagicPacket */
3352 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3353
3354 return enable_irq_wake(ndev->irq);
3355}
3356
3357static int sh_eth_wol_restore(struct net_device *ndev)
3358{
3359 struct sh_eth_private *mdp = netdev_priv(ndev);
3360 int ret;
3361
3362 napi_enable(&mdp->napi);
3363
3364 /* Disable MagicPacket */
3365 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3366
3367 /* The device needs to be reset to restore MagicPacket logic
3368 * for next wakeup. If we close and open the device it will
3369 * both be reset and all registers restored. This is what
3370 * happens during suspend and resume without WoL enabled.
3371 */
3372 ret = sh_eth_close(ndev);
3373 if (ret < 0)
3374 return ret;
3375 ret = sh_eth_open(ndev);
3376 if (ret < 0)
3377 return ret;
3378
3379 return disable_irq_wake(ndev->irq);
3380}
3381
3382static int sh_eth_suspend(struct device *dev)
3383{
3384 struct net_device *ndev = dev_get_drvdata(dev);
3385 struct sh_eth_private *mdp = netdev_priv(ndev);
3386 int ret = 0;
3387
3388 if (!netif_running(ndev))
3389 return 0;
3390
3391 netif_device_detach(ndev);
3392
3393 if (mdp->wol_enabled)
3394 ret = sh_eth_wol_setup(ndev);
3395 else
3396 ret = sh_eth_close(ndev);
3397
3398 return ret;
3399}
3400
3401static int sh_eth_resume(struct device *dev)
3402{
3403 struct net_device *ndev = dev_get_drvdata(dev);
3404 struct sh_eth_private *mdp = netdev_priv(ndev);
3405 int ret = 0;
3406
3407 if (!netif_running(ndev))
3408 return 0;
3409
3410 if (mdp->wol_enabled)
3411 ret = sh_eth_wol_restore(ndev);
3412 else
3413 ret = sh_eth_open(ndev);
3414
3415 if (ret < 0)
3416 return ret;
3417
3418 netif_device_attach(ndev);
3419
3420 return ret;
3421}
3422#endif
3423
3424static int sh_eth_runtime_nop(struct device *dev)
3425{
3426 /* Runtime PM callback shared between ->runtime_suspend()
3427 * and ->runtime_resume(). Simply returns success.
3428 *
3429 * This driver re-initializes all registers after
3430 * pm_runtime_get_sync() anyway so there is no need
3431 * to save and restore registers here.
3432 */
3433 return 0;
3434}
3435
3436static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3437 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3438 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3439};
3440#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3441#else
3442#define SH_ETH_PM_OPS NULL
3443#endif
3444
3445static const struct platform_device_id sh_eth_id_table[] = {
3446 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3447 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3448 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3449 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3450 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3451 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3452 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3453 { }
3454};
3455MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3456
3457static struct platform_driver sh_eth_driver = {
3458 .probe = sh_eth_drv_probe,
3459 .remove = sh_eth_drv_remove,
3460 .id_table = sh_eth_id_table,
3461 .driver = {
3462 .name = CARDNAME,
3463 .pm = SH_ETH_PM_OPS,
3464 .of_match_table = of_match_ptr(sh_eth_match_table),
3465 },
3466};
3467
3468module_platform_driver(sh_eth_driver);
3469
3470MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3471MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3472MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0
2/* SuperH Ethernet device driver
3 *
4 * Copyright (C) 2014 Renesas Electronics Corporation
5 * Copyright (C) 2006-2012 Nobuhiro Iwamatsu
6 * Copyright (C) 2008-2014 Renesas Solutions Corp.
7 * Copyright (C) 2013-2017 Cogent Embedded, Inc.
8 * Copyright (C) 2014 Codethink Limited
9 */
10
11#include <linux/module.h>
12#include <linux/kernel.h>
13#include <linux/spinlock.h>
14#include <linux/interrupt.h>
15#include <linux/dma-mapping.h>
16#include <linux/etherdevice.h>
17#include <linux/delay.h>
18#include <linux/platform_device.h>
19#include <linux/mdio-bitbang.h>
20#include <linux/netdevice.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/of_irq.h>
24#include <linux/of_net.h>
25#include <linux/phy.h>
26#include <linux/cache.h>
27#include <linux/io.h>
28#include <linux/pm_runtime.h>
29#include <linux/slab.h>
30#include <linux/ethtool.h>
31#include <linux/if_vlan.h>
32#include <linux/sh_eth.h>
33#include <linux/of_mdio.h>
34
35#include "sh_eth.h"
36
37#define SH_ETH_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR| \
41 NETIF_MSG_TX_ERR)
42
43#define SH_ETH_OFFSET_INVALID ((u16)~0)
44
45#define SH_ETH_OFFSET_DEFAULTS \
46 [0 ... SH_ETH_MAX_REGISTER_OFFSET - 1] = SH_ETH_OFFSET_INVALID
47
48static const u16 sh_eth_offset_gigabit[SH_ETH_MAX_REGISTER_OFFSET] = {
49 SH_ETH_OFFSET_DEFAULTS,
50
51 [EDSR] = 0x0000,
52 [EDMR] = 0x0400,
53 [EDTRR] = 0x0408,
54 [EDRRR] = 0x0410,
55 [EESR] = 0x0428,
56 [EESIPR] = 0x0430,
57 [TDLAR] = 0x0010,
58 [TDFAR] = 0x0014,
59 [TDFXR] = 0x0018,
60 [TDFFR] = 0x001c,
61 [RDLAR] = 0x0030,
62 [RDFAR] = 0x0034,
63 [RDFXR] = 0x0038,
64 [RDFFR] = 0x003c,
65 [TRSCER] = 0x0438,
66 [RMFCR] = 0x0440,
67 [TFTR] = 0x0448,
68 [FDR] = 0x0450,
69 [RMCR] = 0x0458,
70 [RPADIR] = 0x0460,
71 [FCFTR] = 0x0468,
72 [CSMR] = 0x04E4,
73
74 [ECMR] = 0x0500,
75 [ECSR] = 0x0510,
76 [ECSIPR] = 0x0518,
77 [PIR] = 0x0520,
78 [PSR] = 0x0528,
79 [PIPR] = 0x052c,
80 [RFLR] = 0x0508,
81 [APR] = 0x0554,
82 [MPR] = 0x0558,
83 [PFTCR] = 0x055c,
84 [PFRCR] = 0x0560,
85 [TPAUSER] = 0x0564,
86 [GECMR] = 0x05b0,
87 [BCULR] = 0x05b4,
88 [MAHR] = 0x05c0,
89 [MALR] = 0x05c8,
90 [TROCR] = 0x0700,
91 [CDCR] = 0x0708,
92 [LCCR] = 0x0710,
93 [CEFCR] = 0x0740,
94 [FRECR] = 0x0748,
95 [TSFRCR] = 0x0750,
96 [TLFRCR] = 0x0758,
97 [RFCR] = 0x0760,
98 [CERCR] = 0x0768,
99 [CEECR] = 0x0770,
100 [MAFCR] = 0x0778,
101 [RMII_MII] = 0x0790,
102
103 [ARSTR] = 0x0000,
104 [TSU_CTRST] = 0x0004,
105 [TSU_FWEN0] = 0x0010,
106 [TSU_FWEN1] = 0x0014,
107 [TSU_FCM] = 0x0018,
108 [TSU_BSYSL0] = 0x0020,
109 [TSU_BSYSL1] = 0x0024,
110 [TSU_PRISL0] = 0x0028,
111 [TSU_PRISL1] = 0x002c,
112 [TSU_FWSL0] = 0x0030,
113 [TSU_FWSL1] = 0x0034,
114 [TSU_FWSLC] = 0x0038,
115 [TSU_QTAGM0] = 0x0040,
116 [TSU_QTAGM1] = 0x0044,
117 [TSU_FWSR] = 0x0050,
118 [TSU_FWINMK] = 0x0054,
119 [TSU_ADQT0] = 0x0048,
120 [TSU_ADQT1] = 0x004c,
121 [TSU_VTAG0] = 0x0058,
122 [TSU_VTAG1] = 0x005c,
123 [TSU_ADSBSY] = 0x0060,
124 [TSU_TEN] = 0x0064,
125 [TSU_POST1] = 0x0070,
126 [TSU_POST2] = 0x0074,
127 [TSU_POST3] = 0x0078,
128 [TSU_POST4] = 0x007c,
129 [TSU_ADRH0] = 0x0100,
130
131 [TXNLCR0] = 0x0080,
132 [TXALCR0] = 0x0084,
133 [RXNLCR0] = 0x0088,
134 [RXALCR0] = 0x008c,
135 [FWNLCR0] = 0x0090,
136 [FWALCR0] = 0x0094,
137 [TXNLCR1] = 0x00a0,
138 [TXALCR1] = 0x00a4,
139 [RXNLCR1] = 0x00a8,
140 [RXALCR1] = 0x00ac,
141 [FWNLCR1] = 0x00b0,
142 [FWALCR1] = 0x00b4,
143};
144
145static const u16 sh_eth_offset_fast_rz[SH_ETH_MAX_REGISTER_OFFSET] = {
146 SH_ETH_OFFSET_DEFAULTS,
147
148 [EDSR] = 0x0000,
149 [EDMR] = 0x0400,
150 [EDTRR] = 0x0408,
151 [EDRRR] = 0x0410,
152 [EESR] = 0x0428,
153 [EESIPR] = 0x0430,
154 [TDLAR] = 0x0010,
155 [TDFAR] = 0x0014,
156 [TDFXR] = 0x0018,
157 [TDFFR] = 0x001c,
158 [RDLAR] = 0x0030,
159 [RDFAR] = 0x0034,
160 [RDFXR] = 0x0038,
161 [RDFFR] = 0x003c,
162 [TRSCER] = 0x0438,
163 [RMFCR] = 0x0440,
164 [TFTR] = 0x0448,
165 [FDR] = 0x0450,
166 [RMCR] = 0x0458,
167 [RPADIR] = 0x0460,
168 [FCFTR] = 0x0468,
169 [CSMR] = 0x04E4,
170
171 [ECMR] = 0x0500,
172 [RFLR] = 0x0508,
173 [ECSR] = 0x0510,
174 [ECSIPR] = 0x0518,
175 [PIR] = 0x0520,
176 [APR] = 0x0554,
177 [MPR] = 0x0558,
178 [PFTCR] = 0x055c,
179 [PFRCR] = 0x0560,
180 [TPAUSER] = 0x0564,
181 [MAHR] = 0x05c0,
182 [MALR] = 0x05c8,
183 [CEFCR] = 0x0740,
184 [FRECR] = 0x0748,
185 [TSFRCR] = 0x0750,
186 [TLFRCR] = 0x0758,
187 [RFCR] = 0x0760,
188 [MAFCR] = 0x0778,
189
190 [ARSTR] = 0x0000,
191 [TSU_CTRST] = 0x0004,
192 [TSU_FWSLC] = 0x0038,
193 [TSU_VTAG0] = 0x0058,
194 [TSU_ADSBSY] = 0x0060,
195 [TSU_TEN] = 0x0064,
196 [TSU_POST1] = 0x0070,
197 [TSU_POST2] = 0x0074,
198 [TSU_POST3] = 0x0078,
199 [TSU_POST4] = 0x007c,
200 [TSU_ADRH0] = 0x0100,
201
202 [TXNLCR0] = 0x0080,
203 [TXALCR0] = 0x0084,
204 [RXNLCR0] = 0x0088,
205 [RXALCR0] = 0x008C,
206};
207
208static const u16 sh_eth_offset_fast_rcar[SH_ETH_MAX_REGISTER_OFFSET] = {
209 SH_ETH_OFFSET_DEFAULTS,
210
211 [ECMR] = 0x0300,
212 [RFLR] = 0x0308,
213 [ECSR] = 0x0310,
214 [ECSIPR] = 0x0318,
215 [PIR] = 0x0320,
216 [PSR] = 0x0328,
217 [RDMLR] = 0x0340,
218 [IPGR] = 0x0350,
219 [APR] = 0x0354,
220 [MPR] = 0x0358,
221 [RFCF] = 0x0360,
222 [TPAUSER] = 0x0364,
223 [TPAUSECR] = 0x0368,
224 [MAHR] = 0x03c0,
225 [MALR] = 0x03c8,
226 [TROCR] = 0x03d0,
227 [CDCR] = 0x03d4,
228 [LCCR] = 0x03d8,
229 [CNDCR] = 0x03dc,
230 [CEFCR] = 0x03e4,
231 [FRECR] = 0x03e8,
232 [TSFRCR] = 0x03ec,
233 [TLFRCR] = 0x03f0,
234 [RFCR] = 0x03f4,
235 [MAFCR] = 0x03f8,
236
237 [EDMR] = 0x0200,
238 [EDTRR] = 0x0208,
239 [EDRRR] = 0x0210,
240 [TDLAR] = 0x0218,
241 [RDLAR] = 0x0220,
242 [EESR] = 0x0228,
243 [EESIPR] = 0x0230,
244 [TRSCER] = 0x0238,
245 [RMFCR] = 0x0240,
246 [TFTR] = 0x0248,
247 [FDR] = 0x0250,
248 [RMCR] = 0x0258,
249 [TFUCR] = 0x0264,
250 [RFOCR] = 0x0268,
251 [RMIIMODE] = 0x026c,
252 [FCFTR] = 0x0270,
253 [TRIMD] = 0x027c,
254};
255
256static const u16 sh_eth_offset_fast_sh4[SH_ETH_MAX_REGISTER_OFFSET] = {
257 SH_ETH_OFFSET_DEFAULTS,
258
259 [ECMR] = 0x0100,
260 [RFLR] = 0x0108,
261 [ECSR] = 0x0110,
262 [ECSIPR] = 0x0118,
263 [PIR] = 0x0120,
264 [PSR] = 0x0128,
265 [RDMLR] = 0x0140,
266 [IPGR] = 0x0150,
267 [APR] = 0x0154,
268 [MPR] = 0x0158,
269 [TPAUSER] = 0x0164,
270 [RFCF] = 0x0160,
271 [TPAUSECR] = 0x0168,
272 [BCFRR] = 0x016c,
273 [MAHR] = 0x01c0,
274 [MALR] = 0x01c8,
275 [TROCR] = 0x01d0,
276 [CDCR] = 0x01d4,
277 [LCCR] = 0x01d8,
278 [CNDCR] = 0x01dc,
279 [CEFCR] = 0x01e4,
280 [FRECR] = 0x01e8,
281 [TSFRCR] = 0x01ec,
282 [TLFRCR] = 0x01f0,
283 [RFCR] = 0x01f4,
284 [MAFCR] = 0x01f8,
285 [RTRATE] = 0x01fc,
286
287 [EDMR] = 0x0000,
288 [EDTRR] = 0x0008,
289 [EDRRR] = 0x0010,
290 [TDLAR] = 0x0018,
291 [RDLAR] = 0x0020,
292 [EESR] = 0x0028,
293 [EESIPR] = 0x0030,
294 [TRSCER] = 0x0038,
295 [RMFCR] = 0x0040,
296 [TFTR] = 0x0048,
297 [FDR] = 0x0050,
298 [RMCR] = 0x0058,
299 [TFUCR] = 0x0064,
300 [RFOCR] = 0x0068,
301 [FCFTR] = 0x0070,
302 [RPADIR] = 0x0078,
303 [TRIMD] = 0x007c,
304 [RBWAR] = 0x00c8,
305 [RDFAR] = 0x00cc,
306 [TBRAR] = 0x00d4,
307 [TDFAR] = 0x00d8,
308};
309
310static const u16 sh_eth_offset_fast_sh3_sh2[SH_ETH_MAX_REGISTER_OFFSET] = {
311 SH_ETH_OFFSET_DEFAULTS,
312
313 [EDMR] = 0x0000,
314 [EDTRR] = 0x0004,
315 [EDRRR] = 0x0008,
316 [TDLAR] = 0x000c,
317 [RDLAR] = 0x0010,
318 [EESR] = 0x0014,
319 [EESIPR] = 0x0018,
320 [TRSCER] = 0x001c,
321 [RMFCR] = 0x0020,
322 [TFTR] = 0x0024,
323 [FDR] = 0x0028,
324 [RMCR] = 0x002c,
325 [EDOCR] = 0x0030,
326 [FCFTR] = 0x0034,
327 [RPADIR] = 0x0038,
328 [TRIMD] = 0x003c,
329 [RBWAR] = 0x0040,
330 [RDFAR] = 0x0044,
331 [TBRAR] = 0x004c,
332 [TDFAR] = 0x0050,
333
334 [ECMR] = 0x0160,
335 [ECSR] = 0x0164,
336 [ECSIPR] = 0x0168,
337 [PIR] = 0x016c,
338 [MAHR] = 0x0170,
339 [MALR] = 0x0174,
340 [RFLR] = 0x0178,
341 [PSR] = 0x017c,
342 [TROCR] = 0x0180,
343 [CDCR] = 0x0184,
344 [LCCR] = 0x0188,
345 [CNDCR] = 0x018c,
346 [CEFCR] = 0x0194,
347 [FRECR] = 0x0198,
348 [TSFRCR] = 0x019c,
349 [TLFRCR] = 0x01a0,
350 [RFCR] = 0x01a4,
351 [MAFCR] = 0x01a8,
352 [IPGR] = 0x01b4,
353 [APR] = 0x01b8,
354 [MPR] = 0x01bc,
355 [TPAUSER] = 0x01c4,
356 [BCFR] = 0x01cc,
357
358 [ARSTR] = 0x0000,
359 [TSU_CTRST] = 0x0004,
360 [TSU_FWEN0] = 0x0010,
361 [TSU_FWEN1] = 0x0014,
362 [TSU_FCM] = 0x0018,
363 [TSU_BSYSL0] = 0x0020,
364 [TSU_BSYSL1] = 0x0024,
365 [TSU_PRISL0] = 0x0028,
366 [TSU_PRISL1] = 0x002c,
367 [TSU_FWSL0] = 0x0030,
368 [TSU_FWSL1] = 0x0034,
369 [TSU_FWSLC] = 0x0038,
370 [TSU_QTAGM0] = 0x0040,
371 [TSU_QTAGM1] = 0x0044,
372 [TSU_ADQT0] = 0x0048,
373 [TSU_ADQT1] = 0x004c,
374 [TSU_FWSR] = 0x0050,
375 [TSU_FWINMK] = 0x0054,
376 [TSU_ADSBSY] = 0x0060,
377 [TSU_TEN] = 0x0064,
378 [TSU_POST1] = 0x0070,
379 [TSU_POST2] = 0x0074,
380 [TSU_POST3] = 0x0078,
381 [TSU_POST4] = 0x007c,
382
383 [TXNLCR0] = 0x0080,
384 [TXALCR0] = 0x0084,
385 [RXNLCR0] = 0x0088,
386 [RXALCR0] = 0x008c,
387 [FWNLCR0] = 0x0090,
388 [FWALCR0] = 0x0094,
389 [TXNLCR1] = 0x00a0,
390 [TXALCR1] = 0x00a4,
391 [RXNLCR1] = 0x00a8,
392 [RXALCR1] = 0x00ac,
393 [FWNLCR1] = 0x00b0,
394 [FWALCR1] = 0x00b4,
395
396 [TSU_ADRH0] = 0x0100,
397};
398
399static void sh_eth_rcv_snd_disable(struct net_device *ndev);
400static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev);
401
402static void sh_eth_write(struct net_device *ndev, u32 data, int enum_index)
403{
404 struct sh_eth_private *mdp = netdev_priv(ndev);
405 u16 offset = mdp->reg_offset[enum_index];
406
407 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
408 return;
409
410 iowrite32(data, mdp->addr + offset);
411}
412
413static u32 sh_eth_read(struct net_device *ndev, int enum_index)
414{
415 struct sh_eth_private *mdp = netdev_priv(ndev);
416 u16 offset = mdp->reg_offset[enum_index];
417
418 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
419 return ~0U;
420
421 return ioread32(mdp->addr + offset);
422}
423
424static void sh_eth_modify(struct net_device *ndev, int enum_index, u32 clear,
425 u32 set)
426{
427 sh_eth_write(ndev, (sh_eth_read(ndev, enum_index) & ~clear) | set,
428 enum_index);
429}
430
431static u16 sh_eth_tsu_get_offset(struct sh_eth_private *mdp, int enum_index)
432{
433 return mdp->reg_offset[enum_index];
434}
435
436static void sh_eth_tsu_write(struct sh_eth_private *mdp, u32 data,
437 int enum_index)
438{
439 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
440
441 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
442 return;
443
444 iowrite32(data, mdp->tsu_addr + offset);
445}
446
447static u32 sh_eth_tsu_read(struct sh_eth_private *mdp, int enum_index)
448{
449 u16 offset = sh_eth_tsu_get_offset(mdp, enum_index);
450
451 if (WARN_ON(offset == SH_ETH_OFFSET_INVALID))
452 return ~0U;
453
454 return ioread32(mdp->tsu_addr + offset);
455}
456
457static void sh_eth_soft_swap(char *src, int len)
458{
459#ifdef __LITTLE_ENDIAN
460 u32 *p = (u32 *)src;
461 u32 *maxp = p + DIV_ROUND_UP(len, sizeof(u32));
462
463 for (; p < maxp; p++)
464 *p = swab32(*p);
465#endif
466}
467
468static void sh_eth_select_mii(struct net_device *ndev)
469{
470 struct sh_eth_private *mdp = netdev_priv(ndev);
471 u32 value;
472
473 switch (mdp->phy_interface) {
474 case PHY_INTERFACE_MODE_RGMII ... PHY_INTERFACE_MODE_RGMII_TXID:
475 value = 0x3;
476 break;
477 case PHY_INTERFACE_MODE_GMII:
478 value = 0x2;
479 break;
480 case PHY_INTERFACE_MODE_MII:
481 value = 0x1;
482 break;
483 case PHY_INTERFACE_MODE_RMII:
484 value = 0x0;
485 break;
486 default:
487 netdev_warn(ndev,
488 "PHY interface mode was not setup. Set to MII.\n");
489 value = 0x1;
490 break;
491 }
492
493 sh_eth_write(ndev, value, RMII_MII);
494}
495
496static void sh_eth_set_duplex(struct net_device *ndev)
497{
498 struct sh_eth_private *mdp = netdev_priv(ndev);
499
500 sh_eth_modify(ndev, ECMR, ECMR_DM, mdp->duplex ? ECMR_DM : 0);
501}
502
503static void sh_eth_chip_reset(struct net_device *ndev)
504{
505 struct sh_eth_private *mdp = netdev_priv(ndev);
506
507 /* reset device */
508 sh_eth_tsu_write(mdp, ARSTR_ARST, ARSTR);
509 mdelay(1);
510}
511
512static int sh_eth_soft_reset(struct net_device *ndev)
513{
514 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, EDMR_SRST_ETHER);
515 mdelay(3);
516 sh_eth_modify(ndev, EDMR, EDMR_SRST_ETHER, 0);
517
518 return 0;
519}
520
521static int sh_eth_check_soft_reset(struct net_device *ndev)
522{
523 int cnt;
524
525 for (cnt = 100; cnt > 0; cnt--) {
526 if (!(sh_eth_read(ndev, EDMR) & EDMR_SRST_GETHER))
527 return 0;
528 mdelay(1);
529 }
530
531 netdev_err(ndev, "Device reset failed\n");
532 return -ETIMEDOUT;
533}
534
535static int sh_eth_soft_reset_gether(struct net_device *ndev)
536{
537 struct sh_eth_private *mdp = netdev_priv(ndev);
538 int ret;
539
540 sh_eth_write(ndev, EDSR_ENALL, EDSR);
541 sh_eth_modify(ndev, EDMR, EDMR_SRST_GETHER, EDMR_SRST_GETHER);
542
543 ret = sh_eth_check_soft_reset(ndev);
544 if (ret)
545 return ret;
546
547 /* Table Init */
548 sh_eth_write(ndev, 0, TDLAR);
549 sh_eth_write(ndev, 0, TDFAR);
550 sh_eth_write(ndev, 0, TDFXR);
551 sh_eth_write(ndev, 0, TDFFR);
552 sh_eth_write(ndev, 0, RDLAR);
553 sh_eth_write(ndev, 0, RDFAR);
554 sh_eth_write(ndev, 0, RDFXR);
555 sh_eth_write(ndev, 0, RDFFR);
556
557 /* Reset HW CRC register */
558 if (mdp->cd->csmr)
559 sh_eth_write(ndev, 0, CSMR);
560
561 /* Select MII mode */
562 if (mdp->cd->select_mii)
563 sh_eth_select_mii(ndev);
564
565 return ret;
566}
567
568static void sh_eth_set_rate_gether(struct net_device *ndev)
569{
570 struct sh_eth_private *mdp = netdev_priv(ndev);
571
572 switch (mdp->speed) {
573 case 10: /* 10BASE */
574 sh_eth_write(ndev, GECMR_10, GECMR);
575 break;
576 case 100:/* 100BASE */
577 sh_eth_write(ndev, GECMR_100, GECMR);
578 break;
579 case 1000: /* 1000BASE */
580 sh_eth_write(ndev, GECMR_1000, GECMR);
581 break;
582 }
583}
584
585#ifdef CONFIG_OF
586/* R7S72100 */
587static struct sh_eth_cpu_data r7s72100_data = {
588 .soft_reset = sh_eth_soft_reset_gether,
589
590 .chip_reset = sh_eth_chip_reset,
591 .set_duplex = sh_eth_set_duplex,
592
593 .register_type = SH_ETH_REG_FAST_RZ,
594
595 .edtrr_trns = EDTRR_TRNS_GETHER,
596 .ecsr_value = ECSR_ICD,
597 .ecsipr_value = ECSIPR_ICDIP,
598 .eesipr_value = EESIPR_TWB1IP | EESIPR_TWBIP | EESIPR_TC1IP |
599 EESIPR_TABTIP | EESIPR_RABTIP | EESIPR_RFCOFIP |
600 EESIPR_ECIIP |
601 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
602 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
603 EESIPR_RMAFIP | EESIPR_RRFIP |
604 EESIPR_RTLFIP | EESIPR_RTSFIP |
605 EESIPR_PREIP | EESIPR_CERFIP,
606
607 .tx_check = EESR_TC1 | EESR_FTC,
608 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
609 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
610 EESR_TDE,
611 .fdr_value = 0x0000070f,
612
613 .no_psr = 1,
614 .apr = 1,
615 .mpr = 1,
616 .tpauser = 1,
617 .hw_swap = 1,
618 .rpadir = 1,
619 .no_trimd = 1,
620 .no_ade = 1,
621 .xdfar_rw = 1,
622 .csmr = 1,
623 .rx_csum = 1,
624 .tsu = 1,
625 .no_tx_cntrs = 1,
626};
627
628static void sh_eth_chip_reset_r8a7740(struct net_device *ndev)
629{
630 sh_eth_chip_reset(ndev);
631
632 sh_eth_select_mii(ndev);
633}
634
635/* R8A7740 */
636static struct sh_eth_cpu_data r8a7740_data = {
637 .soft_reset = sh_eth_soft_reset_gether,
638
639 .chip_reset = sh_eth_chip_reset_r8a7740,
640 .set_duplex = sh_eth_set_duplex,
641 .set_rate = sh_eth_set_rate_gether,
642
643 .register_type = SH_ETH_REG_GIGABIT,
644
645 .edtrr_trns = EDTRR_TRNS_GETHER,
646 .ecsr_value = ECSR_ICD | ECSR_MPD,
647 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
648 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
649 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
650 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
651 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
652 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
653 EESIPR_CEEFIP | EESIPR_CELFIP |
654 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
655 EESIPR_PREIP | EESIPR_CERFIP,
656
657 .tx_check = EESR_TC1 | EESR_FTC,
658 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
659 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
660 EESR_TDE,
661 .fdr_value = 0x0000070f,
662
663 .apr = 1,
664 .mpr = 1,
665 .tpauser = 1,
666 .bculr = 1,
667 .hw_swap = 1,
668 .rpadir = 1,
669 .no_trimd = 1,
670 .no_ade = 1,
671 .xdfar_rw = 1,
672 .csmr = 1,
673 .rx_csum = 1,
674 .tsu = 1,
675 .select_mii = 1,
676 .magic = 1,
677 .cexcr = 1,
678};
679
680/* There is CPU dependent code */
681static void sh_eth_set_rate_rcar(struct net_device *ndev)
682{
683 struct sh_eth_private *mdp = netdev_priv(ndev);
684
685 switch (mdp->speed) {
686 case 10: /* 10BASE */
687 sh_eth_modify(ndev, ECMR, ECMR_ELB, 0);
688 break;
689 case 100:/* 100BASE */
690 sh_eth_modify(ndev, ECMR, ECMR_ELB, ECMR_ELB);
691 break;
692 }
693}
694
695/* R-Car Gen1 */
696static struct sh_eth_cpu_data rcar_gen1_data = {
697 .soft_reset = sh_eth_soft_reset,
698
699 .set_duplex = sh_eth_set_duplex,
700 .set_rate = sh_eth_set_rate_rcar,
701
702 .register_type = SH_ETH_REG_FAST_RCAR,
703
704 .edtrr_trns = EDTRR_TRNS_ETHER,
705 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
706 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
707 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
708 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
709 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
710 EESIPR_RMAFIP | EESIPR_RRFIP |
711 EESIPR_RTLFIP | EESIPR_RTSFIP |
712 EESIPR_PREIP | EESIPR_CERFIP,
713
714 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
715 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
716 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
717 .fdr_value = 0x00000f0f,
718
719 .apr = 1,
720 .mpr = 1,
721 .tpauser = 1,
722 .hw_swap = 1,
723 .no_xdfar = 1,
724};
725
726/* R-Car Gen2 and RZ/G1 */
727static struct sh_eth_cpu_data rcar_gen2_data = {
728 .soft_reset = sh_eth_soft_reset,
729
730 .set_duplex = sh_eth_set_duplex,
731 .set_rate = sh_eth_set_rate_rcar,
732
733 .register_type = SH_ETH_REG_FAST_RCAR,
734
735 .edtrr_trns = EDTRR_TRNS_ETHER,
736 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
737 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
738 ECSIPR_MPDIP,
739 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
740 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
741 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
742 EESIPR_RMAFIP | EESIPR_RRFIP |
743 EESIPR_RTLFIP | EESIPR_RTSFIP |
744 EESIPR_PREIP | EESIPR_CERFIP,
745
746 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
747 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
748 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
749 .fdr_value = 0x00000f0f,
750
751 .trscer_err_mask = DESC_I_RINT8,
752
753 .apr = 1,
754 .mpr = 1,
755 .tpauser = 1,
756 .hw_swap = 1,
757 .no_xdfar = 1,
758 .rmiimode = 1,
759 .magic = 1,
760};
761
762/* R8A77980 */
763static struct sh_eth_cpu_data r8a77980_data = {
764 .soft_reset = sh_eth_soft_reset_gether,
765
766 .set_duplex = sh_eth_set_duplex,
767 .set_rate = sh_eth_set_rate_gether,
768
769 .register_type = SH_ETH_REG_GIGABIT,
770
771 .edtrr_trns = EDTRR_TRNS_GETHER,
772 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD | ECSR_MPD,
773 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP |
774 ECSIPR_MPDIP,
775 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
776 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
777 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
778 EESIPR_RMAFIP | EESIPR_RRFIP |
779 EESIPR_RTLFIP | EESIPR_RTSFIP |
780 EESIPR_PREIP | EESIPR_CERFIP,
781
782 .tx_check = EESR_FTC | EESR_CD | EESR_TRO,
783 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
784 EESR_RFE | EESR_RDE | EESR_RFRMER |
785 EESR_TFE | EESR_TDE | EESR_ECI,
786 .fdr_value = 0x0000070f,
787
788 .apr = 1,
789 .mpr = 1,
790 .tpauser = 1,
791 .bculr = 1,
792 .hw_swap = 1,
793 .nbst = 1,
794 .rpadir = 1,
795 .no_trimd = 1,
796 .no_ade = 1,
797 .xdfar_rw = 1,
798 .csmr = 1,
799 .rx_csum = 1,
800 .select_mii = 1,
801 .magic = 1,
802 .cexcr = 1,
803};
804
805/* R7S9210 */
806static struct sh_eth_cpu_data r7s9210_data = {
807 .soft_reset = sh_eth_soft_reset,
808
809 .set_duplex = sh_eth_set_duplex,
810 .set_rate = sh_eth_set_rate_rcar,
811
812 .register_type = SH_ETH_REG_FAST_SH4,
813
814 .edtrr_trns = EDTRR_TRNS_ETHER,
815 .ecsr_value = ECSR_ICD,
816 .ecsipr_value = ECSIPR_ICDIP,
817 .eesipr_value = EESIPR_TWBIP | EESIPR_TABTIP | EESIPR_RABTIP |
818 EESIPR_RFCOFIP | EESIPR_ECIIP | EESIPR_FTCIP |
819 EESIPR_TDEIP | EESIPR_TFUFIP | EESIPR_FRIP |
820 EESIPR_RDEIP | EESIPR_RFOFIP | EESIPR_CNDIP |
821 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
822 EESIPR_RMAFIP | EESIPR_RRFIP | EESIPR_RTLFIP |
823 EESIPR_RTSFIP | EESIPR_PREIP | EESIPR_CERFIP,
824
825 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
826 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
827 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
828
829 .fdr_value = 0x0000070f,
830
831 .apr = 1,
832 .mpr = 1,
833 .tpauser = 1,
834 .hw_swap = 1,
835 .rpadir = 1,
836 .no_ade = 1,
837 .xdfar_rw = 1,
838};
839#endif /* CONFIG_OF */
840
841static void sh_eth_set_rate_sh7724(struct net_device *ndev)
842{
843 struct sh_eth_private *mdp = netdev_priv(ndev);
844
845 switch (mdp->speed) {
846 case 10: /* 10BASE */
847 sh_eth_modify(ndev, ECMR, ECMR_RTM, 0);
848 break;
849 case 100:/* 100BASE */
850 sh_eth_modify(ndev, ECMR, ECMR_RTM, ECMR_RTM);
851 break;
852 }
853}
854
855/* SH7724 */
856static struct sh_eth_cpu_data sh7724_data = {
857 .soft_reset = sh_eth_soft_reset,
858
859 .set_duplex = sh_eth_set_duplex,
860 .set_rate = sh_eth_set_rate_sh7724,
861
862 .register_type = SH_ETH_REG_FAST_SH4,
863
864 .edtrr_trns = EDTRR_TRNS_ETHER,
865 .ecsr_value = ECSR_PSRTO | ECSR_LCHNG | ECSR_ICD,
866 .ecsipr_value = ECSIPR_PSRTOIP | ECSIPR_LCHNGIP | ECSIPR_ICDIP,
867 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ADEIP | EESIPR_ECIIP |
868 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
869 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
870 EESIPR_RMAFIP | EESIPR_RRFIP |
871 EESIPR_RTLFIP | EESIPR_RTSFIP |
872 EESIPR_PREIP | EESIPR_CERFIP,
873
874 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
875 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
876 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
877
878 .apr = 1,
879 .mpr = 1,
880 .tpauser = 1,
881 .hw_swap = 1,
882 .rpadir = 1,
883};
884
885static void sh_eth_set_rate_sh7757(struct net_device *ndev)
886{
887 struct sh_eth_private *mdp = netdev_priv(ndev);
888
889 switch (mdp->speed) {
890 case 10: /* 10BASE */
891 sh_eth_write(ndev, 0, RTRATE);
892 break;
893 case 100:/* 100BASE */
894 sh_eth_write(ndev, 1, RTRATE);
895 break;
896 }
897}
898
899/* SH7757 */
900static struct sh_eth_cpu_data sh7757_data = {
901 .soft_reset = sh_eth_soft_reset,
902
903 .set_duplex = sh_eth_set_duplex,
904 .set_rate = sh_eth_set_rate_sh7757,
905
906 .register_type = SH_ETH_REG_FAST_SH4,
907
908 .edtrr_trns = EDTRR_TRNS_ETHER,
909 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
910 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
911 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
912 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
913 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
914 EESIPR_CEEFIP | EESIPR_CELFIP |
915 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
916 EESIPR_PREIP | EESIPR_CERFIP,
917
918 .tx_check = EESR_FTC | EESR_CND | EESR_DLC | EESR_CD | EESR_TRO,
919 .eesr_err_check = EESR_TWB | EESR_TABT | EESR_RABT | EESR_RFE |
920 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
921
922 .irq_flags = IRQF_SHARED,
923 .apr = 1,
924 .mpr = 1,
925 .tpauser = 1,
926 .hw_swap = 1,
927 .no_ade = 1,
928 .rpadir = 1,
929 .rtrate = 1,
930 .dual_port = 1,
931};
932
933#define SH_GIGA_ETH_BASE 0xfee00000UL
934#define GIGA_MALR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c8)
935#define GIGA_MAHR(port) (SH_GIGA_ETH_BASE + 0x800 * (port) + 0x05c0)
936static void sh_eth_chip_reset_giga(struct net_device *ndev)
937{
938 u32 mahr[2], malr[2];
939 int i;
940
941 /* save MAHR and MALR */
942 for (i = 0; i < 2; i++) {
943 malr[i] = ioread32((void *)GIGA_MALR(i));
944 mahr[i] = ioread32((void *)GIGA_MAHR(i));
945 }
946
947 sh_eth_chip_reset(ndev);
948
949 /* restore MAHR and MALR */
950 for (i = 0; i < 2; i++) {
951 iowrite32(malr[i], (void *)GIGA_MALR(i));
952 iowrite32(mahr[i], (void *)GIGA_MAHR(i));
953 }
954}
955
956static void sh_eth_set_rate_giga(struct net_device *ndev)
957{
958 struct sh_eth_private *mdp = netdev_priv(ndev);
959
960 switch (mdp->speed) {
961 case 10: /* 10BASE */
962 sh_eth_write(ndev, 0x00000000, GECMR);
963 break;
964 case 100:/* 100BASE */
965 sh_eth_write(ndev, 0x00000010, GECMR);
966 break;
967 case 1000: /* 1000BASE */
968 sh_eth_write(ndev, 0x00000020, GECMR);
969 break;
970 }
971}
972
973/* SH7757(GETHERC) */
974static struct sh_eth_cpu_data sh7757_data_giga = {
975 .soft_reset = sh_eth_soft_reset_gether,
976
977 .chip_reset = sh_eth_chip_reset_giga,
978 .set_duplex = sh_eth_set_duplex,
979 .set_rate = sh_eth_set_rate_giga,
980
981 .register_type = SH_ETH_REG_GIGABIT,
982
983 .edtrr_trns = EDTRR_TRNS_GETHER,
984 .ecsr_value = ECSR_ICD | ECSR_MPD,
985 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
986 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
987 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
988 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
989 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
990 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
991 EESIPR_CEEFIP | EESIPR_CELFIP |
992 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
993 EESIPR_PREIP | EESIPR_CERFIP,
994
995 .tx_check = EESR_TC1 | EESR_FTC,
996 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
997 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
998 EESR_TDE,
999 .fdr_value = 0x0000072f,
1000
1001 .irq_flags = IRQF_SHARED,
1002 .apr = 1,
1003 .mpr = 1,
1004 .tpauser = 1,
1005 .bculr = 1,
1006 .hw_swap = 1,
1007 .rpadir = 1,
1008 .no_trimd = 1,
1009 .no_ade = 1,
1010 .xdfar_rw = 1,
1011 .tsu = 1,
1012 .cexcr = 1,
1013 .dual_port = 1,
1014};
1015
1016/* SH7734 */
1017static struct sh_eth_cpu_data sh7734_data = {
1018 .soft_reset = sh_eth_soft_reset_gether,
1019
1020 .chip_reset = sh_eth_chip_reset,
1021 .set_duplex = sh_eth_set_duplex,
1022 .set_rate = sh_eth_set_rate_gether,
1023
1024 .register_type = SH_ETH_REG_GIGABIT,
1025
1026 .edtrr_trns = EDTRR_TRNS_GETHER,
1027 .ecsr_value = ECSR_ICD | ECSR_MPD,
1028 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1029 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1030 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1031 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1032 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1033 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1034 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1035 EESIPR_PREIP | EESIPR_CERFIP,
1036
1037 .tx_check = EESR_TC1 | EESR_FTC,
1038 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1039 EESR_RFE | EESR_RDE | EESR_RFRMER | EESR_TFE |
1040 EESR_TDE,
1041
1042 .apr = 1,
1043 .mpr = 1,
1044 .tpauser = 1,
1045 .bculr = 1,
1046 .hw_swap = 1,
1047 .no_trimd = 1,
1048 .no_ade = 1,
1049 .xdfar_rw = 1,
1050 .tsu = 1,
1051 .csmr = 1,
1052 .rx_csum = 1,
1053 .select_mii = 1,
1054 .magic = 1,
1055 .cexcr = 1,
1056};
1057
1058/* SH7763 */
1059static struct sh_eth_cpu_data sh7763_data = {
1060 .soft_reset = sh_eth_soft_reset_gether,
1061
1062 .chip_reset = sh_eth_chip_reset,
1063 .set_duplex = sh_eth_set_duplex,
1064 .set_rate = sh_eth_set_rate_gether,
1065
1066 .register_type = SH_ETH_REG_GIGABIT,
1067
1068 .edtrr_trns = EDTRR_TRNS_GETHER,
1069 .ecsr_value = ECSR_ICD | ECSR_MPD,
1070 .ecsipr_value = ECSIPR_LCHNGIP | ECSIPR_ICDIP | ECSIPR_MPDIP,
1071 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1072 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1073 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1074 EESIPR_DLCIP | EESIPR_CDIP | EESIPR_TROIP |
1075 EESIPR_RMAFIP | EESIPR_CEEFIP | EESIPR_CELFIP |
1076 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1077 EESIPR_PREIP | EESIPR_CERFIP,
1078
1079 .tx_check = EESR_TC1 | EESR_FTC,
1080 .eesr_err_check = EESR_TWB1 | EESR_TWB | EESR_TABT | EESR_RABT |
1081 EESR_RDE | EESR_RFRMER | EESR_TFE | EESR_TDE,
1082
1083 .apr = 1,
1084 .mpr = 1,
1085 .tpauser = 1,
1086 .bculr = 1,
1087 .hw_swap = 1,
1088 .no_trimd = 1,
1089 .no_ade = 1,
1090 .xdfar_rw = 1,
1091 .tsu = 1,
1092 .irq_flags = IRQF_SHARED,
1093 .magic = 1,
1094 .cexcr = 1,
1095 .rx_csum = 1,
1096 .dual_port = 1,
1097};
1098
1099static struct sh_eth_cpu_data sh7619_data = {
1100 .soft_reset = sh_eth_soft_reset,
1101
1102 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1103
1104 .edtrr_trns = EDTRR_TRNS_ETHER,
1105 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1106 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1107 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1108 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1109 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1110 EESIPR_CEEFIP | EESIPR_CELFIP |
1111 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1112 EESIPR_PREIP | EESIPR_CERFIP,
1113
1114 .apr = 1,
1115 .mpr = 1,
1116 .tpauser = 1,
1117 .hw_swap = 1,
1118};
1119
1120static struct sh_eth_cpu_data sh771x_data = {
1121 .soft_reset = sh_eth_soft_reset,
1122
1123 .register_type = SH_ETH_REG_FAST_SH3_SH2,
1124
1125 .edtrr_trns = EDTRR_TRNS_ETHER,
1126 .eesipr_value = EESIPR_RFCOFIP | EESIPR_ECIIP |
1127 EESIPR_FTCIP | EESIPR_TDEIP | EESIPR_TFUFIP |
1128 EESIPR_FRIP | EESIPR_RDEIP | EESIPR_RFOFIP |
1129 0x0000f000 | EESIPR_CNDIP | EESIPR_DLCIP |
1130 EESIPR_CDIP | EESIPR_TROIP | EESIPR_RMAFIP |
1131 EESIPR_CEEFIP | EESIPR_CELFIP |
1132 EESIPR_RRFIP | EESIPR_RTLFIP | EESIPR_RTSFIP |
1133 EESIPR_PREIP | EESIPR_CERFIP,
1134 .tsu = 1,
1135 .dual_port = 1,
1136};
1137
1138static void sh_eth_set_default_cpu_data(struct sh_eth_cpu_data *cd)
1139{
1140 if (!cd->ecsr_value)
1141 cd->ecsr_value = DEFAULT_ECSR_INIT;
1142
1143 if (!cd->ecsipr_value)
1144 cd->ecsipr_value = DEFAULT_ECSIPR_INIT;
1145
1146 if (!cd->fcftr_value)
1147 cd->fcftr_value = DEFAULT_FIFO_F_D_RFF |
1148 DEFAULT_FIFO_F_D_RFD;
1149
1150 if (!cd->fdr_value)
1151 cd->fdr_value = DEFAULT_FDR_INIT;
1152
1153 if (!cd->tx_check)
1154 cd->tx_check = DEFAULT_TX_CHECK;
1155
1156 if (!cd->eesr_err_check)
1157 cd->eesr_err_check = DEFAULT_EESR_ERR_CHECK;
1158
1159 if (!cd->trscer_err_mask)
1160 cd->trscer_err_mask = DEFAULT_TRSCER_ERR_MASK;
1161}
1162
1163static void sh_eth_set_receive_align(struct sk_buff *skb)
1164{
1165 uintptr_t reserve = (uintptr_t)skb->data & (SH_ETH_RX_ALIGN - 1);
1166
1167 if (reserve)
1168 skb_reserve(skb, SH_ETH_RX_ALIGN - reserve);
1169}
1170
1171/* Program the hardware MAC address from dev->dev_addr. */
1172static void update_mac_address(struct net_device *ndev)
1173{
1174 sh_eth_write(ndev,
1175 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
1176 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
1177 sh_eth_write(ndev,
1178 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
1179}
1180
1181/* Get MAC address from SuperH MAC address register
1182 *
1183 * SuperH's Ethernet device doesn't have 'ROM' to MAC address.
1184 * This driver get MAC address that use by bootloader(U-boot or sh-ipl+g).
1185 * When you want use this device, you must set MAC address in bootloader.
1186 *
1187 */
1188static void read_mac_address(struct net_device *ndev, unsigned char *mac)
1189{
1190 if (mac[0] || mac[1] || mac[2] || mac[3] || mac[4] || mac[5]) {
1191 memcpy(ndev->dev_addr, mac, ETH_ALEN);
1192 } else {
1193 u32 mahr = sh_eth_read(ndev, MAHR);
1194 u32 malr = sh_eth_read(ndev, MALR);
1195
1196 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
1197 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
1198 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
1199 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
1200 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
1201 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
1202 }
1203}
1204
1205struct bb_info {
1206 void (*set_gate)(void *addr);
1207 struct mdiobb_ctrl ctrl;
1208 void *addr;
1209};
1210
1211static void sh_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
1212{
1213 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1214 u32 pir;
1215
1216 if (bitbang->set_gate)
1217 bitbang->set_gate(bitbang->addr);
1218
1219 pir = ioread32(bitbang->addr);
1220 if (set)
1221 pir |= mask;
1222 else
1223 pir &= ~mask;
1224 iowrite32(pir, bitbang->addr);
1225}
1226
1227/* Data I/O pin control */
1228static void sh_mmd_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1229{
1230 sh_mdio_ctrl(ctrl, PIR_MMD, bit);
1231}
1232
1233/* Set bit data*/
1234static void sh_set_mdio(struct mdiobb_ctrl *ctrl, int bit)
1235{
1236 sh_mdio_ctrl(ctrl, PIR_MDO, bit);
1237}
1238
1239/* Get bit data*/
1240static int sh_get_mdio(struct mdiobb_ctrl *ctrl)
1241{
1242 struct bb_info *bitbang = container_of(ctrl, struct bb_info, ctrl);
1243
1244 if (bitbang->set_gate)
1245 bitbang->set_gate(bitbang->addr);
1246
1247 return (ioread32(bitbang->addr) & PIR_MDI) != 0;
1248}
1249
1250/* MDC pin control */
1251static void sh_mdc_ctrl(struct mdiobb_ctrl *ctrl, int bit)
1252{
1253 sh_mdio_ctrl(ctrl, PIR_MDC, bit);
1254}
1255
1256/* mdio bus control struct */
1257static struct mdiobb_ops bb_ops = {
1258 .owner = THIS_MODULE,
1259 .set_mdc = sh_mdc_ctrl,
1260 .set_mdio_dir = sh_mmd_ctrl,
1261 .set_mdio_data = sh_set_mdio,
1262 .get_mdio_data = sh_get_mdio,
1263};
1264
1265/* free Tx skb function */
1266static int sh_eth_tx_free(struct net_device *ndev, bool sent_only)
1267{
1268 struct sh_eth_private *mdp = netdev_priv(ndev);
1269 struct sh_eth_txdesc *txdesc;
1270 int free_num = 0;
1271 int entry;
1272 bool sent;
1273
1274 for (; mdp->cur_tx - mdp->dirty_tx > 0; mdp->dirty_tx++) {
1275 entry = mdp->dirty_tx % mdp->num_tx_ring;
1276 txdesc = &mdp->tx_ring[entry];
1277 sent = !(txdesc->status & cpu_to_le32(TD_TACT));
1278 if (sent_only && !sent)
1279 break;
1280 /* TACT bit must be checked before all the following reads */
1281 dma_rmb();
1282 netif_info(mdp, tx_done, ndev,
1283 "tx entry %d status 0x%08x\n",
1284 entry, le32_to_cpu(txdesc->status));
1285 /* Free the original skb. */
1286 if (mdp->tx_skbuff[entry]) {
1287 dma_unmap_single(&mdp->pdev->dev,
1288 le32_to_cpu(txdesc->addr),
1289 le32_to_cpu(txdesc->len) >> 16,
1290 DMA_TO_DEVICE);
1291 dev_kfree_skb_irq(mdp->tx_skbuff[entry]);
1292 mdp->tx_skbuff[entry] = NULL;
1293 free_num++;
1294 }
1295 txdesc->status = cpu_to_le32(TD_TFP);
1296 if (entry >= mdp->num_tx_ring - 1)
1297 txdesc->status |= cpu_to_le32(TD_TDLE);
1298
1299 if (sent) {
1300 ndev->stats.tx_packets++;
1301 ndev->stats.tx_bytes += le32_to_cpu(txdesc->len) >> 16;
1302 }
1303 }
1304 return free_num;
1305}
1306
1307/* free skb and descriptor buffer */
1308static void sh_eth_ring_free(struct net_device *ndev)
1309{
1310 struct sh_eth_private *mdp = netdev_priv(ndev);
1311 int ringsize, i;
1312
1313 if (mdp->rx_ring) {
1314 for (i = 0; i < mdp->num_rx_ring; i++) {
1315 if (mdp->rx_skbuff[i]) {
1316 struct sh_eth_rxdesc *rxdesc = &mdp->rx_ring[i];
1317
1318 dma_unmap_single(&mdp->pdev->dev,
1319 le32_to_cpu(rxdesc->addr),
1320 ALIGN(mdp->rx_buf_sz, 32),
1321 DMA_FROM_DEVICE);
1322 }
1323 }
1324 ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1325 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->rx_ring,
1326 mdp->rx_desc_dma);
1327 mdp->rx_ring = NULL;
1328 }
1329
1330 /* Free Rx skb ringbuffer */
1331 if (mdp->rx_skbuff) {
1332 for (i = 0; i < mdp->num_rx_ring; i++)
1333 dev_kfree_skb(mdp->rx_skbuff[i]);
1334 }
1335 kfree(mdp->rx_skbuff);
1336 mdp->rx_skbuff = NULL;
1337
1338 if (mdp->tx_ring) {
1339 sh_eth_tx_free(ndev, false);
1340
1341 ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1342 dma_free_coherent(&mdp->pdev->dev, ringsize, mdp->tx_ring,
1343 mdp->tx_desc_dma);
1344 mdp->tx_ring = NULL;
1345 }
1346
1347 /* Free Tx skb ringbuffer */
1348 kfree(mdp->tx_skbuff);
1349 mdp->tx_skbuff = NULL;
1350}
1351
1352/* format skb and descriptor buffer */
1353static void sh_eth_ring_format(struct net_device *ndev)
1354{
1355 struct sh_eth_private *mdp = netdev_priv(ndev);
1356 int i;
1357 struct sk_buff *skb;
1358 struct sh_eth_rxdesc *rxdesc = NULL;
1359 struct sh_eth_txdesc *txdesc = NULL;
1360 int rx_ringsize = sizeof(*rxdesc) * mdp->num_rx_ring;
1361 int tx_ringsize = sizeof(*txdesc) * mdp->num_tx_ring;
1362 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1363 dma_addr_t dma_addr;
1364 u32 buf_len;
1365
1366 mdp->cur_rx = 0;
1367 mdp->cur_tx = 0;
1368 mdp->dirty_rx = 0;
1369 mdp->dirty_tx = 0;
1370
1371 memset(mdp->rx_ring, 0, rx_ringsize);
1372
1373 /* build Rx ring buffer */
1374 for (i = 0; i < mdp->num_rx_ring; i++) {
1375 /* skb */
1376 mdp->rx_skbuff[i] = NULL;
1377 skb = netdev_alloc_skb(ndev, skbuff_size);
1378 if (skb == NULL)
1379 break;
1380 sh_eth_set_receive_align(skb);
1381
1382 /* The size of the buffer is a multiple of 32 bytes. */
1383 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1384 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, buf_len,
1385 DMA_FROM_DEVICE);
1386 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1387 kfree_skb(skb);
1388 break;
1389 }
1390 mdp->rx_skbuff[i] = skb;
1391
1392 /* RX descriptor */
1393 rxdesc = &mdp->rx_ring[i];
1394 rxdesc->len = cpu_to_le32(buf_len << 16);
1395 rxdesc->addr = cpu_to_le32(dma_addr);
1396 rxdesc->status = cpu_to_le32(RD_RACT | RD_RFP);
1397
1398 /* Rx descriptor address set */
1399 if (i == 0) {
1400 sh_eth_write(ndev, mdp->rx_desc_dma, RDLAR);
1401 if (mdp->cd->xdfar_rw)
1402 sh_eth_write(ndev, mdp->rx_desc_dma, RDFAR);
1403 }
1404 }
1405
1406 mdp->dirty_rx = (u32) (i - mdp->num_rx_ring);
1407
1408 /* Mark the last entry as wrapping the ring. */
1409 if (rxdesc)
1410 rxdesc->status |= cpu_to_le32(RD_RDLE);
1411
1412 memset(mdp->tx_ring, 0, tx_ringsize);
1413
1414 /* build Tx ring buffer */
1415 for (i = 0; i < mdp->num_tx_ring; i++) {
1416 mdp->tx_skbuff[i] = NULL;
1417 txdesc = &mdp->tx_ring[i];
1418 txdesc->status = cpu_to_le32(TD_TFP);
1419 txdesc->len = cpu_to_le32(0);
1420 if (i == 0) {
1421 /* Tx descriptor address set */
1422 sh_eth_write(ndev, mdp->tx_desc_dma, TDLAR);
1423 if (mdp->cd->xdfar_rw)
1424 sh_eth_write(ndev, mdp->tx_desc_dma, TDFAR);
1425 }
1426 }
1427
1428 txdesc->status |= cpu_to_le32(TD_TDLE);
1429}
1430
1431/* Get skb and descriptor buffer */
1432static int sh_eth_ring_init(struct net_device *ndev)
1433{
1434 struct sh_eth_private *mdp = netdev_priv(ndev);
1435 int rx_ringsize, tx_ringsize;
1436
1437 /* +26 gets the maximum ethernet encapsulation, +7 & ~7 because the
1438 * card needs room to do 8 byte alignment, +2 so we can reserve
1439 * the first 2 bytes, and +16 gets room for the status word from the
1440 * card.
1441 */
1442 mdp->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ :
1443 (((ndev->mtu + 26 + 7) & ~7) + 2 + 16));
1444 if (mdp->cd->rpadir)
1445 mdp->rx_buf_sz += NET_IP_ALIGN;
1446
1447 /* Allocate RX and TX skb rings */
1448 mdp->rx_skbuff = kcalloc(mdp->num_rx_ring, sizeof(*mdp->rx_skbuff),
1449 GFP_KERNEL);
1450 if (!mdp->rx_skbuff)
1451 return -ENOMEM;
1452
1453 mdp->tx_skbuff = kcalloc(mdp->num_tx_ring, sizeof(*mdp->tx_skbuff),
1454 GFP_KERNEL);
1455 if (!mdp->tx_skbuff)
1456 goto ring_free;
1457
1458 /* Allocate all Rx descriptors. */
1459 rx_ringsize = sizeof(struct sh_eth_rxdesc) * mdp->num_rx_ring;
1460 mdp->rx_ring = dma_alloc_coherent(&mdp->pdev->dev, rx_ringsize,
1461 &mdp->rx_desc_dma, GFP_KERNEL);
1462 if (!mdp->rx_ring)
1463 goto ring_free;
1464
1465 mdp->dirty_rx = 0;
1466
1467 /* Allocate all Tx descriptors. */
1468 tx_ringsize = sizeof(struct sh_eth_txdesc) * mdp->num_tx_ring;
1469 mdp->tx_ring = dma_alloc_coherent(&mdp->pdev->dev, tx_ringsize,
1470 &mdp->tx_desc_dma, GFP_KERNEL);
1471 if (!mdp->tx_ring)
1472 goto ring_free;
1473 return 0;
1474
1475ring_free:
1476 /* Free Rx and Tx skb ring buffer and DMA buffer */
1477 sh_eth_ring_free(ndev);
1478
1479 return -ENOMEM;
1480}
1481
1482static int sh_eth_dev_init(struct net_device *ndev)
1483{
1484 struct sh_eth_private *mdp = netdev_priv(ndev);
1485 int ret;
1486
1487 /* Soft Reset */
1488 ret = mdp->cd->soft_reset(ndev);
1489 if (ret)
1490 return ret;
1491
1492 if (mdp->cd->rmiimode)
1493 sh_eth_write(ndev, 0x1, RMIIMODE);
1494
1495 /* Descriptor format */
1496 sh_eth_ring_format(ndev);
1497 if (mdp->cd->rpadir)
1498 sh_eth_write(ndev, NET_IP_ALIGN << 16, RPADIR);
1499
1500 /* all sh_eth int mask */
1501 sh_eth_write(ndev, 0, EESIPR);
1502
1503#if defined(__LITTLE_ENDIAN)
1504 if (mdp->cd->hw_swap)
1505 sh_eth_write(ndev, EDMR_EL, EDMR);
1506 else
1507#endif
1508 sh_eth_write(ndev, 0, EDMR);
1509
1510 /* FIFO size set */
1511 sh_eth_write(ndev, mdp->cd->fdr_value, FDR);
1512 sh_eth_write(ndev, 0, TFTR);
1513
1514 /* Frame recv control (enable multiple-packets per rx irq) */
1515 sh_eth_write(ndev, RMCR_RNC, RMCR);
1516
1517 sh_eth_write(ndev, mdp->cd->trscer_err_mask, TRSCER);
1518
1519 /* DMA transfer burst mode */
1520 if (mdp->cd->nbst)
1521 sh_eth_modify(ndev, EDMR, EDMR_NBST, EDMR_NBST);
1522
1523 /* Burst cycle count upper-limit */
1524 if (mdp->cd->bculr)
1525 sh_eth_write(ndev, 0x800, BCULR);
1526
1527 sh_eth_write(ndev, mdp->cd->fcftr_value, FCFTR);
1528
1529 if (!mdp->cd->no_trimd)
1530 sh_eth_write(ndev, 0, TRIMD);
1531
1532 /* Recv frame limit set register */
1533 sh_eth_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN,
1534 RFLR);
1535
1536 sh_eth_modify(ndev, EESR, 0, 0);
1537 mdp->irq_enabled = true;
1538 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1539
1540 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
1541 sh_eth_write(ndev, ECMR_ZPF | (mdp->duplex ? ECMR_DM : 0) |
1542 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
1543 ECMR_TE | ECMR_RE, ECMR);
1544
1545 if (mdp->cd->set_rate)
1546 mdp->cd->set_rate(ndev);
1547
1548 /* E-MAC Status Register clear */
1549 sh_eth_write(ndev, mdp->cd->ecsr_value, ECSR);
1550
1551 /* E-MAC Interrupt Enable register */
1552 sh_eth_write(ndev, mdp->cd->ecsipr_value, ECSIPR);
1553
1554 /* Set MAC address */
1555 update_mac_address(ndev);
1556
1557 /* mask reset */
1558 if (mdp->cd->apr)
1559 sh_eth_write(ndev, 1, APR);
1560 if (mdp->cd->mpr)
1561 sh_eth_write(ndev, 1, MPR);
1562 if (mdp->cd->tpauser)
1563 sh_eth_write(ndev, TPAUSER_UNLIMITED, TPAUSER);
1564
1565 /* Setting the Rx mode will start the Rx process. */
1566 sh_eth_write(ndev, EDRRR_R, EDRRR);
1567
1568 return ret;
1569}
1570
1571static void sh_eth_dev_exit(struct net_device *ndev)
1572{
1573 struct sh_eth_private *mdp = netdev_priv(ndev);
1574 int i;
1575
1576 /* Deactivate all TX descriptors, so DMA should stop at next
1577 * packet boundary if it's currently running
1578 */
1579 for (i = 0; i < mdp->num_tx_ring; i++)
1580 mdp->tx_ring[i].status &= ~cpu_to_le32(TD_TACT);
1581
1582 /* Disable TX FIFO egress to MAC */
1583 sh_eth_rcv_snd_disable(ndev);
1584
1585 /* Stop RX DMA at next packet boundary */
1586 sh_eth_write(ndev, 0, EDRRR);
1587
1588 /* Aside from TX DMA, we can't tell when the hardware is
1589 * really stopped, so we need to reset to make sure.
1590 * Before doing that, wait for long enough to *probably*
1591 * finish transmitting the last packet and poll stats.
1592 */
1593 msleep(2); /* max frame time at 10 Mbps < 1250 us */
1594 sh_eth_get_stats(ndev);
1595 mdp->cd->soft_reset(ndev);
1596
1597 /* Set the RMII mode again if required */
1598 if (mdp->cd->rmiimode)
1599 sh_eth_write(ndev, 0x1, RMIIMODE);
1600
1601 /* Set MAC address again */
1602 update_mac_address(ndev);
1603}
1604
1605static void sh_eth_rx_csum(struct sk_buff *skb)
1606{
1607 u8 *hw_csum;
1608
1609 /* The hardware checksum is 2 bytes appended to packet data */
1610 if (unlikely(skb->len < sizeof(__sum16)))
1611 return;
1612 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
1613 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
1614 skb->ip_summed = CHECKSUM_COMPLETE;
1615 skb_trim(skb, skb->len - sizeof(__sum16));
1616}
1617
1618/* Packet receive function */
1619static int sh_eth_rx(struct net_device *ndev, u32 intr_status, int *quota)
1620{
1621 struct sh_eth_private *mdp = netdev_priv(ndev);
1622 struct sh_eth_rxdesc *rxdesc;
1623
1624 int entry = mdp->cur_rx % mdp->num_rx_ring;
1625 int boguscnt = (mdp->dirty_rx + mdp->num_rx_ring) - mdp->cur_rx;
1626 int limit;
1627 struct sk_buff *skb;
1628 u32 desc_status;
1629 int skbuff_size = mdp->rx_buf_sz + SH_ETH_RX_ALIGN + 32 - 1;
1630 dma_addr_t dma_addr;
1631 u16 pkt_len;
1632 u32 buf_len;
1633
1634 boguscnt = min(boguscnt, *quota);
1635 limit = boguscnt;
1636 rxdesc = &mdp->rx_ring[entry];
1637 while (!(rxdesc->status & cpu_to_le32(RD_RACT))) {
1638 /* RACT bit must be checked before all the following reads */
1639 dma_rmb();
1640 desc_status = le32_to_cpu(rxdesc->status);
1641 pkt_len = le32_to_cpu(rxdesc->len) & RD_RFL;
1642
1643 if (--boguscnt < 0)
1644 break;
1645
1646 netif_info(mdp, rx_status, ndev,
1647 "rx entry %d status 0x%08x len %d\n",
1648 entry, desc_status, pkt_len);
1649
1650 if (!(desc_status & RDFEND))
1651 ndev->stats.rx_length_errors++;
1652
1653 /* In case of almost all GETHER/ETHERs, the Receive Frame State
1654 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
1655 * bit 0. However, in case of the R8A7740 and R7S72100
1656 * the RFS bits are from bit 25 to bit 16. So, the
1657 * driver needs right shifting by 16.
1658 */
1659 if (mdp->cd->csmr)
1660 desc_status >>= 16;
1661
1662 skb = mdp->rx_skbuff[entry];
1663 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
1664 RD_RFS5 | RD_RFS6 | RD_RFS10)) {
1665 ndev->stats.rx_errors++;
1666 if (desc_status & RD_RFS1)
1667 ndev->stats.rx_crc_errors++;
1668 if (desc_status & RD_RFS2)
1669 ndev->stats.rx_frame_errors++;
1670 if (desc_status & RD_RFS3)
1671 ndev->stats.rx_length_errors++;
1672 if (desc_status & RD_RFS4)
1673 ndev->stats.rx_length_errors++;
1674 if (desc_status & RD_RFS6)
1675 ndev->stats.rx_missed_errors++;
1676 if (desc_status & RD_RFS10)
1677 ndev->stats.rx_over_errors++;
1678 } else if (skb) {
1679 dma_addr = le32_to_cpu(rxdesc->addr);
1680 if (!mdp->cd->hw_swap)
1681 sh_eth_soft_swap(
1682 phys_to_virt(ALIGN(dma_addr, 4)),
1683 pkt_len + 2);
1684 mdp->rx_skbuff[entry] = NULL;
1685 if (mdp->cd->rpadir)
1686 skb_reserve(skb, NET_IP_ALIGN);
1687 dma_unmap_single(&mdp->pdev->dev, dma_addr,
1688 ALIGN(mdp->rx_buf_sz, 32),
1689 DMA_FROM_DEVICE);
1690 skb_put(skb, pkt_len);
1691 skb->protocol = eth_type_trans(skb, ndev);
1692 if (ndev->features & NETIF_F_RXCSUM)
1693 sh_eth_rx_csum(skb);
1694 netif_receive_skb(skb);
1695 ndev->stats.rx_packets++;
1696 ndev->stats.rx_bytes += pkt_len;
1697 if (desc_status & RD_RFS8)
1698 ndev->stats.multicast++;
1699 }
1700 entry = (++mdp->cur_rx) % mdp->num_rx_ring;
1701 rxdesc = &mdp->rx_ring[entry];
1702 }
1703
1704 /* Refill the Rx ring buffers. */
1705 for (; mdp->cur_rx - mdp->dirty_rx > 0; mdp->dirty_rx++) {
1706 entry = mdp->dirty_rx % mdp->num_rx_ring;
1707 rxdesc = &mdp->rx_ring[entry];
1708 /* The size of the buffer is 32 byte boundary. */
1709 buf_len = ALIGN(mdp->rx_buf_sz, 32);
1710 rxdesc->len = cpu_to_le32(buf_len << 16);
1711
1712 if (mdp->rx_skbuff[entry] == NULL) {
1713 skb = netdev_alloc_skb(ndev, skbuff_size);
1714 if (skb == NULL)
1715 break; /* Better luck next round. */
1716 sh_eth_set_receive_align(skb);
1717 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data,
1718 buf_len, DMA_FROM_DEVICE);
1719 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
1720 kfree_skb(skb);
1721 break;
1722 }
1723 mdp->rx_skbuff[entry] = skb;
1724
1725 skb_checksum_none_assert(skb);
1726 rxdesc->addr = cpu_to_le32(dma_addr);
1727 }
1728 dma_wmb(); /* RACT bit must be set after all the above writes */
1729 if (entry >= mdp->num_rx_ring - 1)
1730 rxdesc->status |=
1731 cpu_to_le32(RD_RACT | RD_RFP | RD_RDLE);
1732 else
1733 rxdesc->status |= cpu_to_le32(RD_RACT | RD_RFP);
1734 }
1735
1736 /* Restart Rx engine if stopped. */
1737 /* If we don't need to check status, don't. -KDU */
1738 if (!(sh_eth_read(ndev, EDRRR) & EDRRR_R)) {
1739 /* fix the values for the next receiving if RDE is set */
1740 if (intr_status & EESR_RDE && !mdp->cd->no_xdfar) {
1741 u32 count = (sh_eth_read(ndev, RDFAR) -
1742 sh_eth_read(ndev, RDLAR)) >> 4;
1743
1744 mdp->cur_rx = count;
1745 mdp->dirty_rx = count;
1746 }
1747 sh_eth_write(ndev, EDRRR_R, EDRRR);
1748 }
1749
1750 *quota -= limit - boguscnt - 1;
1751
1752 return *quota <= 0;
1753}
1754
1755static void sh_eth_rcv_snd_disable(struct net_device *ndev)
1756{
1757 /* disable tx and rx */
1758 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
1759}
1760
1761static void sh_eth_rcv_snd_enable(struct net_device *ndev)
1762{
1763 /* enable tx and rx */
1764 sh_eth_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
1765}
1766
1767/* E-MAC interrupt handler */
1768static void sh_eth_emac_interrupt(struct net_device *ndev)
1769{
1770 struct sh_eth_private *mdp = netdev_priv(ndev);
1771 u32 felic_stat;
1772 u32 link_stat;
1773
1774 felic_stat = sh_eth_read(ndev, ECSR) & sh_eth_read(ndev, ECSIPR);
1775 sh_eth_write(ndev, felic_stat, ECSR); /* clear int */
1776 if (felic_stat & ECSR_ICD)
1777 ndev->stats.tx_carrier_errors++;
1778 if (felic_stat & ECSR_MPD)
1779 pm_wakeup_event(&mdp->pdev->dev, 0);
1780 if (felic_stat & ECSR_LCHNG) {
1781 /* Link Changed */
1782 if (mdp->cd->no_psr || mdp->no_ether_link)
1783 return;
1784 link_stat = sh_eth_read(ndev, PSR);
1785 if (mdp->ether_link_active_low)
1786 link_stat = ~link_stat;
1787 if (!(link_stat & PHY_ST_LINK)) {
1788 sh_eth_rcv_snd_disable(ndev);
1789 } else {
1790 /* Link Up */
1791 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, 0);
1792 /* clear int */
1793 sh_eth_modify(ndev, ECSR, 0, 0);
1794 sh_eth_modify(ndev, EESIPR, EESIPR_ECIIP, EESIPR_ECIIP);
1795 /* enable tx and rx */
1796 sh_eth_rcv_snd_enable(ndev);
1797 }
1798 }
1799}
1800
1801/* error control function */
1802static void sh_eth_error(struct net_device *ndev, u32 intr_status)
1803{
1804 struct sh_eth_private *mdp = netdev_priv(ndev);
1805 u32 mask;
1806
1807 if (intr_status & EESR_TWB) {
1808 /* Unused write back interrupt */
1809 if (intr_status & EESR_TABT) { /* Transmit Abort int */
1810 ndev->stats.tx_aborted_errors++;
1811 netif_err(mdp, tx_err, ndev, "Transmit Abort\n");
1812 }
1813 }
1814
1815 if (intr_status & EESR_RABT) {
1816 /* Receive Abort int */
1817 if (intr_status & EESR_RFRMER) {
1818 /* Receive Frame Overflow int */
1819 ndev->stats.rx_frame_errors++;
1820 }
1821 }
1822
1823 if (intr_status & EESR_TDE) {
1824 /* Transmit Descriptor Empty int */
1825 ndev->stats.tx_fifo_errors++;
1826 netif_err(mdp, tx_err, ndev, "Transmit Descriptor Empty\n");
1827 }
1828
1829 if (intr_status & EESR_TFE) {
1830 /* FIFO under flow */
1831 ndev->stats.tx_fifo_errors++;
1832 netif_err(mdp, tx_err, ndev, "Transmit FIFO Under flow\n");
1833 }
1834
1835 if (intr_status & EESR_RDE) {
1836 /* Receive Descriptor Empty int */
1837 ndev->stats.rx_over_errors++;
1838 }
1839
1840 if (intr_status & EESR_RFE) {
1841 /* Receive FIFO Overflow int */
1842 ndev->stats.rx_fifo_errors++;
1843 }
1844
1845 if (!mdp->cd->no_ade && (intr_status & EESR_ADE)) {
1846 /* Address Error */
1847 ndev->stats.tx_fifo_errors++;
1848 netif_err(mdp, tx_err, ndev, "Address Error\n");
1849 }
1850
1851 mask = EESR_TWB | EESR_TABT | EESR_ADE | EESR_TDE | EESR_TFE;
1852 if (mdp->cd->no_ade)
1853 mask &= ~EESR_ADE;
1854 if (intr_status & mask) {
1855 /* Tx error */
1856 u32 edtrr = sh_eth_read(ndev, EDTRR);
1857
1858 /* dmesg */
1859 netdev_err(ndev, "TX error. status=%8.8x cur_tx=%8.8x dirty_tx=%8.8x state=%8.8x EDTRR=%8.8x.\n",
1860 intr_status, mdp->cur_tx, mdp->dirty_tx,
1861 (u32)ndev->state, edtrr);
1862 /* dirty buffer free */
1863 sh_eth_tx_free(ndev, true);
1864
1865 /* SH7712 BUG */
1866 if (edtrr ^ mdp->cd->edtrr_trns) {
1867 /* tx dma start */
1868 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
1869 }
1870 /* wakeup */
1871 netif_wake_queue(ndev);
1872 }
1873}
1874
1875static irqreturn_t sh_eth_interrupt(int irq, void *netdev)
1876{
1877 struct net_device *ndev = netdev;
1878 struct sh_eth_private *mdp = netdev_priv(ndev);
1879 struct sh_eth_cpu_data *cd = mdp->cd;
1880 irqreturn_t ret = IRQ_NONE;
1881 u32 intr_status, intr_enable;
1882
1883 spin_lock(&mdp->lock);
1884
1885 /* Get interrupt status */
1886 intr_status = sh_eth_read(ndev, EESR);
1887 /* Mask it with the interrupt mask, forcing ECI interrupt to be always
1888 * enabled since it's the one that comes thru regardless of the mask,
1889 * and we need to fully handle it in sh_eth_emac_interrupt() in order
1890 * to quench it as it doesn't get cleared by just writing 1 to the ECI
1891 * bit...
1892 */
1893 intr_enable = sh_eth_read(ndev, EESIPR);
1894 intr_status &= intr_enable | EESIPR_ECIIP;
1895 if (intr_status & (EESR_RX_CHECK | cd->tx_check | EESR_ECI |
1896 cd->eesr_err_check))
1897 ret = IRQ_HANDLED;
1898 else
1899 goto out;
1900
1901 if (unlikely(!mdp->irq_enabled)) {
1902 sh_eth_write(ndev, 0, EESIPR);
1903 goto out;
1904 }
1905
1906 if (intr_status & EESR_RX_CHECK) {
1907 if (napi_schedule_prep(&mdp->napi)) {
1908 /* Mask Rx interrupts */
1909 sh_eth_write(ndev, intr_enable & ~EESR_RX_CHECK,
1910 EESIPR);
1911 __napi_schedule(&mdp->napi);
1912 } else {
1913 netdev_warn(ndev,
1914 "ignoring interrupt, status 0x%08x, mask 0x%08x.\n",
1915 intr_status, intr_enable);
1916 }
1917 }
1918
1919 /* Tx Check */
1920 if (intr_status & cd->tx_check) {
1921 /* Clear Tx interrupts */
1922 sh_eth_write(ndev, intr_status & cd->tx_check, EESR);
1923
1924 sh_eth_tx_free(ndev, true);
1925 netif_wake_queue(ndev);
1926 }
1927
1928 /* E-MAC interrupt */
1929 if (intr_status & EESR_ECI)
1930 sh_eth_emac_interrupt(ndev);
1931
1932 if (intr_status & cd->eesr_err_check) {
1933 /* Clear error interrupts */
1934 sh_eth_write(ndev, intr_status & cd->eesr_err_check, EESR);
1935
1936 sh_eth_error(ndev, intr_status);
1937 }
1938
1939out:
1940 spin_unlock(&mdp->lock);
1941
1942 return ret;
1943}
1944
1945static int sh_eth_poll(struct napi_struct *napi, int budget)
1946{
1947 struct sh_eth_private *mdp = container_of(napi, struct sh_eth_private,
1948 napi);
1949 struct net_device *ndev = napi->dev;
1950 int quota = budget;
1951 u32 intr_status;
1952
1953 for (;;) {
1954 intr_status = sh_eth_read(ndev, EESR);
1955 if (!(intr_status & EESR_RX_CHECK))
1956 break;
1957 /* Clear Rx interrupts */
1958 sh_eth_write(ndev, intr_status & EESR_RX_CHECK, EESR);
1959
1960 if (sh_eth_rx(ndev, intr_status, "a))
1961 goto out;
1962 }
1963
1964 napi_complete(napi);
1965
1966 /* Reenable Rx interrupts */
1967 if (mdp->irq_enabled)
1968 sh_eth_write(ndev, mdp->cd->eesipr_value, EESIPR);
1969out:
1970 return budget - quota;
1971}
1972
1973/* PHY state control function */
1974static void sh_eth_adjust_link(struct net_device *ndev)
1975{
1976 struct sh_eth_private *mdp = netdev_priv(ndev);
1977 struct phy_device *phydev = ndev->phydev;
1978 unsigned long flags;
1979 int new_state = 0;
1980
1981 spin_lock_irqsave(&mdp->lock, flags);
1982
1983 /* Disable TX and RX right over here, if E-MAC change is ignored */
1984 if (mdp->cd->no_psr || mdp->no_ether_link)
1985 sh_eth_rcv_snd_disable(ndev);
1986
1987 if (phydev->link) {
1988 if (phydev->duplex != mdp->duplex) {
1989 new_state = 1;
1990 mdp->duplex = phydev->duplex;
1991 if (mdp->cd->set_duplex)
1992 mdp->cd->set_duplex(ndev);
1993 }
1994
1995 if (phydev->speed != mdp->speed) {
1996 new_state = 1;
1997 mdp->speed = phydev->speed;
1998 if (mdp->cd->set_rate)
1999 mdp->cd->set_rate(ndev);
2000 }
2001 if (!mdp->link) {
2002 sh_eth_modify(ndev, ECMR, ECMR_TXF, 0);
2003 new_state = 1;
2004 mdp->link = phydev->link;
2005 }
2006 } else if (mdp->link) {
2007 new_state = 1;
2008 mdp->link = 0;
2009 mdp->speed = 0;
2010 mdp->duplex = -1;
2011 }
2012
2013 /* Enable TX and RX right over here, if E-MAC change is ignored */
2014 if ((mdp->cd->no_psr || mdp->no_ether_link) && phydev->link)
2015 sh_eth_rcv_snd_enable(ndev);
2016
2017 spin_unlock_irqrestore(&mdp->lock, flags);
2018
2019 if (new_state && netif_msg_link(mdp))
2020 phy_print_status(phydev);
2021}
2022
2023/* PHY init function */
2024static int sh_eth_phy_init(struct net_device *ndev)
2025{
2026 struct device_node *np = ndev->dev.parent->of_node;
2027 struct sh_eth_private *mdp = netdev_priv(ndev);
2028 struct phy_device *phydev;
2029
2030 mdp->link = 0;
2031 mdp->speed = 0;
2032 mdp->duplex = -1;
2033
2034 /* Try connect to PHY */
2035 if (np) {
2036 struct device_node *pn;
2037
2038 pn = of_parse_phandle(np, "phy-handle", 0);
2039 phydev = of_phy_connect(ndev, pn,
2040 sh_eth_adjust_link, 0,
2041 mdp->phy_interface);
2042
2043 of_node_put(pn);
2044 if (!phydev)
2045 phydev = ERR_PTR(-ENOENT);
2046 } else {
2047 char phy_id[MII_BUS_ID_SIZE + 3];
2048
2049 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT,
2050 mdp->mii_bus->id, mdp->phy_id);
2051
2052 phydev = phy_connect(ndev, phy_id, sh_eth_adjust_link,
2053 mdp->phy_interface);
2054 }
2055
2056 if (IS_ERR(phydev)) {
2057 netdev_err(ndev, "failed to connect PHY\n");
2058 return PTR_ERR(phydev);
2059 }
2060
2061 /* mask with MAC supported features */
2062 if (mdp->cd->register_type != SH_ETH_REG_GIGABIT) {
2063 int err = phy_set_max_speed(phydev, SPEED_100);
2064 if (err) {
2065 netdev_err(ndev, "failed to limit PHY to 100 Mbit/s\n");
2066 phy_disconnect(phydev);
2067 return err;
2068 }
2069 }
2070
2071 phy_attached_info(phydev);
2072
2073 return 0;
2074}
2075
2076/* PHY control start function */
2077static int sh_eth_phy_start(struct net_device *ndev)
2078{
2079 int ret;
2080
2081 ret = sh_eth_phy_init(ndev);
2082 if (ret)
2083 return ret;
2084
2085 phy_start(ndev->phydev);
2086
2087 return 0;
2088}
2089
2090/* If it is ever necessary to increase SH_ETH_REG_DUMP_MAX_REGS, the
2091 * version must be bumped as well. Just adding registers up to that
2092 * limit is fine, as long as the existing register indices don't
2093 * change.
2094 */
2095#define SH_ETH_REG_DUMP_VERSION 1
2096#define SH_ETH_REG_DUMP_MAX_REGS 256
2097
2098static size_t __sh_eth_get_regs(struct net_device *ndev, u32 *buf)
2099{
2100 struct sh_eth_private *mdp = netdev_priv(ndev);
2101 struct sh_eth_cpu_data *cd = mdp->cd;
2102 u32 *valid_map;
2103 size_t len;
2104
2105 BUILD_BUG_ON(SH_ETH_MAX_REGISTER_OFFSET > SH_ETH_REG_DUMP_MAX_REGS);
2106
2107 /* Dump starts with a bitmap that tells ethtool which
2108 * registers are defined for this chip.
2109 */
2110 len = DIV_ROUND_UP(SH_ETH_REG_DUMP_MAX_REGS, 32);
2111 if (buf) {
2112 valid_map = buf;
2113 buf += len;
2114 } else {
2115 valid_map = NULL;
2116 }
2117
2118 /* Add a register to the dump, if it has a defined offset.
2119 * This automatically skips most undefined registers, but for
2120 * some it is also necessary to check a capability flag in
2121 * struct sh_eth_cpu_data.
2122 */
2123#define mark_reg_valid(reg) valid_map[reg / 32] |= 1U << (reg % 32)
2124#define add_reg_from(reg, read_expr) do { \
2125 if (mdp->reg_offset[reg] != SH_ETH_OFFSET_INVALID) { \
2126 if (buf) { \
2127 mark_reg_valid(reg); \
2128 *buf++ = read_expr; \
2129 } \
2130 ++len; \
2131 } \
2132 } while (0)
2133#define add_reg(reg) add_reg_from(reg, sh_eth_read(ndev, reg))
2134#define add_tsu_reg(reg) add_reg_from(reg, sh_eth_tsu_read(mdp, reg))
2135
2136 add_reg(EDSR);
2137 add_reg(EDMR);
2138 add_reg(EDTRR);
2139 add_reg(EDRRR);
2140 add_reg(EESR);
2141 add_reg(EESIPR);
2142 add_reg(TDLAR);
2143 add_reg(TDFAR);
2144 add_reg(TDFXR);
2145 add_reg(TDFFR);
2146 add_reg(RDLAR);
2147 add_reg(RDFAR);
2148 add_reg(RDFXR);
2149 add_reg(RDFFR);
2150 add_reg(TRSCER);
2151 add_reg(RMFCR);
2152 add_reg(TFTR);
2153 add_reg(FDR);
2154 add_reg(RMCR);
2155 add_reg(TFUCR);
2156 add_reg(RFOCR);
2157 if (cd->rmiimode)
2158 add_reg(RMIIMODE);
2159 add_reg(FCFTR);
2160 if (cd->rpadir)
2161 add_reg(RPADIR);
2162 if (!cd->no_trimd)
2163 add_reg(TRIMD);
2164 add_reg(ECMR);
2165 add_reg(ECSR);
2166 add_reg(ECSIPR);
2167 add_reg(PIR);
2168 if (!cd->no_psr)
2169 add_reg(PSR);
2170 add_reg(RDMLR);
2171 add_reg(RFLR);
2172 add_reg(IPGR);
2173 if (cd->apr)
2174 add_reg(APR);
2175 if (cd->mpr)
2176 add_reg(MPR);
2177 add_reg(RFCR);
2178 add_reg(RFCF);
2179 if (cd->tpauser)
2180 add_reg(TPAUSER);
2181 add_reg(TPAUSECR);
2182 add_reg(GECMR);
2183 if (cd->bculr)
2184 add_reg(BCULR);
2185 add_reg(MAHR);
2186 add_reg(MALR);
2187 add_reg(TROCR);
2188 add_reg(CDCR);
2189 add_reg(LCCR);
2190 add_reg(CNDCR);
2191 add_reg(CEFCR);
2192 add_reg(FRECR);
2193 add_reg(TSFRCR);
2194 add_reg(TLFRCR);
2195 add_reg(CERCR);
2196 add_reg(CEECR);
2197 add_reg(MAFCR);
2198 if (cd->rtrate)
2199 add_reg(RTRATE);
2200 if (cd->csmr)
2201 add_reg(CSMR);
2202 if (cd->select_mii)
2203 add_reg(RMII_MII);
2204 if (cd->tsu) {
2205 add_tsu_reg(ARSTR);
2206 add_tsu_reg(TSU_CTRST);
2207 add_tsu_reg(TSU_FWEN0);
2208 add_tsu_reg(TSU_FWEN1);
2209 add_tsu_reg(TSU_FCM);
2210 add_tsu_reg(TSU_BSYSL0);
2211 add_tsu_reg(TSU_BSYSL1);
2212 add_tsu_reg(TSU_PRISL0);
2213 add_tsu_reg(TSU_PRISL1);
2214 add_tsu_reg(TSU_FWSL0);
2215 add_tsu_reg(TSU_FWSL1);
2216 add_tsu_reg(TSU_FWSLC);
2217 add_tsu_reg(TSU_QTAGM0);
2218 add_tsu_reg(TSU_QTAGM1);
2219 add_tsu_reg(TSU_FWSR);
2220 add_tsu_reg(TSU_FWINMK);
2221 add_tsu_reg(TSU_ADQT0);
2222 add_tsu_reg(TSU_ADQT1);
2223 add_tsu_reg(TSU_VTAG0);
2224 add_tsu_reg(TSU_VTAG1);
2225 add_tsu_reg(TSU_ADSBSY);
2226 add_tsu_reg(TSU_TEN);
2227 add_tsu_reg(TSU_POST1);
2228 add_tsu_reg(TSU_POST2);
2229 add_tsu_reg(TSU_POST3);
2230 add_tsu_reg(TSU_POST4);
2231 /* This is the start of a table, not just a single register. */
2232 if (buf) {
2233 unsigned int i;
2234
2235 mark_reg_valid(TSU_ADRH0);
2236 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES * 2; i++)
2237 *buf++ = ioread32(mdp->tsu_addr +
2238 mdp->reg_offset[TSU_ADRH0] +
2239 i * 4);
2240 }
2241 len += SH_ETH_TSU_CAM_ENTRIES * 2;
2242 }
2243
2244#undef mark_reg_valid
2245#undef add_reg_from
2246#undef add_reg
2247#undef add_tsu_reg
2248
2249 return len * 4;
2250}
2251
2252static int sh_eth_get_regs_len(struct net_device *ndev)
2253{
2254 return __sh_eth_get_regs(ndev, NULL);
2255}
2256
2257static void sh_eth_get_regs(struct net_device *ndev, struct ethtool_regs *regs,
2258 void *buf)
2259{
2260 struct sh_eth_private *mdp = netdev_priv(ndev);
2261
2262 regs->version = SH_ETH_REG_DUMP_VERSION;
2263
2264 pm_runtime_get_sync(&mdp->pdev->dev);
2265 __sh_eth_get_regs(ndev, buf);
2266 pm_runtime_put_sync(&mdp->pdev->dev);
2267}
2268
2269static u32 sh_eth_get_msglevel(struct net_device *ndev)
2270{
2271 struct sh_eth_private *mdp = netdev_priv(ndev);
2272 return mdp->msg_enable;
2273}
2274
2275static void sh_eth_set_msglevel(struct net_device *ndev, u32 value)
2276{
2277 struct sh_eth_private *mdp = netdev_priv(ndev);
2278 mdp->msg_enable = value;
2279}
2280
2281static const char sh_eth_gstrings_stats[][ETH_GSTRING_LEN] = {
2282 "rx_current", "tx_current",
2283 "rx_dirty", "tx_dirty",
2284};
2285#define SH_ETH_STATS_LEN ARRAY_SIZE(sh_eth_gstrings_stats)
2286
2287static int sh_eth_get_sset_count(struct net_device *netdev, int sset)
2288{
2289 switch (sset) {
2290 case ETH_SS_STATS:
2291 return SH_ETH_STATS_LEN;
2292 default:
2293 return -EOPNOTSUPP;
2294 }
2295}
2296
2297static void sh_eth_get_ethtool_stats(struct net_device *ndev,
2298 struct ethtool_stats *stats, u64 *data)
2299{
2300 struct sh_eth_private *mdp = netdev_priv(ndev);
2301 int i = 0;
2302
2303 /* device-specific stats */
2304 data[i++] = mdp->cur_rx;
2305 data[i++] = mdp->cur_tx;
2306 data[i++] = mdp->dirty_rx;
2307 data[i++] = mdp->dirty_tx;
2308}
2309
2310static void sh_eth_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
2311{
2312 switch (stringset) {
2313 case ETH_SS_STATS:
2314 memcpy(data, *sh_eth_gstrings_stats,
2315 sizeof(sh_eth_gstrings_stats));
2316 break;
2317 }
2318}
2319
2320static void sh_eth_get_ringparam(struct net_device *ndev,
2321 struct ethtool_ringparam *ring)
2322{
2323 struct sh_eth_private *mdp = netdev_priv(ndev);
2324
2325 ring->rx_max_pending = RX_RING_MAX;
2326 ring->tx_max_pending = TX_RING_MAX;
2327 ring->rx_pending = mdp->num_rx_ring;
2328 ring->tx_pending = mdp->num_tx_ring;
2329}
2330
2331static int sh_eth_set_ringparam(struct net_device *ndev,
2332 struct ethtool_ringparam *ring)
2333{
2334 struct sh_eth_private *mdp = netdev_priv(ndev);
2335 int ret;
2336
2337 if (ring->tx_pending > TX_RING_MAX ||
2338 ring->rx_pending > RX_RING_MAX ||
2339 ring->tx_pending < TX_RING_MIN ||
2340 ring->rx_pending < RX_RING_MIN)
2341 return -EINVAL;
2342 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
2343 return -EINVAL;
2344
2345 if (netif_running(ndev)) {
2346 netif_device_detach(ndev);
2347 netif_tx_disable(ndev);
2348
2349 /* Serialise with the interrupt handler and NAPI, then
2350 * disable interrupts. We have to clear the
2351 * irq_enabled flag first to ensure that interrupts
2352 * won't be re-enabled.
2353 */
2354 mdp->irq_enabled = false;
2355 synchronize_irq(ndev->irq);
2356 napi_synchronize(&mdp->napi);
2357 sh_eth_write(ndev, 0x0000, EESIPR);
2358
2359 sh_eth_dev_exit(ndev);
2360
2361 /* Free all the skbuffs in the Rx queue and the DMA buffers. */
2362 sh_eth_ring_free(ndev);
2363 }
2364
2365 /* Set new parameters */
2366 mdp->num_rx_ring = ring->rx_pending;
2367 mdp->num_tx_ring = ring->tx_pending;
2368
2369 if (netif_running(ndev)) {
2370 ret = sh_eth_ring_init(ndev);
2371 if (ret < 0) {
2372 netdev_err(ndev, "%s: sh_eth_ring_init failed.\n",
2373 __func__);
2374 return ret;
2375 }
2376 ret = sh_eth_dev_init(ndev);
2377 if (ret < 0) {
2378 netdev_err(ndev, "%s: sh_eth_dev_init failed.\n",
2379 __func__);
2380 return ret;
2381 }
2382
2383 netif_device_attach(ndev);
2384 }
2385
2386 return 0;
2387}
2388
2389static void sh_eth_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2390{
2391 struct sh_eth_private *mdp = netdev_priv(ndev);
2392
2393 wol->supported = 0;
2394 wol->wolopts = 0;
2395
2396 if (mdp->cd->magic) {
2397 wol->supported = WAKE_MAGIC;
2398 wol->wolopts = mdp->wol_enabled ? WAKE_MAGIC : 0;
2399 }
2400}
2401
2402static int sh_eth_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
2403{
2404 struct sh_eth_private *mdp = netdev_priv(ndev);
2405
2406 if (!mdp->cd->magic || wol->wolopts & ~WAKE_MAGIC)
2407 return -EOPNOTSUPP;
2408
2409 mdp->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
2410
2411 device_set_wakeup_enable(&mdp->pdev->dev, mdp->wol_enabled);
2412
2413 return 0;
2414}
2415
2416static const struct ethtool_ops sh_eth_ethtool_ops = {
2417 .get_regs_len = sh_eth_get_regs_len,
2418 .get_regs = sh_eth_get_regs,
2419 .nway_reset = phy_ethtool_nway_reset,
2420 .get_msglevel = sh_eth_get_msglevel,
2421 .set_msglevel = sh_eth_set_msglevel,
2422 .get_link = ethtool_op_get_link,
2423 .get_strings = sh_eth_get_strings,
2424 .get_ethtool_stats = sh_eth_get_ethtool_stats,
2425 .get_sset_count = sh_eth_get_sset_count,
2426 .get_ringparam = sh_eth_get_ringparam,
2427 .set_ringparam = sh_eth_set_ringparam,
2428 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2429 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2430 .get_wol = sh_eth_get_wol,
2431 .set_wol = sh_eth_set_wol,
2432};
2433
2434/* network device open function */
2435static int sh_eth_open(struct net_device *ndev)
2436{
2437 struct sh_eth_private *mdp = netdev_priv(ndev);
2438 int ret;
2439
2440 pm_runtime_get_sync(&mdp->pdev->dev);
2441
2442 napi_enable(&mdp->napi);
2443
2444 ret = request_irq(ndev->irq, sh_eth_interrupt,
2445 mdp->cd->irq_flags, ndev->name, ndev);
2446 if (ret) {
2447 netdev_err(ndev, "Can not assign IRQ number\n");
2448 goto out_napi_off;
2449 }
2450
2451 /* Descriptor set */
2452 ret = sh_eth_ring_init(ndev);
2453 if (ret)
2454 goto out_free_irq;
2455
2456 /* device init */
2457 ret = sh_eth_dev_init(ndev);
2458 if (ret)
2459 goto out_free_irq;
2460
2461 /* PHY control start*/
2462 ret = sh_eth_phy_start(ndev);
2463 if (ret)
2464 goto out_free_irq;
2465
2466 netif_start_queue(ndev);
2467
2468 mdp->is_opened = 1;
2469
2470 return ret;
2471
2472out_free_irq:
2473 free_irq(ndev->irq, ndev);
2474out_napi_off:
2475 napi_disable(&mdp->napi);
2476 pm_runtime_put_sync(&mdp->pdev->dev);
2477 return ret;
2478}
2479
2480/* Timeout function */
2481static void sh_eth_tx_timeout(struct net_device *ndev)
2482{
2483 struct sh_eth_private *mdp = netdev_priv(ndev);
2484 struct sh_eth_rxdesc *rxdesc;
2485 int i;
2486
2487 netif_stop_queue(ndev);
2488
2489 netif_err(mdp, timer, ndev,
2490 "transmit timed out, status %8.8x, resetting...\n",
2491 sh_eth_read(ndev, EESR));
2492
2493 /* tx_errors count up */
2494 ndev->stats.tx_errors++;
2495
2496 /* Free all the skbuffs in the Rx queue. */
2497 for (i = 0; i < mdp->num_rx_ring; i++) {
2498 rxdesc = &mdp->rx_ring[i];
2499 rxdesc->status = cpu_to_le32(0);
2500 rxdesc->addr = cpu_to_le32(0xBADF00D0);
2501 dev_kfree_skb(mdp->rx_skbuff[i]);
2502 mdp->rx_skbuff[i] = NULL;
2503 }
2504 for (i = 0; i < mdp->num_tx_ring; i++) {
2505 dev_kfree_skb(mdp->tx_skbuff[i]);
2506 mdp->tx_skbuff[i] = NULL;
2507 }
2508
2509 /* device init */
2510 sh_eth_dev_init(ndev);
2511
2512 netif_start_queue(ndev);
2513}
2514
2515/* Packet transmit function */
2516static int sh_eth_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2517{
2518 struct sh_eth_private *mdp = netdev_priv(ndev);
2519 struct sh_eth_txdesc *txdesc;
2520 dma_addr_t dma_addr;
2521 u32 entry;
2522 unsigned long flags;
2523
2524 spin_lock_irqsave(&mdp->lock, flags);
2525 if ((mdp->cur_tx - mdp->dirty_tx) >= (mdp->num_tx_ring - 4)) {
2526 if (!sh_eth_tx_free(ndev, true)) {
2527 netif_warn(mdp, tx_queued, ndev, "TxFD exhausted.\n");
2528 netif_stop_queue(ndev);
2529 spin_unlock_irqrestore(&mdp->lock, flags);
2530 return NETDEV_TX_BUSY;
2531 }
2532 }
2533 spin_unlock_irqrestore(&mdp->lock, flags);
2534
2535 if (skb_put_padto(skb, ETH_ZLEN))
2536 return NETDEV_TX_OK;
2537
2538 entry = mdp->cur_tx % mdp->num_tx_ring;
2539 mdp->tx_skbuff[entry] = skb;
2540 txdesc = &mdp->tx_ring[entry];
2541 /* soft swap. */
2542 if (!mdp->cd->hw_swap)
2543 sh_eth_soft_swap(PTR_ALIGN(skb->data, 4), skb->len + 2);
2544 dma_addr = dma_map_single(&mdp->pdev->dev, skb->data, skb->len,
2545 DMA_TO_DEVICE);
2546 if (dma_mapping_error(&mdp->pdev->dev, dma_addr)) {
2547 kfree_skb(skb);
2548 return NETDEV_TX_OK;
2549 }
2550 txdesc->addr = cpu_to_le32(dma_addr);
2551 txdesc->len = cpu_to_le32(skb->len << 16);
2552
2553 dma_wmb(); /* TACT bit must be set after all the above writes */
2554 if (entry >= mdp->num_tx_ring - 1)
2555 txdesc->status |= cpu_to_le32(TD_TACT | TD_TDLE);
2556 else
2557 txdesc->status |= cpu_to_le32(TD_TACT);
2558
2559 mdp->cur_tx++;
2560
2561 if (!(sh_eth_read(ndev, EDTRR) & mdp->cd->edtrr_trns))
2562 sh_eth_write(ndev, mdp->cd->edtrr_trns, EDTRR);
2563
2564 return NETDEV_TX_OK;
2565}
2566
2567/* The statistics registers have write-clear behaviour, which means we
2568 * will lose any increment between the read and write. We mitigate
2569 * this by only clearing when we read a non-zero value, so we will
2570 * never falsely report a total of zero.
2571 */
2572static void
2573sh_eth_update_stat(struct net_device *ndev, unsigned long *stat, int reg)
2574{
2575 u32 delta = sh_eth_read(ndev, reg);
2576
2577 if (delta) {
2578 *stat += delta;
2579 sh_eth_write(ndev, 0, reg);
2580 }
2581}
2582
2583static struct net_device_stats *sh_eth_get_stats(struct net_device *ndev)
2584{
2585 struct sh_eth_private *mdp = netdev_priv(ndev);
2586
2587 if (mdp->cd->no_tx_cntrs)
2588 return &ndev->stats;
2589
2590 if (!mdp->is_opened)
2591 return &ndev->stats;
2592
2593 sh_eth_update_stat(ndev, &ndev->stats.tx_dropped, TROCR);
2594 sh_eth_update_stat(ndev, &ndev->stats.collisions, CDCR);
2595 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors, LCCR);
2596
2597 if (mdp->cd->cexcr) {
2598 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2599 CERCR);
2600 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2601 CEECR);
2602 } else {
2603 sh_eth_update_stat(ndev, &ndev->stats.tx_carrier_errors,
2604 CNDCR);
2605 }
2606
2607 return &ndev->stats;
2608}
2609
2610/* device close function */
2611static int sh_eth_close(struct net_device *ndev)
2612{
2613 struct sh_eth_private *mdp = netdev_priv(ndev);
2614
2615 netif_stop_queue(ndev);
2616
2617 /* Serialise with the interrupt handler and NAPI, then disable
2618 * interrupts. We have to clear the irq_enabled flag first to
2619 * ensure that interrupts won't be re-enabled.
2620 */
2621 mdp->irq_enabled = false;
2622 synchronize_irq(ndev->irq);
2623 napi_disable(&mdp->napi);
2624 sh_eth_write(ndev, 0x0000, EESIPR);
2625
2626 sh_eth_dev_exit(ndev);
2627
2628 /* PHY Disconnect */
2629 if (ndev->phydev) {
2630 phy_stop(ndev->phydev);
2631 phy_disconnect(ndev->phydev);
2632 }
2633
2634 free_irq(ndev->irq, ndev);
2635
2636 /* Free all the skbuffs in the Rx queue and the DMA buffer. */
2637 sh_eth_ring_free(ndev);
2638
2639 pm_runtime_put_sync(&mdp->pdev->dev);
2640
2641 mdp->is_opened = 0;
2642
2643 return 0;
2644}
2645
2646/* ioctl to device function */
2647static int sh_eth_do_ioctl(struct net_device *ndev, struct ifreq *rq, int cmd)
2648{
2649 struct phy_device *phydev = ndev->phydev;
2650
2651 if (!netif_running(ndev))
2652 return -EINVAL;
2653
2654 if (!phydev)
2655 return -ENODEV;
2656
2657 return phy_mii_ioctl(phydev, rq, cmd);
2658}
2659
2660static int sh_eth_change_mtu(struct net_device *ndev, int new_mtu)
2661{
2662 if (netif_running(ndev))
2663 return -EBUSY;
2664
2665 ndev->mtu = new_mtu;
2666 netdev_update_features(ndev);
2667
2668 return 0;
2669}
2670
2671/* For TSU_POSTn. Please refer to the manual about this (strange) bitfields */
2672static u32 sh_eth_tsu_get_post_mask(int entry)
2673{
2674 return 0x0f << (28 - ((entry % 8) * 4));
2675}
2676
2677static u32 sh_eth_tsu_get_post_bit(struct sh_eth_private *mdp, int entry)
2678{
2679 return (0x08 >> (mdp->port << 1)) << (28 - ((entry % 8) * 4));
2680}
2681
2682static void sh_eth_tsu_enable_cam_entry_post(struct net_device *ndev,
2683 int entry)
2684{
2685 struct sh_eth_private *mdp = netdev_priv(ndev);
2686 int reg = TSU_POST1 + entry / 8;
2687 u32 tmp;
2688
2689 tmp = sh_eth_tsu_read(mdp, reg);
2690 sh_eth_tsu_write(mdp, tmp | sh_eth_tsu_get_post_bit(mdp, entry), reg);
2691}
2692
2693static bool sh_eth_tsu_disable_cam_entry_post(struct net_device *ndev,
2694 int entry)
2695{
2696 struct sh_eth_private *mdp = netdev_priv(ndev);
2697 int reg = TSU_POST1 + entry / 8;
2698 u32 post_mask, ref_mask, tmp;
2699
2700 post_mask = sh_eth_tsu_get_post_mask(entry);
2701 ref_mask = sh_eth_tsu_get_post_bit(mdp, entry) & ~post_mask;
2702
2703 tmp = sh_eth_tsu_read(mdp, reg);
2704 sh_eth_tsu_write(mdp, tmp & ~post_mask, reg);
2705
2706 /* If other port enables, the function returns "true" */
2707 return tmp & ref_mask;
2708}
2709
2710static int sh_eth_tsu_busy(struct net_device *ndev)
2711{
2712 int timeout = SH_ETH_TSU_TIMEOUT_MS * 100;
2713 struct sh_eth_private *mdp = netdev_priv(ndev);
2714
2715 while ((sh_eth_tsu_read(mdp, TSU_ADSBSY) & TSU_ADSBSY_0)) {
2716 udelay(10);
2717 timeout--;
2718 if (timeout <= 0) {
2719 netdev_err(ndev, "%s: timeout\n", __func__);
2720 return -ETIMEDOUT;
2721 }
2722 }
2723
2724 return 0;
2725}
2726
2727static int sh_eth_tsu_write_entry(struct net_device *ndev, u16 offset,
2728 const u8 *addr)
2729{
2730 struct sh_eth_private *mdp = netdev_priv(ndev);
2731 u32 val;
2732
2733 val = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
2734 iowrite32(val, mdp->tsu_addr + offset);
2735 if (sh_eth_tsu_busy(ndev) < 0)
2736 return -EBUSY;
2737
2738 val = addr[4] << 8 | addr[5];
2739 iowrite32(val, mdp->tsu_addr + offset + 4);
2740 if (sh_eth_tsu_busy(ndev) < 0)
2741 return -EBUSY;
2742
2743 return 0;
2744}
2745
2746static void sh_eth_tsu_read_entry(struct net_device *ndev, u16 offset, u8 *addr)
2747{
2748 struct sh_eth_private *mdp = netdev_priv(ndev);
2749 u32 val;
2750
2751 val = ioread32(mdp->tsu_addr + offset);
2752 addr[0] = (val >> 24) & 0xff;
2753 addr[1] = (val >> 16) & 0xff;
2754 addr[2] = (val >> 8) & 0xff;
2755 addr[3] = val & 0xff;
2756 val = ioread32(mdp->tsu_addr + offset + 4);
2757 addr[4] = (val >> 8) & 0xff;
2758 addr[5] = val & 0xff;
2759}
2760
2761
2762static int sh_eth_tsu_find_entry(struct net_device *ndev, const u8 *addr)
2763{
2764 struct sh_eth_private *mdp = netdev_priv(ndev);
2765 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2766 int i;
2767 u8 c_addr[ETH_ALEN];
2768
2769 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2770 sh_eth_tsu_read_entry(ndev, reg_offset, c_addr);
2771 if (ether_addr_equal(addr, c_addr))
2772 return i;
2773 }
2774
2775 return -ENOENT;
2776}
2777
2778static int sh_eth_tsu_find_empty(struct net_device *ndev)
2779{
2780 u8 blank[ETH_ALEN];
2781 int entry;
2782
2783 memset(blank, 0, sizeof(blank));
2784 entry = sh_eth_tsu_find_entry(ndev, blank);
2785 return (entry < 0) ? -ENOMEM : entry;
2786}
2787
2788static int sh_eth_tsu_disable_cam_entry_table(struct net_device *ndev,
2789 int entry)
2790{
2791 struct sh_eth_private *mdp = netdev_priv(ndev);
2792 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2793 int ret;
2794 u8 blank[ETH_ALEN];
2795
2796 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) &
2797 ~(1 << (31 - entry)), TSU_TEN);
2798
2799 memset(blank, 0, sizeof(blank));
2800 ret = sh_eth_tsu_write_entry(ndev, reg_offset + entry * 8, blank);
2801 if (ret < 0)
2802 return ret;
2803 return 0;
2804}
2805
2806static int sh_eth_tsu_add_entry(struct net_device *ndev, const u8 *addr)
2807{
2808 struct sh_eth_private *mdp = netdev_priv(ndev);
2809 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2810 int i, ret;
2811
2812 if (!mdp->cd->tsu)
2813 return 0;
2814
2815 i = sh_eth_tsu_find_entry(ndev, addr);
2816 if (i < 0) {
2817 /* No entry found, create one */
2818 i = sh_eth_tsu_find_empty(ndev);
2819 if (i < 0)
2820 return -ENOMEM;
2821 ret = sh_eth_tsu_write_entry(ndev, reg_offset + i * 8, addr);
2822 if (ret < 0)
2823 return ret;
2824
2825 /* Enable the entry */
2826 sh_eth_tsu_write(mdp, sh_eth_tsu_read(mdp, TSU_TEN) |
2827 (1 << (31 - i)), TSU_TEN);
2828 }
2829
2830 /* Entry found or created, enable POST */
2831 sh_eth_tsu_enable_cam_entry_post(ndev, i);
2832
2833 return 0;
2834}
2835
2836static int sh_eth_tsu_del_entry(struct net_device *ndev, const u8 *addr)
2837{
2838 struct sh_eth_private *mdp = netdev_priv(ndev);
2839 int i, ret;
2840
2841 if (!mdp->cd->tsu)
2842 return 0;
2843
2844 i = sh_eth_tsu_find_entry(ndev, addr);
2845 if (i) {
2846 /* Entry found */
2847 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2848 goto done;
2849
2850 /* Disable the entry if both ports was disabled */
2851 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2852 if (ret < 0)
2853 return ret;
2854 }
2855done:
2856 return 0;
2857}
2858
2859static int sh_eth_tsu_purge_all(struct net_device *ndev)
2860{
2861 struct sh_eth_private *mdp = netdev_priv(ndev);
2862 int i, ret;
2863
2864 if (!mdp->cd->tsu)
2865 return 0;
2866
2867 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++) {
2868 if (sh_eth_tsu_disable_cam_entry_post(ndev, i))
2869 continue;
2870
2871 /* Disable the entry if both ports was disabled */
2872 ret = sh_eth_tsu_disable_cam_entry_table(ndev, i);
2873 if (ret < 0)
2874 return ret;
2875 }
2876
2877 return 0;
2878}
2879
2880static void sh_eth_tsu_purge_mcast(struct net_device *ndev)
2881{
2882 struct sh_eth_private *mdp = netdev_priv(ndev);
2883 u16 reg_offset = sh_eth_tsu_get_offset(mdp, TSU_ADRH0);
2884 u8 addr[ETH_ALEN];
2885 int i;
2886
2887 if (!mdp->cd->tsu)
2888 return;
2889
2890 for (i = 0; i < SH_ETH_TSU_CAM_ENTRIES; i++, reg_offset += 8) {
2891 sh_eth_tsu_read_entry(ndev, reg_offset, addr);
2892 if (is_multicast_ether_addr(addr))
2893 sh_eth_tsu_del_entry(ndev, addr);
2894 }
2895}
2896
2897/* Update promiscuous flag and multicast filter */
2898static void sh_eth_set_rx_mode(struct net_device *ndev)
2899{
2900 struct sh_eth_private *mdp = netdev_priv(ndev);
2901 u32 ecmr_bits;
2902 int mcast_all = 0;
2903 unsigned long flags;
2904
2905 spin_lock_irqsave(&mdp->lock, flags);
2906 /* Initial condition is MCT = 1, PRM = 0.
2907 * Depending on ndev->flags, set PRM or clear MCT
2908 */
2909 ecmr_bits = sh_eth_read(ndev, ECMR) & ~ECMR_PRM;
2910 if (mdp->cd->tsu)
2911 ecmr_bits |= ECMR_MCT;
2912
2913 if (!(ndev->flags & IFF_MULTICAST)) {
2914 sh_eth_tsu_purge_mcast(ndev);
2915 mcast_all = 1;
2916 }
2917 if (ndev->flags & IFF_ALLMULTI) {
2918 sh_eth_tsu_purge_mcast(ndev);
2919 ecmr_bits &= ~ECMR_MCT;
2920 mcast_all = 1;
2921 }
2922
2923 if (ndev->flags & IFF_PROMISC) {
2924 sh_eth_tsu_purge_all(ndev);
2925 ecmr_bits = (ecmr_bits & ~ECMR_MCT) | ECMR_PRM;
2926 } else if (mdp->cd->tsu) {
2927 struct netdev_hw_addr *ha;
2928 netdev_for_each_mc_addr(ha, ndev) {
2929 if (mcast_all && is_multicast_ether_addr(ha->addr))
2930 continue;
2931
2932 if (sh_eth_tsu_add_entry(ndev, ha->addr) < 0) {
2933 if (!mcast_all) {
2934 sh_eth_tsu_purge_mcast(ndev);
2935 ecmr_bits &= ~ECMR_MCT;
2936 mcast_all = 1;
2937 }
2938 }
2939 }
2940 }
2941
2942 /* update the ethernet mode */
2943 sh_eth_write(ndev, ecmr_bits, ECMR);
2944
2945 spin_unlock_irqrestore(&mdp->lock, flags);
2946}
2947
2948static void sh_eth_set_rx_csum(struct net_device *ndev, bool enable)
2949{
2950 struct sh_eth_private *mdp = netdev_priv(ndev);
2951 unsigned long flags;
2952
2953 spin_lock_irqsave(&mdp->lock, flags);
2954
2955 /* Disable TX and RX */
2956 sh_eth_rcv_snd_disable(ndev);
2957
2958 /* Modify RX Checksum setting */
2959 sh_eth_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
2960
2961 /* Enable TX and RX */
2962 sh_eth_rcv_snd_enable(ndev);
2963
2964 spin_unlock_irqrestore(&mdp->lock, flags);
2965}
2966
2967static int sh_eth_set_features(struct net_device *ndev,
2968 netdev_features_t features)
2969{
2970 netdev_features_t changed = ndev->features ^ features;
2971 struct sh_eth_private *mdp = netdev_priv(ndev);
2972
2973 if (changed & NETIF_F_RXCSUM && mdp->cd->rx_csum)
2974 sh_eth_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
2975
2976 ndev->features = features;
2977
2978 return 0;
2979}
2980
2981static int sh_eth_get_vtag_index(struct sh_eth_private *mdp)
2982{
2983 if (!mdp->port)
2984 return TSU_VTAG0;
2985 else
2986 return TSU_VTAG1;
2987}
2988
2989static int sh_eth_vlan_rx_add_vid(struct net_device *ndev,
2990 __be16 proto, u16 vid)
2991{
2992 struct sh_eth_private *mdp = netdev_priv(ndev);
2993 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
2994
2995 if (unlikely(!mdp->cd->tsu))
2996 return -EPERM;
2997
2998 /* No filtering if vid = 0 */
2999 if (!vid)
3000 return 0;
3001
3002 mdp->vlan_num_ids++;
3003
3004 /* The controller has one VLAN tag HW filter. So, if the filter is
3005 * already enabled, the driver disables it and the filte
3006 */
3007 if (mdp->vlan_num_ids > 1) {
3008 /* disable VLAN filter */
3009 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
3010 return 0;
3011 }
3012
3013 sh_eth_tsu_write(mdp, TSU_VTAG_ENABLE | (vid & TSU_VTAG_VID_MASK),
3014 vtag_reg_index);
3015
3016 return 0;
3017}
3018
3019static int sh_eth_vlan_rx_kill_vid(struct net_device *ndev,
3020 __be16 proto, u16 vid)
3021{
3022 struct sh_eth_private *mdp = netdev_priv(ndev);
3023 int vtag_reg_index = sh_eth_get_vtag_index(mdp);
3024
3025 if (unlikely(!mdp->cd->tsu))
3026 return -EPERM;
3027
3028 /* No filtering if vid = 0 */
3029 if (!vid)
3030 return 0;
3031
3032 mdp->vlan_num_ids--;
3033 sh_eth_tsu_write(mdp, 0, vtag_reg_index);
3034
3035 return 0;
3036}
3037
3038/* SuperH's TSU register init function */
3039static void sh_eth_tsu_init(struct sh_eth_private *mdp)
3040{
3041 if (!mdp->cd->dual_port) {
3042 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3043 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL,
3044 TSU_FWSLC); /* Enable POST registers */
3045 return;
3046 }
3047
3048 sh_eth_tsu_write(mdp, 0, TSU_FWEN0); /* Disable forward(0->1) */
3049 sh_eth_tsu_write(mdp, 0, TSU_FWEN1); /* Disable forward(1->0) */
3050 sh_eth_tsu_write(mdp, 0, TSU_FCM); /* forward fifo 3k-3k */
3051 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL0);
3052 sh_eth_tsu_write(mdp, 0xc, TSU_BSYSL1);
3053 sh_eth_tsu_write(mdp, 0, TSU_PRISL0);
3054 sh_eth_tsu_write(mdp, 0, TSU_PRISL1);
3055 sh_eth_tsu_write(mdp, 0, TSU_FWSL0);
3056 sh_eth_tsu_write(mdp, 0, TSU_FWSL1);
3057 sh_eth_tsu_write(mdp, TSU_FWSLC_POSTENU | TSU_FWSLC_POSTENL, TSU_FWSLC);
3058 sh_eth_tsu_write(mdp, 0, TSU_QTAGM0); /* Disable QTAG(0->1) */
3059 sh_eth_tsu_write(mdp, 0, TSU_QTAGM1); /* Disable QTAG(1->0) */
3060 sh_eth_tsu_write(mdp, 0, TSU_FWSR); /* all interrupt status clear */
3061 sh_eth_tsu_write(mdp, 0, TSU_FWINMK); /* Disable all interrupt */
3062 sh_eth_tsu_write(mdp, 0, TSU_TEN); /* Disable all CAM entry */
3063 sh_eth_tsu_write(mdp, 0, TSU_POST1); /* Disable CAM entry [ 0- 7] */
3064 sh_eth_tsu_write(mdp, 0, TSU_POST2); /* Disable CAM entry [ 8-15] */
3065 sh_eth_tsu_write(mdp, 0, TSU_POST3); /* Disable CAM entry [16-23] */
3066 sh_eth_tsu_write(mdp, 0, TSU_POST4); /* Disable CAM entry [24-31] */
3067}
3068
3069/* MDIO bus release function */
3070static int sh_mdio_release(struct sh_eth_private *mdp)
3071{
3072 /* unregister mdio bus */
3073 mdiobus_unregister(mdp->mii_bus);
3074
3075 /* free bitbang info */
3076 free_mdio_bitbang(mdp->mii_bus);
3077
3078 return 0;
3079}
3080
3081/* MDIO bus init function */
3082static int sh_mdio_init(struct sh_eth_private *mdp,
3083 struct sh_eth_plat_data *pd)
3084{
3085 int ret;
3086 struct bb_info *bitbang;
3087 struct platform_device *pdev = mdp->pdev;
3088 struct device *dev = &mdp->pdev->dev;
3089
3090 /* create bit control struct for PHY */
3091 bitbang = devm_kzalloc(dev, sizeof(struct bb_info), GFP_KERNEL);
3092 if (!bitbang)
3093 return -ENOMEM;
3094
3095 /* bitbang init */
3096 bitbang->addr = mdp->addr + mdp->reg_offset[PIR];
3097 bitbang->set_gate = pd->set_mdio_gate;
3098 bitbang->ctrl.ops = &bb_ops;
3099
3100 /* MII controller setting */
3101 mdp->mii_bus = alloc_mdio_bitbang(&bitbang->ctrl);
3102 if (!mdp->mii_bus)
3103 return -ENOMEM;
3104
3105 /* Hook up MII support for ethtool */
3106 mdp->mii_bus->name = "sh_mii";
3107 mdp->mii_bus->parent = dev;
3108 snprintf(mdp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
3109 pdev->name, pdev->id);
3110
3111 /* register MDIO bus */
3112 if (pd->phy_irq > 0)
3113 mdp->mii_bus->irq[pd->phy] = pd->phy_irq;
3114
3115 ret = of_mdiobus_register(mdp->mii_bus, dev->of_node);
3116 if (ret)
3117 goto out_free_bus;
3118
3119 return 0;
3120
3121out_free_bus:
3122 free_mdio_bitbang(mdp->mii_bus);
3123 return ret;
3124}
3125
3126static const u16 *sh_eth_get_register_offset(int register_type)
3127{
3128 const u16 *reg_offset = NULL;
3129
3130 switch (register_type) {
3131 case SH_ETH_REG_GIGABIT:
3132 reg_offset = sh_eth_offset_gigabit;
3133 break;
3134 case SH_ETH_REG_FAST_RZ:
3135 reg_offset = sh_eth_offset_fast_rz;
3136 break;
3137 case SH_ETH_REG_FAST_RCAR:
3138 reg_offset = sh_eth_offset_fast_rcar;
3139 break;
3140 case SH_ETH_REG_FAST_SH4:
3141 reg_offset = sh_eth_offset_fast_sh4;
3142 break;
3143 case SH_ETH_REG_FAST_SH3_SH2:
3144 reg_offset = sh_eth_offset_fast_sh3_sh2;
3145 break;
3146 }
3147
3148 return reg_offset;
3149}
3150
3151static const struct net_device_ops sh_eth_netdev_ops = {
3152 .ndo_open = sh_eth_open,
3153 .ndo_stop = sh_eth_close,
3154 .ndo_start_xmit = sh_eth_start_xmit,
3155 .ndo_get_stats = sh_eth_get_stats,
3156 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3157 .ndo_tx_timeout = sh_eth_tx_timeout,
3158 .ndo_do_ioctl = sh_eth_do_ioctl,
3159 .ndo_change_mtu = sh_eth_change_mtu,
3160 .ndo_validate_addr = eth_validate_addr,
3161 .ndo_set_mac_address = eth_mac_addr,
3162 .ndo_set_features = sh_eth_set_features,
3163};
3164
3165static const struct net_device_ops sh_eth_netdev_ops_tsu = {
3166 .ndo_open = sh_eth_open,
3167 .ndo_stop = sh_eth_close,
3168 .ndo_start_xmit = sh_eth_start_xmit,
3169 .ndo_get_stats = sh_eth_get_stats,
3170 .ndo_set_rx_mode = sh_eth_set_rx_mode,
3171 .ndo_vlan_rx_add_vid = sh_eth_vlan_rx_add_vid,
3172 .ndo_vlan_rx_kill_vid = sh_eth_vlan_rx_kill_vid,
3173 .ndo_tx_timeout = sh_eth_tx_timeout,
3174 .ndo_do_ioctl = sh_eth_do_ioctl,
3175 .ndo_change_mtu = sh_eth_change_mtu,
3176 .ndo_validate_addr = eth_validate_addr,
3177 .ndo_set_mac_address = eth_mac_addr,
3178 .ndo_set_features = sh_eth_set_features,
3179};
3180
3181#ifdef CONFIG_OF
3182static struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3183{
3184 struct device_node *np = dev->of_node;
3185 struct sh_eth_plat_data *pdata;
3186 const char *mac_addr;
3187 int ret;
3188
3189 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
3190 if (!pdata)
3191 return NULL;
3192
3193 ret = of_get_phy_mode(np);
3194 if (ret < 0)
3195 return NULL;
3196 pdata->phy_interface = ret;
3197
3198 mac_addr = of_get_mac_address(np);
3199 if (!IS_ERR(mac_addr))
3200 ether_addr_copy(pdata->mac_addr, mac_addr);
3201
3202 pdata->no_ether_link =
3203 of_property_read_bool(np, "renesas,no-ether-link");
3204 pdata->ether_link_active_low =
3205 of_property_read_bool(np, "renesas,ether-link-active-low");
3206
3207 return pdata;
3208}
3209
3210static const struct of_device_id sh_eth_match_table[] = {
3211 { .compatible = "renesas,gether-r8a7740", .data = &r8a7740_data },
3212 { .compatible = "renesas,ether-r8a7743", .data = &rcar_gen2_data },
3213 { .compatible = "renesas,ether-r8a7745", .data = &rcar_gen2_data },
3214 { .compatible = "renesas,ether-r8a7778", .data = &rcar_gen1_data },
3215 { .compatible = "renesas,ether-r8a7779", .data = &rcar_gen1_data },
3216 { .compatible = "renesas,ether-r8a7790", .data = &rcar_gen2_data },
3217 { .compatible = "renesas,ether-r8a7791", .data = &rcar_gen2_data },
3218 { .compatible = "renesas,ether-r8a7793", .data = &rcar_gen2_data },
3219 { .compatible = "renesas,ether-r8a7794", .data = &rcar_gen2_data },
3220 { .compatible = "renesas,gether-r8a77980", .data = &r8a77980_data },
3221 { .compatible = "renesas,ether-r7s72100", .data = &r7s72100_data },
3222 { .compatible = "renesas,ether-r7s9210", .data = &r7s9210_data },
3223 { .compatible = "renesas,rcar-gen1-ether", .data = &rcar_gen1_data },
3224 { .compatible = "renesas,rcar-gen2-ether", .data = &rcar_gen2_data },
3225 { }
3226};
3227MODULE_DEVICE_TABLE(of, sh_eth_match_table);
3228#else
3229static inline struct sh_eth_plat_data *sh_eth_parse_dt(struct device *dev)
3230{
3231 return NULL;
3232}
3233#endif
3234
3235static int sh_eth_drv_probe(struct platform_device *pdev)
3236{
3237 struct resource *res;
3238 struct sh_eth_plat_data *pd = dev_get_platdata(&pdev->dev);
3239 const struct platform_device_id *id = platform_get_device_id(pdev);
3240 struct sh_eth_private *mdp;
3241 struct net_device *ndev;
3242 int ret;
3243
3244 /* get base addr */
3245 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3246
3247 ndev = alloc_etherdev(sizeof(struct sh_eth_private));
3248 if (!ndev)
3249 return -ENOMEM;
3250
3251 pm_runtime_enable(&pdev->dev);
3252 pm_runtime_get_sync(&pdev->dev);
3253
3254 ret = platform_get_irq(pdev, 0);
3255 if (ret < 0)
3256 goto out_release;
3257 ndev->irq = ret;
3258
3259 SET_NETDEV_DEV(ndev, &pdev->dev);
3260
3261 mdp = netdev_priv(ndev);
3262 mdp->num_tx_ring = TX_RING_SIZE;
3263 mdp->num_rx_ring = RX_RING_SIZE;
3264 mdp->addr = devm_ioremap_resource(&pdev->dev, res);
3265 if (IS_ERR(mdp->addr)) {
3266 ret = PTR_ERR(mdp->addr);
3267 goto out_release;
3268 }
3269
3270 ndev->base_addr = res->start;
3271
3272 spin_lock_init(&mdp->lock);
3273 mdp->pdev = pdev;
3274
3275 if (pdev->dev.of_node)
3276 pd = sh_eth_parse_dt(&pdev->dev);
3277 if (!pd) {
3278 dev_err(&pdev->dev, "no platform data\n");
3279 ret = -EINVAL;
3280 goto out_release;
3281 }
3282
3283 /* get PHY ID */
3284 mdp->phy_id = pd->phy;
3285 mdp->phy_interface = pd->phy_interface;
3286 mdp->no_ether_link = pd->no_ether_link;
3287 mdp->ether_link_active_low = pd->ether_link_active_low;
3288
3289 /* set cpu data */
3290 if (id)
3291 mdp->cd = (struct sh_eth_cpu_data *)id->driver_data;
3292 else
3293 mdp->cd = (struct sh_eth_cpu_data *)of_device_get_match_data(&pdev->dev);
3294
3295 mdp->reg_offset = sh_eth_get_register_offset(mdp->cd->register_type);
3296 if (!mdp->reg_offset) {
3297 dev_err(&pdev->dev, "Unknown register type (%d)\n",
3298 mdp->cd->register_type);
3299 ret = -EINVAL;
3300 goto out_release;
3301 }
3302 sh_eth_set_default_cpu_data(mdp->cd);
3303
3304 /* User's manual states max MTU should be 2048 but due to the
3305 * alignment calculations in sh_eth_ring_init() the practical
3306 * MTU is a bit less. Maybe this can be optimized some more.
3307 */
3308 ndev->max_mtu = 2000 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
3309 ndev->min_mtu = ETH_MIN_MTU;
3310
3311 if (mdp->cd->rx_csum) {
3312 ndev->features = NETIF_F_RXCSUM;
3313 ndev->hw_features = NETIF_F_RXCSUM;
3314 }
3315
3316 /* set function */
3317 if (mdp->cd->tsu)
3318 ndev->netdev_ops = &sh_eth_netdev_ops_tsu;
3319 else
3320 ndev->netdev_ops = &sh_eth_netdev_ops;
3321 ndev->ethtool_ops = &sh_eth_ethtool_ops;
3322 ndev->watchdog_timeo = TX_TIMEOUT;
3323
3324 /* debug message level */
3325 mdp->msg_enable = SH_ETH_DEF_MSG_ENABLE;
3326
3327 /* read and set MAC address */
3328 read_mac_address(ndev, pd->mac_addr);
3329 if (!is_valid_ether_addr(ndev->dev_addr)) {
3330 dev_warn(&pdev->dev,
3331 "no valid MAC address supplied, using a random one.\n");
3332 eth_hw_addr_random(ndev);
3333 }
3334
3335 if (mdp->cd->tsu) {
3336 int port = pdev->id < 0 ? 0 : pdev->id % 2;
3337 struct resource *rtsu;
3338
3339 rtsu = platform_get_resource(pdev, IORESOURCE_MEM, 1);
3340 if (!rtsu) {
3341 dev_err(&pdev->dev, "no TSU resource\n");
3342 ret = -ENODEV;
3343 goto out_release;
3344 }
3345 /* We can only request the TSU region for the first port
3346 * of the two sharing this TSU for the probe to succeed...
3347 */
3348 if (port == 0 &&
3349 !devm_request_mem_region(&pdev->dev, rtsu->start,
3350 resource_size(rtsu),
3351 dev_name(&pdev->dev))) {
3352 dev_err(&pdev->dev, "can't request TSU resource.\n");
3353 ret = -EBUSY;
3354 goto out_release;
3355 }
3356 /* ioremap the TSU registers */
3357 mdp->tsu_addr = devm_ioremap(&pdev->dev, rtsu->start,
3358 resource_size(rtsu));
3359 if (!mdp->tsu_addr) {
3360 dev_err(&pdev->dev, "TSU region ioremap() failed.\n");
3361 ret = -ENOMEM;
3362 goto out_release;
3363 }
3364 mdp->port = port;
3365 ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
3366
3367 /* Need to init only the first port of the two sharing a TSU */
3368 if (port == 0) {
3369 if (mdp->cd->chip_reset)
3370 mdp->cd->chip_reset(ndev);
3371
3372 /* TSU init (Init only)*/
3373 sh_eth_tsu_init(mdp);
3374 }
3375 }
3376
3377 if (mdp->cd->rmiimode)
3378 sh_eth_write(ndev, 0x1, RMIIMODE);
3379
3380 /* MDIO bus init */
3381 ret = sh_mdio_init(mdp, pd);
3382 if (ret) {
3383 if (ret != -EPROBE_DEFER)
3384 dev_err(&pdev->dev, "MDIO init failed: %d\n", ret);
3385 goto out_release;
3386 }
3387
3388 netif_napi_add(ndev, &mdp->napi, sh_eth_poll, 64);
3389
3390 /* network device register */
3391 ret = register_netdev(ndev);
3392 if (ret)
3393 goto out_napi_del;
3394
3395 if (mdp->cd->magic)
3396 device_set_wakeup_capable(&pdev->dev, 1);
3397
3398 /* print device information */
3399 netdev_info(ndev, "Base address at 0x%x, %pM, IRQ %d.\n",
3400 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
3401
3402 pm_runtime_put(&pdev->dev);
3403 platform_set_drvdata(pdev, ndev);
3404
3405 return ret;
3406
3407out_napi_del:
3408 netif_napi_del(&mdp->napi);
3409 sh_mdio_release(mdp);
3410
3411out_release:
3412 /* net_dev free */
3413 free_netdev(ndev);
3414
3415 pm_runtime_put(&pdev->dev);
3416 pm_runtime_disable(&pdev->dev);
3417 return ret;
3418}
3419
3420static int sh_eth_drv_remove(struct platform_device *pdev)
3421{
3422 struct net_device *ndev = platform_get_drvdata(pdev);
3423 struct sh_eth_private *mdp = netdev_priv(ndev);
3424
3425 unregister_netdev(ndev);
3426 netif_napi_del(&mdp->napi);
3427 sh_mdio_release(mdp);
3428 pm_runtime_disable(&pdev->dev);
3429 free_netdev(ndev);
3430
3431 return 0;
3432}
3433
3434#ifdef CONFIG_PM
3435#ifdef CONFIG_PM_SLEEP
3436static int sh_eth_wol_setup(struct net_device *ndev)
3437{
3438 struct sh_eth_private *mdp = netdev_priv(ndev);
3439
3440 /* Only allow ECI interrupts */
3441 synchronize_irq(ndev->irq);
3442 napi_disable(&mdp->napi);
3443 sh_eth_write(ndev, EESIPR_ECIIP, EESIPR);
3444
3445 /* Enable MagicPacket */
3446 sh_eth_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
3447
3448 return enable_irq_wake(ndev->irq);
3449}
3450
3451static int sh_eth_wol_restore(struct net_device *ndev)
3452{
3453 struct sh_eth_private *mdp = netdev_priv(ndev);
3454 int ret;
3455
3456 napi_enable(&mdp->napi);
3457
3458 /* Disable MagicPacket */
3459 sh_eth_modify(ndev, ECMR, ECMR_MPDE, 0);
3460
3461 /* The device needs to be reset to restore MagicPacket logic
3462 * for next wakeup. If we close and open the device it will
3463 * both be reset and all registers restored. This is what
3464 * happens during suspend and resume without WoL enabled.
3465 */
3466 ret = sh_eth_close(ndev);
3467 if (ret < 0)
3468 return ret;
3469 ret = sh_eth_open(ndev);
3470 if (ret < 0)
3471 return ret;
3472
3473 return disable_irq_wake(ndev->irq);
3474}
3475
3476static int sh_eth_suspend(struct device *dev)
3477{
3478 struct net_device *ndev = dev_get_drvdata(dev);
3479 struct sh_eth_private *mdp = netdev_priv(ndev);
3480 int ret = 0;
3481
3482 if (!netif_running(ndev))
3483 return 0;
3484
3485 netif_device_detach(ndev);
3486
3487 if (mdp->wol_enabled)
3488 ret = sh_eth_wol_setup(ndev);
3489 else
3490 ret = sh_eth_close(ndev);
3491
3492 return ret;
3493}
3494
3495static int sh_eth_resume(struct device *dev)
3496{
3497 struct net_device *ndev = dev_get_drvdata(dev);
3498 struct sh_eth_private *mdp = netdev_priv(ndev);
3499 int ret = 0;
3500
3501 if (!netif_running(ndev))
3502 return 0;
3503
3504 if (mdp->wol_enabled)
3505 ret = sh_eth_wol_restore(ndev);
3506 else
3507 ret = sh_eth_open(ndev);
3508
3509 if (ret < 0)
3510 return ret;
3511
3512 netif_device_attach(ndev);
3513
3514 return ret;
3515}
3516#endif
3517
3518static int sh_eth_runtime_nop(struct device *dev)
3519{
3520 /* Runtime PM callback shared between ->runtime_suspend()
3521 * and ->runtime_resume(). Simply returns success.
3522 *
3523 * This driver re-initializes all registers after
3524 * pm_runtime_get_sync() anyway so there is no need
3525 * to save and restore registers here.
3526 */
3527 return 0;
3528}
3529
3530static const struct dev_pm_ops sh_eth_dev_pm_ops = {
3531 SET_SYSTEM_SLEEP_PM_OPS(sh_eth_suspend, sh_eth_resume)
3532 SET_RUNTIME_PM_OPS(sh_eth_runtime_nop, sh_eth_runtime_nop, NULL)
3533};
3534#define SH_ETH_PM_OPS (&sh_eth_dev_pm_ops)
3535#else
3536#define SH_ETH_PM_OPS NULL
3537#endif
3538
3539static const struct platform_device_id sh_eth_id_table[] = {
3540 { "sh7619-ether", (kernel_ulong_t)&sh7619_data },
3541 { "sh771x-ether", (kernel_ulong_t)&sh771x_data },
3542 { "sh7724-ether", (kernel_ulong_t)&sh7724_data },
3543 { "sh7734-gether", (kernel_ulong_t)&sh7734_data },
3544 { "sh7757-ether", (kernel_ulong_t)&sh7757_data },
3545 { "sh7757-gether", (kernel_ulong_t)&sh7757_data_giga },
3546 { "sh7763-gether", (kernel_ulong_t)&sh7763_data },
3547 { }
3548};
3549MODULE_DEVICE_TABLE(platform, sh_eth_id_table);
3550
3551static struct platform_driver sh_eth_driver = {
3552 .probe = sh_eth_drv_probe,
3553 .remove = sh_eth_drv_remove,
3554 .id_table = sh_eth_id_table,
3555 .driver = {
3556 .name = CARDNAME,
3557 .pm = SH_ETH_PM_OPS,
3558 .of_match_table = of_match_ptr(sh_eth_match_table),
3559 },
3560};
3561
3562module_platform_driver(sh_eth_driver);
3563
3564MODULE_AUTHOR("Nobuhiro Iwamatsu, Yoshihiro Shimoda");
3565MODULE_DESCRIPTION("Renesas SuperH Ethernet driver");
3566MODULE_LICENSE("GPL v2");