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1/*
2 * Amlogic SD/eMMC driver for the GX/S905 family SoCs
3 *
4 * Copyright (c) 2016 BayLibre, SAS.
5 * Author: Kevin Hilman <khilman@baylibre.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 * The full GNU General Public License is included in this distribution
19 * in the file called COPYING.
20 */
21#include <linux/kernel.h>
22#include <linux/module.h>
23#include <linux/init.h>
24#include <linux/device.h>
25#include <linux/of_device.h>
26#include <linux/platform_device.h>
27#include <linux/ioport.h>
28#include <linux/spinlock.h>
29#include <linux/dma-mapping.h>
30#include <linux/mmc/host.h>
31#include <linux/mmc/mmc.h>
32#include <linux/mmc/sdio.h>
33#include <linux/mmc/slot-gpio.h>
34#include <linux/io.h>
35#include <linux/clk.h>
36#include <linux/clk-provider.h>
37#include <linux/regulator/consumer.h>
38#include <linux/interrupt.h>
39#include <linux/bitfield.h>
40#include <linux/pinctrl/consumer.h>
41
42#define DRIVER_NAME "meson-gx-mmc"
43
44#define SD_EMMC_CLOCK 0x0
45#define CLK_DIV_MASK GENMASK(5, 0)
46#define CLK_SRC_MASK GENMASK(7, 6)
47#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
48#define CLK_TX_PHASE_MASK GENMASK(11, 10)
49#define CLK_RX_PHASE_MASK GENMASK(13, 12)
50#define CLK_TX_DELAY_MASK GENMASK(19, 16)
51#define CLK_RX_DELAY_MASK GENMASK(23, 20)
52#define CLK_DELAY_STEP_PS 200
53#define CLK_PHASE_STEP 30
54#define CLK_PHASE_POINT_NUM (360 / CLK_PHASE_STEP)
55#define CLK_ALWAYS_ON BIT(24)
56
57#define SD_EMMC_DELAY 0x4
58#define SD_EMMC_ADJUST 0x8
59#define SD_EMMC_CALOUT 0x10
60#define SD_EMMC_START 0x40
61#define START_DESC_INIT BIT(0)
62#define START_DESC_BUSY BIT(1)
63#define START_DESC_ADDR_MASK GENMASK(31, 2)
64
65#define SD_EMMC_CFG 0x44
66#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
67#define CFG_BUS_WIDTH_1 0x0
68#define CFG_BUS_WIDTH_4 0x1
69#define CFG_BUS_WIDTH_8 0x2
70#define CFG_DDR BIT(2)
71#define CFG_BLK_LEN_MASK GENMASK(7, 4)
72#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
73#define CFG_RC_CC_MASK GENMASK(15, 12)
74#define CFG_STOP_CLOCK BIT(22)
75#define CFG_CLK_ALWAYS_ON BIT(18)
76#define CFG_CHK_DS BIT(20)
77#define CFG_AUTO_CLK BIT(23)
78
79#define SD_EMMC_STATUS 0x48
80#define STATUS_BUSY BIT(31)
81#define STATUS_DATI GENMASK(23, 16)
82
83#define SD_EMMC_IRQ_EN 0x4c
84#define IRQ_RXD_ERR_MASK GENMASK(7, 0)
85#define IRQ_TXD_ERR BIT(8)
86#define IRQ_DESC_ERR BIT(9)
87#define IRQ_RESP_ERR BIT(10)
88#define IRQ_CRC_ERR \
89 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
90#define IRQ_RESP_TIMEOUT BIT(11)
91#define IRQ_DESC_TIMEOUT BIT(12)
92#define IRQ_TIMEOUTS \
93 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
94#define IRQ_END_OF_CHAIN BIT(13)
95#define IRQ_RESP_STATUS BIT(14)
96#define IRQ_SDIO BIT(15)
97#define IRQ_EN_MASK \
98 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
99 IRQ_SDIO)
100
101#define SD_EMMC_CMD_CFG 0x50
102#define SD_EMMC_CMD_ARG 0x54
103#define SD_EMMC_CMD_DAT 0x58
104#define SD_EMMC_CMD_RSP 0x5c
105#define SD_EMMC_CMD_RSP1 0x60
106#define SD_EMMC_CMD_RSP2 0x64
107#define SD_EMMC_CMD_RSP3 0x68
108
109#define SD_EMMC_RXD 0x94
110#define SD_EMMC_TXD 0x94
111#define SD_EMMC_LAST_REG SD_EMMC_TXD
112
113#define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
114#define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
115#define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
116#define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
117#define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
118#define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
119
120#define SD_EMMC_PRE_REQ_DONE BIT(0)
121#define SD_EMMC_DESC_CHAIN_MODE BIT(1)
122
123#define MUX_CLK_NUM_PARENTS 2
124
125struct sd_emmc_desc {
126 u32 cmd_cfg;
127 u32 cmd_arg;
128 u32 cmd_data;
129 u32 cmd_resp;
130};
131
132struct meson_host {
133 struct device *dev;
134 struct mmc_host *mmc;
135 struct mmc_command *cmd;
136
137 spinlock_t lock;
138 void __iomem *regs;
139 struct clk *core_clk;
140 struct clk *mmc_clk;
141 struct clk *rx_clk;
142 struct clk *tx_clk;
143 unsigned long req_rate;
144
145 struct pinctrl *pinctrl;
146 struct pinctrl_state *pins_default;
147 struct pinctrl_state *pins_clk_gate;
148
149 unsigned int bounce_buf_size;
150 void *bounce_buf;
151 dma_addr_t bounce_dma_addr;
152 struct sd_emmc_desc *descs;
153 dma_addr_t descs_dma_addr;
154
155 bool vqmmc_enabled;
156};
157
158#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
159#define CMD_CFG_BLOCK_MODE BIT(9)
160#define CMD_CFG_R1B BIT(10)
161#define CMD_CFG_END_OF_CHAIN BIT(11)
162#define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
163#define CMD_CFG_NO_RESP BIT(16)
164#define CMD_CFG_NO_CMD BIT(17)
165#define CMD_CFG_DATA_IO BIT(18)
166#define CMD_CFG_DATA_WR BIT(19)
167#define CMD_CFG_RESP_NOCRC BIT(20)
168#define CMD_CFG_RESP_128 BIT(21)
169#define CMD_CFG_RESP_NUM BIT(22)
170#define CMD_CFG_DATA_NUM BIT(23)
171#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
172#define CMD_CFG_ERROR BIT(30)
173#define CMD_CFG_OWNER BIT(31)
174
175#define CMD_DATA_MASK GENMASK(31, 2)
176#define CMD_DATA_BIG_ENDIAN BIT(1)
177#define CMD_DATA_SRAM BIT(0)
178#define CMD_RESP_MASK GENMASK(31, 1)
179#define CMD_RESP_SRAM BIT(0)
180
181struct meson_mmc_phase {
182 struct clk_hw hw;
183 void __iomem *reg;
184 unsigned long phase_mask;
185 unsigned long delay_mask;
186 unsigned int delay_step_ps;
187};
188
189#define to_meson_mmc_phase(_hw) container_of(_hw, struct meson_mmc_phase, hw)
190
191static int meson_mmc_clk_get_phase(struct clk_hw *hw)
192{
193 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
194 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
195 unsigned long period_ps, p, d;
196 int degrees;
197 u32 val;
198
199 val = readl(mmc->reg);
200 p = (val & mmc->phase_mask) >> __ffs(mmc->phase_mask);
201 degrees = p * 360 / phase_num;
202
203 if (mmc->delay_mask) {
204 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
205 clk_get_rate(hw->clk));
206 d = (val & mmc->delay_mask) >> __ffs(mmc->delay_mask);
207 degrees += d * mmc->delay_step_ps * 360 / period_ps;
208 degrees %= 360;
209 }
210
211 return degrees;
212}
213
214static void meson_mmc_apply_phase_delay(struct meson_mmc_phase *mmc,
215 unsigned int phase,
216 unsigned int delay)
217{
218 u32 val;
219
220 val = readl(mmc->reg);
221 val &= ~mmc->phase_mask;
222 val |= phase << __ffs(mmc->phase_mask);
223
224 if (mmc->delay_mask) {
225 val &= ~mmc->delay_mask;
226 val |= delay << __ffs(mmc->delay_mask);
227 }
228
229 writel(val, mmc->reg);
230}
231
232static int meson_mmc_clk_set_phase(struct clk_hw *hw, int degrees)
233{
234 struct meson_mmc_phase *mmc = to_meson_mmc_phase(hw);
235 unsigned int phase_num = 1 << hweight_long(mmc->phase_mask);
236 unsigned long period_ps, d = 0, r;
237 uint64_t p;
238
239 p = degrees % 360;
240
241 if (!mmc->delay_mask) {
242 p = DIV_ROUND_CLOSEST_ULL(p, 360 / phase_num);
243 } else {
244 period_ps = DIV_ROUND_UP((unsigned long)NSEC_PER_SEC * 1000,
245 clk_get_rate(hw->clk));
246
247 /* First compute the phase index (p), the remainder (r) is the
248 * part we'll try to acheive using the delays (d).
249 */
250 r = do_div(p, 360 / phase_num);
251 d = DIV_ROUND_CLOSEST(r * period_ps,
252 360 * mmc->delay_step_ps);
253 d = min(d, mmc->delay_mask >> __ffs(mmc->delay_mask));
254 }
255
256 meson_mmc_apply_phase_delay(mmc, p, d);
257 return 0;
258}
259
260static const struct clk_ops meson_mmc_clk_phase_ops = {
261 .get_phase = meson_mmc_clk_get_phase,
262 .set_phase = meson_mmc_clk_set_phase,
263};
264
265static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
266{
267 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
268
269 if (!timeout)
270 return SD_EMMC_CMD_TIMEOUT_DATA;
271
272 timeout = roundup_pow_of_two(timeout);
273
274 return min(timeout, 32768U); /* max. 2^15 ms */
275}
276
277static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
278{
279 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
280 return cmd->mrq->cmd;
281 else if (mmc_op_multi(cmd->opcode) &&
282 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
283 return cmd->mrq->stop;
284 else
285 return NULL;
286}
287
288static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
289 struct mmc_request *mrq)
290{
291 struct mmc_data *data = mrq->data;
292 struct scatterlist *sg;
293 int i;
294 bool use_desc_chain_mode = true;
295
296 /*
297 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
298 * reported. For some strange reason this occurs in descriptor
299 * chain mode only. So let's fall back to bounce buffer mode
300 * for command SD_IO_RW_EXTENDED.
301 */
302 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED)
303 return;
304
305 for_each_sg(data->sg, sg, data->sg_len, i)
306 /* check for 8 byte alignment */
307 if (sg->offset & 7) {
308 WARN_ONCE(1, "unaligned scatterlist buffer\n");
309 use_desc_chain_mode = false;
310 break;
311 }
312
313 if (use_desc_chain_mode)
314 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
315}
316
317static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
318{
319 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
320}
321
322static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
323{
324 return data && data->flags & MMC_DATA_READ &&
325 !meson_mmc_desc_chain_mode(data);
326}
327
328static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
329{
330 struct mmc_data *data = mrq->data;
331
332 if (!data)
333 return;
334
335 meson_mmc_get_transfer_mode(mmc, mrq);
336 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
337
338 if (!meson_mmc_desc_chain_mode(data))
339 return;
340
341 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
342 mmc_get_dma_dir(data));
343 if (!data->sg_count)
344 dev_err(mmc_dev(mmc), "dma_map_sg failed");
345}
346
347static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
348 int err)
349{
350 struct mmc_data *data = mrq->data;
351
352 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
353 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
354 mmc_get_dma_dir(data));
355}
356
357static bool meson_mmc_timing_is_ddr(struct mmc_ios *ios)
358{
359 if (ios->timing == MMC_TIMING_MMC_DDR52 ||
360 ios->timing == MMC_TIMING_UHS_DDR50 ||
361 ios->timing == MMC_TIMING_MMC_HS400)
362 return true;
363
364 return false;
365}
366
367/*
368 * Gating the clock on this controller is tricky. It seems the mmc clock
369 * is also used by the controller. It may crash during some operation if the
370 * clock is stopped. The safest thing to do, whenever possible, is to keep
371 * clock running at stop it at the pad using the pinmux.
372 */
373static void meson_mmc_clk_gate(struct meson_host *host)
374{
375 u32 cfg;
376
377 if (host->pins_clk_gate) {
378 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
379 } else {
380 /*
381 * If the pinmux is not provided - default to the classic and
382 * unsafe method
383 */
384 cfg = readl(host->regs + SD_EMMC_CFG);
385 cfg |= CFG_STOP_CLOCK;
386 writel(cfg, host->regs + SD_EMMC_CFG);
387 }
388}
389
390static void meson_mmc_clk_ungate(struct meson_host *host)
391{
392 u32 cfg;
393
394 if (host->pins_clk_gate)
395 pinctrl_select_state(host->pinctrl, host->pins_default);
396
397 /* Make sure the clock is not stopped in the controller */
398 cfg = readl(host->regs + SD_EMMC_CFG);
399 cfg &= ~CFG_STOP_CLOCK;
400 writel(cfg, host->regs + SD_EMMC_CFG);
401}
402
403static int meson_mmc_clk_set(struct meson_host *host, struct mmc_ios *ios)
404{
405 struct mmc_host *mmc = host->mmc;
406 unsigned long rate = ios->clock;
407 int ret;
408 u32 cfg;
409
410 /* DDR modes require higher module clock */
411 if (meson_mmc_timing_is_ddr(ios))
412 rate <<= 1;
413
414 /* Same request - bail-out */
415 if (host->req_rate == rate)
416 return 0;
417
418 /* stop clock */
419 meson_mmc_clk_gate(host);
420 host->req_rate = 0;
421
422 if (!rate) {
423 mmc->actual_clock = 0;
424 /* return with clock being stopped */
425 return 0;
426 }
427
428 /* Stop the clock during rate change to avoid glitches */
429 cfg = readl(host->regs + SD_EMMC_CFG);
430 cfg |= CFG_STOP_CLOCK;
431 writel(cfg, host->regs + SD_EMMC_CFG);
432
433 ret = clk_set_rate(host->mmc_clk, rate);
434 if (ret) {
435 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
436 rate, ret);
437 return ret;
438 }
439
440 host->req_rate = rate;
441 mmc->actual_clock = clk_get_rate(host->mmc_clk);
442
443 /* We should report the real output frequency of the controller */
444 if (meson_mmc_timing_is_ddr(ios))
445 mmc->actual_clock >>= 1;
446
447 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
448 if (ios->clock != mmc->actual_clock)
449 dev_dbg(host->dev, "requested rate was %u\n", ios->clock);
450
451 /* (re)start clock */
452 meson_mmc_clk_ungate(host);
453
454 return 0;
455}
456
457/*
458 * The SD/eMMC IP block has an internal mux and divider used for
459 * generating the MMC clock. Use the clock framework to create and
460 * manage these clocks.
461 */
462static int meson_mmc_clk_init(struct meson_host *host)
463{
464 struct clk_init_data init;
465 struct clk_mux *mux;
466 struct clk_divider *div;
467 struct meson_mmc_phase *core, *tx, *rx;
468 struct clk *clk;
469 char clk_name[32];
470 int i, ret = 0;
471 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
472 const char *clk_parent[1];
473 u32 clk_reg;
474
475 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
476 clk_reg = 0;
477 clk_reg |= CLK_ALWAYS_ON;
478 clk_reg |= CLK_DIV_MASK;
479 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
480
481 /* get the mux parents */
482 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
483 struct clk *clk;
484 char name[16];
485
486 snprintf(name, sizeof(name), "clkin%d", i);
487 clk = devm_clk_get(host->dev, name);
488 if (IS_ERR(clk)) {
489 if (clk != ERR_PTR(-EPROBE_DEFER))
490 dev_err(host->dev, "Missing clock %s\n", name);
491 return PTR_ERR(clk);
492 }
493
494 mux_parent_names[i] = __clk_get_name(clk);
495 }
496
497 /* create the mux */
498 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
499 if (!mux)
500 return -ENOMEM;
501
502 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
503 init.name = clk_name;
504 init.ops = &clk_mux_ops;
505 init.flags = 0;
506 init.parent_names = mux_parent_names;
507 init.num_parents = MUX_CLK_NUM_PARENTS;
508
509 mux->reg = host->regs + SD_EMMC_CLOCK;
510 mux->shift = __ffs(CLK_SRC_MASK);
511 mux->mask = CLK_SRC_MASK >> mux->shift;
512 mux->hw.init = &init;
513
514 clk = devm_clk_register(host->dev, &mux->hw);
515 if (WARN_ON(IS_ERR(clk)))
516 return PTR_ERR(clk);
517
518 /* create the divider */
519 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
520 if (!div)
521 return -ENOMEM;
522
523 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
524 init.name = clk_name;
525 init.ops = &clk_divider_ops;
526 init.flags = CLK_SET_RATE_PARENT;
527 clk_parent[0] = __clk_get_name(clk);
528 init.parent_names = clk_parent;
529 init.num_parents = 1;
530
531 div->reg = host->regs + SD_EMMC_CLOCK;
532 div->shift = __ffs(CLK_DIV_MASK);
533 div->width = __builtin_popcountl(CLK_DIV_MASK);
534 div->hw.init = &init;
535 div->flags = CLK_DIVIDER_ONE_BASED;
536
537 clk = devm_clk_register(host->dev, &div->hw);
538 if (WARN_ON(IS_ERR(clk)))
539 return PTR_ERR(clk);
540
541 /* create the mmc core clock */
542 core = devm_kzalloc(host->dev, sizeof(*core), GFP_KERNEL);
543 if (!core)
544 return -ENOMEM;
545
546 snprintf(clk_name, sizeof(clk_name), "%s#core", dev_name(host->dev));
547 init.name = clk_name;
548 init.ops = &meson_mmc_clk_phase_ops;
549 init.flags = CLK_SET_RATE_PARENT;
550 clk_parent[0] = __clk_get_name(clk);
551 init.parent_names = clk_parent;
552 init.num_parents = 1;
553
554 core->reg = host->regs + SD_EMMC_CLOCK;
555 core->phase_mask = CLK_CORE_PHASE_MASK;
556 core->hw.init = &init;
557
558 host->mmc_clk = devm_clk_register(host->dev, &core->hw);
559 if (WARN_ON(PTR_ERR_OR_ZERO(host->mmc_clk)))
560 return PTR_ERR(host->mmc_clk);
561
562 /* create the mmc tx clock */
563 tx = devm_kzalloc(host->dev, sizeof(*tx), GFP_KERNEL);
564 if (!tx)
565 return -ENOMEM;
566
567 snprintf(clk_name, sizeof(clk_name), "%s#tx", dev_name(host->dev));
568 init.name = clk_name;
569 init.ops = &meson_mmc_clk_phase_ops;
570 init.flags = 0;
571 clk_parent[0] = __clk_get_name(host->mmc_clk);
572 init.parent_names = clk_parent;
573 init.num_parents = 1;
574
575 tx->reg = host->regs + SD_EMMC_CLOCK;
576 tx->phase_mask = CLK_TX_PHASE_MASK;
577 tx->delay_mask = CLK_TX_DELAY_MASK;
578 tx->delay_step_ps = CLK_DELAY_STEP_PS;
579 tx->hw.init = &init;
580
581 host->tx_clk = devm_clk_register(host->dev, &tx->hw);
582 if (WARN_ON(PTR_ERR_OR_ZERO(host->tx_clk)))
583 return PTR_ERR(host->tx_clk);
584
585 /* create the mmc rx clock */
586 rx = devm_kzalloc(host->dev, sizeof(*rx), GFP_KERNEL);
587 if (!rx)
588 return -ENOMEM;
589
590 snprintf(clk_name, sizeof(clk_name), "%s#rx", dev_name(host->dev));
591 init.name = clk_name;
592 init.ops = &meson_mmc_clk_phase_ops;
593 init.flags = 0;
594 clk_parent[0] = __clk_get_name(host->mmc_clk);
595 init.parent_names = clk_parent;
596 init.num_parents = 1;
597
598 rx->reg = host->regs + SD_EMMC_CLOCK;
599 rx->phase_mask = CLK_RX_PHASE_MASK;
600 rx->delay_mask = CLK_RX_DELAY_MASK;
601 rx->delay_step_ps = CLK_DELAY_STEP_PS;
602 rx->hw.init = &init;
603
604 host->rx_clk = devm_clk_register(host->dev, &rx->hw);
605 if (WARN_ON(PTR_ERR_OR_ZERO(host->rx_clk)))
606 return PTR_ERR(host->rx_clk);
607
608 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
609 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
610 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
611 if (ret)
612 return ret;
613
614 /*
615 * Set phases : These values are mostly the datasheet recommended ones
616 * except for the Tx phase. Datasheet recommends 180 but some cards
617 * fail at initialisation with it. 270 works just fine, it fixes these
618 * initialisation issues and enable eMMC DDR52 mode.
619 */
620 clk_set_phase(host->mmc_clk, 180);
621 clk_set_phase(host->tx_clk, 270);
622 clk_set_phase(host->rx_clk, 0);
623
624 return clk_prepare_enable(host->mmc_clk);
625}
626
627static void meson_mmc_shift_map(unsigned long *map, unsigned long shift)
628{
629 DECLARE_BITMAP(left, CLK_PHASE_POINT_NUM);
630 DECLARE_BITMAP(right, CLK_PHASE_POINT_NUM);
631
632 /*
633 * shift the bitmap right and reintroduce the dropped bits on the left
634 * of the bitmap
635 */
636 bitmap_shift_right(right, map, shift, CLK_PHASE_POINT_NUM);
637 bitmap_shift_left(left, map, CLK_PHASE_POINT_NUM - shift,
638 CLK_PHASE_POINT_NUM);
639 bitmap_or(map, left, right, CLK_PHASE_POINT_NUM);
640}
641
642static void meson_mmc_find_next_region(unsigned long *map,
643 unsigned long *start,
644 unsigned long *stop)
645{
646 *start = find_next_bit(map, CLK_PHASE_POINT_NUM, *start);
647 *stop = find_next_zero_bit(map, CLK_PHASE_POINT_NUM, *start);
648}
649
650static int meson_mmc_find_tuning_point(unsigned long *test)
651{
652 unsigned long shift, stop, offset = 0, start = 0, size = 0;
653
654 /* Get the all good/all bad situation out the way */
655 if (bitmap_full(test, CLK_PHASE_POINT_NUM))
656 return 0; /* All points are good so point 0 will do */
657 else if (bitmap_empty(test, CLK_PHASE_POINT_NUM))
658 return -EIO; /* No successful tuning point */
659
660 /*
661 * Now we know there is a least one region find. Make sure it does
662 * not wrap by the shifting the bitmap if necessary
663 */
664 shift = find_first_zero_bit(test, CLK_PHASE_POINT_NUM);
665 if (shift != 0)
666 meson_mmc_shift_map(test, shift);
667
668 while (start < CLK_PHASE_POINT_NUM) {
669 meson_mmc_find_next_region(test, &start, &stop);
670
671 if ((stop - start) > size) {
672 offset = start;
673 size = stop - start;
674 }
675
676 start = stop;
677 }
678
679 /* Get the center point of the region */
680 offset += (size / 2);
681
682 /* Shift the result back */
683 offset = (offset + shift) % CLK_PHASE_POINT_NUM;
684
685 return offset;
686}
687
688static int meson_mmc_clk_phase_tuning(struct mmc_host *mmc, u32 opcode,
689 struct clk *clk)
690{
691 int point, ret;
692 DECLARE_BITMAP(test, CLK_PHASE_POINT_NUM);
693
694 dev_dbg(mmc_dev(mmc), "%s phase/delay tunning...\n",
695 __clk_get_name(clk));
696 bitmap_zero(test, CLK_PHASE_POINT_NUM);
697
698 /* Explore tuning points */
699 for (point = 0; point < CLK_PHASE_POINT_NUM; point++) {
700 clk_set_phase(clk, point * CLK_PHASE_STEP);
701 ret = mmc_send_tuning(mmc, opcode, NULL);
702 if (!ret)
703 set_bit(point, test);
704 }
705
706 /* Find the optimal tuning point and apply it */
707 point = meson_mmc_find_tuning_point(test);
708 if (point < 0)
709 return point; /* tuning failed */
710
711 clk_set_phase(clk, point * CLK_PHASE_STEP);
712 dev_dbg(mmc_dev(mmc), "success with phase: %d\n",
713 clk_get_phase(clk));
714 return 0;
715}
716
717static int meson_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
718{
719 struct meson_host *host = mmc_priv(mmc);
720
721 return meson_mmc_clk_phase_tuning(mmc, opcode, host->rx_clk);
722}
723
724static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
725{
726 struct meson_host *host = mmc_priv(mmc);
727 u32 bus_width, val;
728 int err;
729
730 /*
731 * GPIO regulator, only controls switching between 1v8 and
732 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
733 */
734 switch (ios->power_mode) {
735 case MMC_POWER_OFF:
736 if (!IS_ERR(mmc->supply.vmmc))
737 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
738
739 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
740 regulator_disable(mmc->supply.vqmmc);
741 host->vqmmc_enabled = false;
742 }
743
744 break;
745
746 case MMC_POWER_UP:
747 if (!IS_ERR(mmc->supply.vmmc))
748 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
749
750 /* Reset rx phase */
751 clk_set_phase(host->rx_clk, 0);
752
753 break;
754
755 case MMC_POWER_ON:
756 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
757 int ret = regulator_enable(mmc->supply.vqmmc);
758
759 if (ret < 0)
760 dev_err(host->dev,
761 "failed to enable vqmmc regulator\n");
762 else
763 host->vqmmc_enabled = true;
764 }
765
766 break;
767 }
768
769 /* Bus width */
770 switch (ios->bus_width) {
771 case MMC_BUS_WIDTH_1:
772 bus_width = CFG_BUS_WIDTH_1;
773 break;
774 case MMC_BUS_WIDTH_4:
775 bus_width = CFG_BUS_WIDTH_4;
776 break;
777 case MMC_BUS_WIDTH_8:
778 bus_width = CFG_BUS_WIDTH_8;
779 break;
780 default:
781 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
782 ios->bus_width);
783 bus_width = CFG_BUS_WIDTH_4;
784 }
785
786 val = readl(host->regs + SD_EMMC_CFG);
787 val &= ~CFG_BUS_WIDTH_MASK;
788 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
789
790 val &= ~CFG_DDR;
791 if (meson_mmc_timing_is_ddr(ios))
792 val |= CFG_DDR;
793
794 val &= ~CFG_CHK_DS;
795 if (ios->timing == MMC_TIMING_MMC_HS400)
796 val |= CFG_CHK_DS;
797
798 err = meson_mmc_clk_set(host, ios);
799 if (err)
800 dev_err(host->dev, "Failed to set clock: %d\n,", err);
801
802 writel(val, host->regs + SD_EMMC_CFG);
803 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
804}
805
806static void meson_mmc_request_done(struct mmc_host *mmc,
807 struct mmc_request *mrq)
808{
809 struct meson_host *host = mmc_priv(mmc);
810
811 host->cmd = NULL;
812 mmc_request_done(host->mmc, mrq);
813}
814
815static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
816{
817 struct meson_host *host = mmc_priv(mmc);
818 u32 cfg, blksz_old;
819
820 cfg = readl(host->regs + SD_EMMC_CFG);
821 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
822
823 if (!is_power_of_2(blksz))
824 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
825
826 blksz = ilog2(blksz);
827
828 /* check if block-size matches, if not update */
829 if (blksz == blksz_old)
830 return;
831
832 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
833 blksz_old, blksz);
834
835 cfg &= ~CFG_BLK_LEN_MASK;
836 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
837 writel(cfg, host->regs + SD_EMMC_CFG);
838}
839
840static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
841{
842 if (cmd->flags & MMC_RSP_PRESENT) {
843 if (cmd->flags & MMC_RSP_136)
844 *cmd_cfg |= CMD_CFG_RESP_128;
845 *cmd_cfg |= CMD_CFG_RESP_NUM;
846
847 if (!(cmd->flags & MMC_RSP_CRC))
848 *cmd_cfg |= CMD_CFG_RESP_NOCRC;
849
850 if (cmd->flags & MMC_RSP_BUSY)
851 *cmd_cfg |= CMD_CFG_R1B;
852 } else {
853 *cmd_cfg |= CMD_CFG_NO_RESP;
854 }
855}
856
857static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
858{
859 struct meson_host *host = mmc_priv(mmc);
860 struct sd_emmc_desc *desc = host->descs;
861 struct mmc_data *data = host->cmd->data;
862 struct scatterlist *sg;
863 u32 start;
864 int i;
865
866 if (data->flags & MMC_DATA_WRITE)
867 cmd_cfg |= CMD_CFG_DATA_WR;
868
869 if (data->blocks > 1) {
870 cmd_cfg |= CMD_CFG_BLOCK_MODE;
871 meson_mmc_set_blksz(mmc, data->blksz);
872 }
873
874 for_each_sg(data->sg, sg, data->sg_count, i) {
875 unsigned int len = sg_dma_len(sg);
876
877 if (data->blocks > 1)
878 len /= data->blksz;
879
880 desc[i].cmd_cfg = cmd_cfg;
881 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
882 if (i > 0)
883 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
884 desc[i].cmd_arg = host->cmd->arg;
885 desc[i].cmd_resp = 0;
886 desc[i].cmd_data = sg_dma_address(sg);
887 }
888 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
889
890 dma_wmb(); /* ensure descriptor is written before kicked */
891 start = host->descs_dma_addr | START_DESC_BUSY;
892 writel(start, host->regs + SD_EMMC_START);
893}
894
895static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
896{
897 struct meson_host *host = mmc_priv(mmc);
898 struct mmc_data *data = cmd->data;
899 u32 cmd_cfg = 0, cmd_data = 0;
900 unsigned int xfer_bytes = 0;
901
902 /* Setup descriptors */
903 dma_rmb();
904
905 host->cmd = cmd;
906
907 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
908 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
909
910 meson_mmc_set_response_bits(cmd, &cmd_cfg);
911
912 /* data? */
913 if (data) {
914 data->bytes_xfered = 0;
915 cmd_cfg |= CMD_CFG_DATA_IO;
916 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
917 ilog2(meson_mmc_get_timeout_msecs(data)));
918
919 if (meson_mmc_desc_chain_mode(data)) {
920 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
921 return;
922 }
923
924 if (data->blocks > 1) {
925 cmd_cfg |= CMD_CFG_BLOCK_MODE;
926 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
927 data->blocks);
928 meson_mmc_set_blksz(mmc, data->blksz);
929 } else {
930 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
931 }
932
933 xfer_bytes = data->blksz * data->blocks;
934 if (data->flags & MMC_DATA_WRITE) {
935 cmd_cfg |= CMD_CFG_DATA_WR;
936 WARN_ON(xfer_bytes > host->bounce_buf_size);
937 sg_copy_to_buffer(data->sg, data->sg_len,
938 host->bounce_buf, xfer_bytes);
939 dma_wmb();
940 }
941
942 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
943 } else {
944 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
945 ilog2(SD_EMMC_CMD_TIMEOUT));
946 }
947
948 /* Last descriptor */
949 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
950 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
951 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
952 writel(0, host->regs + SD_EMMC_CMD_RSP);
953 wmb(); /* ensure descriptor is written before kicked */
954 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
955}
956
957static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
958{
959 struct meson_host *host = mmc_priv(mmc);
960 bool needs_pre_post_req = mrq->data &&
961 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
962
963 if (needs_pre_post_req) {
964 meson_mmc_get_transfer_mode(mmc, mrq);
965 if (!meson_mmc_desc_chain_mode(mrq->data))
966 needs_pre_post_req = false;
967 }
968
969 if (needs_pre_post_req)
970 meson_mmc_pre_req(mmc, mrq);
971
972 /* Stop execution */
973 writel(0, host->regs + SD_EMMC_START);
974
975 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
976
977 if (needs_pre_post_req)
978 meson_mmc_post_req(mmc, mrq, 0);
979}
980
981static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
982{
983 struct meson_host *host = mmc_priv(mmc);
984
985 if (cmd->flags & MMC_RSP_136) {
986 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
987 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
988 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
989 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
990 } else if (cmd->flags & MMC_RSP_PRESENT) {
991 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
992 }
993}
994
995static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
996{
997 struct meson_host *host = dev_id;
998 struct mmc_command *cmd;
999 struct mmc_data *data;
1000 u32 irq_en, status, raw_status;
1001 irqreturn_t ret = IRQ_NONE;
1002
1003 if (WARN_ON(!host) || WARN_ON(!host->cmd))
1004 return IRQ_NONE;
1005
1006 spin_lock(&host->lock);
1007
1008 cmd = host->cmd;
1009 data = cmd->data;
1010 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
1011 raw_status = readl(host->regs + SD_EMMC_STATUS);
1012 status = raw_status & irq_en;
1013
1014 cmd->error = 0;
1015 if (status & IRQ_CRC_ERR) {
1016 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
1017 cmd->error = -EILSEQ;
1018 ret = IRQ_HANDLED;
1019 goto out;
1020 }
1021
1022 if (status & IRQ_TIMEOUTS) {
1023 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
1024 cmd->error = -ETIMEDOUT;
1025 ret = IRQ_HANDLED;
1026 goto out;
1027 }
1028
1029 meson_mmc_read_resp(host->mmc, cmd);
1030
1031 if (status & IRQ_SDIO) {
1032 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
1033 ret = IRQ_HANDLED;
1034 }
1035
1036 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
1037 if (data && !cmd->error)
1038 data->bytes_xfered = data->blksz * data->blocks;
1039 if (meson_mmc_bounce_buf_read(data) ||
1040 meson_mmc_get_next_command(cmd))
1041 ret = IRQ_WAKE_THREAD;
1042 else
1043 ret = IRQ_HANDLED;
1044 }
1045
1046out:
1047 /* ack all enabled interrupts */
1048 writel(irq_en, host->regs + SD_EMMC_STATUS);
1049
1050 if (ret == IRQ_HANDLED)
1051 meson_mmc_request_done(host->mmc, cmd->mrq);
1052 else if (ret == IRQ_NONE)
1053 dev_warn(host->dev,
1054 "Unexpected IRQ! status=0x%08x, irq_en=0x%08x\n",
1055 raw_status, irq_en);
1056
1057 spin_unlock(&host->lock);
1058 return ret;
1059}
1060
1061static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
1062{
1063 struct meson_host *host = dev_id;
1064 struct mmc_command *next_cmd, *cmd = host->cmd;
1065 struct mmc_data *data;
1066 unsigned int xfer_bytes;
1067
1068 if (WARN_ON(!cmd))
1069 return IRQ_NONE;
1070
1071 data = cmd->data;
1072 if (meson_mmc_bounce_buf_read(data)) {
1073 xfer_bytes = data->blksz * data->blocks;
1074 WARN_ON(xfer_bytes > host->bounce_buf_size);
1075 sg_copy_from_buffer(data->sg, data->sg_len,
1076 host->bounce_buf, xfer_bytes);
1077 }
1078
1079 next_cmd = meson_mmc_get_next_command(cmd);
1080 if (next_cmd)
1081 meson_mmc_start_cmd(host->mmc, next_cmd);
1082 else
1083 meson_mmc_request_done(host->mmc, cmd->mrq);
1084
1085 return IRQ_HANDLED;
1086}
1087
1088/*
1089 * NOTE: we only need this until the GPIO/pinctrl driver can handle
1090 * interrupts. For now, the MMC core will use this for polling.
1091 */
1092static int meson_mmc_get_cd(struct mmc_host *mmc)
1093{
1094 int status = mmc_gpio_get_cd(mmc);
1095
1096 if (status == -ENOSYS)
1097 return 1; /* assume present */
1098
1099 return status;
1100}
1101
1102static void meson_mmc_cfg_init(struct meson_host *host)
1103{
1104 u32 cfg = 0;
1105
1106 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
1107 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
1108 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
1109 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
1110
1111 writel(cfg, host->regs + SD_EMMC_CFG);
1112}
1113
1114static int meson_mmc_card_busy(struct mmc_host *mmc)
1115{
1116 struct meson_host *host = mmc_priv(mmc);
1117 u32 regval;
1118
1119 regval = readl(host->regs + SD_EMMC_STATUS);
1120
1121 /* We are only interrested in lines 0 to 3, so mask the other ones */
1122 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1123}
1124
1125static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1126{
1127 /* vqmmc regulator is available */
1128 if (!IS_ERR(mmc->supply.vqmmc)) {
1129 /*
1130 * The usual amlogic setup uses a GPIO to switch from one
1131 * regulator to the other. While the voltage ramp up is
1132 * pretty fast, care must be taken when switching from 3.3v
1133 * to 1.8v. Please make sure the regulator framework is aware
1134 * of your own regulator constraints
1135 */
1136 return mmc_regulator_set_vqmmc(mmc, ios);
1137 }
1138
1139 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1140 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1141 return 0;
1142
1143 return -EINVAL;
1144}
1145
1146static const struct mmc_host_ops meson_mmc_ops = {
1147 .request = meson_mmc_request,
1148 .set_ios = meson_mmc_set_ios,
1149 .get_cd = meson_mmc_get_cd,
1150 .pre_req = meson_mmc_pre_req,
1151 .post_req = meson_mmc_post_req,
1152 .execute_tuning = meson_mmc_execute_tuning,
1153 .card_busy = meson_mmc_card_busy,
1154 .start_signal_voltage_switch = meson_mmc_voltage_switch,
1155};
1156
1157static int meson_mmc_probe(struct platform_device *pdev)
1158{
1159 struct resource *res;
1160 struct meson_host *host;
1161 struct mmc_host *mmc;
1162 int ret, irq;
1163
1164 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1165 if (!mmc)
1166 return -ENOMEM;
1167 host = mmc_priv(mmc);
1168 host->mmc = mmc;
1169 host->dev = &pdev->dev;
1170 dev_set_drvdata(&pdev->dev, host);
1171
1172 spin_lock_init(&host->lock);
1173
1174 /* Get regulators and the supported OCR mask */
1175 host->vqmmc_enabled = false;
1176 ret = mmc_regulator_get_supply(mmc);
1177 if (ret)
1178 goto free_host;
1179
1180 ret = mmc_of_parse(mmc);
1181 if (ret) {
1182 if (ret != -EPROBE_DEFER)
1183 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1184 goto free_host;
1185 }
1186
1187 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1188 host->regs = devm_ioremap_resource(&pdev->dev, res);
1189 if (IS_ERR(host->regs)) {
1190 ret = PTR_ERR(host->regs);
1191 goto free_host;
1192 }
1193
1194 irq = platform_get_irq(pdev, 0);
1195 if (irq <= 0) {
1196 dev_err(&pdev->dev, "failed to get interrupt resource.\n");
1197 ret = -EINVAL;
1198 goto free_host;
1199 }
1200
1201 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1202 if (IS_ERR(host->pinctrl)) {
1203 ret = PTR_ERR(host->pinctrl);
1204 goto free_host;
1205 }
1206
1207 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1208 PINCTRL_STATE_DEFAULT);
1209 if (IS_ERR(host->pins_default)) {
1210 ret = PTR_ERR(host->pins_default);
1211 goto free_host;
1212 }
1213
1214 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1215 "clk-gate");
1216 if (IS_ERR(host->pins_clk_gate)) {
1217 dev_warn(&pdev->dev,
1218 "can't get clk-gate pinctrl, using clk_stop bit\n");
1219 host->pins_clk_gate = NULL;
1220 }
1221
1222 host->core_clk = devm_clk_get(&pdev->dev, "core");
1223 if (IS_ERR(host->core_clk)) {
1224 ret = PTR_ERR(host->core_clk);
1225 goto free_host;
1226 }
1227
1228 ret = clk_prepare_enable(host->core_clk);
1229 if (ret)
1230 goto free_host;
1231
1232 ret = meson_mmc_clk_init(host);
1233 if (ret)
1234 goto err_core_clk;
1235
1236 /* set config to sane default */
1237 meson_mmc_cfg_init(host);
1238
1239 /* Stop execution */
1240 writel(0, host->regs + SD_EMMC_START);
1241
1242 /* clear, ack and enable interrupts */
1243 writel(0, host->regs + SD_EMMC_IRQ_EN);
1244 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1245 host->regs + SD_EMMC_STATUS);
1246 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1247 host->regs + SD_EMMC_IRQ_EN);
1248
1249 ret = devm_request_threaded_irq(&pdev->dev, irq, meson_mmc_irq,
1250 meson_mmc_irq_thread, IRQF_SHARED,
1251 NULL, host);
1252 if (ret)
1253 goto err_init_clk;
1254
1255 mmc->caps |= MMC_CAP_CMD23;
1256 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1257 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1258 mmc->max_segs = SD_EMMC_DESC_BUF_LEN / sizeof(struct sd_emmc_desc);
1259 mmc->max_seg_size = mmc->max_req_size;
1260
1261 /* data bounce buffer */
1262 host->bounce_buf_size = mmc->max_req_size;
1263 host->bounce_buf =
1264 dma_alloc_coherent(host->dev, host->bounce_buf_size,
1265 &host->bounce_dma_addr, GFP_KERNEL);
1266 if (host->bounce_buf == NULL) {
1267 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1268 ret = -ENOMEM;
1269 goto err_init_clk;
1270 }
1271
1272 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1273 &host->descs_dma_addr, GFP_KERNEL);
1274 if (!host->descs) {
1275 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1276 ret = -ENOMEM;
1277 goto err_bounce_buf;
1278 }
1279
1280 mmc->ops = &meson_mmc_ops;
1281 mmc_add_host(mmc);
1282
1283 return 0;
1284
1285err_bounce_buf:
1286 dma_free_coherent(host->dev, host->bounce_buf_size,
1287 host->bounce_buf, host->bounce_dma_addr);
1288err_init_clk:
1289 clk_disable_unprepare(host->mmc_clk);
1290err_core_clk:
1291 clk_disable_unprepare(host->core_clk);
1292free_host:
1293 mmc_free_host(mmc);
1294 return ret;
1295}
1296
1297static int meson_mmc_remove(struct platform_device *pdev)
1298{
1299 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1300
1301 mmc_remove_host(host->mmc);
1302
1303 /* disable interrupts */
1304 writel(0, host->regs + SD_EMMC_IRQ_EN);
1305
1306 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1307 host->descs, host->descs_dma_addr);
1308 dma_free_coherent(host->dev, host->bounce_buf_size,
1309 host->bounce_buf, host->bounce_dma_addr);
1310
1311 clk_disable_unprepare(host->mmc_clk);
1312 clk_disable_unprepare(host->core_clk);
1313
1314 mmc_free_host(host->mmc);
1315 return 0;
1316}
1317
1318static const struct of_device_id meson_mmc_of_match[] = {
1319 { .compatible = "amlogic,meson-gx-mmc", },
1320 { .compatible = "amlogic,meson-gxbb-mmc", },
1321 { .compatible = "amlogic,meson-gxl-mmc", },
1322 { .compatible = "amlogic,meson-gxm-mmc", },
1323 {}
1324};
1325MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1326
1327static struct platform_driver meson_mmc_driver = {
1328 .probe = meson_mmc_probe,
1329 .remove = meson_mmc_remove,
1330 .driver = {
1331 .name = DRIVER_NAME,
1332 .of_match_table = of_match_ptr(meson_mmc_of_match),
1333 },
1334};
1335
1336module_platform_driver(meson_mmc_driver);
1337
1338MODULE_DESCRIPTION("Amlogic S905*/GX* SD/eMMC driver");
1339MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1340MODULE_LICENSE("GPL v2");
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Amlogic SD/eMMC driver for the GX/S905 family SoCs
4 *
5 * Copyright (c) 2016 BayLibre, SAS.
6 * Author: Kevin Hilman <khilman@baylibre.com>
7 */
8#include <linux/kernel.h>
9#include <linux/module.h>
10#include <linux/init.h>
11#include <linux/delay.h>
12#include <linux/device.h>
13#include <linux/iopoll.h>
14#include <linux/of_device.h>
15#include <linux/platform_device.h>
16#include <linux/ioport.h>
17#include <linux/dma-mapping.h>
18#include <linux/mmc/host.h>
19#include <linux/mmc/mmc.h>
20#include <linux/mmc/sdio.h>
21#include <linux/mmc/slot-gpio.h>
22#include <linux/io.h>
23#include <linux/clk.h>
24#include <linux/clk-provider.h>
25#include <linux/regulator/consumer.h>
26#include <linux/reset.h>
27#include <linux/interrupt.h>
28#include <linux/bitfield.h>
29#include <linux/pinctrl/consumer.h>
30
31#define DRIVER_NAME "meson-gx-mmc"
32
33#define SD_EMMC_CLOCK 0x0
34#define CLK_DIV_MASK GENMASK(5, 0)
35#define CLK_SRC_MASK GENMASK(7, 6)
36#define CLK_CORE_PHASE_MASK GENMASK(9, 8)
37#define CLK_TX_PHASE_MASK GENMASK(11, 10)
38#define CLK_RX_PHASE_MASK GENMASK(13, 12)
39#define CLK_PHASE_0 0
40#define CLK_PHASE_180 2
41#define CLK_V2_TX_DELAY_MASK GENMASK(19, 16)
42#define CLK_V2_RX_DELAY_MASK GENMASK(23, 20)
43#define CLK_V2_ALWAYS_ON BIT(24)
44
45#define CLK_V3_TX_DELAY_MASK GENMASK(21, 16)
46#define CLK_V3_RX_DELAY_MASK GENMASK(27, 22)
47#define CLK_V3_ALWAYS_ON BIT(28)
48
49#define CLK_TX_DELAY_MASK(h) (h->data->tx_delay_mask)
50#define CLK_RX_DELAY_MASK(h) (h->data->rx_delay_mask)
51#define CLK_ALWAYS_ON(h) (h->data->always_on)
52
53#define SD_EMMC_DELAY 0x4
54#define SD_EMMC_ADJUST 0x8
55#define ADJUST_ADJ_DELAY_MASK GENMASK(21, 16)
56#define ADJUST_DS_EN BIT(15)
57#define ADJUST_ADJ_EN BIT(13)
58
59#define SD_EMMC_DELAY1 0x4
60#define SD_EMMC_DELAY2 0x8
61#define SD_EMMC_V3_ADJUST 0xc
62
63#define SD_EMMC_CALOUT 0x10
64#define SD_EMMC_START 0x40
65#define START_DESC_INIT BIT(0)
66#define START_DESC_BUSY BIT(1)
67#define START_DESC_ADDR_MASK GENMASK(31, 2)
68
69#define SD_EMMC_CFG 0x44
70#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
71#define CFG_BUS_WIDTH_1 0x0
72#define CFG_BUS_WIDTH_4 0x1
73#define CFG_BUS_WIDTH_8 0x2
74#define CFG_DDR BIT(2)
75#define CFG_BLK_LEN_MASK GENMASK(7, 4)
76#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
77#define CFG_RC_CC_MASK GENMASK(15, 12)
78#define CFG_STOP_CLOCK BIT(22)
79#define CFG_CLK_ALWAYS_ON BIT(18)
80#define CFG_CHK_DS BIT(20)
81#define CFG_AUTO_CLK BIT(23)
82#define CFG_ERR_ABORT BIT(27)
83
84#define SD_EMMC_STATUS 0x48
85#define STATUS_BUSY BIT(31)
86#define STATUS_DESC_BUSY BIT(30)
87#define STATUS_DATI GENMASK(23, 16)
88
89#define SD_EMMC_IRQ_EN 0x4c
90#define IRQ_RXD_ERR_MASK GENMASK(7, 0)
91#define IRQ_TXD_ERR BIT(8)
92#define IRQ_DESC_ERR BIT(9)
93#define IRQ_RESP_ERR BIT(10)
94#define IRQ_CRC_ERR \
95 (IRQ_RXD_ERR_MASK | IRQ_TXD_ERR | IRQ_DESC_ERR | IRQ_RESP_ERR)
96#define IRQ_RESP_TIMEOUT BIT(11)
97#define IRQ_DESC_TIMEOUT BIT(12)
98#define IRQ_TIMEOUTS \
99 (IRQ_RESP_TIMEOUT | IRQ_DESC_TIMEOUT)
100#define IRQ_END_OF_CHAIN BIT(13)
101#define IRQ_RESP_STATUS BIT(14)
102#define IRQ_SDIO BIT(15)
103#define IRQ_EN_MASK \
104 (IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN | IRQ_RESP_STATUS |\
105 IRQ_SDIO)
106
107#define SD_EMMC_CMD_CFG 0x50
108#define SD_EMMC_CMD_ARG 0x54
109#define SD_EMMC_CMD_DAT 0x58
110#define SD_EMMC_CMD_RSP 0x5c
111#define SD_EMMC_CMD_RSP1 0x60
112#define SD_EMMC_CMD_RSP2 0x64
113#define SD_EMMC_CMD_RSP3 0x68
114
115#define SD_EMMC_RXD 0x94
116#define SD_EMMC_TXD 0x94
117#define SD_EMMC_LAST_REG SD_EMMC_TXD
118
119#define SD_EMMC_SRAM_DATA_BUF_LEN 1536
120#define SD_EMMC_SRAM_DATA_BUF_OFF 0x200
121
122#define SD_EMMC_CFG_BLK_SIZE 512 /* internal buffer max: 512 bytes */
123#define SD_EMMC_CFG_RESP_TIMEOUT 256 /* in clock cycles */
124#define SD_EMMC_CMD_TIMEOUT 1024 /* in ms */
125#define SD_EMMC_CMD_TIMEOUT_DATA 4096 /* in ms */
126#define SD_EMMC_CFG_CMD_GAP 16 /* in clock cycles */
127#define SD_EMMC_DESC_BUF_LEN PAGE_SIZE
128
129#define SD_EMMC_PRE_REQ_DONE BIT(0)
130#define SD_EMMC_DESC_CHAIN_MODE BIT(1)
131
132#define MUX_CLK_NUM_PARENTS 2
133
134struct meson_mmc_data {
135 unsigned int tx_delay_mask;
136 unsigned int rx_delay_mask;
137 unsigned int always_on;
138 unsigned int adjust;
139};
140
141struct sd_emmc_desc {
142 u32 cmd_cfg;
143 u32 cmd_arg;
144 u32 cmd_data;
145 u32 cmd_resp;
146};
147
148struct meson_host {
149 struct device *dev;
150 struct meson_mmc_data *data;
151 struct mmc_host *mmc;
152 struct mmc_command *cmd;
153
154 void __iomem *regs;
155 struct clk *core_clk;
156 struct clk *mux_clk;
157 struct clk *mmc_clk;
158 unsigned long req_rate;
159 bool ddr;
160
161 bool dram_access_quirk;
162
163 struct pinctrl *pinctrl;
164 struct pinctrl_state *pins_default;
165 struct pinctrl_state *pins_clk_gate;
166
167 unsigned int bounce_buf_size;
168 void *bounce_buf;
169 dma_addr_t bounce_dma_addr;
170 struct sd_emmc_desc *descs;
171 dma_addr_t descs_dma_addr;
172
173 int irq;
174
175 bool vqmmc_enabled;
176};
177
178#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
179#define CMD_CFG_BLOCK_MODE BIT(9)
180#define CMD_CFG_R1B BIT(10)
181#define CMD_CFG_END_OF_CHAIN BIT(11)
182#define CMD_CFG_TIMEOUT_MASK GENMASK(15, 12)
183#define CMD_CFG_NO_RESP BIT(16)
184#define CMD_CFG_NO_CMD BIT(17)
185#define CMD_CFG_DATA_IO BIT(18)
186#define CMD_CFG_DATA_WR BIT(19)
187#define CMD_CFG_RESP_NOCRC BIT(20)
188#define CMD_CFG_RESP_128 BIT(21)
189#define CMD_CFG_RESP_NUM BIT(22)
190#define CMD_CFG_DATA_NUM BIT(23)
191#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
192#define CMD_CFG_ERROR BIT(30)
193#define CMD_CFG_OWNER BIT(31)
194
195#define CMD_DATA_MASK GENMASK(31, 2)
196#define CMD_DATA_BIG_ENDIAN BIT(1)
197#define CMD_DATA_SRAM BIT(0)
198#define CMD_RESP_MASK GENMASK(31, 1)
199#define CMD_RESP_SRAM BIT(0)
200
201static unsigned int meson_mmc_get_timeout_msecs(struct mmc_data *data)
202{
203 unsigned int timeout = data->timeout_ns / NSEC_PER_MSEC;
204
205 if (!timeout)
206 return SD_EMMC_CMD_TIMEOUT_DATA;
207
208 timeout = roundup_pow_of_two(timeout);
209
210 return min(timeout, 32768U); /* max. 2^15 ms */
211}
212
213static struct mmc_command *meson_mmc_get_next_command(struct mmc_command *cmd)
214{
215 if (cmd->opcode == MMC_SET_BLOCK_COUNT && !cmd->error)
216 return cmd->mrq->cmd;
217 else if (mmc_op_multi(cmd->opcode) &&
218 (!cmd->mrq->sbc || cmd->error || cmd->data->error))
219 return cmd->mrq->stop;
220 else
221 return NULL;
222}
223
224static void meson_mmc_get_transfer_mode(struct mmc_host *mmc,
225 struct mmc_request *mrq)
226{
227 struct meson_host *host = mmc_priv(mmc);
228 struct mmc_data *data = mrq->data;
229 struct scatterlist *sg;
230 int i;
231 bool use_desc_chain_mode = true;
232
233 /*
234 * When Controller DMA cannot directly access DDR memory, disable
235 * support for Chain Mode to directly use the internal SRAM using
236 * the bounce buffer mode.
237 */
238 if (host->dram_access_quirk)
239 return;
240
241 /*
242 * Broken SDIO with AP6255-based WiFi on Khadas VIM Pro has been
243 * reported. For some strange reason this occurs in descriptor
244 * chain mode only. So let's fall back to bounce buffer mode
245 * for command SD_IO_RW_EXTENDED.
246 */
247 if (mrq->cmd->opcode == SD_IO_RW_EXTENDED)
248 return;
249
250 for_each_sg(data->sg, sg, data->sg_len, i)
251 /* check for 8 byte alignment */
252 if (sg->offset & 7) {
253 WARN_ONCE(1, "unaligned scatterlist buffer\n");
254 use_desc_chain_mode = false;
255 break;
256 }
257
258 if (use_desc_chain_mode)
259 data->host_cookie |= SD_EMMC_DESC_CHAIN_MODE;
260}
261
262static inline bool meson_mmc_desc_chain_mode(const struct mmc_data *data)
263{
264 return data->host_cookie & SD_EMMC_DESC_CHAIN_MODE;
265}
266
267static inline bool meson_mmc_bounce_buf_read(const struct mmc_data *data)
268{
269 return data && data->flags & MMC_DATA_READ &&
270 !meson_mmc_desc_chain_mode(data);
271}
272
273static void meson_mmc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq)
274{
275 struct mmc_data *data = mrq->data;
276
277 if (!data)
278 return;
279
280 meson_mmc_get_transfer_mode(mmc, mrq);
281 data->host_cookie |= SD_EMMC_PRE_REQ_DONE;
282
283 if (!meson_mmc_desc_chain_mode(data))
284 return;
285
286 data->sg_count = dma_map_sg(mmc_dev(mmc), data->sg, data->sg_len,
287 mmc_get_dma_dir(data));
288 if (!data->sg_count)
289 dev_err(mmc_dev(mmc), "dma_map_sg failed");
290}
291
292static void meson_mmc_post_req(struct mmc_host *mmc, struct mmc_request *mrq,
293 int err)
294{
295 struct mmc_data *data = mrq->data;
296
297 if (data && meson_mmc_desc_chain_mode(data) && data->sg_count)
298 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len,
299 mmc_get_dma_dir(data));
300}
301
302/*
303 * Gating the clock on this controller is tricky. It seems the mmc clock
304 * is also used by the controller. It may crash during some operation if the
305 * clock is stopped. The safest thing to do, whenever possible, is to keep
306 * clock running at stop it at the pad using the pinmux.
307 */
308static void meson_mmc_clk_gate(struct meson_host *host)
309{
310 u32 cfg;
311
312 if (host->pins_clk_gate) {
313 pinctrl_select_state(host->pinctrl, host->pins_clk_gate);
314 } else {
315 /*
316 * If the pinmux is not provided - default to the classic and
317 * unsafe method
318 */
319 cfg = readl(host->regs + SD_EMMC_CFG);
320 cfg |= CFG_STOP_CLOCK;
321 writel(cfg, host->regs + SD_EMMC_CFG);
322 }
323}
324
325static void meson_mmc_clk_ungate(struct meson_host *host)
326{
327 u32 cfg;
328
329 if (host->pins_clk_gate)
330 pinctrl_select_state(host->pinctrl, host->pins_default);
331
332 /* Make sure the clock is not stopped in the controller */
333 cfg = readl(host->regs + SD_EMMC_CFG);
334 cfg &= ~CFG_STOP_CLOCK;
335 writel(cfg, host->regs + SD_EMMC_CFG);
336}
337
338static int meson_mmc_clk_set(struct meson_host *host, unsigned long rate,
339 bool ddr)
340{
341 struct mmc_host *mmc = host->mmc;
342 int ret;
343 u32 cfg;
344
345 /* Same request - bail-out */
346 if (host->ddr == ddr && host->req_rate == rate)
347 return 0;
348
349 /* stop clock */
350 meson_mmc_clk_gate(host);
351 host->req_rate = 0;
352 mmc->actual_clock = 0;
353
354 /* return with clock being stopped */
355 if (!rate)
356 return 0;
357
358 /* Stop the clock during rate change to avoid glitches */
359 cfg = readl(host->regs + SD_EMMC_CFG);
360 cfg |= CFG_STOP_CLOCK;
361 writel(cfg, host->regs + SD_EMMC_CFG);
362
363 if (ddr) {
364 /* DDR modes require higher module clock */
365 rate <<= 1;
366 cfg |= CFG_DDR;
367 } else {
368 cfg &= ~CFG_DDR;
369 }
370 writel(cfg, host->regs + SD_EMMC_CFG);
371 host->ddr = ddr;
372
373 ret = clk_set_rate(host->mmc_clk, rate);
374 if (ret) {
375 dev_err(host->dev, "Unable to set cfg_div_clk to %lu. ret=%d\n",
376 rate, ret);
377 return ret;
378 }
379
380 host->req_rate = rate;
381 mmc->actual_clock = clk_get_rate(host->mmc_clk);
382
383 /* We should report the real output frequency of the controller */
384 if (ddr) {
385 host->req_rate >>= 1;
386 mmc->actual_clock >>= 1;
387 }
388
389 dev_dbg(host->dev, "clk rate: %u Hz\n", mmc->actual_clock);
390 if (rate != mmc->actual_clock)
391 dev_dbg(host->dev, "requested rate was %lu\n", rate);
392
393 /* (re)start clock */
394 meson_mmc_clk_ungate(host);
395
396 return 0;
397}
398
399/*
400 * The SD/eMMC IP block has an internal mux and divider used for
401 * generating the MMC clock. Use the clock framework to create and
402 * manage these clocks.
403 */
404static int meson_mmc_clk_init(struct meson_host *host)
405{
406 struct clk_init_data init;
407 struct clk_mux *mux;
408 struct clk_divider *div;
409 char clk_name[32];
410 int i, ret = 0;
411 const char *mux_parent_names[MUX_CLK_NUM_PARENTS];
412 const char *clk_parent[1];
413 u32 clk_reg;
414
415 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
416 clk_reg = CLK_ALWAYS_ON(host);
417 clk_reg |= CLK_DIV_MASK;
418 clk_reg |= FIELD_PREP(CLK_CORE_PHASE_MASK, CLK_PHASE_180);
419 clk_reg |= FIELD_PREP(CLK_TX_PHASE_MASK, CLK_PHASE_0);
420 clk_reg |= FIELD_PREP(CLK_RX_PHASE_MASK, CLK_PHASE_0);
421 writel(clk_reg, host->regs + SD_EMMC_CLOCK);
422
423 /* get the mux parents */
424 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
425 struct clk *clk;
426 char name[16];
427
428 snprintf(name, sizeof(name), "clkin%d", i);
429 clk = devm_clk_get(host->dev, name);
430 if (IS_ERR(clk)) {
431 if (clk != ERR_PTR(-EPROBE_DEFER))
432 dev_err(host->dev, "Missing clock %s\n", name);
433 return PTR_ERR(clk);
434 }
435
436 mux_parent_names[i] = __clk_get_name(clk);
437 }
438
439 /* create the mux */
440 mux = devm_kzalloc(host->dev, sizeof(*mux), GFP_KERNEL);
441 if (!mux)
442 return -ENOMEM;
443
444 snprintf(clk_name, sizeof(clk_name), "%s#mux", dev_name(host->dev));
445 init.name = clk_name;
446 init.ops = &clk_mux_ops;
447 init.flags = 0;
448 init.parent_names = mux_parent_names;
449 init.num_parents = MUX_CLK_NUM_PARENTS;
450
451 mux->reg = host->regs + SD_EMMC_CLOCK;
452 mux->shift = __ffs(CLK_SRC_MASK);
453 mux->mask = CLK_SRC_MASK >> mux->shift;
454 mux->hw.init = &init;
455
456 host->mux_clk = devm_clk_register(host->dev, &mux->hw);
457 if (WARN_ON(IS_ERR(host->mux_clk)))
458 return PTR_ERR(host->mux_clk);
459
460 /* create the divider */
461 div = devm_kzalloc(host->dev, sizeof(*div), GFP_KERNEL);
462 if (!div)
463 return -ENOMEM;
464
465 snprintf(clk_name, sizeof(clk_name), "%s#div", dev_name(host->dev));
466 init.name = clk_name;
467 init.ops = &clk_divider_ops;
468 init.flags = CLK_SET_RATE_PARENT;
469 clk_parent[0] = __clk_get_name(host->mux_clk);
470 init.parent_names = clk_parent;
471 init.num_parents = 1;
472
473 div->reg = host->regs + SD_EMMC_CLOCK;
474 div->shift = __ffs(CLK_DIV_MASK);
475 div->width = __builtin_popcountl(CLK_DIV_MASK);
476 div->hw.init = &init;
477 div->flags = CLK_DIVIDER_ONE_BASED;
478
479 host->mmc_clk = devm_clk_register(host->dev, &div->hw);
480 if (WARN_ON(IS_ERR(host->mmc_clk)))
481 return PTR_ERR(host->mmc_clk);
482
483 /* init SD_EMMC_CLOCK to sane defaults w/min clock rate */
484 host->mmc->f_min = clk_round_rate(host->mmc_clk, 400000);
485 ret = clk_set_rate(host->mmc_clk, host->mmc->f_min);
486 if (ret)
487 return ret;
488
489 return clk_prepare_enable(host->mmc_clk);
490}
491
492static void meson_mmc_disable_resampling(struct meson_host *host)
493{
494 unsigned int val = readl(host->regs + host->data->adjust);
495
496 val &= ~ADJUST_ADJ_EN;
497 writel(val, host->regs + host->data->adjust);
498}
499
500static void meson_mmc_reset_resampling(struct meson_host *host)
501{
502 unsigned int val;
503
504 meson_mmc_disable_resampling(host);
505
506 val = readl(host->regs + host->data->adjust);
507 val &= ~ADJUST_ADJ_DELAY_MASK;
508 writel(val, host->regs + host->data->adjust);
509}
510
511static int meson_mmc_resampling_tuning(struct mmc_host *mmc, u32 opcode)
512{
513 struct meson_host *host = mmc_priv(mmc);
514 unsigned int val, dly, max_dly, i;
515 int ret;
516
517 /* Resampling is done using the source clock */
518 max_dly = DIV_ROUND_UP(clk_get_rate(host->mux_clk),
519 clk_get_rate(host->mmc_clk));
520
521 val = readl(host->regs + host->data->adjust);
522 val |= ADJUST_ADJ_EN;
523 writel(val, host->regs + host->data->adjust);
524
525 if (mmc->doing_retune)
526 dly = FIELD_GET(ADJUST_ADJ_DELAY_MASK, val) + 1;
527 else
528 dly = 0;
529
530 for (i = 0; i < max_dly; i++) {
531 val &= ~ADJUST_ADJ_DELAY_MASK;
532 val |= FIELD_PREP(ADJUST_ADJ_DELAY_MASK, (dly + i) % max_dly);
533 writel(val, host->regs + host->data->adjust);
534
535 ret = mmc_send_tuning(mmc, opcode, NULL);
536 if (!ret) {
537 dev_dbg(mmc_dev(mmc), "resampling delay: %u\n",
538 (dly + i) % max_dly);
539 return 0;
540 }
541 }
542
543 meson_mmc_reset_resampling(host);
544 return -EIO;
545}
546
547static int meson_mmc_prepare_ios_clock(struct meson_host *host,
548 struct mmc_ios *ios)
549{
550 bool ddr;
551
552 switch (ios->timing) {
553 case MMC_TIMING_MMC_DDR52:
554 case MMC_TIMING_UHS_DDR50:
555 ddr = true;
556 break;
557
558 default:
559 ddr = false;
560 break;
561 }
562
563 return meson_mmc_clk_set(host, ios->clock, ddr);
564}
565
566static void meson_mmc_check_resampling(struct meson_host *host,
567 struct mmc_ios *ios)
568{
569 switch (ios->timing) {
570 case MMC_TIMING_LEGACY:
571 case MMC_TIMING_MMC_HS:
572 case MMC_TIMING_SD_HS:
573 case MMC_TIMING_MMC_DDR52:
574 meson_mmc_disable_resampling(host);
575 break;
576 }
577}
578
579static void meson_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
580{
581 struct meson_host *host = mmc_priv(mmc);
582 u32 bus_width, val;
583 int err;
584
585 /*
586 * GPIO regulator, only controls switching between 1v8 and
587 * 3v3, doesn't support MMC_POWER_OFF, MMC_POWER_ON.
588 */
589 switch (ios->power_mode) {
590 case MMC_POWER_OFF:
591 if (!IS_ERR(mmc->supply.vmmc))
592 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
593
594 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
595 regulator_disable(mmc->supply.vqmmc);
596 host->vqmmc_enabled = false;
597 }
598
599 break;
600
601 case MMC_POWER_UP:
602 if (!IS_ERR(mmc->supply.vmmc))
603 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
604
605 break;
606
607 case MMC_POWER_ON:
608 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
609 int ret = regulator_enable(mmc->supply.vqmmc);
610
611 if (ret < 0)
612 dev_err(host->dev,
613 "failed to enable vqmmc regulator\n");
614 else
615 host->vqmmc_enabled = true;
616 }
617
618 break;
619 }
620
621 /* Bus width */
622 switch (ios->bus_width) {
623 case MMC_BUS_WIDTH_1:
624 bus_width = CFG_BUS_WIDTH_1;
625 break;
626 case MMC_BUS_WIDTH_4:
627 bus_width = CFG_BUS_WIDTH_4;
628 break;
629 case MMC_BUS_WIDTH_8:
630 bus_width = CFG_BUS_WIDTH_8;
631 break;
632 default:
633 dev_err(host->dev, "Invalid ios->bus_width: %u. Setting to 4.\n",
634 ios->bus_width);
635 bus_width = CFG_BUS_WIDTH_4;
636 }
637
638 val = readl(host->regs + SD_EMMC_CFG);
639 val &= ~CFG_BUS_WIDTH_MASK;
640 val |= FIELD_PREP(CFG_BUS_WIDTH_MASK, bus_width);
641 writel(val, host->regs + SD_EMMC_CFG);
642
643 meson_mmc_check_resampling(host, ios);
644 err = meson_mmc_prepare_ios_clock(host, ios);
645 if (err)
646 dev_err(host->dev, "Failed to set clock: %d\n,", err);
647
648 dev_dbg(host->dev, "SD_EMMC_CFG: 0x%08x\n", val);
649}
650
651static void meson_mmc_request_done(struct mmc_host *mmc,
652 struct mmc_request *mrq)
653{
654 struct meson_host *host = mmc_priv(mmc);
655
656 host->cmd = NULL;
657 mmc_request_done(host->mmc, mrq);
658}
659
660static void meson_mmc_set_blksz(struct mmc_host *mmc, unsigned int blksz)
661{
662 struct meson_host *host = mmc_priv(mmc);
663 u32 cfg, blksz_old;
664
665 cfg = readl(host->regs + SD_EMMC_CFG);
666 blksz_old = FIELD_GET(CFG_BLK_LEN_MASK, cfg);
667
668 if (!is_power_of_2(blksz))
669 dev_err(host->dev, "blksz %u is not a power of 2\n", blksz);
670
671 blksz = ilog2(blksz);
672
673 /* check if block-size matches, if not update */
674 if (blksz == blksz_old)
675 return;
676
677 dev_dbg(host->dev, "%s: update blk_len %d -> %d\n", __func__,
678 blksz_old, blksz);
679
680 cfg &= ~CFG_BLK_LEN_MASK;
681 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, blksz);
682 writel(cfg, host->regs + SD_EMMC_CFG);
683}
684
685static void meson_mmc_set_response_bits(struct mmc_command *cmd, u32 *cmd_cfg)
686{
687 if (cmd->flags & MMC_RSP_PRESENT) {
688 if (cmd->flags & MMC_RSP_136)
689 *cmd_cfg |= CMD_CFG_RESP_128;
690 *cmd_cfg |= CMD_CFG_RESP_NUM;
691
692 if (!(cmd->flags & MMC_RSP_CRC))
693 *cmd_cfg |= CMD_CFG_RESP_NOCRC;
694
695 if (cmd->flags & MMC_RSP_BUSY)
696 *cmd_cfg |= CMD_CFG_R1B;
697 } else {
698 *cmd_cfg |= CMD_CFG_NO_RESP;
699 }
700}
701
702static void meson_mmc_desc_chain_transfer(struct mmc_host *mmc, u32 cmd_cfg)
703{
704 struct meson_host *host = mmc_priv(mmc);
705 struct sd_emmc_desc *desc = host->descs;
706 struct mmc_data *data = host->cmd->data;
707 struct scatterlist *sg;
708 u32 start;
709 int i;
710
711 if (data->flags & MMC_DATA_WRITE)
712 cmd_cfg |= CMD_CFG_DATA_WR;
713
714 if (data->blocks > 1) {
715 cmd_cfg |= CMD_CFG_BLOCK_MODE;
716 meson_mmc_set_blksz(mmc, data->blksz);
717 }
718
719 for_each_sg(data->sg, sg, data->sg_count, i) {
720 unsigned int len = sg_dma_len(sg);
721
722 if (data->blocks > 1)
723 len /= data->blksz;
724
725 desc[i].cmd_cfg = cmd_cfg;
726 desc[i].cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, len);
727 if (i > 0)
728 desc[i].cmd_cfg |= CMD_CFG_NO_CMD;
729 desc[i].cmd_arg = host->cmd->arg;
730 desc[i].cmd_resp = 0;
731 desc[i].cmd_data = sg_dma_address(sg);
732 }
733 desc[data->sg_count - 1].cmd_cfg |= CMD_CFG_END_OF_CHAIN;
734
735 dma_wmb(); /* ensure descriptor is written before kicked */
736 start = host->descs_dma_addr | START_DESC_BUSY;
737 writel(start, host->regs + SD_EMMC_START);
738}
739
740static void meson_mmc_start_cmd(struct mmc_host *mmc, struct mmc_command *cmd)
741{
742 struct meson_host *host = mmc_priv(mmc);
743 struct mmc_data *data = cmd->data;
744 u32 cmd_cfg = 0, cmd_data = 0;
745 unsigned int xfer_bytes = 0;
746
747 /* Setup descriptors */
748 dma_rmb();
749
750 host->cmd = cmd;
751
752 cmd_cfg |= FIELD_PREP(CMD_CFG_CMD_INDEX_MASK, cmd->opcode);
753 cmd_cfg |= CMD_CFG_OWNER; /* owned by CPU */
754 cmd_cfg |= CMD_CFG_ERROR; /* stop in case of error */
755
756 meson_mmc_set_response_bits(cmd, &cmd_cfg);
757
758 /* data? */
759 if (data) {
760 data->bytes_xfered = 0;
761 cmd_cfg |= CMD_CFG_DATA_IO;
762 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
763 ilog2(meson_mmc_get_timeout_msecs(data)));
764
765 if (meson_mmc_desc_chain_mode(data)) {
766 meson_mmc_desc_chain_transfer(mmc, cmd_cfg);
767 return;
768 }
769
770 if (data->blocks > 1) {
771 cmd_cfg |= CMD_CFG_BLOCK_MODE;
772 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK,
773 data->blocks);
774 meson_mmc_set_blksz(mmc, data->blksz);
775 } else {
776 cmd_cfg |= FIELD_PREP(CMD_CFG_LENGTH_MASK, data->blksz);
777 }
778
779 xfer_bytes = data->blksz * data->blocks;
780 if (data->flags & MMC_DATA_WRITE) {
781 cmd_cfg |= CMD_CFG_DATA_WR;
782 WARN_ON(xfer_bytes > host->bounce_buf_size);
783 sg_copy_to_buffer(data->sg, data->sg_len,
784 host->bounce_buf, xfer_bytes);
785 dma_wmb();
786 }
787
788 cmd_data = host->bounce_dma_addr & CMD_DATA_MASK;
789 } else {
790 cmd_cfg |= FIELD_PREP(CMD_CFG_TIMEOUT_MASK,
791 ilog2(SD_EMMC_CMD_TIMEOUT));
792 }
793
794 /* Last descriptor */
795 cmd_cfg |= CMD_CFG_END_OF_CHAIN;
796 writel(cmd_cfg, host->regs + SD_EMMC_CMD_CFG);
797 writel(cmd_data, host->regs + SD_EMMC_CMD_DAT);
798 writel(0, host->regs + SD_EMMC_CMD_RSP);
799 wmb(); /* ensure descriptor is written before kicked */
800 writel(cmd->arg, host->regs + SD_EMMC_CMD_ARG);
801}
802
803static void meson_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
804{
805 struct meson_host *host = mmc_priv(mmc);
806 bool needs_pre_post_req = mrq->data &&
807 !(mrq->data->host_cookie & SD_EMMC_PRE_REQ_DONE);
808
809 if (needs_pre_post_req) {
810 meson_mmc_get_transfer_mode(mmc, mrq);
811 if (!meson_mmc_desc_chain_mode(mrq->data))
812 needs_pre_post_req = false;
813 }
814
815 if (needs_pre_post_req)
816 meson_mmc_pre_req(mmc, mrq);
817
818 /* Stop execution */
819 writel(0, host->regs + SD_EMMC_START);
820
821 meson_mmc_start_cmd(mmc, mrq->sbc ?: mrq->cmd);
822
823 if (needs_pre_post_req)
824 meson_mmc_post_req(mmc, mrq, 0);
825}
826
827static void meson_mmc_read_resp(struct mmc_host *mmc, struct mmc_command *cmd)
828{
829 struct meson_host *host = mmc_priv(mmc);
830
831 if (cmd->flags & MMC_RSP_136) {
832 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP3);
833 cmd->resp[1] = readl(host->regs + SD_EMMC_CMD_RSP2);
834 cmd->resp[2] = readl(host->regs + SD_EMMC_CMD_RSP1);
835 cmd->resp[3] = readl(host->regs + SD_EMMC_CMD_RSP);
836 } else if (cmd->flags & MMC_RSP_PRESENT) {
837 cmd->resp[0] = readl(host->regs + SD_EMMC_CMD_RSP);
838 }
839}
840
841static irqreturn_t meson_mmc_irq(int irq, void *dev_id)
842{
843 struct meson_host *host = dev_id;
844 struct mmc_command *cmd;
845 struct mmc_data *data;
846 u32 irq_en, status, raw_status;
847 irqreturn_t ret = IRQ_NONE;
848
849 irq_en = readl(host->regs + SD_EMMC_IRQ_EN);
850 raw_status = readl(host->regs + SD_EMMC_STATUS);
851 status = raw_status & irq_en;
852
853 if (!status) {
854 dev_dbg(host->dev,
855 "Unexpected IRQ! irq_en 0x%08x - status 0x%08x\n",
856 irq_en, raw_status);
857 return IRQ_NONE;
858 }
859
860 if (WARN_ON(!host) || WARN_ON(!host->cmd))
861 return IRQ_NONE;
862
863 /* ack all raised interrupts */
864 writel(status, host->regs + SD_EMMC_STATUS);
865
866 cmd = host->cmd;
867 data = cmd->data;
868 cmd->error = 0;
869 if (status & IRQ_CRC_ERR) {
870 dev_dbg(host->dev, "CRC Error - status 0x%08x\n", status);
871 cmd->error = -EILSEQ;
872 ret = IRQ_WAKE_THREAD;
873 goto out;
874 }
875
876 if (status & IRQ_TIMEOUTS) {
877 dev_dbg(host->dev, "Timeout - status 0x%08x\n", status);
878 cmd->error = -ETIMEDOUT;
879 ret = IRQ_WAKE_THREAD;
880 goto out;
881 }
882
883 meson_mmc_read_resp(host->mmc, cmd);
884
885 if (status & IRQ_SDIO) {
886 dev_dbg(host->dev, "IRQ: SDIO TODO.\n");
887 ret = IRQ_HANDLED;
888 }
889
890 if (status & (IRQ_END_OF_CHAIN | IRQ_RESP_STATUS)) {
891 if (data && !cmd->error)
892 data->bytes_xfered = data->blksz * data->blocks;
893 if (meson_mmc_bounce_buf_read(data) ||
894 meson_mmc_get_next_command(cmd))
895 ret = IRQ_WAKE_THREAD;
896 else
897 ret = IRQ_HANDLED;
898 }
899
900out:
901 if (cmd->error) {
902 /* Stop desc in case of errors */
903 u32 start = readl(host->regs + SD_EMMC_START);
904
905 start &= ~START_DESC_BUSY;
906 writel(start, host->regs + SD_EMMC_START);
907 }
908
909 if (ret == IRQ_HANDLED)
910 meson_mmc_request_done(host->mmc, cmd->mrq);
911
912 return ret;
913}
914
915static int meson_mmc_wait_desc_stop(struct meson_host *host)
916{
917 u32 status;
918
919 /*
920 * It may sometimes take a while for it to actually halt. Here, we
921 * are giving it 5ms to comply
922 *
923 * If we don't confirm the descriptor is stopped, it might raise new
924 * IRQs after we have called mmc_request_done() which is bad.
925 */
926
927 return readl_poll_timeout(host->regs + SD_EMMC_STATUS, status,
928 !(status & (STATUS_BUSY | STATUS_DESC_BUSY)),
929 100, 5000);
930}
931
932static irqreturn_t meson_mmc_irq_thread(int irq, void *dev_id)
933{
934 struct meson_host *host = dev_id;
935 struct mmc_command *next_cmd, *cmd = host->cmd;
936 struct mmc_data *data;
937 unsigned int xfer_bytes;
938
939 if (WARN_ON(!cmd))
940 return IRQ_NONE;
941
942 if (cmd->error) {
943 meson_mmc_wait_desc_stop(host);
944 meson_mmc_request_done(host->mmc, cmd->mrq);
945
946 return IRQ_HANDLED;
947 }
948
949 data = cmd->data;
950 if (meson_mmc_bounce_buf_read(data)) {
951 xfer_bytes = data->blksz * data->blocks;
952 WARN_ON(xfer_bytes > host->bounce_buf_size);
953 sg_copy_from_buffer(data->sg, data->sg_len,
954 host->bounce_buf, xfer_bytes);
955 }
956
957 next_cmd = meson_mmc_get_next_command(cmd);
958 if (next_cmd)
959 meson_mmc_start_cmd(host->mmc, next_cmd);
960 else
961 meson_mmc_request_done(host->mmc, cmd->mrq);
962
963 return IRQ_HANDLED;
964}
965
966/*
967 * NOTE: we only need this until the GPIO/pinctrl driver can handle
968 * interrupts. For now, the MMC core will use this for polling.
969 */
970static int meson_mmc_get_cd(struct mmc_host *mmc)
971{
972 int status = mmc_gpio_get_cd(mmc);
973
974 if (status == -ENOSYS)
975 return 1; /* assume present */
976
977 return status;
978}
979
980static void meson_mmc_cfg_init(struct meson_host *host)
981{
982 u32 cfg = 0;
983
984 cfg |= FIELD_PREP(CFG_RESP_TIMEOUT_MASK,
985 ilog2(SD_EMMC_CFG_RESP_TIMEOUT));
986 cfg |= FIELD_PREP(CFG_RC_CC_MASK, ilog2(SD_EMMC_CFG_CMD_GAP));
987 cfg |= FIELD_PREP(CFG_BLK_LEN_MASK, ilog2(SD_EMMC_CFG_BLK_SIZE));
988
989 /* abort chain on R/W errors */
990 cfg |= CFG_ERR_ABORT;
991
992 writel(cfg, host->regs + SD_EMMC_CFG);
993}
994
995static int meson_mmc_card_busy(struct mmc_host *mmc)
996{
997 struct meson_host *host = mmc_priv(mmc);
998 u32 regval;
999
1000 regval = readl(host->regs + SD_EMMC_STATUS);
1001
1002 /* We are only interrested in lines 0 to 3, so mask the other ones */
1003 return !(FIELD_GET(STATUS_DATI, regval) & 0xf);
1004}
1005
1006static int meson_mmc_voltage_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1007{
1008 /* vqmmc regulator is available */
1009 if (!IS_ERR(mmc->supply.vqmmc)) {
1010 /*
1011 * The usual amlogic setup uses a GPIO to switch from one
1012 * regulator to the other. While the voltage ramp up is
1013 * pretty fast, care must be taken when switching from 3.3v
1014 * to 1.8v. Please make sure the regulator framework is aware
1015 * of your own regulator constraints
1016 */
1017 return mmc_regulator_set_vqmmc(mmc, ios);
1018 }
1019
1020 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */
1021 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330)
1022 return 0;
1023
1024 return -EINVAL;
1025}
1026
1027static const struct mmc_host_ops meson_mmc_ops = {
1028 .request = meson_mmc_request,
1029 .set_ios = meson_mmc_set_ios,
1030 .get_cd = meson_mmc_get_cd,
1031 .pre_req = meson_mmc_pre_req,
1032 .post_req = meson_mmc_post_req,
1033 .execute_tuning = meson_mmc_resampling_tuning,
1034 .card_busy = meson_mmc_card_busy,
1035 .start_signal_voltage_switch = meson_mmc_voltage_switch,
1036};
1037
1038static int meson_mmc_probe(struct platform_device *pdev)
1039{
1040 struct resource *res;
1041 struct meson_host *host;
1042 struct mmc_host *mmc;
1043 int ret;
1044
1045 mmc = mmc_alloc_host(sizeof(struct meson_host), &pdev->dev);
1046 if (!mmc)
1047 return -ENOMEM;
1048 host = mmc_priv(mmc);
1049 host->mmc = mmc;
1050 host->dev = &pdev->dev;
1051 dev_set_drvdata(&pdev->dev, host);
1052
1053 /* The G12A SDIO Controller needs an SRAM bounce buffer */
1054 host->dram_access_quirk = device_property_read_bool(&pdev->dev,
1055 "amlogic,dram-access-quirk");
1056
1057 /* Get regulators and the supported OCR mask */
1058 host->vqmmc_enabled = false;
1059 ret = mmc_regulator_get_supply(mmc);
1060 if (ret)
1061 goto free_host;
1062
1063 ret = mmc_of_parse(mmc);
1064 if (ret) {
1065 if (ret != -EPROBE_DEFER)
1066 dev_warn(&pdev->dev, "error parsing DT: %d\n", ret);
1067 goto free_host;
1068 }
1069
1070 host->data = (struct meson_mmc_data *)
1071 of_device_get_match_data(&pdev->dev);
1072 if (!host->data) {
1073 ret = -EINVAL;
1074 goto free_host;
1075 }
1076
1077 ret = device_reset_optional(&pdev->dev);
1078 if (ret) {
1079 if (ret != -EPROBE_DEFER)
1080 dev_err(&pdev->dev, "device reset failed: %d\n", ret);
1081
1082 return ret;
1083 }
1084
1085 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1086 host->regs = devm_ioremap_resource(&pdev->dev, res);
1087 if (IS_ERR(host->regs)) {
1088 ret = PTR_ERR(host->regs);
1089 goto free_host;
1090 }
1091
1092 host->irq = platform_get_irq(pdev, 0);
1093 if (host->irq <= 0) {
1094 ret = -EINVAL;
1095 goto free_host;
1096 }
1097
1098 host->pinctrl = devm_pinctrl_get(&pdev->dev);
1099 if (IS_ERR(host->pinctrl)) {
1100 ret = PTR_ERR(host->pinctrl);
1101 goto free_host;
1102 }
1103
1104 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1105 PINCTRL_STATE_DEFAULT);
1106 if (IS_ERR(host->pins_default)) {
1107 ret = PTR_ERR(host->pins_default);
1108 goto free_host;
1109 }
1110
1111 host->pins_clk_gate = pinctrl_lookup_state(host->pinctrl,
1112 "clk-gate");
1113 if (IS_ERR(host->pins_clk_gate)) {
1114 dev_warn(&pdev->dev,
1115 "can't get clk-gate pinctrl, using clk_stop bit\n");
1116 host->pins_clk_gate = NULL;
1117 }
1118
1119 host->core_clk = devm_clk_get(&pdev->dev, "core");
1120 if (IS_ERR(host->core_clk)) {
1121 ret = PTR_ERR(host->core_clk);
1122 goto free_host;
1123 }
1124
1125 ret = clk_prepare_enable(host->core_clk);
1126 if (ret)
1127 goto free_host;
1128
1129 ret = meson_mmc_clk_init(host);
1130 if (ret)
1131 goto err_core_clk;
1132
1133 /* set config to sane default */
1134 meson_mmc_cfg_init(host);
1135
1136 /* Stop execution */
1137 writel(0, host->regs + SD_EMMC_START);
1138
1139 /* clear, ack and enable interrupts */
1140 writel(0, host->regs + SD_EMMC_IRQ_EN);
1141 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1142 host->regs + SD_EMMC_STATUS);
1143 writel(IRQ_CRC_ERR | IRQ_TIMEOUTS | IRQ_END_OF_CHAIN,
1144 host->regs + SD_EMMC_IRQ_EN);
1145
1146 ret = request_threaded_irq(host->irq, meson_mmc_irq,
1147 meson_mmc_irq_thread, IRQF_ONESHOT,
1148 dev_name(&pdev->dev), host);
1149 if (ret)
1150 goto err_init_clk;
1151
1152 mmc->caps |= MMC_CAP_CMD23;
1153 if (host->dram_access_quirk) {
1154 /* Limit to the available sram memory */
1155 mmc->max_segs = SD_EMMC_SRAM_DATA_BUF_LEN / mmc->max_blk_size;
1156 mmc->max_blk_count = mmc->max_segs;
1157 } else {
1158 mmc->max_blk_count = CMD_CFG_LENGTH_MASK;
1159 mmc->max_segs = SD_EMMC_DESC_BUF_LEN /
1160 sizeof(struct sd_emmc_desc);
1161 }
1162 mmc->max_req_size = mmc->max_blk_count * mmc->max_blk_size;
1163 mmc->max_seg_size = mmc->max_req_size;
1164
1165 /*
1166 * At the moment, we don't know how to reliably enable HS400.
1167 * From the different datasheets, it is not even clear if this mode
1168 * is officially supported by any of the SoCs
1169 */
1170 mmc->caps2 &= ~MMC_CAP2_HS400;
1171
1172 if (host->dram_access_quirk) {
1173 /*
1174 * The MMC Controller embeds 1,5KiB of internal SRAM
1175 * that can be used to be used as bounce buffer.
1176 * In the case of the G12A SDIO controller, use these
1177 * instead of the DDR memory
1178 */
1179 host->bounce_buf_size = SD_EMMC_SRAM_DATA_BUF_LEN;
1180 host->bounce_buf = host->regs + SD_EMMC_SRAM_DATA_BUF_OFF;
1181 host->bounce_dma_addr = res->start + SD_EMMC_SRAM_DATA_BUF_OFF;
1182 } else {
1183 /* data bounce buffer */
1184 host->bounce_buf_size = mmc->max_req_size;
1185 host->bounce_buf =
1186 dma_alloc_coherent(host->dev, host->bounce_buf_size,
1187 &host->bounce_dma_addr, GFP_KERNEL);
1188 if (host->bounce_buf == NULL) {
1189 dev_err(host->dev, "Unable to map allocate DMA bounce buffer.\n");
1190 ret = -ENOMEM;
1191 goto err_free_irq;
1192 }
1193 }
1194
1195 host->descs = dma_alloc_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1196 &host->descs_dma_addr, GFP_KERNEL);
1197 if (!host->descs) {
1198 dev_err(host->dev, "Allocating descriptor DMA buffer failed\n");
1199 ret = -ENOMEM;
1200 goto err_bounce_buf;
1201 }
1202
1203 mmc->ops = &meson_mmc_ops;
1204 mmc_add_host(mmc);
1205
1206 return 0;
1207
1208err_bounce_buf:
1209 if (!host->dram_access_quirk)
1210 dma_free_coherent(host->dev, host->bounce_buf_size,
1211 host->bounce_buf, host->bounce_dma_addr);
1212err_free_irq:
1213 free_irq(host->irq, host);
1214err_init_clk:
1215 clk_disable_unprepare(host->mmc_clk);
1216err_core_clk:
1217 clk_disable_unprepare(host->core_clk);
1218free_host:
1219 mmc_free_host(mmc);
1220 return ret;
1221}
1222
1223static int meson_mmc_remove(struct platform_device *pdev)
1224{
1225 struct meson_host *host = dev_get_drvdata(&pdev->dev);
1226
1227 mmc_remove_host(host->mmc);
1228
1229 /* disable interrupts */
1230 writel(0, host->regs + SD_EMMC_IRQ_EN);
1231 free_irq(host->irq, host);
1232
1233 dma_free_coherent(host->dev, SD_EMMC_DESC_BUF_LEN,
1234 host->descs, host->descs_dma_addr);
1235
1236 if (!host->dram_access_quirk)
1237 dma_free_coherent(host->dev, host->bounce_buf_size,
1238 host->bounce_buf, host->bounce_dma_addr);
1239
1240 clk_disable_unprepare(host->mmc_clk);
1241 clk_disable_unprepare(host->core_clk);
1242
1243 mmc_free_host(host->mmc);
1244 return 0;
1245}
1246
1247static const struct meson_mmc_data meson_gx_data = {
1248 .tx_delay_mask = CLK_V2_TX_DELAY_MASK,
1249 .rx_delay_mask = CLK_V2_RX_DELAY_MASK,
1250 .always_on = CLK_V2_ALWAYS_ON,
1251 .adjust = SD_EMMC_ADJUST,
1252};
1253
1254static const struct meson_mmc_data meson_axg_data = {
1255 .tx_delay_mask = CLK_V3_TX_DELAY_MASK,
1256 .rx_delay_mask = CLK_V3_RX_DELAY_MASK,
1257 .always_on = CLK_V3_ALWAYS_ON,
1258 .adjust = SD_EMMC_V3_ADJUST,
1259};
1260
1261static const struct of_device_id meson_mmc_of_match[] = {
1262 { .compatible = "amlogic,meson-gx-mmc", .data = &meson_gx_data },
1263 { .compatible = "amlogic,meson-gxbb-mmc", .data = &meson_gx_data },
1264 { .compatible = "amlogic,meson-gxl-mmc", .data = &meson_gx_data },
1265 { .compatible = "amlogic,meson-gxm-mmc", .data = &meson_gx_data },
1266 { .compatible = "amlogic,meson-axg-mmc", .data = &meson_axg_data },
1267 {}
1268};
1269MODULE_DEVICE_TABLE(of, meson_mmc_of_match);
1270
1271static struct platform_driver meson_mmc_driver = {
1272 .probe = meson_mmc_probe,
1273 .remove = meson_mmc_remove,
1274 .driver = {
1275 .name = DRIVER_NAME,
1276 .of_match_table = of_match_ptr(meson_mmc_of_match),
1277 },
1278};
1279
1280module_platform_driver(meson_mmc_driver);
1281
1282MODULE_DESCRIPTION("Amlogic S905*/GX*/AXG SD/eMMC driver");
1283MODULE_AUTHOR("Kevin Hilman <khilman@baylibre.com>");
1284MODULE_LICENSE("GPL v2");