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1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Christian König <christian.koenig@amd.com>
29 */
30
31#include <linux/firmware.h>
32#include <linux/module.h>
33#include <linux/mmu_notifier.h>
34#include <linux/interval_tree.h>
35#include <drm/drmP.h>
36#include <drm/drm.h>
37
38#include "amdgpu.h"
39
40struct amdgpu_mn {
41 /* constant after initialisation */
42 struct amdgpu_device *adev;
43 struct mm_struct *mm;
44 struct mmu_notifier mn;
45
46 /* only used on destruction */
47 struct work_struct work;
48
49 /* protected by adev->mn_lock */
50 struct hlist_node node;
51
52 /* objects protected by lock */
53 struct rw_semaphore lock;
54 struct rb_root_cached objects;
55 struct mutex read_lock;
56 atomic_t recursion;
57};
58
59struct amdgpu_mn_node {
60 struct interval_tree_node it;
61 struct list_head bos;
62};
63
64/**
65 * amdgpu_mn_destroy - destroy the rmn
66 *
67 * @work: previously sheduled work item
68 *
69 * Lazy destroys the notifier from a work item
70 */
71static void amdgpu_mn_destroy(struct work_struct *work)
72{
73 struct amdgpu_mn *rmn = container_of(work, struct amdgpu_mn, work);
74 struct amdgpu_device *adev = rmn->adev;
75 struct amdgpu_mn_node *node, *next_node;
76 struct amdgpu_bo *bo, *next_bo;
77
78 mutex_lock(&adev->mn_lock);
79 down_write(&rmn->lock);
80 hash_del(&rmn->node);
81 rbtree_postorder_for_each_entry_safe(node, next_node,
82 &rmn->objects.rb_root, it.rb) {
83 list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) {
84 bo->mn = NULL;
85 list_del_init(&bo->mn_list);
86 }
87 kfree(node);
88 }
89 up_write(&rmn->lock);
90 mutex_unlock(&adev->mn_lock);
91 mmu_notifier_unregister_no_release(&rmn->mn, rmn->mm);
92 kfree(rmn);
93}
94
95/**
96 * amdgpu_mn_release - callback to notify about mm destruction
97 *
98 * @mn: our notifier
99 * @mn: the mm this callback is about
100 *
101 * Shedule a work item to lazy destroy our notifier.
102 */
103static void amdgpu_mn_release(struct mmu_notifier *mn,
104 struct mm_struct *mm)
105{
106 struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
107 INIT_WORK(&rmn->work, amdgpu_mn_destroy);
108 schedule_work(&rmn->work);
109}
110
111
112/**
113 * amdgpu_mn_lock - take the write side lock for this mn
114 */
115void amdgpu_mn_lock(struct amdgpu_mn *mn)
116{
117 if (mn)
118 down_write(&mn->lock);
119}
120
121/**
122 * amdgpu_mn_unlock - drop the write side lock for this mn
123 */
124void amdgpu_mn_unlock(struct amdgpu_mn *mn)
125{
126 if (mn)
127 up_write(&mn->lock);
128}
129
130/**
131 * amdgpu_mn_read_lock - take the rmn read lock
132 *
133 * @rmn: our notifier
134 *
135 * Take the rmn read side lock.
136 */
137static void amdgpu_mn_read_lock(struct amdgpu_mn *rmn)
138{
139 mutex_lock(&rmn->read_lock);
140 if (atomic_inc_return(&rmn->recursion) == 1)
141 down_read_non_owner(&rmn->lock);
142 mutex_unlock(&rmn->read_lock);
143}
144
145/**
146 * amdgpu_mn_read_unlock - drop the rmn read lock
147 *
148 * @rmn: our notifier
149 *
150 * Drop the rmn read side lock.
151 */
152static void amdgpu_mn_read_unlock(struct amdgpu_mn *rmn)
153{
154 if (atomic_dec_return(&rmn->recursion) == 0)
155 up_read_non_owner(&rmn->lock);
156}
157
158/**
159 * amdgpu_mn_invalidate_node - unmap all BOs of a node
160 *
161 * @node: the node with the BOs to unmap
162 *
163 * We block for all BOs and unmap them by move them
164 * into system domain again.
165 */
166static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node,
167 unsigned long start,
168 unsigned long end)
169{
170 struct amdgpu_bo *bo;
171 long r;
172
173 list_for_each_entry(bo, &node->bos, mn_list) {
174
175 if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end))
176 continue;
177
178 r = reservation_object_wait_timeout_rcu(bo->tbo.resv,
179 true, false, MAX_SCHEDULE_TIMEOUT);
180 if (r <= 0)
181 DRM_ERROR("(%ld) failed to wait for user bo\n", r);
182
183 amdgpu_ttm_tt_mark_user_pages(bo->tbo.ttm);
184 }
185}
186
187/**
188 * amdgpu_mn_invalidate_range_start - callback to notify about mm change
189 *
190 * @mn: our notifier
191 * @mn: the mm this callback is about
192 * @start: start of updated range
193 * @end: end of updated range
194 *
195 * We block for all BOs between start and end to be idle and
196 * unmap them by move them into system domain again.
197 */
198static void amdgpu_mn_invalidate_range_start(struct mmu_notifier *mn,
199 struct mm_struct *mm,
200 unsigned long start,
201 unsigned long end)
202{
203 struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
204 struct interval_tree_node *it;
205
206 /* notification is exclusive, but interval is inclusive */
207 end -= 1;
208
209 amdgpu_mn_read_lock(rmn);
210
211 it = interval_tree_iter_first(&rmn->objects, start, end);
212 while (it) {
213 struct amdgpu_mn_node *node;
214
215 node = container_of(it, struct amdgpu_mn_node, it);
216 it = interval_tree_iter_next(it, start, end);
217
218 amdgpu_mn_invalidate_node(node, start, end);
219 }
220}
221
222/**
223 * amdgpu_mn_invalidate_range_end - callback to notify about mm change
224 *
225 * @mn: our notifier
226 * @mn: the mm this callback is about
227 * @start: start of updated range
228 * @end: end of updated range
229 *
230 * Release the lock again to allow new command submissions.
231 */
232static void amdgpu_mn_invalidate_range_end(struct mmu_notifier *mn,
233 struct mm_struct *mm,
234 unsigned long start,
235 unsigned long end)
236{
237 struct amdgpu_mn *rmn = container_of(mn, struct amdgpu_mn, mn);
238
239 amdgpu_mn_read_unlock(rmn);
240}
241
242static const struct mmu_notifier_ops amdgpu_mn_ops = {
243 .release = amdgpu_mn_release,
244 .invalidate_range_start = amdgpu_mn_invalidate_range_start,
245 .invalidate_range_end = amdgpu_mn_invalidate_range_end,
246};
247
248/**
249 * amdgpu_mn_get - create notifier context
250 *
251 * @adev: amdgpu device pointer
252 *
253 * Creates a notifier context for current->mm.
254 */
255struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev)
256{
257 struct mm_struct *mm = current->mm;
258 struct amdgpu_mn *rmn;
259 int r;
260
261 mutex_lock(&adev->mn_lock);
262 if (down_write_killable(&mm->mmap_sem)) {
263 mutex_unlock(&adev->mn_lock);
264 return ERR_PTR(-EINTR);
265 }
266
267 hash_for_each_possible(adev->mn_hash, rmn, node, (unsigned long)mm)
268 if (rmn->mm == mm)
269 goto release_locks;
270
271 rmn = kzalloc(sizeof(*rmn), GFP_KERNEL);
272 if (!rmn) {
273 rmn = ERR_PTR(-ENOMEM);
274 goto release_locks;
275 }
276
277 rmn->adev = adev;
278 rmn->mm = mm;
279 rmn->mn.ops = &amdgpu_mn_ops;
280 init_rwsem(&rmn->lock);
281 rmn->objects = RB_ROOT_CACHED;
282 mutex_init(&rmn->read_lock);
283 atomic_set(&rmn->recursion, 0);
284
285 r = __mmu_notifier_register(&rmn->mn, mm);
286 if (r)
287 goto free_rmn;
288
289 hash_add(adev->mn_hash, &rmn->node, (unsigned long)mm);
290
291release_locks:
292 up_write(&mm->mmap_sem);
293 mutex_unlock(&adev->mn_lock);
294
295 return rmn;
296
297free_rmn:
298 up_write(&mm->mmap_sem);
299 mutex_unlock(&adev->mn_lock);
300 kfree(rmn);
301
302 return ERR_PTR(r);
303}
304
305/**
306 * amdgpu_mn_register - register a BO for notifier updates
307 *
308 * @bo: amdgpu buffer object
309 * @addr: userptr addr we should monitor
310 *
311 * Registers an MMU notifier for the given BO at the specified address.
312 * Returns 0 on success, -ERRNO if anything goes wrong.
313 */
314int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
315{
316 unsigned long end = addr + amdgpu_bo_size(bo) - 1;
317 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
318 struct amdgpu_mn *rmn;
319 struct amdgpu_mn_node *node = NULL;
320 struct list_head bos;
321 struct interval_tree_node *it;
322
323 rmn = amdgpu_mn_get(adev);
324 if (IS_ERR(rmn))
325 return PTR_ERR(rmn);
326
327 INIT_LIST_HEAD(&bos);
328
329 down_write(&rmn->lock);
330
331 while ((it = interval_tree_iter_first(&rmn->objects, addr, end))) {
332 kfree(node);
333 node = container_of(it, struct amdgpu_mn_node, it);
334 interval_tree_remove(&node->it, &rmn->objects);
335 addr = min(it->start, addr);
336 end = max(it->last, end);
337 list_splice(&node->bos, &bos);
338 }
339
340 if (!node) {
341 node = kmalloc(sizeof(struct amdgpu_mn_node), GFP_KERNEL);
342 if (!node) {
343 up_write(&rmn->lock);
344 return -ENOMEM;
345 }
346 }
347
348 bo->mn = rmn;
349
350 node->it.start = addr;
351 node->it.last = end;
352 INIT_LIST_HEAD(&node->bos);
353 list_splice(&bos, &node->bos);
354 list_add(&bo->mn_list, &node->bos);
355
356 interval_tree_insert(&node->it, &rmn->objects);
357
358 up_write(&rmn->lock);
359
360 return 0;
361}
362
363/**
364 * amdgpu_mn_unregister - unregister a BO for notifier updates
365 *
366 * @bo: amdgpu buffer object
367 *
368 * Remove any registration of MMU notifier updates from the buffer object.
369 */
370void amdgpu_mn_unregister(struct amdgpu_bo *bo)
371{
372 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
373 struct amdgpu_mn *rmn;
374 struct list_head *head;
375
376 mutex_lock(&adev->mn_lock);
377
378 rmn = bo->mn;
379 if (rmn == NULL) {
380 mutex_unlock(&adev->mn_lock);
381 return;
382 }
383
384 down_write(&rmn->lock);
385
386 /* save the next list entry for later */
387 head = bo->mn_list.next;
388
389 bo->mn = NULL;
390 list_del_init(&bo->mn_list);
391
392 if (list_empty(head)) {
393 struct amdgpu_mn_node *node;
394 node = container_of(head, struct amdgpu_mn_node, bos);
395 interval_tree_remove(&node->it, &rmn->objects);
396 kfree(node);
397 }
398
399 up_write(&rmn->lock);
400 mutex_unlock(&adev->mn_lock);
401}
402
1/*
2 * Copyright 2014 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Christian König <christian.koenig@amd.com>
29 */
30
31/**
32 * DOC: MMU Notifier
33 *
34 * For coherent userptr handling registers an MMU notifier to inform the driver
35 * about updates on the page tables of a process.
36 *
37 * When somebody tries to invalidate the page tables we block the update until
38 * all operations on the pages in question are completed, then those pages are
39 * marked as accessed and also dirty if it wasn't a read only access.
40 *
41 * New command submissions using the userptrs in question are delayed until all
42 * page table invalidation are completed and we once more see a coherent process
43 * address space.
44 */
45
46#include <linux/firmware.h>
47#include <linux/module.h>
48#include <drm/drm.h>
49
50#include "amdgpu.h"
51#include "amdgpu_amdkfd.h"
52
53/**
54 * struct amdgpu_mn_node
55 *
56 * @it: interval node defining start-last of the affected address range
57 * @bos: list of all BOs in the affected address range
58 *
59 * Manages all BOs which are affected of a certain range of address space.
60 */
61struct amdgpu_mn_node {
62 struct interval_tree_node it;
63 struct list_head bos;
64};
65
66/**
67 * amdgpu_mn_destroy - destroy the HMM mirror
68 *
69 * @work: previously sheduled work item
70 *
71 * Lazy destroys the notifier from a work item
72 */
73static void amdgpu_mn_destroy(struct work_struct *work)
74{
75 struct amdgpu_mn *amn = container_of(work, struct amdgpu_mn, work);
76 struct amdgpu_device *adev = amn->adev;
77 struct amdgpu_mn_node *node, *next_node;
78 struct amdgpu_bo *bo, *next_bo;
79
80 mutex_lock(&adev->mn_lock);
81 down_write(&amn->lock);
82 hash_del(&amn->node);
83 rbtree_postorder_for_each_entry_safe(node, next_node,
84 &amn->objects.rb_root, it.rb) {
85 list_for_each_entry_safe(bo, next_bo, &node->bos, mn_list) {
86 bo->mn = NULL;
87 list_del_init(&bo->mn_list);
88 }
89 kfree(node);
90 }
91 up_write(&amn->lock);
92 mutex_unlock(&adev->mn_lock);
93
94 hmm_mirror_unregister(&amn->mirror);
95 kfree(amn);
96}
97
98/**
99 * amdgpu_hmm_mirror_release - callback to notify about mm destruction
100 *
101 * @mirror: the HMM mirror (mm) this callback is about
102 *
103 * Shedule a work item to lazy destroy HMM mirror.
104 */
105static void amdgpu_hmm_mirror_release(struct hmm_mirror *mirror)
106{
107 struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
108
109 INIT_WORK(&amn->work, amdgpu_mn_destroy);
110 schedule_work(&amn->work);
111}
112
113/**
114 * amdgpu_mn_lock - take the write side lock for this notifier
115 *
116 * @mn: our notifier
117 */
118void amdgpu_mn_lock(struct amdgpu_mn *mn)
119{
120 if (mn)
121 down_write(&mn->lock);
122}
123
124/**
125 * amdgpu_mn_unlock - drop the write side lock for this notifier
126 *
127 * @mn: our notifier
128 */
129void amdgpu_mn_unlock(struct amdgpu_mn *mn)
130{
131 if (mn)
132 up_write(&mn->lock);
133}
134
135/**
136 * amdgpu_mn_read_lock - take the read side lock for this notifier
137 *
138 * @amn: our notifier
139 */
140static int amdgpu_mn_read_lock(struct amdgpu_mn *amn, bool blockable)
141{
142 if (blockable)
143 down_read(&amn->lock);
144 else if (!down_read_trylock(&amn->lock))
145 return -EAGAIN;
146
147 return 0;
148}
149
150/**
151 * amdgpu_mn_read_unlock - drop the read side lock for this notifier
152 *
153 * @amn: our notifier
154 */
155static void amdgpu_mn_read_unlock(struct amdgpu_mn *amn)
156{
157 up_read(&amn->lock);
158}
159
160/**
161 * amdgpu_mn_invalidate_node - unmap all BOs of a node
162 *
163 * @node: the node with the BOs to unmap
164 * @start: start of address range affected
165 * @end: end of address range affected
166 *
167 * Block for operations on BOs to finish and mark pages as accessed and
168 * potentially dirty.
169 */
170static void amdgpu_mn_invalidate_node(struct amdgpu_mn_node *node,
171 unsigned long start,
172 unsigned long end)
173{
174 struct amdgpu_bo *bo;
175 long r;
176
177 list_for_each_entry(bo, &node->bos, mn_list) {
178
179 if (!amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm, start, end))
180 continue;
181
182 r = dma_resv_wait_timeout_rcu(bo->tbo.base.resv,
183 true, false, MAX_SCHEDULE_TIMEOUT);
184 if (r <= 0)
185 DRM_ERROR("(%ld) failed to wait for user bo\n", r);
186 }
187}
188
189/**
190 * amdgpu_mn_sync_pagetables_gfx - callback to notify about mm change
191 *
192 * @mirror: the hmm_mirror (mm) is about to update
193 * @update: the update start, end address
194 *
195 * Block for operations on BOs to finish and mark pages as accessed and
196 * potentially dirty.
197 */
198static int
199amdgpu_mn_sync_pagetables_gfx(struct hmm_mirror *mirror,
200 const struct mmu_notifier_range *update)
201{
202 struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
203 unsigned long start = update->start;
204 unsigned long end = update->end;
205 bool blockable = mmu_notifier_range_blockable(update);
206 struct interval_tree_node *it;
207
208 /* notification is exclusive, but interval is inclusive */
209 end -= 1;
210
211 /* TODO we should be able to split locking for interval tree and
212 * amdgpu_mn_invalidate_node
213 */
214 if (amdgpu_mn_read_lock(amn, blockable))
215 return -EAGAIN;
216
217 it = interval_tree_iter_first(&amn->objects, start, end);
218 while (it) {
219 struct amdgpu_mn_node *node;
220
221 if (!blockable) {
222 amdgpu_mn_read_unlock(amn);
223 return -EAGAIN;
224 }
225
226 node = container_of(it, struct amdgpu_mn_node, it);
227 it = interval_tree_iter_next(it, start, end);
228
229 amdgpu_mn_invalidate_node(node, start, end);
230 }
231
232 amdgpu_mn_read_unlock(amn);
233
234 return 0;
235}
236
237/**
238 * amdgpu_mn_sync_pagetables_hsa - callback to notify about mm change
239 *
240 * @mirror: the hmm_mirror (mm) is about to update
241 * @update: the update start, end address
242 *
243 * We temporarily evict all BOs between start and end. This
244 * necessitates evicting all user-mode queues of the process. The BOs
245 * are restorted in amdgpu_mn_invalidate_range_end_hsa.
246 */
247static int
248amdgpu_mn_sync_pagetables_hsa(struct hmm_mirror *mirror,
249 const struct mmu_notifier_range *update)
250{
251 struct amdgpu_mn *amn = container_of(mirror, struct amdgpu_mn, mirror);
252 unsigned long start = update->start;
253 unsigned long end = update->end;
254 bool blockable = mmu_notifier_range_blockable(update);
255 struct interval_tree_node *it;
256
257 /* notification is exclusive, but interval is inclusive */
258 end -= 1;
259
260 if (amdgpu_mn_read_lock(amn, blockable))
261 return -EAGAIN;
262
263 it = interval_tree_iter_first(&amn->objects, start, end);
264 while (it) {
265 struct amdgpu_mn_node *node;
266 struct amdgpu_bo *bo;
267
268 if (!blockable) {
269 amdgpu_mn_read_unlock(amn);
270 return -EAGAIN;
271 }
272
273 node = container_of(it, struct amdgpu_mn_node, it);
274 it = interval_tree_iter_next(it, start, end);
275
276 list_for_each_entry(bo, &node->bos, mn_list) {
277 struct kgd_mem *mem = bo->kfd_bo;
278
279 if (amdgpu_ttm_tt_affect_userptr(bo->tbo.ttm,
280 start, end))
281 amdgpu_amdkfd_evict_userptr(mem, amn->mm);
282 }
283 }
284
285 amdgpu_mn_read_unlock(amn);
286
287 return 0;
288}
289
290/* Low bits of any reasonable mm pointer will be unused due to struct
291 * alignment. Use these bits to make a unique key from the mm pointer
292 * and notifier type.
293 */
294#define AMDGPU_MN_KEY(mm, type) ((unsigned long)(mm) + (type))
295
296static struct hmm_mirror_ops amdgpu_hmm_mirror_ops[] = {
297 [AMDGPU_MN_TYPE_GFX] = {
298 .sync_cpu_device_pagetables = amdgpu_mn_sync_pagetables_gfx,
299 .release = amdgpu_hmm_mirror_release
300 },
301 [AMDGPU_MN_TYPE_HSA] = {
302 .sync_cpu_device_pagetables = amdgpu_mn_sync_pagetables_hsa,
303 .release = amdgpu_hmm_mirror_release
304 },
305};
306
307/**
308 * amdgpu_mn_get - create HMM mirror context
309 *
310 * @adev: amdgpu device pointer
311 * @type: type of MMU notifier context
312 *
313 * Creates a HMM mirror context for current->mm.
314 */
315struct amdgpu_mn *amdgpu_mn_get(struct amdgpu_device *adev,
316 enum amdgpu_mn_type type)
317{
318 struct mm_struct *mm = current->mm;
319 struct amdgpu_mn *amn;
320 unsigned long key = AMDGPU_MN_KEY(mm, type);
321 int r;
322
323 mutex_lock(&adev->mn_lock);
324 if (down_write_killable(&mm->mmap_sem)) {
325 mutex_unlock(&adev->mn_lock);
326 return ERR_PTR(-EINTR);
327 }
328
329 hash_for_each_possible(adev->mn_hash, amn, node, key)
330 if (AMDGPU_MN_KEY(amn->mm, amn->type) == key)
331 goto release_locks;
332
333 amn = kzalloc(sizeof(*amn), GFP_KERNEL);
334 if (!amn) {
335 amn = ERR_PTR(-ENOMEM);
336 goto release_locks;
337 }
338
339 amn->adev = adev;
340 amn->mm = mm;
341 init_rwsem(&amn->lock);
342 amn->type = type;
343 amn->objects = RB_ROOT_CACHED;
344
345 amn->mirror.ops = &amdgpu_hmm_mirror_ops[type];
346 r = hmm_mirror_register(&amn->mirror, mm);
347 if (r)
348 goto free_amn;
349
350 hash_add(adev->mn_hash, &amn->node, AMDGPU_MN_KEY(mm, type));
351
352release_locks:
353 up_write(&mm->mmap_sem);
354 mutex_unlock(&adev->mn_lock);
355
356 return amn;
357
358free_amn:
359 up_write(&mm->mmap_sem);
360 mutex_unlock(&adev->mn_lock);
361 kfree(amn);
362
363 return ERR_PTR(r);
364}
365
366/**
367 * amdgpu_mn_register - register a BO for notifier updates
368 *
369 * @bo: amdgpu buffer object
370 * @addr: userptr addr we should monitor
371 *
372 * Registers an HMM mirror for the given BO at the specified address.
373 * Returns 0 on success, -ERRNO if anything goes wrong.
374 */
375int amdgpu_mn_register(struct amdgpu_bo *bo, unsigned long addr)
376{
377 unsigned long end = addr + amdgpu_bo_size(bo) - 1;
378 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
379 enum amdgpu_mn_type type =
380 bo->kfd_bo ? AMDGPU_MN_TYPE_HSA : AMDGPU_MN_TYPE_GFX;
381 struct amdgpu_mn *amn;
382 struct amdgpu_mn_node *node = NULL, *new_node;
383 struct list_head bos;
384 struct interval_tree_node *it;
385
386 amn = amdgpu_mn_get(adev, type);
387 if (IS_ERR(amn))
388 return PTR_ERR(amn);
389
390 new_node = kmalloc(sizeof(*new_node), GFP_KERNEL);
391 if (!new_node)
392 return -ENOMEM;
393
394 INIT_LIST_HEAD(&bos);
395
396 down_write(&amn->lock);
397
398 while ((it = interval_tree_iter_first(&amn->objects, addr, end))) {
399 kfree(node);
400 node = container_of(it, struct amdgpu_mn_node, it);
401 interval_tree_remove(&node->it, &amn->objects);
402 addr = min(it->start, addr);
403 end = max(it->last, end);
404 list_splice(&node->bos, &bos);
405 }
406
407 if (!node)
408 node = new_node;
409 else
410 kfree(new_node);
411
412 bo->mn = amn;
413
414 node->it.start = addr;
415 node->it.last = end;
416 INIT_LIST_HEAD(&node->bos);
417 list_splice(&bos, &node->bos);
418 list_add(&bo->mn_list, &node->bos);
419
420 interval_tree_insert(&node->it, &amn->objects);
421
422 up_write(&amn->lock);
423
424 return 0;
425}
426
427/**
428 * amdgpu_mn_unregister - unregister a BO for HMM mirror updates
429 *
430 * @bo: amdgpu buffer object
431 *
432 * Remove any registration of HMM mirror updates from the buffer object.
433 */
434void amdgpu_mn_unregister(struct amdgpu_bo *bo)
435{
436 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
437 struct amdgpu_mn *amn;
438 struct list_head *head;
439
440 mutex_lock(&adev->mn_lock);
441
442 amn = bo->mn;
443 if (amn == NULL) {
444 mutex_unlock(&adev->mn_lock);
445 return;
446 }
447
448 down_write(&amn->lock);
449
450 /* save the next list entry for later */
451 head = bo->mn_list.next;
452
453 bo->mn = NULL;
454 list_del_init(&bo->mn_list);
455
456 if (list_empty(head)) {
457 struct amdgpu_mn_node *node;
458
459 node = container_of(head, struct amdgpu_mn_node, bos);
460 interval_tree_remove(&node->it, &amn->objects);
461 kfree(node);
462 }
463
464 up_write(&amn->lock);
465 mutex_unlock(&adev->mn_lock);
466}
467
468/* flags used by HMM internal, not related to CPU/GPU PTE flags */
469static const uint64_t hmm_range_flags[HMM_PFN_FLAG_MAX] = {
470 (1 << 0), /* HMM_PFN_VALID */
471 (1 << 1), /* HMM_PFN_WRITE */
472 0 /* HMM_PFN_DEVICE_PRIVATE */
473};
474
475static const uint64_t hmm_range_values[HMM_PFN_VALUE_MAX] = {
476 0xfffffffffffffffeUL, /* HMM_PFN_ERROR */
477 0, /* HMM_PFN_NONE */
478 0xfffffffffffffffcUL /* HMM_PFN_SPECIAL */
479};
480
481void amdgpu_hmm_init_range(struct hmm_range *range)
482{
483 if (range) {
484 range->flags = hmm_range_flags;
485 range->values = hmm_range_values;
486 range->pfn_shift = PAGE_SHIFT;
487 }
488}