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1/*
2 * TI DaVinci GPIO Support
3 *
4 * Copyright (c) 2006-2007 David Brownell
5 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12#include <linux/gpio/driver.h>
13#include <linux/errno.h>
14#include <linux/kernel.h>
15#include <linux/clk.h>
16#include <linux/err.h>
17#include <linux/io.h>
18#include <linux/irq.h>
19#include <linux/irqdomain.h>
20#include <linux/module.h>
21#include <linux/of.h>
22#include <linux/of_device.h>
23#include <linux/pinctrl/consumer.h>
24#include <linux/platform_device.h>
25#include <linux/platform_data/gpio-davinci.h>
26#include <linux/irqchip/chained_irq.h>
27
28struct davinci_gpio_regs {
29 u32 dir;
30 u32 out_data;
31 u32 set_data;
32 u32 clr_data;
33 u32 in_data;
34 u32 set_rising;
35 u32 clr_rising;
36 u32 set_falling;
37 u32 clr_falling;
38 u32 intstat;
39};
40
41typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
42
43#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
44#define MAX_LABEL_SIZE 20
45
46static void __iomem *gpio_base;
47static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
48
49static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
50{
51 struct davinci_gpio_regs __iomem *g;
52
53 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
54
55 return g;
56}
57
58static int davinci_gpio_irq_setup(struct platform_device *pdev);
59
60/*--------------------------------------------------------------------------*/
61
62/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
63static inline int __davinci_direction(struct gpio_chip *chip,
64 unsigned offset, bool out, int value)
65{
66 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
67 struct davinci_gpio_regs __iomem *g;
68 unsigned long flags;
69 u32 temp;
70 int bank = offset / 32;
71 u32 mask = __gpio_mask(offset);
72
73 g = d->regs[bank];
74 spin_lock_irqsave(&d->lock, flags);
75 temp = readl_relaxed(&g->dir);
76 if (out) {
77 temp &= ~mask;
78 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
79 } else {
80 temp |= mask;
81 }
82 writel_relaxed(temp, &g->dir);
83 spin_unlock_irqrestore(&d->lock, flags);
84
85 return 0;
86}
87
88static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
89{
90 return __davinci_direction(chip, offset, false, 0);
91}
92
93static int
94davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
95{
96 return __davinci_direction(chip, offset, true, value);
97}
98
99/*
100 * Read the pin's value (works even if it's set up as output);
101 * returns zero/nonzero.
102 *
103 * Note that changes are synched to the GPIO clock, so reading values back
104 * right after you've set them may give old values.
105 */
106static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
107{
108 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
109 struct davinci_gpio_regs __iomem *g;
110 int bank = offset / 32;
111
112 g = d->regs[bank];
113
114 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
115}
116
117/*
118 * Assuming the pin is muxed as a gpio output, set its output value.
119 */
120static void
121davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
122{
123 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
124 struct davinci_gpio_regs __iomem *g;
125 int bank = offset / 32;
126
127 g = d->regs[bank];
128
129 writel_relaxed(__gpio_mask(offset),
130 value ? &g->set_data : &g->clr_data);
131}
132
133static struct davinci_gpio_platform_data *
134davinci_gpio_get_pdata(struct platform_device *pdev)
135{
136 struct device_node *dn = pdev->dev.of_node;
137 struct davinci_gpio_platform_data *pdata;
138 int ret;
139 u32 val;
140
141 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
142 return dev_get_platdata(&pdev->dev);
143
144 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
145 if (!pdata)
146 return NULL;
147
148 ret = of_property_read_u32(dn, "ti,ngpio", &val);
149 if (ret)
150 goto of_err;
151
152 pdata->ngpio = val;
153
154 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
155 if (ret)
156 goto of_err;
157
158 pdata->gpio_unbanked = val;
159
160 return pdata;
161
162of_err:
163 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
164 return NULL;
165}
166
167static int davinci_gpio_probe(struct platform_device *pdev)
168{
169 static int ctrl_num, bank_base;
170 int gpio, bank, ret = 0;
171 unsigned ngpio, nbank;
172 struct davinci_gpio_controller *chips;
173 struct davinci_gpio_platform_data *pdata;
174 struct device *dev = &pdev->dev;
175 struct resource *res;
176 char label[MAX_LABEL_SIZE];
177
178 pdata = davinci_gpio_get_pdata(pdev);
179 if (!pdata) {
180 dev_err(dev, "No platform data found\n");
181 return -EINVAL;
182 }
183
184 dev->platform_data = pdata;
185
186 /*
187 * The gpio banks conceptually expose a segmented bitmap,
188 * and "ngpio" is one more than the largest zero-based
189 * bit index that's valid.
190 */
191 ngpio = pdata->ngpio;
192 if (ngpio == 0) {
193 dev_err(dev, "How many GPIOs?\n");
194 return -EINVAL;
195 }
196
197 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
198 ngpio = ARCH_NR_GPIOS;
199
200 nbank = DIV_ROUND_UP(ngpio, 32);
201 chips = devm_kzalloc(dev,
202 nbank * sizeof(struct davinci_gpio_controller),
203 GFP_KERNEL);
204 if (!chips)
205 return -ENOMEM;
206
207 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
208 gpio_base = devm_ioremap_resource(dev, res);
209 if (IS_ERR(gpio_base))
210 return PTR_ERR(gpio_base);
211
212 snprintf(label, MAX_LABEL_SIZE, "davinci_gpio.%d", ctrl_num++);
213 chips->chip.label = devm_kstrdup(dev, label, GFP_KERNEL);
214 if (!chips->chip.label)
215 return -ENOMEM;
216
217 chips->chip.direction_input = davinci_direction_in;
218 chips->chip.get = davinci_gpio_get;
219 chips->chip.direction_output = davinci_direction_out;
220 chips->chip.set = davinci_gpio_set;
221
222 chips->chip.ngpio = ngpio;
223 chips->chip.base = bank_base;
224
225#ifdef CONFIG_OF_GPIO
226 chips->chip.of_gpio_n_cells = 2;
227 chips->chip.parent = dev;
228 chips->chip.of_node = dev->of_node;
229
230 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
231 chips->chip.request = gpiochip_generic_request;
232 chips->chip.free = gpiochip_generic_free;
233 }
234#endif
235 spin_lock_init(&chips->lock);
236 bank_base += ngpio;
237
238 for (gpio = 0, bank = 0; gpio < ngpio; gpio += 32, bank++)
239 chips->regs[bank] = gpio_base + offset_array[bank];
240
241 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
242 if (ret)
243 goto err;
244
245 platform_set_drvdata(pdev, chips);
246 ret = davinci_gpio_irq_setup(pdev);
247 if (ret)
248 goto err;
249
250 return 0;
251
252err:
253 /* Revert the static variable increments */
254 ctrl_num--;
255 bank_base -= ngpio;
256
257 return ret;
258}
259
260/*--------------------------------------------------------------------------*/
261/*
262 * We expect irqs will normally be set up as input pins, but they can also be
263 * used as output pins ... which is convenient for testing.
264 *
265 * NOTE: The first few GPIOs also have direct INTC hookups in addition
266 * to their GPIOBNK0 irq, with a bit less overhead.
267 *
268 * All those INTC hookups (direct, plus several IRQ banks) can also
269 * serve as EDMA event triggers.
270 */
271
272static void gpio_irq_disable(struct irq_data *d)
273{
274 struct davinci_gpio_regs __iomem *g = irq2regs(d);
275 u32 mask = (u32) irq_data_get_irq_handler_data(d);
276
277 writel_relaxed(mask, &g->clr_falling);
278 writel_relaxed(mask, &g->clr_rising);
279}
280
281static void gpio_irq_enable(struct irq_data *d)
282{
283 struct davinci_gpio_regs __iomem *g = irq2regs(d);
284 u32 mask = (u32) irq_data_get_irq_handler_data(d);
285 unsigned status = irqd_get_trigger_type(d);
286
287 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
288 if (!status)
289 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
290
291 if (status & IRQ_TYPE_EDGE_FALLING)
292 writel_relaxed(mask, &g->set_falling);
293 if (status & IRQ_TYPE_EDGE_RISING)
294 writel_relaxed(mask, &g->set_rising);
295}
296
297static int gpio_irq_type(struct irq_data *d, unsigned trigger)
298{
299 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
300 return -EINVAL;
301
302 return 0;
303}
304
305static struct irq_chip gpio_irqchip = {
306 .name = "GPIO",
307 .irq_enable = gpio_irq_enable,
308 .irq_disable = gpio_irq_disable,
309 .irq_set_type = gpio_irq_type,
310 .flags = IRQCHIP_SET_TYPE_MASKED,
311};
312
313static void gpio_irq_handler(struct irq_desc *desc)
314{
315 struct davinci_gpio_regs __iomem *g;
316 u32 mask = 0xffff;
317 int bank_num;
318 struct davinci_gpio_controller *d;
319 struct davinci_gpio_irq_data *irqdata;
320
321 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
322 bank_num = irqdata->bank_num;
323 g = irqdata->regs;
324 d = irqdata->chip;
325
326 /* we only care about one bank */
327 if ((bank_num % 2) == 1)
328 mask <<= 16;
329
330 /* temporarily mask (level sensitive) parent IRQ */
331 chained_irq_enter(irq_desc_get_chip(desc), desc);
332 while (1) {
333 u32 status;
334 int bit;
335 irq_hw_number_t hw_irq;
336
337 /* ack any irqs */
338 status = readl_relaxed(&g->intstat) & mask;
339 if (!status)
340 break;
341 writel_relaxed(status, &g->intstat);
342
343 /* now demux them to the right lowlevel handler */
344
345 while (status) {
346 bit = __ffs(status);
347 status &= ~BIT(bit);
348 /* Max number of gpios per controller is 144 so
349 * hw_irq will be in [0..143]
350 */
351 hw_irq = (bank_num / 2) * 32 + bit;
352
353 generic_handle_irq(
354 irq_find_mapping(d->irq_domain, hw_irq));
355 }
356 }
357 chained_irq_exit(irq_desc_get_chip(desc), desc);
358 /* now it may re-trigger */
359}
360
361static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
362{
363 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
364
365 if (d->irq_domain)
366 return irq_create_mapping(d->irq_domain, offset);
367 else
368 return -ENXIO;
369}
370
371static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
372{
373 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
374
375 /*
376 * NOTE: we assume for now that only irqs in the first gpio_chip
377 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
378 */
379 if (offset < d->gpio_unbanked)
380 return d->base_irq + offset;
381 else
382 return -ENODEV;
383}
384
385static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
386{
387 struct davinci_gpio_controller *d;
388 struct davinci_gpio_regs __iomem *g;
389 u32 mask;
390
391 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
392 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
393 mask = __gpio_mask(data->irq - d->base_irq);
394
395 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
396 return -EINVAL;
397
398 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
399 ? &g->set_falling : &g->clr_falling);
400 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
401 ? &g->set_rising : &g->clr_rising);
402
403 return 0;
404}
405
406static int
407davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
408 irq_hw_number_t hw)
409{
410 struct davinci_gpio_controller *chips =
411 (struct davinci_gpio_controller *)d->host_data;
412 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
413
414 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
415 "davinci_gpio");
416 irq_set_irq_type(irq, IRQ_TYPE_NONE);
417 irq_set_chip_data(irq, (__force void *)g);
418 irq_set_handler_data(irq, (void *)__gpio_mask(hw));
419
420 return 0;
421}
422
423static const struct irq_domain_ops davinci_gpio_irq_ops = {
424 .map = davinci_gpio_irq_map,
425 .xlate = irq_domain_xlate_onetwocell,
426};
427
428static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
429{
430 static struct irq_chip_type gpio_unbanked;
431
432 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
433
434 return &gpio_unbanked.chip;
435};
436
437static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
438{
439 static struct irq_chip gpio_unbanked;
440
441 gpio_unbanked = *irq_get_chip(irq);
442 return &gpio_unbanked;
443};
444
445static const struct of_device_id davinci_gpio_ids[];
446
447/*
448 * NOTE: for suspend/resume, probably best to make a platform_device with
449 * suspend_late/resume_resume calls hooking into results of the set_wake()
450 * calls ... so if no gpios are wakeup events the clock can be disabled,
451 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
452 * (dm6446) can be set appropriately for GPIOV33 pins.
453 */
454
455static int davinci_gpio_irq_setup(struct platform_device *pdev)
456{
457 unsigned gpio, bank;
458 int irq;
459 int ret;
460 struct clk *clk;
461 u32 binten = 0;
462 unsigned ngpio, bank_irq;
463 struct device *dev = &pdev->dev;
464 struct resource *res;
465 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
466 struct davinci_gpio_platform_data *pdata = dev->platform_data;
467 struct davinci_gpio_regs __iomem *g;
468 struct irq_domain *irq_domain = NULL;
469 const struct of_device_id *match;
470 struct irq_chip *irq_chip;
471 struct davinci_gpio_irq_data *irqdata;
472 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
473
474 /*
475 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
476 */
477 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
478 match = of_match_device(of_match_ptr(davinci_gpio_ids),
479 dev);
480 if (match)
481 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
482
483 ngpio = pdata->ngpio;
484 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
485 if (!res) {
486 dev_err(dev, "Invalid IRQ resource\n");
487 return -EBUSY;
488 }
489
490 bank_irq = res->start;
491
492 if (!bank_irq) {
493 dev_err(dev, "Invalid IRQ resource\n");
494 return -ENODEV;
495 }
496
497 clk = devm_clk_get(dev, "gpio");
498 if (IS_ERR(clk)) {
499 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
500 return PTR_ERR(clk);
501 }
502 ret = clk_prepare_enable(clk);
503 if (ret)
504 return ret;
505
506 if (!pdata->gpio_unbanked) {
507 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
508 if (irq < 0) {
509 dev_err(dev, "Couldn't allocate IRQ numbers\n");
510 clk_disable_unprepare(clk);
511 return irq;
512 }
513
514 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
515 &davinci_gpio_irq_ops,
516 chips);
517 if (!irq_domain) {
518 dev_err(dev, "Couldn't register an IRQ domain\n");
519 clk_disable_unprepare(clk);
520 return -ENODEV;
521 }
522 }
523
524 /*
525 * Arrange gpio_to_irq() support, handling either direct IRQs or
526 * banked IRQs. Having GPIOs in the first GPIO bank use direct
527 * IRQs, while the others use banked IRQs, would need some setup
528 * tweaks to recognize hardware which can do that.
529 */
530 chips->chip.to_irq = gpio_to_irq_banked;
531 chips->irq_domain = irq_domain;
532
533 /*
534 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
535 * controller only handling trigger modes. We currently assume no
536 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
537 */
538 if (pdata->gpio_unbanked) {
539 /* pass "bank 0" GPIO IRQs to AINTC */
540 chips->chip.to_irq = gpio_to_irq_unbanked;
541 chips->base_irq = bank_irq;
542 chips->gpio_unbanked = pdata->gpio_unbanked;
543 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
544
545 /* AINTC handles mask/unmask; GPIO handles triggering */
546 irq = bank_irq;
547 irq_chip = gpio_get_irq_chip(irq);
548 irq_chip->name = "GPIO-AINTC";
549 irq_chip->irq_set_type = gpio_irq_type_unbanked;
550
551 /* default trigger: both edges */
552 g = chips->regs[0];
553 writel_relaxed(~0, &g->set_falling);
554 writel_relaxed(~0, &g->set_rising);
555
556 /* set the direct IRQs up to use that irqchip */
557 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++, irq++) {
558 irq_set_chip(irq, irq_chip);
559 irq_set_handler_data(irq, chips);
560 irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
561 }
562
563 goto done;
564 }
565
566 /*
567 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
568 * then chain through our own handler.
569 */
570 for (gpio = 0, bank = 0; gpio < ngpio; bank++, bank_irq++, gpio += 16) {
571 /* disabled by default, enabled only as needed
572 * There are register sets for 32 GPIOs. 2 banks of 16
573 * GPIOs are covered by each set of registers hence divide by 2
574 */
575 g = chips->regs[bank / 2];
576 writel_relaxed(~0, &g->clr_falling);
577 writel_relaxed(~0, &g->clr_rising);
578
579 /*
580 * Each chip handles 32 gpios, and each irq bank consists of 16
581 * gpio irqs. Pass the irq bank's corresponding controller to
582 * the chained irq handler.
583 */
584 irqdata = devm_kzalloc(&pdev->dev,
585 sizeof(struct
586 davinci_gpio_irq_data),
587 GFP_KERNEL);
588 if (!irqdata) {
589 clk_disable_unprepare(clk);
590 return -ENOMEM;
591 }
592
593 irqdata->regs = g;
594 irqdata->bank_num = bank;
595 irqdata->chip = chips;
596
597 irq_set_chained_handler_and_data(bank_irq, gpio_irq_handler,
598 irqdata);
599
600 binten |= BIT(bank);
601 }
602
603done:
604 /*
605 * BINTEN -- per-bank interrupt enable. genirq would also let these
606 * bits be set/cleared dynamically.
607 */
608 writel_relaxed(binten, gpio_base + BINTEN);
609
610 return 0;
611}
612
613#if IS_ENABLED(CONFIG_OF)
614static const struct of_device_id davinci_gpio_ids[] = {
615 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
616 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
617 { /* sentinel */ },
618};
619MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
620#endif
621
622static struct platform_driver davinci_gpio_driver = {
623 .probe = davinci_gpio_probe,
624 .driver = {
625 .name = "davinci_gpio",
626 .of_match_table = of_match_ptr(davinci_gpio_ids),
627 },
628};
629
630/**
631 * GPIO driver registration needs to be done before machine_init functions
632 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
633 */
634static int __init davinci_gpio_drv_reg(void)
635{
636 return platform_driver_register(&davinci_gpio_driver);
637}
638postcore_initcall(davinci_gpio_drv_reg);
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * TI DaVinci GPIO Support
4 *
5 * Copyright (c) 2006-2007 David Brownell
6 * Copyright (c) 2007, MontaVista Software, Inc. <source@mvista.com>
7 */
8
9#include <linux/gpio/driver.h>
10#include <linux/errno.h>
11#include <linux/kernel.h>
12#include <linux/clk.h>
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/irq.h>
16#include <linux/irqdomain.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/pinctrl/consumer.h>
21#include <linux/platform_device.h>
22#include <linux/platform_data/gpio-davinci.h>
23#include <linux/irqchip/chained_irq.h>
24#include <linux/spinlock.h>
25
26#include <asm-generic/gpio.h>
27
28#define MAX_REGS_BANKS 5
29#define MAX_INT_PER_BANK 32
30
31struct davinci_gpio_regs {
32 u32 dir;
33 u32 out_data;
34 u32 set_data;
35 u32 clr_data;
36 u32 in_data;
37 u32 set_rising;
38 u32 clr_rising;
39 u32 set_falling;
40 u32 clr_falling;
41 u32 intstat;
42};
43
44typedef struct irq_chip *(*gpio_get_irq_chip_cb_t)(unsigned int irq);
45
46#define BINTEN 0x8 /* GPIO Interrupt Per-Bank Enable Register */
47
48static void __iomem *gpio_base;
49static unsigned int offset_array[5] = {0x10, 0x38, 0x60, 0x88, 0xb0};
50
51struct davinci_gpio_irq_data {
52 void __iomem *regs;
53 struct davinci_gpio_controller *chip;
54 int bank_num;
55};
56
57struct davinci_gpio_controller {
58 struct gpio_chip chip;
59 struct irq_domain *irq_domain;
60 /* Serialize access to GPIO registers */
61 spinlock_t lock;
62 void __iomem *regs[MAX_REGS_BANKS];
63 int gpio_unbanked;
64 int irqs[MAX_INT_PER_BANK];
65};
66
67static inline u32 __gpio_mask(unsigned gpio)
68{
69 return 1 << (gpio % 32);
70}
71
72static inline struct davinci_gpio_regs __iomem *irq2regs(struct irq_data *d)
73{
74 struct davinci_gpio_regs __iomem *g;
75
76 g = (__force struct davinci_gpio_regs __iomem *)irq_data_get_irq_chip_data(d);
77
78 return g;
79}
80
81static int davinci_gpio_irq_setup(struct platform_device *pdev);
82
83/*--------------------------------------------------------------------------*/
84
85/* board setup code *MUST* setup pinmux and enable the GPIO clock. */
86static inline int __davinci_direction(struct gpio_chip *chip,
87 unsigned offset, bool out, int value)
88{
89 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
90 struct davinci_gpio_regs __iomem *g;
91 unsigned long flags;
92 u32 temp;
93 int bank = offset / 32;
94 u32 mask = __gpio_mask(offset);
95
96 g = d->regs[bank];
97 spin_lock_irqsave(&d->lock, flags);
98 temp = readl_relaxed(&g->dir);
99 if (out) {
100 temp &= ~mask;
101 writel_relaxed(mask, value ? &g->set_data : &g->clr_data);
102 } else {
103 temp |= mask;
104 }
105 writel_relaxed(temp, &g->dir);
106 spin_unlock_irqrestore(&d->lock, flags);
107
108 return 0;
109}
110
111static int davinci_direction_in(struct gpio_chip *chip, unsigned offset)
112{
113 return __davinci_direction(chip, offset, false, 0);
114}
115
116static int
117davinci_direction_out(struct gpio_chip *chip, unsigned offset, int value)
118{
119 return __davinci_direction(chip, offset, true, value);
120}
121
122/*
123 * Read the pin's value (works even if it's set up as output);
124 * returns zero/nonzero.
125 *
126 * Note that changes are synched to the GPIO clock, so reading values back
127 * right after you've set them may give old values.
128 */
129static int davinci_gpio_get(struct gpio_chip *chip, unsigned offset)
130{
131 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
132 struct davinci_gpio_regs __iomem *g;
133 int bank = offset / 32;
134
135 g = d->regs[bank];
136
137 return !!(__gpio_mask(offset) & readl_relaxed(&g->in_data));
138}
139
140/*
141 * Assuming the pin is muxed as a gpio output, set its output value.
142 */
143static void
144davinci_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
145{
146 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
147 struct davinci_gpio_regs __iomem *g;
148 int bank = offset / 32;
149
150 g = d->regs[bank];
151
152 writel_relaxed(__gpio_mask(offset),
153 value ? &g->set_data : &g->clr_data);
154}
155
156static struct davinci_gpio_platform_data *
157davinci_gpio_get_pdata(struct platform_device *pdev)
158{
159 struct device_node *dn = pdev->dev.of_node;
160 struct davinci_gpio_platform_data *pdata;
161 int ret;
162 u32 val;
163
164 if (!IS_ENABLED(CONFIG_OF) || !pdev->dev.of_node)
165 return dev_get_platdata(&pdev->dev);
166
167 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
168 if (!pdata)
169 return NULL;
170
171 ret = of_property_read_u32(dn, "ti,ngpio", &val);
172 if (ret)
173 goto of_err;
174
175 pdata->ngpio = val;
176
177 ret = of_property_read_u32(dn, "ti,davinci-gpio-unbanked", &val);
178 if (ret)
179 goto of_err;
180
181 pdata->gpio_unbanked = val;
182
183 return pdata;
184
185of_err:
186 dev_err(&pdev->dev, "Populating pdata from DT failed: err %d\n", ret);
187 return NULL;
188}
189
190static int davinci_gpio_probe(struct platform_device *pdev)
191{
192 int bank, i, ret = 0;
193 unsigned int ngpio, nbank, nirq;
194 struct davinci_gpio_controller *chips;
195 struct davinci_gpio_platform_data *pdata;
196 struct device *dev = &pdev->dev;
197
198 pdata = davinci_gpio_get_pdata(pdev);
199 if (!pdata) {
200 dev_err(dev, "No platform data found\n");
201 return -EINVAL;
202 }
203
204 dev->platform_data = pdata;
205
206 /*
207 * The gpio banks conceptually expose a segmented bitmap,
208 * and "ngpio" is one more than the largest zero-based
209 * bit index that's valid.
210 */
211 ngpio = pdata->ngpio;
212 if (ngpio == 0) {
213 dev_err(dev, "How many GPIOs?\n");
214 return -EINVAL;
215 }
216
217 if (WARN_ON(ARCH_NR_GPIOS < ngpio))
218 ngpio = ARCH_NR_GPIOS;
219
220 /*
221 * If there are unbanked interrupts then the number of
222 * interrupts is equal to number of gpios else all are banked so
223 * number of interrupts is equal to number of banks(each with 16 gpios)
224 */
225 if (pdata->gpio_unbanked)
226 nirq = pdata->gpio_unbanked;
227 else
228 nirq = DIV_ROUND_UP(ngpio, 16);
229
230 chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
231 if (!chips)
232 return -ENOMEM;
233
234 gpio_base = devm_platform_ioremap_resource(pdev, 0);
235 if (IS_ERR(gpio_base))
236 return PTR_ERR(gpio_base);
237
238 for (i = 0; i < nirq; i++) {
239 chips->irqs[i] = platform_get_irq(pdev, i);
240 if (chips->irqs[i] < 0) {
241 if (chips->irqs[i] != -EPROBE_DEFER)
242 dev_info(dev, "IRQ not populated, err = %d\n",
243 chips->irqs[i]);
244 return chips->irqs[i];
245 }
246 }
247
248 chips->chip.label = dev_name(dev);
249
250 chips->chip.direction_input = davinci_direction_in;
251 chips->chip.get = davinci_gpio_get;
252 chips->chip.direction_output = davinci_direction_out;
253 chips->chip.set = davinci_gpio_set;
254
255 chips->chip.ngpio = ngpio;
256 chips->chip.base = pdata->no_auto_base ? pdata->base : -1;
257
258#ifdef CONFIG_OF_GPIO
259 chips->chip.of_gpio_n_cells = 2;
260 chips->chip.parent = dev;
261 chips->chip.of_node = dev->of_node;
262
263 if (of_property_read_bool(dev->of_node, "gpio-ranges")) {
264 chips->chip.request = gpiochip_generic_request;
265 chips->chip.free = gpiochip_generic_free;
266 }
267#endif
268 spin_lock_init(&chips->lock);
269
270 nbank = DIV_ROUND_UP(ngpio, 32);
271 for (bank = 0; bank < nbank; bank++)
272 chips->regs[bank] = gpio_base + offset_array[bank];
273
274 ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
275 if (ret)
276 return ret;
277
278 platform_set_drvdata(pdev, chips);
279 ret = davinci_gpio_irq_setup(pdev);
280 if (ret)
281 return ret;
282
283 return 0;
284}
285
286/*--------------------------------------------------------------------------*/
287/*
288 * We expect irqs will normally be set up as input pins, but they can also be
289 * used as output pins ... which is convenient for testing.
290 *
291 * NOTE: The first few GPIOs also have direct INTC hookups in addition
292 * to their GPIOBNK0 irq, with a bit less overhead.
293 *
294 * All those INTC hookups (direct, plus several IRQ banks) can also
295 * serve as EDMA event triggers.
296 */
297
298static void gpio_irq_disable(struct irq_data *d)
299{
300 struct davinci_gpio_regs __iomem *g = irq2regs(d);
301 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
302
303 writel_relaxed(mask, &g->clr_falling);
304 writel_relaxed(mask, &g->clr_rising);
305}
306
307static void gpio_irq_enable(struct irq_data *d)
308{
309 struct davinci_gpio_regs __iomem *g = irq2regs(d);
310 uintptr_t mask = (uintptr_t)irq_data_get_irq_handler_data(d);
311 unsigned status = irqd_get_trigger_type(d);
312
313 status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
314 if (!status)
315 status = IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
316
317 if (status & IRQ_TYPE_EDGE_FALLING)
318 writel_relaxed(mask, &g->set_falling);
319 if (status & IRQ_TYPE_EDGE_RISING)
320 writel_relaxed(mask, &g->set_rising);
321}
322
323static int gpio_irq_type(struct irq_data *d, unsigned trigger)
324{
325 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
326 return -EINVAL;
327
328 return 0;
329}
330
331static struct irq_chip gpio_irqchip = {
332 .name = "GPIO",
333 .irq_enable = gpio_irq_enable,
334 .irq_disable = gpio_irq_disable,
335 .irq_set_type = gpio_irq_type,
336 .flags = IRQCHIP_SET_TYPE_MASKED,
337};
338
339static void gpio_irq_handler(struct irq_desc *desc)
340{
341 struct davinci_gpio_regs __iomem *g;
342 u32 mask = 0xffff;
343 int bank_num;
344 struct davinci_gpio_controller *d;
345 struct davinci_gpio_irq_data *irqdata;
346
347 irqdata = (struct davinci_gpio_irq_data *)irq_desc_get_handler_data(desc);
348 bank_num = irqdata->bank_num;
349 g = irqdata->regs;
350 d = irqdata->chip;
351
352 /* we only care about one bank */
353 if ((bank_num % 2) == 1)
354 mask <<= 16;
355
356 /* temporarily mask (level sensitive) parent IRQ */
357 chained_irq_enter(irq_desc_get_chip(desc), desc);
358 while (1) {
359 u32 status;
360 int bit;
361 irq_hw_number_t hw_irq;
362
363 /* ack any irqs */
364 status = readl_relaxed(&g->intstat) & mask;
365 if (!status)
366 break;
367 writel_relaxed(status, &g->intstat);
368
369 /* now demux them to the right lowlevel handler */
370
371 while (status) {
372 bit = __ffs(status);
373 status &= ~BIT(bit);
374 /* Max number of gpios per controller is 144 so
375 * hw_irq will be in [0..143]
376 */
377 hw_irq = (bank_num / 2) * 32 + bit;
378
379 generic_handle_irq(
380 irq_find_mapping(d->irq_domain, hw_irq));
381 }
382 }
383 chained_irq_exit(irq_desc_get_chip(desc), desc);
384 /* now it may re-trigger */
385}
386
387static int gpio_to_irq_banked(struct gpio_chip *chip, unsigned offset)
388{
389 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
390
391 if (d->irq_domain)
392 return irq_create_mapping(d->irq_domain, offset);
393 else
394 return -ENXIO;
395}
396
397static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
398{
399 struct davinci_gpio_controller *d = gpiochip_get_data(chip);
400
401 /*
402 * NOTE: we assume for now that only irqs in the first gpio_chip
403 * can provide direct-mapped IRQs to AINTC (up to 32 GPIOs).
404 */
405 if (offset < d->gpio_unbanked)
406 return d->irqs[offset];
407 else
408 return -ENODEV;
409}
410
411static int gpio_irq_type_unbanked(struct irq_data *data, unsigned trigger)
412{
413 struct davinci_gpio_controller *d;
414 struct davinci_gpio_regs __iomem *g;
415 u32 mask, i;
416
417 d = (struct davinci_gpio_controller *)irq_data_get_irq_handler_data(data);
418 g = (struct davinci_gpio_regs __iomem *)d->regs[0];
419 for (i = 0; i < MAX_INT_PER_BANK; i++)
420 if (data->irq == d->irqs[i])
421 break;
422
423 if (i == MAX_INT_PER_BANK)
424 return -EINVAL;
425
426 mask = __gpio_mask(i);
427
428 if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
429 return -EINVAL;
430
431 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_FALLING)
432 ? &g->set_falling : &g->clr_falling);
433 writel_relaxed(mask, (trigger & IRQ_TYPE_EDGE_RISING)
434 ? &g->set_rising : &g->clr_rising);
435
436 return 0;
437}
438
439static int
440davinci_gpio_irq_map(struct irq_domain *d, unsigned int irq,
441 irq_hw_number_t hw)
442{
443 struct davinci_gpio_controller *chips =
444 (struct davinci_gpio_controller *)d->host_data;
445 struct davinci_gpio_regs __iomem *g = chips->regs[hw / 32];
446
447 irq_set_chip_and_handler_name(irq, &gpio_irqchip, handle_simple_irq,
448 "davinci_gpio");
449 irq_set_irq_type(irq, IRQ_TYPE_NONE);
450 irq_set_chip_data(irq, (__force void *)g);
451 irq_set_handler_data(irq, (void *)(uintptr_t)__gpio_mask(hw));
452
453 return 0;
454}
455
456static const struct irq_domain_ops davinci_gpio_irq_ops = {
457 .map = davinci_gpio_irq_map,
458 .xlate = irq_domain_xlate_onetwocell,
459};
460
461static struct irq_chip *davinci_gpio_get_irq_chip(unsigned int irq)
462{
463 static struct irq_chip_type gpio_unbanked;
464
465 gpio_unbanked = *irq_data_get_chip_type(irq_get_irq_data(irq));
466
467 return &gpio_unbanked.chip;
468};
469
470static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
471{
472 static struct irq_chip gpio_unbanked;
473
474 gpio_unbanked = *irq_get_chip(irq);
475 return &gpio_unbanked;
476};
477
478static const struct of_device_id davinci_gpio_ids[];
479
480/*
481 * NOTE: for suspend/resume, probably best to make a platform_device with
482 * suspend_late/resume_resume calls hooking into results of the set_wake()
483 * calls ... so if no gpios are wakeup events the clock can be disabled,
484 * with outputs left at previously set levels, and so that VDD3P3V.IOPWDN0
485 * (dm6446) can be set appropriately for GPIOV33 pins.
486 */
487
488static int davinci_gpio_irq_setup(struct platform_device *pdev)
489{
490 unsigned gpio, bank;
491 int irq;
492 int ret;
493 struct clk *clk;
494 u32 binten = 0;
495 unsigned ngpio;
496 struct device *dev = &pdev->dev;
497 struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
498 struct davinci_gpio_platform_data *pdata = dev->platform_data;
499 struct davinci_gpio_regs __iomem *g;
500 struct irq_domain *irq_domain = NULL;
501 const struct of_device_id *match;
502 struct irq_chip *irq_chip;
503 struct davinci_gpio_irq_data *irqdata;
504 gpio_get_irq_chip_cb_t gpio_get_irq_chip;
505
506 /*
507 * Use davinci_gpio_get_irq_chip by default to handle non DT cases
508 */
509 gpio_get_irq_chip = davinci_gpio_get_irq_chip;
510 match = of_match_device(of_match_ptr(davinci_gpio_ids),
511 dev);
512 if (match)
513 gpio_get_irq_chip = (gpio_get_irq_chip_cb_t)match->data;
514
515 ngpio = pdata->ngpio;
516
517 clk = devm_clk_get(dev, "gpio");
518 if (IS_ERR(clk)) {
519 dev_err(dev, "Error %ld getting gpio clock\n", PTR_ERR(clk));
520 return PTR_ERR(clk);
521 }
522
523 ret = clk_prepare_enable(clk);
524 if (ret)
525 return ret;
526
527 if (!pdata->gpio_unbanked) {
528 irq = devm_irq_alloc_descs(dev, -1, 0, ngpio, 0);
529 if (irq < 0) {
530 dev_err(dev, "Couldn't allocate IRQ numbers\n");
531 clk_disable_unprepare(clk);
532 return irq;
533 }
534
535 irq_domain = irq_domain_add_legacy(dev->of_node, ngpio, irq, 0,
536 &davinci_gpio_irq_ops,
537 chips);
538 if (!irq_domain) {
539 dev_err(dev, "Couldn't register an IRQ domain\n");
540 clk_disable_unprepare(clk);
541 return -ENODEV;
542 }
543 }
544
545 /*
546 * Arrange gpio_to_irq() support, handling either direct IRQs or
547 * banked IRQs. Having GPIOs in the first GPIO bank use direct
548 * IRQs, while the others use banked IRQs, would need some setup
549 * tweaks to recognize hardware which can do that.
550 */
551 chips->chip.to_irq = gpio_to_irq_banked;
552 chips->irq_domain = irq_domain;
553
554 /*
555 * AINTC can handle direct/unbanked IRQs for GPIOs, with the GPIO
556 * controller only handling trigger modes. We currently assume no
557 * IRQ mux conflicts; gpio_irq_type_unbanked() is only for GPIOs.
558 */
559 if (pdata->gpio_unbanked) {
560 /* pass "bank 0" GPIO IRQs to AINTC */
561 chips->chip.to_irq = gpio_to_irq_unbanked;
562 chips->gpio_unbanked = pdata->gpio_unbanked;
563 binten = GENMASK(pdata->gpio_unbanked / 16, 0);
564
565 /* AINTC handles mask/unmask; GPIO handles triggering */
566 irq = chips->irqs[0];
567 irq_chip = gpio_get_irq_chip(irq);
568 irq_chip->name = "GPIO-AINTC";
569 irq_chip->irq_set_type = gpio_irq_type_unbanked;
570
571 /* default trigger: both edges */
572 g = chips->regs[0];
573 writel_relaxed(~0, &g->set_falling);
574 writel_relaxed(~0, &g->set_rising);
575
576 /* set the direct IRQs up to use that irqchip */
577 for (gpio = 0; gpio < pdata->gpio_unbanked; gpio++) {
578 irq_set_chip(chips->irqs[gpio], irq_chip);
579 irq_set_handler_data(chips->irqs[gpio], chips);
580 irq_set_status_flags(chips->irqs[gpio],
581 IRQ_TYPE_EDGE_BOTH);
582 }
583
584 goto done;
585 }
586
587 /*
588 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
589 * then chain through our own handler.
590 */
591 for (gpio = 0, bank = 0; gpio < ngpio; bank++, gpio += 16) {
592 /* disabled by default, enabled only as needed
593 * There are register sets for 32 GPIOs. 2 banks of 16
594 * GPIOs are covered by each set of registers hence divide by 2
595 */
596 g = chips->regs[bank / 2];
597 writel_relaxed(~0, &g->clr_falling);
598 writel_relaxed(~0, &g->clr_rising);
599
600 /*
601 * Each chip handles 32 gpios, and each irq bank consists of 16
602 * gpio irqs. Pass the irq bank's corresponding controller to
603 * the chained irq handler.
604 */
605 irqdata = devm_kzalloc(&pdev->dev,
606 sizeof(struct
607 davinci_gpio_irq_data),
608 GFP_KERNEL);
609 if (!irqdata) {
610 clk_disable_unprepare(clk);
611 return -ENOMEM;
612 }
613
614 irqdata->regs = g;
615 irqdata->bank_num = bank;
616 irqdata->chip = chips;
617
618 irq_set_chained_handler_and_data(chips->irqs[bank],
619 gpio_irq_handler, irqdata);
620
621 binten |= BIT(bank);
622 }
623
624done:
625 /*
626 * BINTEN -- per-bank interrupt enable. genirq would also let these
627 * bits be set/cleared dynamically.
628 */
629 writel_relaxed(binten, gpio_base + BINTEN);
630
631 return 0;
632}
633
634static const struct of_device_id davinci_gpio_ids[] = {
635 { .compatible = "ti,keystone-gpio", keystone_gpio_get_irq_chip},
636 { .compatible = "ti,am654-gpio", keystone_gpio_get_irq_chip},
637 { .compatible = "ti,dm6441-gpio", davinci_gpio_get_irq_chip},
638 { /* sentinel */ },
639};
640MODULE_DEVICE_TABLE(of, davinci_gpio_ids);
641
642static struct platform_driver davinci_gpio_driver = {
643 .probe = davinci_gpio_probe,
644 .driver = {
645 .name = "davinci_gpio",
646 .of_match_table = of_match_ptr(davinci_gpio_ids),
647 },
648};
649
650/**
651 * GPIO driver registration needs to be done before machine_init functions
652 * access GPIO. Hence davinci_gpio_drv_reg() is a postcore_initcall.
653 */
654static int __init davinci_gpio_drv_reg(void)
655{
656 return platform_driver_register(&davinci_gpio_driver);
657}
658postcore_initcall(davinci_gpio_drv_reg);