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1/*
2 * Copyright (c) 2017 Andreas Färber
3 *
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 */
6
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8
9/ {
10 compatible = "actions,s900";
11 interrupt-parent = <&gic>;
12 #address-cells = <2>;
13 #size-cells = <2>;
14
15 cpus {
16 #address-cells = <2>;
17 #size-cells = <0>;
18
19 cpu0: cpu@0 {
20 device_type = "cpu";
21 compatible = "arm,cortex-a53", "arm,armv8";
22 reg = <0x0 0x0>;
23 enable-method = "psci";
24 };
25
26 cpu1: cpu@1 {
27 device_type = "cpu";
28 compatible = "arm,cortex-a53", "arm,armv8";
29 reg = <0x0 0x1>;
30 enable-method = "psci";
31 };
32
33 cpu2: cpu@2 {
34 device_type = "cpu";
35 compatible = "arm,cortex-a53", "arm,armv8";
36 reg = <0x0 0x2>;
37 enable-method = "psci";
38 };
39
40 cpu3: cpu@3 {
41 device_type = "cpu";
42 compatible = "arm,cortex-a53", "arm,armv8";
43 reg = <0x0 0x3>;
44 enable-method = "psci";
45 };
46 };
47
48 reserved-memory {
49 #address-cells = <2>;
50 #size-cells = <2>;
51 ranges;
52
53 secmon@1f000000 {
54 reg = <0x0 0x1f000000 0x0 0x1000000>;
55 no-map;
56 };
57 };
58
59 psci {
60 compatible = "arm,psci-0.2";
61 method = "smc";
62 };
63
64 arm-pmu {
65 compatible = "arm,cortex-a53-pmu";
66 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
67 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
70 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
71 };
72
73 timer {
74 compatible = "arm,armv8-timer";
75 interrupts = <GIC_PPI 13
76 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
77 <GIC_PPI 14
78 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
79 <GIC_PPI 11
80 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
81 <GIC_PPI 10
82 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
83 };
84
85 hosc: hosc {
86 compatible = "fixed-clock";
87 clock-frequency = <24000000>;
88 #clock-cells = <0>;
89 };
90
91 soc {
92 compatible = "simple-bus";
93 #address-cells = <2>;
94 #size-cells = <2>;
95 ranges;
96
97 gic: interrupt-controller@e00f1000 {
98 compatible = "arm,gic-400";
99 reg = <0x0 0xe00f1000 0x0 0x1000>,
100 <0x0 0xe00f2000 0x0 0x2000>,
101 <0x0 0xe00f4000 0x0 0x2000>,
102 <0x0 0xe00f6000 0x0 0x2000>;
103 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
104 interrupt-controller;
105 #interrupt-cells = <3>;
106 };
107
108 uart0: serial@e0120000 {
109 compatible = "actions,s900-uart", "actions,owl-uart";
110 reg = <0x0 0xe0120000 0x0 0x2000>;
111 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
112 status = "disabled";
113 };
114
115 uart1: serial@e0122000 {
116 compatible = "actions,s900-uart", "actions,owl-uart";
117 reg = <0x0 0xe0122000 0x0 0x2000>;
118 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
119 status = "disabled";
120 };
121
122 uart2: serial@e0124000 {
123 compatible = "actions,s900-uart", "actions,owl-uart";
124 reg = <0x0 0xe0124000 0x0 0x2000>;
125 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
126 status = "disabled";
127 };
128
129 uart3: serial@e0126000 {
130 compatible = "actions,s900-uart", "actions,owl-uart";
131 reg = <0x0 0xe0126000 0x0 0x2000>;
132 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
133 status = "disabled";
134 };
135
136 uart4: serial@e0128000 {
137 compatible = "actions,s900-uart", "actions,owl-uart";
138 reg = <0x0 0xe0128000 0x0 0x2000>;
139 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
140 status = "disabled";
141 };
142
143 uart5: serial@e012a000 {
144 compatible = "actions,s900-uart", "actions,owl-uart";
145 reg = <0x0 0xe012a000 0x0 0x2000>;
146 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
147 status = "disabled";
148 };
149
150 uart6: serial@e012c000 {
151 compatible = "actions,s900-uart", "actions,owl-uart";
152 reg = <0x0 0xe012c000 0x0 0x2000>;
153 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
154 status = "disabled";
155 };
156
157 timer: timer@e0228000 {
158 compatible = "actions,s900-timer";
159 reg = <0x0 0xe0228000 0x0 0x8000>;
160 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
161 interrupt-names = "timer1";
162 };
163 };
164};
1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2017 Andreas Färber
4 */
5
6#include <dt-bindings/clock/actions,s900-cmu.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/reset/actions,s900-reset.h>
9
10/ {
11 compatible = "actions,s900";
12 interrupt-parent = <&gic>;
13 #address-cells = <2>;
14 #size-cells = <2>;
15
16 cpus {
17 #address-cells = <2>;
18 #size-cells = <0>;
19
20 cpu0: cpu@0 {
21 device_type = "cpu";
22 compatible = "arm,cortex-a53";
23 reg = <0x0 0x0>;
24 enable-method = "psci";
25 };
26
27 cpu1: cpu@1 {
28 device_type = "cpu";
29 compatible = "arm,cortex-a53";
30 reg = <0x0 0x1>;
31 enable-method = "psci";
32 };
33
34 cpu2: cpu@2 {
35 device_type = "cpu";
36 compatible = "arm,cortex-a53";
37 reg = <0x0 0x2>;
38 enable-method = "psci";
39 };
40
41 cpu3: cpu@3 {
42 device_type = "cpu";
43 compatible = "arm,cortex-a53";
44 reg = <0x0 0x3>;
45 enable-method = "psci";
46 };
47 };
48
49 reserved-memory {
50 #address-cells = <2>;
51 #size-cells = <2>;
52 ranges;
53
54 secmon@1f000000 {
55 reg = <0x0 0x1f000000 0x0 0x1000000>;
56 no-map;
57 };
58 };
59
60 psci {
61 compatible = "arm,psci-0.2";
62 method = "smc";
63 };
64
65 arm-pmu {
66 compatible = "arm,cortex-a53-pmu";
67 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
68 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
69 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
70 <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
71 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
72 };
73
74 timer {
75 compatible = "arm,armv8-timer";
76 interrupts = <GIC_PPI 13
77 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
78 <GIC_PPI 14
79 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
80 <GIC_PPI 11
81 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
82 <GIC_PPI 10
83 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
84 };
85
86 hosc: hosc {
87 compatible = "fixed-clock";
88 clock-frequency = <24000000>;
89 #clock-cells = <0>;
90 };
91
92 losc: losc {
93 compatible = "fixed-clock";
94 clock-frequency = <32768>;
95 #clock-cells = <0>;
96 };
97
98 diff24M: diff24M {
99 compatible = "fixed-clock";
100 clock-frequency = <24000000>;
101 #clock-cells = <0>;
102 };
103
104 soc {
105 compatible = "simple-bus";
106 #address-cells = <2>;
107 #size-cells = <2>;
108 ranges;
109
110 gic: interrupt-controller@e00f1000 {
111 compatible = "arm,gic-400";
112 reg = <0x0 0xe00f1000 0x0 0x1000>,
113 <0x0 0xe00f2000 0x0 0x2000>,
114 <0x0 0xe00f4000 0x0 0x2000>,
115 <0x0 0xe00f6000 0x0 0x2000>;
116 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
117 interrupt-controller;
118 #interrupt-cells = <3>;
119 };
120
121 uart0: serial@e0120000 {
122 compatible = "actions,s900-uart", "actions,owl-uart";
123 reg = <0x0 0xe0120000 0x0 0x2000>;
124 clocks = <&cmu CLK_UART0>;
125 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
126 status = "disabled";
127 };
128
129 uart1: serial@e0122000 {
130 compatible = "actions,s900-uart", "actions,owl-uart";
131 reg = <0x0 0xe0122000 0x0 0x2000>;
132 clocks = <&cmu CLK_UART1>;
133 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
134 status = "disabled";
135 };
136
137 uart2: serial@e0124000 {
138 compatible = "actions,s900-uart", "actions,owl-uart";
139 reg = <0x0 0xe0124000 0x0 0x2000>;
140 clocks = <&cmu CLK_UART2>;
141 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
142 status = "disabled";
143 };
144
145 uart3: serial@e0126000 {
146 compatible = "actions,s900-uart", "actions,owl-uart";
147 reg = <0x0 0xe0126000 0x0 0x2000>;
148 clocks = <&cmu CLK_UART3>;
149 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
150 status = "disabled";
151 };
152
153 uart4: serial@e0128000 {
154 compatible = "actions,s900-uart", "actions,owl-uart";
155 reg = <0x0 0xe0128000 0x0 0x2000>;
156 clocks = <&cmu CLK_UART4>;
157 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
158 status = "disabled";
159 };
160
161 uart5: serial@e012a000 {
162 compatible = "actions,s900-uart", "actions,owl-uart";
163 reg = <0x0 0xe012a000 0x0 0x2000>;
164 clocks = <&cmu CLK_UART5>;
165 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
166 status = "disabled";
167 };
168
169 uart6: serial@e012c000 {
170 compatible = "actions,s900-uart", "actions,owl-uart";
171 reg = <0x0 0xe012c000 0x0 0x2000>;
172 clocks = <&cmu CLK_UART6>;
173 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
174 status = "disabled";
175 };
176
177 sps: power-controller@e012e000 {
178 compatible = "actions,s900-sps";
179 reg = <0x0 0xe012e000 0x0 0x2000>;
180 #power-domain-cells = <1>;
181 };
182
183 cmu: clock-controller@e0160000 {
184 compatible = "actions,s900-cmu";
185 reg = <0x0 0xe0160000 0x0 0x1000>;
186 clocks = <&hosc>, <&losc>;
187 #clock-cells = <1>;
188 #reset-cells = <1>;
189 };
190
191 i2c0: i2c@e0170000 {
192 compatible = "actions,s900-i2c";
193 reg = <0 0xe0170000 0 0x1000>;
194 clocks = <&cmu CLK_I2C0>;
195 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
196 #address-cells = <1>;
197 #size-cells = <0>;
198 status = "disabled";
199 };
200
201 i2c1: i2c@e0172000 {
202 compatible = "actions,s900-i2c";
203 reg = <0 0xe0172000 0 0x1000>;
204 clocks = <&cmu CLK_I2C1>;
205 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
206 #address-cells = <1>;
207 #size-cells = <0>;
208 status = "disabled";
209 };
210
211 i2c2: i2c@e0174000 {
212 compatible = "actions,s900-i2c";
213 reg = <0 0xe0174000 0 0x1000>;
214 clocks = <&cmu CLK_I2C2>;
215 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
216 #address-cells = <1>;
217 #size-cells = <0>;
218 status = "disabled";
219 };
220
221 i2c3: i2c@e0176000 {
222 compatible = "actions,s900-i2c";
223 reg = <0 0xe0176000 0 0x1000>;
224 clocks = <&cmu CLK_I2C3>;
225 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
226 #address-cells = <1>;
227 #size-cells = <0>;
228 status = "disabled";
229 };
230
231 i2c4: i2c@e0178000 {
232 compatible = "actions,s900-i2c";
233 reg = <0 0xe0178000 0 0x1000>;
234 clocks = <&cmu CLK_I2C4>;
235 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
236 #address-cells = <1>;
237 #size-cells = <0>;
238 status = "disabled";
239 };
240
241 i2c5: i2c@e017a000 {
242 compatible = "actions,s900-i2c";
243 reg = <0 0xe017a000 0 0x1000>;
244 clocks = <&cmu CLK_I2C5>;
245 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
246 #address-cells = <1>;
247 #size-cells = <0>;
248 status = "disabled";
249 };
250
251 pinctrl: pinctrl@e01b0000 {
252 compatible = "actions,s900-pinctrl";
253 reg = <0x0 0xe01b0000 0x0 0x1000>;
254 clocks = <&cmu CLK_GPIO>;
255 gpio-controller;
256 gpio-ranges = <&pinctrl 0 0 146>;
257 #gpio-cells = <2>;
258 interrupt-controller;
259 #interrupt-cells = <2>;
260 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
262 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>,
263 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
264 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
265 <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
266 };
267
268 timer: timer@e0228000 {
269 compatible = "actions,s900-timer";
270 reg = <0x0 0xe0228000 0x0 0x8000>;
271 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
272 interrupt-names = "timer1";
273 };
274
275 dma: dma-controller@e0260000 {
276 compatible = "actions,s900-dma";
277 reg = <0x0 0xe0260000 0x0 0x1000>;
278 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
279 <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
280 <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
282 #dma-cells = <1>;
283 dma-channels = <12>;
284 dma-requests = <46>;
285 clocks = <&cmu CLK_DMAC>;
286 };
287 };
288};