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1/*
2 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
3 *
4 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
5 *
6 * Licensed under GPLv2 or later
7 */
8
9/include/ "skeleton.dtsi"
10
11/ {
12 compatible = "wm,wm8850";
13
14 cpus {
15 #address-cells = <1>;
16 #size-cells = <0>;
17
18 cpu@0 {
19 device_type = "cpu";
20 compatible = "arm,cortex-a9";
21 reg = <0x0>;
22 };
23 };
24
25 aliases {
26 serial0 = &uart0;
27 serial1 = &uart1;
28 serial2 = &uart2;
29 serial3 = &uart3;
30 };
31
32 soc {
33 #address-cells = <1>;
34 #size-cells = <1>;
35 compatible = "simple-bus";
36 ranges;
37 interrupt-parent = <&intc0>;
38
39 intc0: interrupt-controller@d8140000 {
40 compatible = "via,vt8500-intc";
41 interrupt-controller;
42 reg = <0xd8140000 0x10000>;
43 #interrupt-cells = <1>;
44 };
45
46 /* Secondary IC cascaded to intc0 */
47 intc1: interrupt-controller@d8150000 {
48 compatible = "via,vt8500-intc";
49 interrupt-controller;
50 #interrupt-cells = <1>;
51 reg = <0xD8150000 0x10000>;
52 interrupts = <56 57 58 59 60 61 62 63>;
53 };
54
55 pinctrl: pinctrl@d8110000 {
56 compatible = "wm,wm8850-pinctrl";
57 reg = <0xd8110000 0x10000>;
58 interrupt-controller;
59 #interrupt-cells = <2>;
60 gpio-controller;
61 #gpio-cells = <2>;
62 };
63
64 pmc@d8130000 {
65 compatible = "via,vt8500-pmc";
66 reg = <0xd8130000 0x1000>;
67
68 clocks {
69 #address-cells = <1>;
70 #size-cells = <0>;
71
72 ref25: ref25M {
73 #clock-cells = <0>;
74 compatible = "fixed-clock";
75 clock-frequency = <25000000>;
76 };
77
78 ref24: ref24M {
79 #clock-cells = <0>;
80 compatible = "fixed-clock";
81 clock-frequency = <24000000>;
82 };
83
84 plla: plla {
85 #clock-cells = <0>;
86 compatible = "wm,wm8850-pll-clock";
87 clocks = <&ref24>;
88 reg = <0x200>;
89 };
90
91 pllb: pllb {
92 #clock-cells = <0>;
93 compatible = "wm,wm8850-pll-clock";
94 clocks = <&ref24>;
95 reg = <0x204>;
96 };
97
98 pllc: pllc {
99 #clock-cells = <0>;
100 compatible = "wm,wm8850-pll-clock";
101 clocks = <&ref24>;
102 reg = <0x208>;
103 };
104
105 plld: plld {
106 #clock-cells = <0>;
107 compatible = "wm,wm8850-pll-clock";
108 clocks = <&ref24>;
109 reg = <0x20c>;
110 };
111
112 plle: plle {
113 #clock-cells = <0>;
114 compatible = "wm,wm8850-pll-clock";
115 clocks = <&ref24>;
116 reg = <0x210>;
117 };
118
119 pllf: pllf {
120 #clock-cells = <0>;
121 compatible = "wm,wm8850-pll-clock";
122 clocks = <&ref24>;
123 reg = <0x214>;
124 };
125
126 pllg: pllg {
127 #clock-cells = <0>;
128 compatible = "wm,wm8850-pll-clock";
129 clocks = <&ref24>;
130 reg = <0x218>;
131 };
132
133 clkarm: arm {
134 #clock-cells = <0>;
135 compatible = "via,vt8500-device-clock";
136 clocks = <&plla>;
137 divisor-reg = <0x300>;
138 };
139
140 clkahb: ahb {
141 #clock-cells = <0>;
142 compatible = "via,vt8500-device-clock";
143 clocks = <&pllb>;
144 divisor-reg = <0x304>;
145 };
146
147 clkapb: apb {
148 #clock-cells = <0>;
149 compatible = "via,vt8500-device-clock";
150 clocks = <&pllb>;
151 divisor-reg = <0x320>;
152 };
153
154 clkddr: ddr {
155 #clock-cells = <0>;
156 compatible = "via,vt8500-device-clock";
157 clocks = <&plld>;
158 divisor-reg = <0x310>;
159 };
160
161 clkuart0: uart0 {
162 #clock-cells = <0>;
163 compatible = "via,vt8500-device-clock";
164 clocks = <&ref24>;
165 enable-reg = <0x254>;
166 enable-bit = <24>;
167 };
168
169 clkuart1: uart1 {
170 #clock-cells = <0>;
171 compatible = "via,vt8500-device-clock";
172 clocks = <&ref24>;
173 enable-reg = <0x254>;
174 enable-bit = <25>;
175 };
176
177 clkuart2: uart2 {
178 #clock-cells = <0>;
179 compatible = "via,vt8500-device-clock";
180 clocks = <&ref24>;
181 enable-reg = <0x254>;
182 enable-bit = <26>;
183 };
184
185 clkuart3: uart3 {
186 #clock-cells = <0>;
187 compatible = "via,vt8500-device-clock";
188 clocks = <&ref24>;
189 enable-reg = <0x254>;
190 enable-bit = <27>;
191 };
192
193 clkpwm: pwm {
194 #clock-cells = <0>;
195 compatible = "via,vt8500-device-clock";
196 clocks = <&pllb>;
197 divisor-reg = <0x350>;
198 enable-reg = <0x250>;
199 enable-bit = <17>;
200 };
201
202 clksdhc: sdhc {
203 #clock-cells = <0>;
204 compatible = "via,vt8500-device-clock";
205 clocks = <&pllb>;
206 divisor-reg = <0x330>;
207 divisor-mask = <0x3f>;
208 enable-reg = <0x250>;
209 enable-bit = <0>;
210 };
211 };
212 };
213
214 fb: fb@d8051700 {
215 compatible = "wm,wm8505-fb";
216 reg = <0xd8051700 0x200>;
217 };
218
219 ge_rops@d8050400 {
220 compatible = "wm,prizm-ge-rops";
221 reg = <0xd8050400 0x100>;
222 };
223
224 pwm: pwm@d8220000 {
225 #pwm-cells = <3>;
226 compatible = "via,vt8500-pwm";
227 reg = <0xd8220000 0x100>;
228 clocks = <&clkpwm>;
229 };
230
231 timer@d8130100 {
232 compatible = "via,vt8500-timer";
233 reg = <0xd8130100 0x28>;
234 interrupts = <36>;
235 };
236
237 ehci@d8007900 {
238 compatible = "via,vt8500-ehci";
239 reg = <0xd8007900 0x200>;
240 interrupts = <26>;
241 };
242
243 uhci@d8007b00 {
244 compatible = "platform-uhci";
245 reg = <0xd8007b00 0x200>;
246 interrupts = <26>;
247 };
248
249 uhci@d8008d00 {
250 compatible = "platform-uhci";
251 reg = <0xd8008d00 0x200>;
252 interrupts = <26>;
253 };
254
255 uart0: serial@d8200000 {
256 compatible = "via,vt8500-uart";
257 reg = <0xd8200000 0x1040>;
258 interrupts = <32>;
259 clocks = <&clkuart0>;
260 status = "disabled";
261 };
262
263 uart1: serial@d82b0000 {
264 compatible = "via,vt8500-uart";
265 reg = <0xd82b0000 0x1040>;
266 interrupts = <33>;
267 clocks = <&clkuart1>;
268 status = "disabled";
269 };
270
271 uart2: serial@d8210000 {
272 compatible = "via,vt8500-uart";
273 reg = <0xd8210000 0x1040>;
274 interrupts = <47>;
275 clocks = <&clkuart2>;
276 status = "disabled";
277 };
278
279 uart3: serial@d82c0000 {
280 compatible = "via,vt8500-uart";
281 reg = <0xd82c0000 0x1040>;
282 interrupts = <50>;
283 clocks = <&clkuart3>;
284 status = "disabled";
285 };
286
287 rtc@d8100000 {
288 compatible = "via,vt8500-rtc";
289 reg = <0xd8100000 0x10000>;
290 interrupts = <48>;
291 };
292
293 sdhc@d800a000 {
294 compatible = "wm,wm8505-sdhc";
295 reg = <0xd800a000 0x1000>;
296 interrupts = <20 21>;
297 clocks = <&clksdhc>;
298 bus-width = <4>;
299 sdon-inverted;
300 };
301
302 ethernet@d8004000 {
303 compatible = "via,vt8500-rhine";
304 reg = <0xd8004000 0x100>;
305 interrupts = <10>;
306 };
307 };
308};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC
4 *
5 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
6 */
7
8/ {
9 #address-cells = <1>;
10 #size-cells = <1>;
11 compatible = "wm,wm8850";
12
13 cpus {
14 #address-cells = <1>;
15 #size-cells = <0>;
16
17 cpu@0 {
18 device_type = "cpu";
19 compatible = "arm,cortex-a9";
20 reg = <0x0>;
21 };
22 };
23
24 memory {
25 device_type = "memory";
26 reg = <0x0 0x0>;
27 };
28
29 aliases {
30 serial0 = &uart0;
31 serial1 = &uart1;
32 serial2 = &uart2;
33 serial3 = &uart3;
34 };
35
36 soc {
37 #address-cells = <1>;
38 #size-cells = <1>;
39 compatible = "simple-bus";
40 ranges;
41 interrupt-parent = <&intc0>;
42
43 intc0: interrupt-controller@d8140000 {
44 compatible = "via,vt8500-intc";
45 interrupt-controller;
46 reg = <0xd8140000 0x10000>;
47 #interrupt-cells = <1>;
48 };
49
50 /* Secondary IC cascaded to intc0 */
51 intc1: interrupt-controller@d8150000 {
52 compatible = "via,vt8500-intc";
53 interrupt-controller;
54 #interrupt-cells = <1>;
55 reg = <0xD8150000 0x10000>;
56 interrupts = <56 57 58 59 60 61 62 63>;
57 };
58
59 pinctrl: pinctrl@d8110000 {
60 compatible = "wm,wm8850-pinctrl";
61 reg = <0xd8110000 0x10000>;
62 interrupt-controller;
63 #interrupt-cells = <2>;
64 gpio-controller;
65 #gpio-cells = <2>;
66 };
67
68 pmc@d8130000 {
69 compatible = "via,vt8500-pmc";
70 reg = <0xd8130000 0x1000>;
71
72 clocks {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 ref25: ref25M {
77 #clock-cells = <0>;
78 compatible = "fixed-clock";
79 clock-frequency = <25000000>;
80 };
81
82 ref24: ref24M {
83 #clock-cells = <0>;
84 compatible = "fixed-clock";
85 clock-frequency = <24000000>;
86 };
87
88 plla: plla {
89 #clock-cells = <0>;
90 compatible = "wm,wm8850-pll-clock";
91 clocks = <&ref24>;
92 reg = <0x200>;
93 };
94
95 pllb: pllb {
96 #clock-cells = <0>;
97 compatible = "wm,wm8850-pll-clock";
98 clocks = <&ref24>;
99 reg = <0x204>;
100 };
101
102 pllc: pllc {
103 #clock-cells = <0>;
104 compatible = "wm,wm8850-pll-clock";
105 clocks = <&ref24>;
106 reg = <0x208>;
107 };
108
109 plld: plld {
110 #clock-cells = <0>;
111 compatible = "wm,wm8850-pll-clock";
112 clocks = <&ref24>;
113 reg = <0x20c>;
114 };
115
116 plle: plle {
117 #clock-cells = <0>;
118 compatible = "wm,wm8850-pll-clock";
119 clocks = <&ref24>;
120 reg = <0x210>;
121 };
122
123 pllf: pllf {
124 #clock-cells = <0>;
125 compatible = "wm,wm8850-pll-clock";
126 clocks = <&ref24>;
127 reg = <0x214>;
128 };
129
130 pllg: pllg {
131 #clock-cells = <0>;
132 compatible = "wm,wm8850-pll-clock";
133 clocks = <&ref24>;
134 reg = <0x218>;
135 };
136
137 clkarm: arm {
138 #clock-cells = <0>;
139 compatible = "via,vt8500-device-clock";
140 clocks = <&plla>;
141 divisor-reg = <0x300>;
142 };
143
144 clkahb: ahb {
145 #clock-cells = <0>;
146 compatible = "via,vt8500-device-clock";
147 clocks = <&pllb>;
148 divisor-reg = <0x304>;
149 };
150
151 clkapb: apb {
152 #clock-cells = <0>;
153 compatible = "via,vt8500-device-clock";
154 clocks = <&pllb>;
155 divisor-reg = <0x320>;
156 };
157
158 clkddr: ddr {
159 #clock-cells = <0>;
160 compatible = "via,vt8500-device-clock";
161 clocks = <&plld>;
162 divisor-reg = <0x310>;
163 };
164
165 clkuart0: uart0 {
166 #clock-cells = <0>;
167 compatible = "via,vt8500-device-clock";
168 clocks = <&ref24>;
169 enable-reg = <0x254>;
170 enable-bit = <24>;
171 };
172
173 clkuart1: uart1 {
174 #clock-cells = <0>;
175 compatible = "via,vt8500-device-clock";
176 clocks = <&ref24>;
177 enable-reg = <0x254>;
178 enable-bit = <25>;
179 };
180
181 clkuart2: uart2 {
182 #clock-cells = <0>;
183 compatible = "via,vt8500-device-clock";
184 clocks = <&ref24>;
185 enable-reg = <0x254>;
186 enable-bit = <26>;
187 };
188
189 clkuart3: uart3 {
190 #clock-cells = <0>;
191 compatible = "via,vt8500-device-clock";
192 clocks = <&ref24>;
193 enable-reg = <0x254>;
194 enable-bit = <27>;
195 };
196
197 clkpwm: pwm {
198 #clock-cells = <0>;
199 compatible = "via,vt8500-device-clock";
200 clocks = <&pllb>;
201 divisor-reg = <0x350>;
202 enable-reg = <0x250>;
203 enable-bit = <17>;
204 };
205
206 clksdhc: sdhc {
207 #clock-cells = <0>;
208 compatible = "via,vt8500-device-clock";
209 clocks = <&pllb>;
210 divisor-reg = <0x330>;
211 divisor-mask = <0x3f>;
212 enable-reg = <0x250>;
213 enable-bit = <0>;
214 };
215 };
216 };
217
218 fb: fb@d8051700 {
219 compatible = "wm,wm8505-fb";
220 reg = <0xd8051700 0x200>;
221 };
222
223 ge_rops@d8050400 {
224 compatible = "wm,prizm-ge-rops";
225 reg = <0xd8050400 0x100>;
226 };
227
228 pwm: pwm@d8220000 {
229 #pwm-cells = <3>;
230 compatible = "via,vt8500-pwm";
231 reg = <0xd8220000 0x100>;
232 clocks = <&clkpwm>;
233 };
234
235 timer@d8130100 {
236 compatible = "via,vt8500-timer";
237 reg = <0xd8130100 0x28>;
238 interrupts = <36>;
239 };
240
241 ehci@d8007900 {
242 compatible = "via,vt8500-ehci";
243 reg = <0xd8007900 0x200>;
244 interrupts = <26>;
245 };
246
247 uhci@d8007b00 {
248 compatible = "platform-uhci";
249 reg = <0xd8007b00 0x200>;
250 interrupts = <26>;
251 };
252
253 uhci@d8008d00 {
254 compatible = "platform-uhci";
255 reg = <0xd8008d00 0x200>;
256 interrupts = <26>;
257 };
258
259 uart0: serial@d8200000 {
260 compatible = "via,vt8500-uart";
261 reg = <0xd8200000 0x1040>;
262 interrupts = <32>;
263 clocks = <&clkuart0>;
264 status = "disabled";
265 };
266
267 uart1: serial@d82b0000 {
268 compatible = "via,vt8500-uart";
269 reg = <0xd82b0000 0x1040>;
270 interrupts = <33>;
271 clocks = <&clkuart1>;
272 status = "disabled";
273 };
274
275 uart2: serial@d8210000 {
276 compatible = "via,vt8500-uart";
277 reg = <0xd8210000 0x1040>;
278 interrupts = <47>;
279 clocks = <&clkuart2>;
280 status = "disabled";
281 };
282
283 uart3: serial@d82c0000 {
284 compatible = "via,vt8500-uart";
285 reg = <0xd82c0000 0x1040>;
286 interrupts = <50>;
287 clocks = <&clkuart3>;
288 status = "disabled";
289 };
290
291 rtc@d8100000 {
292 compatible = "via,vt8500-rtc";
293 reg = <0xd8100000 0x10000>;
294 interrupts = <48>;
295 };
296
297 sdhc@d800a000 {
298 compatible = "wm,wm8505-sdhc";
299 reg = <0xd800a000 0x1000>;
300 interrupts = <20 21>;
301 clocks = <&clksdhc>;
302 bus-width = <4>;
303 sdon-inverted;
304 };
305
306 ethernet@d8004000 {
307 compatible = "via,vt8500-rhine";
308 reg = <0xd8004000 0x100>;
309 interrupts = <10>;
310 };
311 };
312};