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1/*
2 * Copyright 2015 Vishnu Patekar
3 *
4 * Vishnu Patekar <vishnupatekar0510@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46
47#include <dt-bindings/clock/sun8i-a83t-ccu.h>
48#include <dt-bindings/clock/sun8i-de2.h>
49#include <dt-bindings/clock/sun8i-r-ccu.h>
50#include <dt-bindings/reset/sun8i-a83t-ccu.h>
51#include <dt-bindings/reset/sun8i-de2.h>
52#include <dt-bindings/reset/sun8i-r-ccu.h>
53
54/ {
55 interrupt-parent = <&gic>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58
59 cpus {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 cpu0: cpu@0 {
64 clocks = <&ccu CLK_C0CPUX>;
65 clock-names = "cpu";
66 compatible = "arm,cortex-a7";
67 device_type = "cpu";
68 operating-points-v2 = <&cpu0_opp_table>;
69 reg = <0>;
70 };
71
72 cpu@1 {
73 compatible = "arm,cortex-a7";
74 device_type = "cpu";
75 operating-points-v2 = <&cpu0_opp_table>;
76 reg = <1>;
77 };
78
79 cpu@2 {
80 compatible = "arm,cortex-a7";
81 device_type = "cpu";
82 operating-points-v2 = <&cpu0_opp_table>;
83 reg = <2>;
84 };
85
86 cpu@3 {
87 compatible = "arm,cortex-a7";
88 device_type = "cpu";
89 operating-points-v2 = <&cpu0_opp_table>;
90 reg = <3>;
91 };
92
93 cpu100: cpu@100 {
94 clocks = <&ccu CLK_C1CPUX>;
95 clock-names = "cpu";
96 compatible = "arm,cortex-a7";
97 device_type = "cpu";
98 operating-points-v2 = <&cpu1_opp_table>;
99 reg = <0x100>;
100 };
101
102 cpu@101 {
103 compatible = "arm,cortex-a7";
104 device_type = "cpu";
105 operating-points-v2 = <&cpu1_opp_table>;
106 reg = <0x101>;
107 };
108
109 cpu@102 {
110 compatible = "arm,cortex-a7";
111 device_type = "cpu";
112 operating-points-v2 = <&cpu1_opp_table>;
113 reg = <0x102>;
114 };
115
116 cpu@103 {
117 compatible = "arm,cortex-a7";
118 device_type = "cpu";
119 operating-points-v2 = <&cpu1_opp_table>;
120 reg = <0x103>;
121 };
122 };
123
124 timer {
125 compatible = "arm,armv7-timer";
126 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
127 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
128 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
129 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
130 };
131
132 clocks {
133 #address-cells = <1>;
134 #size-cells = <1>;
135 ranges;
136
137 /* TODO: PRCM block has a mux for this. */
138 osc24M: osc24M_clk {
139 #clock-cells = <0>;
140 compatible = "fixed-clock";
141 clock-frequency = <24000000>;
142 clock-accuracy = <50000>;
143 clock-output-names = "osc24M";
144 };
145
146 /*
147 * This is called "internal OSC" in some places.
148 * It is an internal RC-based oscillator.
149 * TODO: Its controls are in the PRCM block.
150 */
151 osc16M: osc16M_clk {
152 #clock-cells = <0>;
153 compatible = "fixed-clock";
154 clock-frequency = <16000000>;
155 clock-output-names = "osc16M";
156 };
157
158 osc16Md512: osc16Md512_clk {
159 #clock-cells = <0>;
160 compatible = "fixed-factor-clock";
161 clock-div = <512>;
162 clock-mult = <1>;
163 clocks = <&osc16M>;
164 clock-output-names = "osc16M-d512";
165 };
166 };
167
168 de: display-engine {
169 compatible = "allwinner,sun8i-a83t-display-engine";
170 allwinner,pipelines = <&mixer0>, <&mixer1>;
171 status = "disabled";
172 };
173
174 memory {
175 reg = <0x40000000 0x80000000>;
176 device_type = "memory";
177 };
178
179 cpu0_opp_table: opp_table0 {
180 compatible = "operating-points-v2";
181 opp-shared;
182
183 opp-480000000 {
184 opp-hz = /bits/ 64 <480000000>;
185 opp-microvolt = <840000>;
186 clock-latency-ns = <244144>; /* 8 32k periods */
187 };
188
189 opp-600000000 {
190 opp-hz = /bits/ 64 <600000000>;
191 opp-microvolt = <840000>;
192 clock-latency-ns = <244144>; /* 8 32k periods */
193 };
194
195 opp-720000000 {
196 opp-hz = /bits/ 64 <720000000>;
197 opp-microvolt = <840000>;
198 clock-latency-ns = <244144>; /* 8 32k periods */
199 };
200
201 opp-864000000 {
202 opp-hz = /bits/ 64 <864000000>;
203 opp-microvolt = <840000>;
204 clock-latency-ns = <244144>; /* 8 32k periods */
205 };
206
207 opp-912000000 {
208 opp-hz = /bits/ 64 <912000000>;
209 opp-microvolt = <840000>;
210 clock-latency-ns = <244144>; /* 8 32k periods */
211 };
212
213 opp-1008000000 {
214 opp-hz = /bits/ 64 <1008000000>;
215 opp-microvolt = <840000>;
216 clock-latency-ns = <244144>; /* 8 32k periods */
217 };
218
219 opp-1128000000 {
220 opp-hz = /bits/ 64 <1128000000>;
221 opp-microvolt = <840000>;
222 clock-latency-ns = <244144>; /* 8 32k periods */
223 };
224
225 opp-1200000000 {
226 opp-hz = /bits/ 64 <1200000000>;
227 opp-microvolt = <840000>;
228 clock-latency-ns = <244144>; /* 8 32k periods */
229 };
230 };
231
232 cpu1_opp_table: opp_table1 {
233 compatible = "operating-points-v2";
234 opp-shared;
235
236 opp-480000000 {
237 opp-hz = /bits/ 64 <480000000>;
238 opp-microvolt = <840000>;
239 clock-latency-ns = <244144>; /* 8 32k periods */
240 };
241
242 opp-600000000 {
243 opp-hz = /bits/ 64 <600000000>;
244 opp-microvolt = <840000>;
245 clock-latency-ns = <244144>; /* 8 32k periods */
246 };
247
248 opp-720000000 {
249 opp-hz = /bits/ 64 <720000000>;
250 opp-microvolt = <840000>;
251 clock-latency-ns = <244144>; /* 8 32k periods */
252 };
253
254 opp-864000000 {
255 opp-hz = /bits/ 64 <864000000>;
256 opp-microvolt = <840000>;
257 clock-latency-ns = <244144>; /* 8 32k periods */
258 };
259
260 opp-912000000 {
261 opp-hz = /bits/ 64 <912000000>;
262 opp-microvolt = <840000>;
263 clock-latency-ns = <244144>; /* 8 32k periods */
264 };
265
266 opp-1008000000 {
267 opp-hz = /bits/ 64 <1008000000>;
268 opp-microvolt = <840000>;
269 clock-latency-ns = <244144>; /* 8 32k periods */
270 };
271
272 opp-1128000000 {
273 opp-hz = /bits/ 64 <1128000000>;
274 opp-microvolt = <840000>;
275 clock-latency-ns = <244144>; /* 8 32k periods */
276 };
277
278 opp-1200000000 {
279 opp-hz = /bits/ 64 <1200000000>;
280 opp-microvolt = <840000>;
281 clock-latency-ns = <244144>; /* 8 32k periods */
282 };
283 };
284
285 soc {
286 compatible = "simple-bus";
287 #address-cells = <1>;
288 #size-cells = <1>;
289 ranges;
290
291 display_clocks: clock@1000000 {
292 compatible = "allwinner,sun8i-a83t-de2-clk";
293 reg = <0x01000000 0x100000>;
294 clocks = <&ccu CLK_PLL_DE>,
295 <&ccu CLK_BUS_DE>;
296 clock-names = "mod",
297 "bus";
298 resets = <&ccu RST_BUS_DE>;
299 #clock-cells = <1>;
300 #reset-cells = <1>;
301 };
302
303 mixer0: mixer@1100000 {
304 compatible = "allwinner,sun8i-a83t-de2-mixer-0";
305 reg = <0x01100000 0x100000>;
306 clocks = <&display_clocks CLK_BUS_MIXER0>,
307 <&display_clocks CLK_MIXER0>;
308 clock-names = "bus",
309 "mod";
310 resets = <&display_clocks RST_MIXER0>;
311
312 ports {
313 #address-cells = <1>;
314 #size-cells = <0>;
315
316 mixer0_out: port@1 {
317 #address-cells = <1>;
318 #size-cells = <0>;
319 reg = <1>;
320
321 mixer0_out_tcon0: endpoint@0 {
322 reg = <0>;
323 remote-endpoint = <&tcon0_in_mixer0>;
324 };
325 };
326 };
327 };
328
329 mixer1: mixer@1200000 {
330 compatible = "allwinner,sun8i-a83t-de2-mixer-1";
331 reg = <0x01200000 0x100000>;
332 clocks = <&display_clocks CLK_BUS_MIXER1>,
333 <&display_clocks CLK_MIXER1>;
334 clock-names = "bus",
335 "mod";
336 resets = <&display_clocks RST_WB>;
337
338 ports {
339 #address-cells = <1>;
340 #size-cells = <0>;
341
342 mixer1_out: port@1 {
343 reg = <1>;
344
345 mixer1_out_tcon1: endpoint {
346 remote-endpoint = <&tcon1_in_mixer1>;
347 };
348 };
349 };
350 };
351
352 syscon: syscon@1c00000 {
353 compatible = "allwinner,sun8i-a83t-system-controller",
354 "syscon";
355 reg = <0x01c00000 0x1000>;
356 };
357
358 dma: dma-controller@1c02000 {
359 compatible = "allwinner,sun8i-a83t-dma";
360 reg = <0x01c02000 0x1000>;
361 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
362 clocks = <&ccu CLK_BUS_DMA>;
363 resets = <&ccu RST_BUS_DMA>;
364 #dma-cells = <1>;
365 };
366
367 tcon0: lcd-controller@1c0c000 {
368 compatible = "allwinner,sun8i-a83t-tcon-lcd";
369 reg = <0x01c0c000 0x1000>;
370 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
371 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
372 clock-names = "ahb", "tcon-ch0";
373 clock-output-names = "tcon-pixel-clock";
374 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
375 reset-names = "lcd", "lvds";
376
377 ports {
378 #address-cells = <1>;
379 #size-cells = <0>;
380
381 tcon0_in: port@0 {
382 #address-cells = <1>;
383 #size-cells = <0>;
384 reg = <0>;
385
386 tcon0_in_mixer0: endpoint@0 {
387 reg = <0>;
388 remote-endpoint = <&mixer0_out_tcon0>;
389 };
390 };
391
392 tcon0_out: port@1 {
393 #address-cells = <1>;
394 #size-cells = <0>;
395 reg = <1>;
396 };
397 };
398 };
399
400 tcon1: lcd-controller@1c0d000 {
401 compatible = "allwinner,sun8i-a83t-tcon-tv";
402 reg = <0x01c0d000 0x1000>;
403 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
404 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
405 clock-names = "ahb", "tcon-ch1";
406 resets = <&ccu RST_BUS_TCON1>;
407 reset-names = "lcd";
408
409 ports {
410 #address-cells = <1>;
411 #size-cells = <0>;
412
413 tcon1_in: port@0 {
414 reg = <0>;
415
416 tcon1_in_mixer1: endpoint {
417 remote-endpoint = <&mixer1_out_tcon1>;
418 };
419 };
420
421 tcon1_out: port@1 {
422 #address-cells = <1>;
423 #size-cells = <0>;
424 reg = <1>;
425
426 tcon1_out_hdmi: endpoint@1 {
427 reg = <1>;
428 remote-endpoint = <&hdmi_in_tcon1>;
429 };
430 };
431 };
432 };
433
434 mmc0: mmc@1c0f000 {
435 compatible = "allwinner,sun8i-a83t-mmc",
436 "allwinner,sun7i-a20-mmc";
437 reg = <0x01c0f000 0x1000>;
438 clocks = <&ccu CLK_BUS_MMC0>,
439 <&ccu CLK_MMC0>,
440 <&ccu CLK_MMC0_OUTPUT>,
441 <&ccu CLK_MMC0_SAMPLE>;
442 clock-names = "ahb",
443 "mmc",
444 "output",
445 "sample";
446 resets = <&ccu RST_BUS_MMC0>;
447 reset-names = "ahb";
448 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
449 status = "disabled";
450 #address-cells = <1>;
451 #size-cells = <0>;
452 };
453
454 mmc1: mmc@1c10000 {
455 compatible = "allwinner,sun8i-a83t-mmc",
456 "allwinner,sun7i-a20-mmc";
457 reg = <0x01c10000 0x1000>;
458 clocks = <&ccu CLK_BUS_MMC1>,
459 <&ccu CLK_MMC1>,
460 <&ccu CLK_MMC1_OUTPUT>,
461 <&ccu CLK_MMC1_SAMPLE>;
462 clock-names = "ahb",
463 "mmc",
464 "output",
465 "sample";
466 resets = <&ccu RST_BUS_MMC1>;
467 reset-names = "ahb";
468 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
469 pinctrl-names = "default";
470 pinctrl-0 = <&mmc1_pins>;
471 status = "disabled";
472 #address-cells = <1>;
473 #size-cells = <0>;
474 };
475
476 mmc2: mmc@1c11000 {
477 compatible = "allwinner,sun8i-a83t-emmc";
478 reg = <0x01c11000 0x1000>;
479 clocks = <&ccu CLK_BUS_MMC2>,
480 <&ccu CLK_MMC2>,
481 <&ccu CLK_MMC2_OUTPUT>,
482 <&ccu CLK_MMC2_SAMPLE>;
483 clock-names = "ahb",
484 "mmc",
485 "output",
486 "sample";
487 resets = <&ccu RST_BUS_MMC2>;
488 reset-names = "ahb";
489 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
490 status = "disabled";
491 #address-cells = <1>;
492 #size-cells = <0>;
493 };
494
495 usb_otg: usb@1c19000 {
496 compatible = "allwinner,sun8i-a83t-musb",
497 "allwinner,sun8i-a33-musb";
498 reg = <0x01c19000 0x0400>;
499 clocks = <&ccu CLK_BUS_OTG>;
500 resets = <&ccu RST_BUS_OTG>;
501 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
502 interrupt-names = "mc";
503 phys = <&usbphy 0>;
504 phy-names = "usb";
505 extcon = <&usbphy 0>;
506 status = "disabled";
507 };
508
509 usbphy: phy@1c19400 {
510 compatible = "allwinner,sun8i-a83t-usb-phy";
511 reg = <0x01c19400 0x10>,
512 <0x01c1a800 0x14>,
513 <0x01c1b800 0x14>;
514 reg-names = "phy_ctrl",
515 "pmu1",
516 "pmu2";
517 clocks = <&ccu CLK_USB_PHY0>,
518 <&ccu CLK_USB_PHY1>,
519 <&ccu CLK_USB_HSIC>,
520 <&ccu CLK_USB_HSIC_12M>;
521 clock-names = "usb0_phy",
522 "usb1_phy",
523 "usb2_phy",
524 "usb2_hsic_12M";
525 resets = <&ccu RST_USB_PHY0>,
526 <&ccu RST_USB_PHY1>,
527 <&ccu RST_USB_HSIC>;
528 reset-names = "usb0_reset",
529 "usb1_reset",
530 "usb2_reset";
531 status = "disabled";
532 #phy-cells = <1>;
533 };
534
535 ehci0: usb@1c1a000 {
536 compatible = "allwinner,sun8i-a83t-ehci",
537 "generic-ehci";
538 reg = <0x01c1a000 0x100>;
539 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
540 clocks = <&ccu CLK_BUS_EHCI0>;
541 resets = <&ccu RST_BUS_EHCI0>;
542 phys = <&usbphy 1>;
543 phy-names = "usb";
544 status = "disabled";
545 };
546
547 ohci0: usb@1c1a400 {
548 compatible = "allwinner,sun8i-a83t-ohci",
549 "generic-ohci";
550 reg = <0x01c1a400 0x100>;
551 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
552 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
553 resets = <&ccu RST_BUS_OHCI0>;
554 phys = <&usbphy 1>;
555 phy-names = "usb";
556 status = "disabled";
557 };
558
559 ehci1: usb@1c1b000 {
560 compatible = "allwinner,sun8i-a83t-ehci",
561 "generic-ehci";
562 reg = <0x01c1b000 0x100>;
563 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
564 clocks = <&ccu CLK_BUS_EHCI1>;
565 resets = <&ccu RST_BUS_EHCI1>;
566 phys = <&usbphy 2>;
567 phy-names = "usb";
568 status = "disabled";
569 };
570
571 ccu: clock@1c20000 {
572 compatible = "allwinner,sun8i-a83t-ccu";
573 reg = <0x01c20000 0x400>;
574 clocks = <&osc24M>, <&osc16Md512>;
575 clock-names = "hosc", "losc";
576 #clock-cells = <1>;
577 #reset-cells = <1>;
578 };
579
580 pio: pinctrl@1c20800 {
581 compatible = "allwinner,sun8i-a83t-pinctrl";
582 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
583 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
585 reg = <0x01c20800 0x400>;
586 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
587 clock-names = "apb", "hosc", "losc";
588 gpio-controller;
589 interrupt-controller;
590 #interrupt-cells = <3>;
591 #gpio-cells = <3>;
592
593 emac_rgmii_pins: emac-rgmii-pins {
594 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
595 "PD11", "PD12", "PD13", "PD14", "PD18",
596 "PD19", "PD21", "PD22", "PD23";
597 function = "gmac";
598 /*
599 * data lines in RGMII mode use DDR mode
600 * and need a higher signal drive strength
601 */
602 drive-strength = <40>;
603 };
604
605 hdmi_pins: hdmi-pins {
606 pins = "PH6", "PH7", "PH8";
607 function = "hdmi";
608 };
609
610 i2c0_pins: i2c0-pins {
611 pins = "PH0", "PH1";
612 function = "i2c0";
613 };
614
615 i2c1_pins: i2c1-pins {
616 pins = "PH2", "PH3";
617 function = "i2c1";
618 };
619
620 i2c2_ph_pins: i2c2-ph-pins {
621 pins = "PH4", "PH5";
622 function = "i2c2";
623 };
624
625 i2s1_pins: i2s1-pins {
626 /* I2S1 does not have external MCLK pin */
627 pins = "PG10", "PG11", "PG12", "PG13";
628 function = "i2s1";
629 };
630
631 lcd_lvds_pins: lcd-lvds-pins {
632 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
633 "PD23", "PD24", "PD25", "PD26", "PD27";
634 function = "lvds0";
635 };
636
637 mmc0_pins: mmc0-pins {
638 pins = "PF0", "PF1", "PF2",
639 "PF3", "PF4", "PF5";
640 function = "mmc0";
641 drive-strength = <30>;
642 bias-pull-up;
643 };
644
645 mmc1_pins: mmc1-pins {
646 pins = "PG0", "PG1", "PG2",
647 "PG3", "PG4", "PG5";
648 function = "mmc1";
649 drive-strength = <30>;
650 bias-pull-up;
651 };
652
653 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
654 pins = "PC5", "PC6", "PC8", "PC9",
655 "PC10", "PC11", "PC12", "PC13",
656 "PC14", "PC15", "PC16";
657 function = "mmc2";
658 drive-strength = <30>;
659 bias-pull-up;
660 };
661
662 pwm_pin: pwm-pin {
663 pins = "PD28";
664 function = "pwm";
665 };
666
667 spdif_tx_pin: spdif-tx-pin {
668 pins = "PE18";
669 function = "spdif";
670 };
671
672 uart0_pb_pins: uart0-pb-pins {
673 pins = "PB9", "PB10";
674 function = "uart0";
675 };
676
677 uart0_pf_pins: uart0-pf-pins {
678 pins = "PF2", "PF4";
679 function = "uart0";
680 };
681
682 uart1_pins: uart1-pins {
683 pins = "PG6", "PG7";
684 function = "uart1";
685 };
686
687 uart1_rts_cts_pins: uart1-rts-cts-pins {
688 pins = "PG8", "PG9";
689 function = "uart1";
690 };
691 };
692
693 timer@1c20c00 {
694 compatible = "allwinner,sun4i-a10-timer";
695 reg = <0x01c20c00 0xa0>;
696 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
697 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
698 clocks = <&osc24M>;
699 };
700
701 watchdog@1c20ca0 {
702 compatible = "allwinner,sun6i-a31-wdt";
703 reg = <0x01c20ca0 0x20>;
704 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
705 clocks = <&osc24M>;
706 };
707
708 spdif: spdif@1c21000 {
709 #sound-dai-cells = <0>;
710 compatible = "allwinner,sun8i-a83t-spdif",
711 "allwinner,sun8i-h3-spdif";
712 reg = <0x01c21000 0x400>;
713 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
714 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
715 resets = <&ccu RST_BUS_SPDIF>;
716 clock-names = "apb", "spdif";
717 dmas = <&dma 2>;
718 dma-names = "tx";
719 pinctrl-names = "default";
720 pinctrl-0 = <&spdif_tx_pin>;
721 status = "disabled";
722 };
723
724 i2s0: i2s@1c22000 {
725 #sound-dai-cells = <0>;
726 compatible = "allwinner,sun8i-a83t-i2s";
727 reg = <0x01c22000 0x400>;
728 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
729 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
730 clock-names = "apb", "mod";
731 dmas = <&dma 3>, <&dma 3>;
732 resets = <&ccu RST_BUS_I2S0>;
733 dma-names = "rx", "tx";
734 status = "disabled";
735 };
736
737 i2s1: i2s@1c22400 {
738 #sound-dai-cells = <0>;
739 compatible = "allwinner,sun8i-a83t-i2s";
740 reg = <0x01c22400 0x400>;
741 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
742 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
743 clock-names = "apb", "mod";
744 dmas = <&dma 4>, <&dma 4>;
745 resets = <&ccu RST_BUS_I2S1>;
746 dma-names = "rx", "tx";
747 pinctrl-names = "default";
748 pinctrl-0 = <&i2s1_pins>;
749 status = "disabled";
750 };
751
752 i2s2: i2s@1c22800 {
753 #sound-dai-cells = <0>;
754 compatible = "allwinner,sun8i-a83t-i2s";
755 reg = <0x01c22800 0x400>;
756 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
757 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
758 clock-names = "apb", "mod";
759 dmas = <&dma 27>;
760 resets = <&ccu RST_BUS_I2S2>;
761 dma-names = "tx";
762 status = "disabled";
763 };
764
765 pwm: pwm@1c21400 {
766 compatible = "allwinner,sun8i-a83t-pwm",
767 "allwinner,sun8i-h3-pwm";
768 reg = <0x01c21400 0x400>;
769 clocks = <&osc24M>;
770 #pwm-cells = <3>;
771 status = "disabled";
772 };
773
774 uart0: serial@1c28000 {
775 compatible = "snps,dw-apb-uart";
776 reg = <0x01c28000 0x400>;
777 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
778 reg-shift = <2>;
779 reg-io-width = <4>;
780 clocks = <&ccu CLK_BUS_UART0>;
781 resets = <&ccu RST_BUS_UART0>;
782 status = "disabled";
783 };
784
785 uart1: serial@1c28400 {
786 compatible = "snps,dw-apb-uart";
787 reg = <0x01c28400 0x400>;
788 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
789 reg-shift = <2>;
790 reg-io-width = <4>;
791 clocks = <&ccu CLK_BUS_UART1>;
792 resets = <&ccu RST_BUS_UART1>;
793 status = "disabled";
794 };
795
796 i2c0: i2c@1c2ac00 {
797 compatible = "allwinner,sun8i-a83t-i2c",
798 "allwinner,sun6i-a31-i2c";
799 reg = <0x01c2ac00 0x400>;
800 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
801 clocks = <&ccu CLK_BUS_I2C0>;
802 resets = <&ccu RST_BUS_I2C0>;
803 pinctrl-names = "default";
804 pinctrl-0 = <&i2c0_pins>;
805 status = "disabled";
806 #address-cells = <1>;
807 #size-cells = <0>;
808 };
809
810 i2c1: i2c@1c2b000 {
811 compatible = "allwinner,sun8i-a83t-i2c",
812 "allwinner,sun6i-a31-i2c";
813 reg = <0x01c2b000 0x400>;
814 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
815 clocks = <&ccu CLK_BUS_I2C1>;
816 resets = <&ccu RST_BUS_I2C1>;
817 pinctrl-names = "default";
818 pinctrl-0 = <&i2c1_pins>;
819 status = "disabled";
820 #address-cells = <1>;
821 #size-cells = <0>;
822 };
823
824 i2c2: i2c@1c2b400 {
825 compatible = "allwinner,sun8i-a83t-i2c",
826 "allwinner,sun6i-a31-i2c";
827 reg = <0x01c2b400 0x400>;
828 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
829 clocks = <&ccu CLK_BUS_I2C2>;
830 resets = <&ccu RST_BUS_I2C2>;
831 status = "disabled";
832 #address-cells = <1>;
833 #size-cells = <0>;
834 };
835
836 emac: ethernet@1c30000 {
837 compatible = "allwinner,sun8i-a83t-emac";
838 syscon = <&syscon>;
839 reg = <0x01c30000 0x104>;
840 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
841 interrupt-names = "macirq";
842 resets = <&ccu 13>;
843 reset-names = "stmmaceth";
844 clocks = <&ccu 27>;
845 clock-names = "stmmaceth";
846 #address-cells = <1>;
847 #size-cells = <0>;
848 status = "disabled";
849
850 mdio: mdio {
851 compatible = "snps,dwmac-mdio";
852 #address-cells = <1>;
853 #size-cells = <0>;
854 };
855 };
856
857 gic: interrupt-controller@1c81000 {
858 compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
859 reg = <0x01c81000 0x1000>,
860 <0x01c82000 0x2000>,
861 <0x01c84000 0x2000>,
862 <0x01c86000 0x2000>;
863 interrupt-controller;
864 #interrupt-cells = <3>;
865 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
866 };
867
868 hdmi: hdmi@1ee0000 {
869 compatible = "allwinner,sun8i-a83t-dw-hdmi";
870 reg = <0x01ee0000 0x10000>;
871 reg-io-width = <1>;
872 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
873 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
874 <&ccu CLK_HDMI>;
875 clock-names = "iahb", "isfr", "tmds";
876 resets = <&ccu RST_BUS_HDMI1>;
877 reset-names = "ctrl";
878 phys = <&hdmi_phy>;
879 phy-names = "hdmi-phy";
880 pinctrl-names = "default";
881 pinctrl-0 = <&hdmi_pins>;
882 status = "disabled";
883
884 ports {
885 #address-cells = <1>;
886 #size-cells = <0>;
887
888 hdmi_in: port@0 {
889 reg = <0>;
890
891 hdmi_in_tcon1: endpoint {
892 remote-endpoint = <&tcon1_out_hdmi>;
893 };
894 };
895
896 hdmi_out: port@1 {
897 reg = <1>;
898 };
899 };
900 };
901
902 hdmi_phy: hdmi-phy@1ef0000 {
903 compatible = "allwinner,sun8i-a83t-hdmi-phy";
904 reg = <0x01ef0000 0x10000>;
905 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
906 clock-names = "bus", "mod";
907 resets = <&ccu RST_BUS_HDMI0>;
908 reset-names = "phy";
909 #phy-cells = <0>;
910 };
911
912 r_intc: interrupt-controller@1f00c00 {
913 compatible = "allwinner,sun8i-a83t-r-intc",
914 "allwinner,sun6i-a31-r-intc";
915 interrupt-controller;
916 #interrupt-cells = <2>;
917 reg = <0x01f00c00 0x400>;
918 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
919 };
920
921 r_ccu: clock@1f01400 {
922 compatible = "allwinner,sun8i-a83t-r-ccu";
923 reg = <0x01f01400 0x400>;
924 clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
925 <&ccu 6>;
926 clock-names = "hosc", "losc", "iosc", "pll-periph";
927 #clock-cells = <1>;
928 #reset-cells = <1>;
929 };
930
931 r_pio: pinctrl@1f02c00 {
932 compatible = "allwinner,sun8i-a83t-r-pinctrl";
933 reg = <0x01f02c00 0x400>;
934 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
935 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
936 <&osc16Md512>;
937 clock-names = "apb", "hosc", "losc";
938 gpio-controller;
939 #gpio-cells = <3>;
940 interrupt-controller;
941 #interrupt-cells = <3>;
942
943 r_rsb_pins: r-rsb-pins {
944 pins = "PL0", "PL1";
945 function = "s_rsb";
946 drive-strength = <20>;
947 bias-pull-up;
948 };
949 };
950
951 r_rsb: rsb@1f03400 {
952 compatible = "allwinner,sun8i-a83t-rsb",
953 "allwinner,sun8i-a23-rsb";
954 reg = <0x01f03400 0x400>;
955 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
956 clocks = <&r_ccu CLK_APB0_RSB>;
957 clock-frequency = <3000000>;
958 resets = <&r_ccu RST_APB0_RSB>;
959 pinctrl-names = "default";
960 pinctrl-0 = <&r_rsb_pins>;
961 status = "disabled";
962 #address-cells = <1>;
963 #size-cells = <0>;
964 };
965 };
966};
1/*
2 * Copyright 2015 Vishnu Patekar
3 *
4 * Vishnu Patekar <vishnupatekar0510@gmail.com>
5 *
6 * This file is dual-licensed: you can use it either under the terms
7 * of the GPL or the X11 license, at your option. Note that this dual
8 * licensing only applies to this file, and not this project as a
9 * whole.
10 *
11 * a) This file is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of the
14 * License, or (at your option) any later version.
15 *
16 * This file is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * Or, alternatively,
22 *
23 * b) Permission is hereby granted, free of charge, to any person
24 * obtaining a copy of this software and associated documentation
25 * files (the "Software"), to deal in the Software without
26 * restriction, including without limitation the rights to use,
27 * copy, modify, merge, publish, distribute, sublicense, and/or
28 * sell copies of the Software, and to permit persons to whom the
29 * Software is furnished to do so, subject to the following
30 * conditions:
31 *
32 * The above copyright notice and this permission notice shall be
33 * included in all copies or substantial portions of the Software.
34 *
35 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
36 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
37 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
38 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
39 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
40 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
41 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
42 * OTHER DEALINGS IN THE SOFTWARE.
43 */
44
45#include <dt-bindings/interrupt-controller/arm-gic.h>
46
47#include <dt-bindings/clock/sun8i-a83t-ccu.h>
48#include <dt-bindings/clock/sun8i-de2.h>
49#include <dt-bindings/clock/sun8i-r-ccu.h>
50#include <dt-bindings/reset/sun8i-a83t-ccu.h>
51#include <dt-bindings/reset/sun8i-de2.h>
52#include <dt-bindings/reset/sun8i-r-ccu.h>
53
54/ {
55 interrupt-parent = <&gic>;
56 #address-cells = <1>;
57 #size-cells = <1>;
58
59 cpus {
60 #address-cells = <1>;
61 #size-cells = <0>;
62
63 cpu0: cpu@0 {
64 compatible = "arm,cortex-a7";
65 device_type = "cpu";
66 clocks = <&ccu CLK_C0CPUX>;
67 operating-points-v2 = <&cpu0_opp_table>;
68 cci-control-port = <&cci_control0>;
69 enable-method = "allwinner,sun8i-a83t-smp";
70 reg = <0>;
71 #cooling-cells = <2>;
72 };
73
74 cpu@1 {
75 compatible = "arm,cortex-a7";
76 device_type = "cpu";
77 clocks = <&ccu CLK_C0CPUX>;
78 operating-points-v2 = <&cpu0_opp_table>;
79 cci-control-port = <&cci_control0>;
80 enable-method = "allwinner,sun8i-a83t-smp";
81 reg = <1>;
82 #cooling-cells = <2>;
83 };
84
85 cpu@2 {
86 compatible = "arm,cortex-a7";
87 device_type = "cpu";
88 clocks = <&ccu CLK_C0CPUX>;
89 operating-points-v2 = <&cpu0_opp_table>;
90 cci-control-port = <&cci_control0>;
91 enable-method = "allwinner,sun8i-a83t-smp";
92 reg = <2>;
93 #cooling-cells = <2>;
94 };
95
96 cpu@3 {
97 compatible = "arm,cortex-a7";
98 device_type = "cpu";
99 clocks = <&ccu CLK_C0CPUX>;
100 operating-points-v2 = <&cpu0_opp_table>;
101 cci-control-port = <&cci_control0>;
102 enable-method = "allwinner,sun8i-a83t-smp";
103 reg = <3>;
104 #cooling-cells = <2>;
105 };
106
107 cpu100: cpu@100 {
108 compatible = "arm,cortex-a7";
109 device_type = "cpu";
110 clocks = <&ccu CLK_C1CPUX>;
111 operating-points-v2 = <&cpu1_opp_table>;
112 cci-control-port = <&cci_control1>;
113 enable-method = "allwinner,sun8i-a83t-smp";
114 reg = <0x100>;
115 #cooling-cells = <2>;
116 };
117
118 cpu@101 {
119 compatible = "arm,cortex-a7";
120 device_type = "cpu";
121 clocks = <&ccu CLK_C1CPUX>;
122 operating-points-v2 = <&cpu1_opp_table>;
123 cci-control-port = <&cci_control1>;
124 enable-method = "allwinner,sun8i-a83t-smp";
125 reg = <0x101>;
126 #cooling-cells = <2>;
127 };
128
129 cpu@102 {
130 compatible = "arm,cortex-a7";
131 device_type = "cpu";
132 clocks = <&ccu CLK_C1CPUX>;
133 operating-points-v2 = <&cpu1_opp_table>;
134 cci-control-port = <&cci_control1>;
135 enable-method = "allwinner,sun8i-a83t-smp";
136 reg = <0x102>;
137 #cooling-cells = <2>;
138 };
139
140 cpu@103 {
141 compatible = "arm,cortex-a7";
142 device_type = "cpu";
143 clocks = <&ccu CLK_C1CPUX>;
144 operating-points-v2 = <&cpu1_opp_table>;
145 cci-control-port = <&cci_control1>;
146 enable-method = "allwinner,sun8i-a83t-smp";
147 reg = <0x103>;
148 #cooling-cells = <2>;
149 };
150 };
151
152 timer {
153 compatible = "arm,armv7-timer";
154 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
155 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
156 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
157 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
158 };
159
160 clocks {
161 #address-cells = <1>;
162 #size-cells = <1>;
163 ranges;
164
165 /* TODO: PRCM block has a mux for this. */
166 osc24M: osc24M_clk {
167 #clock-cells = <0>;
168 compatible = "fixed-clock";
169 clock-frequency = <24000000>;
170 clock-accuracy = <50000>;
171 clock-output-names = "osc24M";
172 };
173
174 /*
175 * This is called "internal OSC" in some places.
176 * It is an internal RC-based oscillator.
177 * TODO: Its controls are in the PRCM block.
178 */
179 osc16M: osc16M_clk {
180 #clock-cells = <0>;
181 compatible = "fixed-clock";
182 clock-frequency = <16000000>;
183 clock-output-names = "osc16M";
184 };
185
186 osc16Md512: osc16Md512_clk {
187 #clock-cells = <0>;
188 compatible = "fixed-factor-clock";
189 clock-div = <512>;
190 clock-mult = <1>;
191 clocks = <&osc16M>;
192 clock-output-names = "osc16M-d512";
193 };
194 };
195
196 de: display-engine {
197 compatible = "allwinner,sun8i-a83t-display-engine";
198 allwinner,pipelines = <&mixer0>, <&mixer1>;
199 status = "disabled";
200 };
201
202 cpu0_opp_table: opp_table0 {
203 compatible = "operating-points-v2";
204 opp-shared;
205
206 opp-480000000 {
207 opp-hz = /bits/ 64 <480000000>;
208 opp-microvolt = <840000>;
209 clock-latency-ns = <244144>; /* 8 32k periods */
210 };
211
212 opp-600000000 {
213 opp-hz = /bits/ 64 <600000000>;
214 opp-microvolt = <840000>;
215 clock-latency-ns = <244144>; /* 8 32k periods */
216 };
217
218 opp-720000000 {
219 opp-hz = /bits/ 64 <720000000>;
220 opp-microvolt = <840000>;
221 clock-latency-ns = <244144>; /* 8 32k periods */
222 };
223
224 opp-864000000 {
225 opp-hz = /bits/ 64 <864000000>;
226 opp-microvolt = <840000>;
227 clock-latency-ns = <244144>; /* 8 32k periods */
228 };
229
230 opp-912000000 {
231 opp-hz = /bits/ 64 <912000000>;
232 opp-microvolt = <840000>;
233 clock-latency-ns = <244144>; /* 8 32k periods */
234 };
235
236 opp-1008000000 {
237 opp-hz = /bits/ 64 <1008000000>;
238 opp-microvolt = <840000>;
239 clock-latency-ns = <244144>; /* 8 32k periods */
240 };
241
242 opp-1128000000 {
243 opp-hz = /bits/ 64 <1128000000>;
244 opp-microvolt = <840000>;
245 clock-latency-ns = <244144>; /* 8 32k periods */
246 };
247
248 opp-1200000000 {
249 opp-hz = /bits/ 64 <1200000000>;
250 opp-microvolt = <840000>;
251 clock-latency-ns = <244144>; /* 8 32k periods */
252 };
253 };
254
255 cpu1_opp_table: opp_table1 {
256 compatible = "operating-points-v2";
257 opp-shared;
258
259 opp-480000000 {
260 opp-hz = /bits/ 64 <480000000>;
261 opp-microvolt = <840000>;
262 clock-latency-ns = <244144>; /* 8 32k periods */
263 };
264
265 opp-600000000 {
266 opp-hz = /bits/ 64 <600000000>;
267 opp-microvolt = <840000>;
268 clock-latency-ns = <244144>; /* 8 32k periods */
269 };
270
271 opp-720000000 {
272 opp-hz = /bits/ 64 <720000000>;
273 opp-microvolt = <840000>;
274 clock-latency-ns = <244144>; /* 8 32k periods */
275 };
276
277 opp-864000000 {
278 opp-hz = /bits/ 64 <864000000>;
279 opp-microvolt = <840000>;
280 clock-latency-ns = <244144>; /* 8 32k periods */
281 };
282
283 opp-912000000 {
284 opp-hz = /bits/ 64 <912000000>;
285 opp-microvolt = <840000>;
286 clock-latency-ns = <244144>; /* 8 32k periods */
287 };
288
289 opp-1008000000 {
290 opp-hz = /bits/ 64 <1008000000>;
291 opp-microvolt = <840000>;
292 clock-latency-ns = <244144>; /* 8 32k periods */
293 };
294
295 opp-1128000000 {
296 opp-hz = /bits/ 64 <1128000000>;
297 opp-microvolt = <840000>;
298 clock-latency-ns = <244144>; /* 8 32k periods */
299 };
300
301 opp-1200000000 {
302 opp-hz = /bits/ 64 <1200000000>;
303 opp-microvolt = <840000>;
304 clock-latency-ns = <244144>; /* 8 32k periods */
305 };
306 };
307
308 soc {
309 compatible = "simple-bus";
310 #address-cells = <1>;
311 #size-cells = <1>;
312 ranges;
313
314 display_clocks: clock@1000000 {
315 compatible = "allwinner,sun8i-a83t-de2-clk";
316 reg = <0x01000000 0x100000>;
317 clocks = <&ccu CLK_BUS_DE>,
318 <&ccu CLK_PLL_DE>;
319 clock-names = "bus",
320 "mod";
321 resets = <&ccu RST_BUS_DE>;
322 #clock-cells = <1>;
323 #reset-cells = <1>;
324 };
325
326 mixer0: mixer@1100000 {
327 compatible = "allwinner,sun8i-a83t-de2-mixer-0";
328 reg = <0x01100000 0x100000>;
329 clocks = <&display_clocks CLK_BUS_MIXER0>,
330 <&display_clocks CLK_MIXER0>;
331 clock-names = "bus",
332 "mod";
333 resets = <&display_clocks RST_MIXER0>;
334
335 ports {
336 #address-cells = <1>;
337 #size-cells = <0>;
338
339 mixer0_out: port@1 {
340 #address-cells = <1>;
341 #size-cells = <0>;
342 reg = <1>;
343
344 mixer0_out_tcon0: endpoint@0 {
345 reg = <0>;
346 remote-endpoint = <&tcon0_in_mixer0>;
347 };
348
349 mixer0_out_tcon1: endpoint@1 {
350 reg = <1>;
351 remote-endpoint = <&tcon1_in_mixer0>;
352 };
353 };
354 };
355 };
356
357 mixer1: mixer@1200000 {
358 compatible = "allwinner,sun8i-a83t-de2-mixer-1";
359 reg = <0x01200000 0x100000>;
360 clocks = <&display_clocks CLK_BUS_MIXER1>,
361 <&display_clocks CLK_MIXER1>;
362 clock-names = "bus",
363 "mod";
364 resets = <&display_clocks RST_WB>;
365
366 ports {
367 #address-cells = <1>;
368 #size-cells = <0>;
369
370 mixer1_out: port@1 {
371 #address-cells = <1>;
372 #size-cells = <0>;
373 reg = <1>;
374
375 mixer1_out_tcon0: endpoint@0 {
376 reg = <0>;
377 remote-endpoint = <&tcon0_in_mixer1>;
378 };
379
380 mixer1_out_tcon1: endpoint@1 {
381 reg = <1>;
382 remote-endpoint = <&tcon1_in_mixer1>;
383 };
384 };
385 };
386 };
387
388 cpucfg@1700000 {
389 compatible = "allwinner,sun8i-a83t-cpucfg";
390 reg = <0x01700000 0x400>;
391 };
392
393 cci@1790000 {
394 compatible = "arm,cci-400";
395 #address-cells = <1>;
396 #size-cells = <1>;
397 reg = <0x01790000 0x10000>;
398 ranges = <0x0 0x01790000 0x10000>;
399
400 cci_control0: slave-if@4000 {
401 compatible = "arm,cci-400-ctrl-if";
402 interface-type = "ace";
403 reg = <0x4000 0x1000>;
404 };
405
406 cci_control1: slave-if@5000 {
407 compatible = "arm,cci-400-ctrl-if";
408 interface-type = "ace";
409 reg = <0x5000 0x1000>;
410 };
411
412 pmu@9000 {
413 compatible = "arm,cci-400-pmu,r1";
414 reg = <0x9000 0x5000>;
415 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
416 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
417 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
418 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
419 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>,
420 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
421 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
422 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
423 };
424 };
425
426 syscon: syscon@1c00000 {
427 compatible = "allwinner,sun8i-a83t-system-controller",
428 "syscon";
429 reg = <0x01c00000 0x1000>;
430 };
431
432 dma: dma-controller@1c02000 {
433 compatible = "allwinner,sun8i-a83t-dma";
434 reg = <0x01c02000 0x1000>;
435 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
436 clocks = <&ccu CLK_BUS_DMA>;
437 resets = <&ccu RST_BUS_DMA>;
438 #dma-cells = <1>;
439 };
440
441 tcon0: lcd-controller@1c0c000 {
442 compatible = "allwinner,sun8i-a83t-tcon-lcd";
443 reg = <0x01c0c000 0x1000>;
444 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
445 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
446 clock-names = "ahb", "tcon-ch0";
447 clock-output-names = "tcon-pixel-clock";
448 #clock-cells = <0>;
449 resets = <&ccu RST_BUS_TCON0>, <&ccu RST_BUS_LVDS>;
450 reset-names = "lcd", "lvds";
451
452 ports {
453 #address-cells = <1>;
454 #size-cells = <0>;
455
456 tcon0_in: port@0 {
457 #address-cells = <1>;
458 #size-cells = <0>;
459 reg = <0>;
460
461 tcon0_in_mixer0: endpoint@0 {
462 reg = <0>;
463 remote-endpoint = <&mixer0_out_tcon0>;
464 };
465
466 tcon0_in_mixer1: endpoint@1 {
467 reg = <1>;
468 remote-endpoint = <&mixer1_out_tcon0>;
469 };
470 };
471
472 tcon0_out: port@1 {
473 reg = <1>;
474 };
475 };
476 };
477
478 tcon1: lcd-controller@1c0d000 {
479 compatible = "allwinner,sun8i-a83t-tcon-tv";
480 reg = <0x01c0d000 0x1000>;
481 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
482 clocks = <&ccu CLK_BUS_TCON1>, <&ccu CLK_TCON1>;
483 clock-names = "ahb", "tcon-ch1";
484 resets = <&ccu RST_BUS_TCON1>;
485 reset-names = "lcd";
486
487 ports {
488 #address-cells = <1>;
489 #size-cells = <0>;
490
491 tcon1_in: port@0 {
492 #address-cells = <1>;
493 #size-cells = <0>;
494 reg = <0>;
495
496 tcon1_in_mixer0: endpoint@0 {
497 reg = <0>;
498 remote-endpoint = <&mixer0_out_tcon1>;
499 };
500
501 tcon1_in_mixer1: endpoint@1 {
502 reg = <1>;
503 remote-endpoint = <&mixer1_out_tcon1>;
504 };
505 };
506
507 tcon1_out: port@1 {
508 #address-cells = <1>;
509 #size-cells = <0>;
510 reg = <1>;
511
512 tcon1_out_hdmi: endpoint@1 {
513 reg = <1>;
514 remote-endpoint = <&hdmi_in_tcon1>;
515 };
516 };
517 };
518 };
519
520 mmc0: mmc@1c0f000 {
521 compatible = "allwinner,sun8i-a83t-mmc",
522 "allwinner,sun7i-a20-mmc";
523 reg = <0x01c0f000 0x1000>;
524 clocks = <&ccu CLK_BUS_MMC0>,
525 <&ccu CLK_MMC0>,
526 <&ccu CLK_MMC0_OUTPUT>,
527 <&ccu CLK_MMC0_SAMPLE>;
528 clock-names = "ahb",
529 "mmc",
530 "output",
531 "sample";
532 resets = <&ccu RST_BUS_MMC0>;
533 reset-names = "ahb";
534 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
535 status = "disabled";
536 #address-cells = <1>;
537 #size-cells = <0>;
538 };
539
540 mmc1: mmc@1c10000 {
541 compatible = "allwinner,sun8i-a83t-mmc",
542 "allwinner,sun7i-a20-mmc";
543 reg = <0x01c10000 0x1000>;
544 clocks = <&ccu CLK_BUS_MMC1>,
545 <&ccu CLK_MMC1>,
546 <&ccu CLK_MMC1_OUTPUT>,
547 <&ccu CLK_MMC1_SAMPLE>;
548 clock-names = "ahb",
549 "mmc",
550 "output",
551 "sample";
552 resets = <&ccu RST_BUS_MMC1>;
553 reset-names = "ahb";
554 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
555 pinctrl-names = "default";
556 pinctrl-0 = <&mmc1_pins>;
557 status = "disabled";
558 #address-cells = <1>;
559 #size-cells = <0>;
560 };
561
562 mmc2: mmc@1c11000 {
563 compatible = "allwinner,sun8i-a83t-emmc";
564 reg = <0x01c11000 0x1000>;
565 clocks = <&ccu CLK_BUS_MMC2>,
566 <&ccu CLK_MMC2>,
567 <&ccu CLK_MMC2_OUTPUT>,
568 <&ccu CLK_MMC2_SAMPLE>;
569 clock-names = "ahb",
570 "mmc",
571 "output",
572 "sample";
573 resets = <&ccu RST_BUS_MMC2>;
574 reset-names = "ahb";
575 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
576 status = "disabled";
577 #address-cells = <1>;
578 #size-cells = <0>;
579 };
580
581 sid: eeprom@1c14000 {
582 compatible = "allwinner,sun8i-a83t-sid";
583 reg = <0x1c14000 0x400>;
584 };
585
586 usb_otg: usb@1c19000 {
587 compatible = "allwinner,sun8i-a83t-musb",
588 "allwinner,sun8i-a33-musb";
589 reg = <0x01c19000 0x0400>;
590 clocks = <&ccu CLK_BUS_OTG>;
591 resets = <&ccu RST_BUS_OTG>;
592 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
593 interrupt-names = "mc";
594 phys = <&usbphy 0>;
595 phy-names = "usb";
596 extcon = <&usbphy 0>;
597 dr_mode = "otg";
598 status = "disabled";
599 };
600
601 usbphy: phy@1c19400 {
602 compatible = "allwinner,sun8i-a83t-usb-phy";
603 reg = <0x01c19400 0x10>,
604 <0x01c1a800 0x14>,
605 <0x01c1b800 0x14>;
606 reg-names = "phy_ctrl",
607 "pmu1",
608 "pmu2";
609 clocks = <&ccu CLK_USB_PHY0>,
610 <&ccu CLK_USB_PHY1>,
611 <&ccu CLK_USB_HSIC>,
612 <&ccu CLK_USB_HSIC_12M>;
613 clock-names = "usb0_phy",
614 "usb1_phy",
615 "usb2_phy",
616 "usb2_hsic_12M";
617 resets = <&ccu RST_USB_PHY0>,
618 <&ccu RST_USB_PHY1>,
619 <&ccu RST_USB_HSIC>;
620 reset-names = "usb0_reset",
621 "usb1_reset",
622 "usb2_reset";
623 status = "disabled";
624 #phy-cells = <1>;
625 };
626
627 ehci0: usb@1c1a000 {
628 compatible = "allwinner,sun8i-a83t-ehci",
629 "generic-ehci";
630 reg = <0x01c1a000 0x100>;
631 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
632 clocks = <&ccu CLK_BUS_EHCI0>;
633 resets = <&ccu RST_BUS_EHCI0>;
634 phys = <&usbphy 1>;
635 phy-names = "usb";
636 status = "disabled";
637 };
638
639 ohci0: usb@1c1a400 {
640 compatible = "allwinner,sun8i-a83t-ohci",
641 "generic-ohci";
642 reg = <0x01c1a400 0x100>;
643 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
644 clocks = <&ccu CLK_BUS_OHCI0>, <&ccu CLK_USB_OHCI0>;
645 resets = <&ccu RST_BUS_OHCI0>;
646 phys = <&usbphy 1>;
647 phy-names = "usb";
648 status = "disabled";
649 };
650
651 ehci1: usb@1c1b000 {
652 compatible = "allwinner,sun8i-a83t-ehci",
653 "generic-ehci";
654 reg = <0x01c1b000 0x100>;
655 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
656 clocks = <&ccu CLK_BUS_EHCI1>;
657 resets = <&ccu RST_BUS_EHCI1>;
658 phys = <&usbphy 2>;
659 phy-names = "usb";
660 status = "disabled";
661 };
662
663 ccu: clock@1c20000 {
664 compatible = "allwinner,sun8i-a83t-ccu";
665 reg = <0x01c20000 0x400>;
666 clocks = <&osc24M>, <&osc16Md512>;
667 clock-names = "hosc", "losc";
668 #clock-cells = <1>;
669 #reset-cells = <1>;
670 };
671
672 pio: pinctrl@1c20800 {
673 compatible = "allwinner,sun8i-a83t-pinctrl";
674 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
675 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>,
676 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
677 reg = <0x01c20800 0x400>;
678 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc16Md512>;
679 clock-names = "apb", "hosc", "losc";
680 gpio-controller;
681 interrupt-controller;
682 #interrupt-cells = <3>;
683 #gpio-cells = <3>;
684
685 /omit-if-no-ref/
686 csi_8bit_parallel_pins: csi-8bit-parallel-pins {
687 pins = "PE0", "PE2", "PE3", "PE6", "PE7",
688 "PE8", "PE9", "PE10", "PE11",
689 "PE12", "PE13";
690 function = "csi";
691 };
692
693 /omit-if-no-ref/
694 csi_mclk_pin: csi-mclk-pin {
695 pins = "PE1";
696 function = "csi";
697 };
698
699 emac_rgmii_pins: emac-rgmii-pins {
700 pins = "PD2", "PD3", "PD4", "PD5", "PD6", "PD7",
701 "PD11", "PD12", "PD13", "PD14", "PD18",
702 "PD19", "PD21", "PD22", "PD23";
703 function = "gmac";
704 /*
705 * data lines in RGMII mode use DDR mode
706 * and need a higher signal drive strength
707 */
708 drive-strength = <40>;
709 };
710
711 hdmi_pins: hdmi-pins {
712 pins = "PH6", "PH7", "PH8";
713 function = "hdmi";
714 };
715
716 i2c0_pins: i2c0-pins {
717 pins = "PH0", "PH1";
718 function = "i2c0";
719 };
720
721 i2c1_pins: i2c1-pins {
722 pins = "PH2", "PH3";
723 function = "i2c1";
724 };
725
726 /omit-if-no-ref/
727 i2c2_pe_pins: i2c2-pe-pins {
728 pins = "PE14", "PE15";
729 function = "i2c2";
730 };
731
732 i2c2_ph_pins: i2c2-ph-pins {
733 pins = "PH4", "PH5";
734 function = "i2c2";
735 };
736
737 i2s1_pins: i2s1-pins {
738 /* I2S1 does not have external MCLK pin */
739 pins = "PG10", "PG11", "PG12", "PG13";
740 function = "i2s1";
741 };
742
743 lcd_lvds_pins: lcd-lvds-pins {
744 pins = "PD18", "PD19", "PD20", "PD21", "PD22",
745 "PD23", "PD24", "PD25", "PD26", "PD27";
746 function = "lvds0";
747 };
748
749 mmc0_pins: mmc0-pins {
750 pins = "PF0", "PF1", "PF2",
751 "PF3", "PF4", "PF5";
752 function = "mmc0";
753 drive-strength = <30>;
754 bias-pull-up;
755 };
756
757 mmc1_pins: mmc1-pins {
758 pins = "PG0", "PG1", "PG2",
759 "PG3", "PG4", "PG5";
760 function = "mmc1";
761 drive-strength = <30>;
762 bias-pull-up;
763 };
764
765 mmc2_8bit_emmc_pins: mmc2-8bit-emmc-pins {
766 pins = "PC5", "PC6", "PC8", "PC9",
767 "PC10", "PC11", "PC12", "PC13",
768 "PC14", "PC15", "PC16";
769 function = "mmc2";
770 drive-strength = <30>;
771 bias-pull-up;
772 };
773
774 pwm_pin: pwm-pin {
775 pins = "PD28";
776 function = "pwm";
777 };
778
779 spdif_tx_pin: spdif-tx-pin {
780 pins = "PE18";
781 function = "spdif";
782 };
783
784 uart0_pb_pins: uart0-pb-pins {
785 pins = "PB9", "PB10";
786 function = "uart0";
787 };
788
789 uart0_pf_pins: uart0-pf-pins {
790 pins = "PF2", "PF4";
791 function = "uart0";
792 };
793
794 uart1_pins: uart1-pins {
795 pins = "PG6", "PG7";
796 function = "uart1";
797 };
798
799 uart1_rts_cts_pins: uart1-rts-cts-pins {
800 pins = "PG8", "PG9";
801 function = "uart1";
802 };
803
804 /omit-if-no-ref/
805 uart2_pb_pins: uart2-pb-pins {
806 pins = "PB0", "PB1";
807 function = "uart2";
808 };
809 };
810
811 timer@1c20c00 {
812 compatible = "allwinner,sun8i-a23-timer";
813 reg = <0x01c20c00 0xa0>;
814 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
815 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
816 clocks = <&osc24M>;
817 };
818
819 watchdog@1c20ca0 {
820 compatible = "allwinner,sun6i-a31-wdt";
821 reg = <0x01c20ca0 0x20>;
822 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&osc24M>;
824 };
825
826 spdif: spdif@1c21000 {
827 #sound-dai-cells = <0>;
828 compatible = "allwinner,sun8i-a83t-spdif",
829 "allwinner,sun8i-h3-spdif";
830 reg = <0x01c21000 0x400>;
831 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
832 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
833 resets = <&ccu RST_BUS_SPDIF>;
834 clock-names = "apb", "spdif";
835 dmas = <&dma 2>;
836 dma-names = "tx";
837 pinctrl-names = "default";
838 pinctrl-0 = <&spdif_tx_pin>;
839 status = "disabled";
840 };
841
842 i2s0: i2s@1c22000 {
843 #sound-dai-cells = <0>;
844 compatible = "allwinner,sun8i-a83t-i2s";
845 reg = <0x01c22000 0x400>;
846 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
847 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
848 clock-names = "apb", "mod";
849 dmas = <&dma 3>, <&dma 3>;
850 resets = <&ccu RST_BUS_I2S0>;
851 dma-names = "rx", "tx";
852 status = "disabled";
853 };
854
855 i2s1: i2s@1c22400 {
856 #sound-dai-cells = <0>;
857 compatible = "allwinner,sun8i-a83t-i2s";
858 reg = <0x01c22400 0x400>;
859 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
860 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
861 clock-names = "apb", "mod";
862 dmas = <&dma 4>, <&dma 4>;
863 resets = <&ccu RST_BUS_I2S1>;
864 dma-names = "rx", "tx";
865 pinctrl-names = "default";
866 pinctrl-0 = <&i2s1_pins>;
867 status = "disabled";
868 };
869
870 i2s2: i2s@1c22800 {
871 #sound-dai-cells = <0>;
872 compatible = "allwinner,sun8i-a83t-i2s";
873 reg = <0x01c22800 0x400>;
874 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
875 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
876 clock-names = "apb", "mod";
877 dmas = <&dma 27>;
878 resets = <&ccu RST_BUS_I2S2>;
879 dma-names = "tx";
880 status = "disabled";
881 };
882
883 pwm: pwm@1c21400 {
884 compatible = "allwinner,sun8i-a83t-pwm",
885 "allwinner,sun8i-h3-pwm";
886 reg = <0x01c21400 0x400>;
887 clocks = <&osc24M>;
888 #pwm-cells = <3>;
889 status = "disabled";
890 };
891
892 uart0: serial@1c28000 {
893 compatible = "snps,dw-apb-uart";
894 reg = <0x01c28000 0x400>;
895 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
896 reg-shift = <2>;
897 reg-io-width = <4>;
898 clocks = <&ccu CLK_BUS_UART0>;
899 resets = <&ccu RST_BUS_UART0>;
900 status = "disabled";
901 };
902
903 uart1: serial@1c28400 {
904 compatible = "snps,dw-apb-uart";
905 reg = <0x01c28400 0x400>;
906 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
907 reg-shift = <2>;
908 reg-io-width = <4>;
909 clocks = <&ccu CLK_BUS_UART1>;
910 resets = <&ccu RST_BUS_UART1>;
911 status = "disabled";
912 };
913
914 uart2: serial@1c28800 {
915 compatible = "snps,dw-apb-uart";
916 reg = <0x01c28800 0x400>;
917 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
918 reg-shift = <2>;
919 reg-io-width = <4>;
920 clocks = <&ccu CLK_BUS_UART2>;
921 resets = <&ccu RST_BUS_UART2>;
922 status = "disabled";
923 };
924
925 uart3: serial@1c28c00 {
926 compatible = "snps,dw-apb-uart";
927 reg = <0x01c28c00 0x400>;
928 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
929 reg-shift = <2>;
930 reg-io-width = <4>;
931 clocks = <&ccu CLK_BUS_UART3>;
932 resets = <&ccu RST_BUS_UART3>;
933 status = "disabled";
934 };
935
936 uart4: serial@1c29000 {
937 compatible = "snps,dw-apb-uart";
938 reg = <0x01c29000 0x400>;
939 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
940 reg-shift = <2>;
941 reg-io-width = <4>;
942 clocks = <&ccu CLK_BUS_UART4>;
943 resets = <&ccu RST_BUS_UART4>;
944 status = "disabled";
945 };
946
947 i2c0: i2c@1c2ac00 {
948 compatible = "allwinner,sun8i-a83t-i2c",
949 "allwinner,sun6i-a31-i2c";
950 reg = <0x01c2ac00 0x400>;
951 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
952 clocks = <&ccu CLK_BUS_I2C0>;
953 resets = <&ccu RST_BUS_I2C0>;
954 pinctrl-names = "default";
955 pinctrl-0 = <&i2c0_pins>;
956 status = "disabled";
957 #address-cells = <1>;
958 #size-cells = <0>;
959 };
960
961 i2c1: i2c@1c2b000 {
962 compatible = "allwinner,sun8i-a83t-i2c",
963 "allwinner,sun6i-a31-i2c";
964 reg = <0x01c2b000 0x400>;
965 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
966 clocks = <&ccu CLK_BUS_I2C1>;
967 resets = <&ccu RST_BUS_I2C1>;
968 pinctrl-names = "default";
969 pinctrl-0 = <&i2c1_pins>;
970 status = "disabled";
971 #address-cells = <1>;
972 #size-cells = <0>;
973 };
974
975 i2c2: i2c@1c2b400 {
976 compatible = "allwinner,sun8i-a83t-i2c",
977 "allwinner,sun6i-a31-i2c";
978 reg = <0x01c2b400 0x400>;
979 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
980 clocks = <&ccu CLK_BUS_I2C2>;
981 resets = <&ccu RST_BUS_I2C2>;
982 status = "disabled";
983 #address-cells = <1>;
984 #size-cells = <0>;
985 };
986
987 emac: ethernet@1c30000 {
988 compatible = "allwinner,sun8i-a83t-emac";
989 syscon = <&syscon>;
990 reg = <0x01c30000 0x104>;
991 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
992 interrupt-names = "macirq";
993 resets = <&ccu 13>;
994 reset-names = "stmmaceth";
995 clocks = <&ccu 27>;
996 clock-names = "stmmaceth";
997 status = "disabled";
998
999 mdio: mdio {
1000 compatible = "snps,dwmac-mdio";
1001 #address-cells = <1>;
1002 #size-cells = <0>;
1003 };
1004 };
1005
1006 gic: interrupt-controller@1c81000 {
1007 compatible = "arm,gic-400";
1008 reg = <0x01c81000 0x1000>,
1009 <0x01c82000 0x2000>,
1010 <0x01c84000 0x2000>,
1011 <0x01c86000 0x2000>;
1012 interrupt-controller;
1013 #interrupt-cells = <3>;
1014 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
1015 };
1016
1017 csi: camera@1cb0000 {
1018 compatible = "allwinner,sun8i-a83t-csi";
1019 reg = <0x01cb0000 0x1000>;
1020 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
1021 clocks = <&ccu CLK_BUS_CSI>,
1022 <&ccu CLK_CSI_SCLK>,
1023 <&ccu CLK_DRAM_CSI>;
1024 clock-names = "bus", "mod", "ram";
1025 resets = <&ccu RST_BUS_CSI>;
1026 status = "disabled";
1027
1028 csi_in: port {
1029 };
1030 };
1031
1032 hdmi: hdmi@1ee0000 {
1033 compatible = "allwinner,sun8i-a83t-dw-hdmi";
1034 reg = <0x01ee0000 0x10000>;
1035 reg-io-width = <1>;
1036 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
1037 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>,
1038 <&ccu CLK_HDMI>;
1039 clock-names = "iahb", "isfr", "tmds";
1040 resets = <&ccu RST_BUS_HDMI1>;
1041 reset-names = "ctrl";
1042 phys = <&hdmi_phy>;
1043 phy-names = "phy";
1044 pinctrl-names = "default";
1045 pinctrl-0 = <&hdmi_pins>;
1046 status = "disabled";
1047
1048 ports {
1049 #address-cells = <1>;
1050 #size-cells = <0>;
1051
1052 hdmi_in: port@0 {
1053 reg = <0>;
1054
1055 hdmi_in_tcon1: endpoint {
1056 remote-endpoint = <&tcon1_out_hdmi>;
1057 };
1058 };
1059
1060 hdmi_out: port@1 {
1061 reg = <1>;
1062 };
1063 };
1064 };
1065
1066 hdmi_phy: hdmi-phy@1ef0000 {
1067 compatible = "allwinner,sun8i-a83t-hdmi-phy";
1068 reg = <0x01ef0000 0x10000>;
1069 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_SLOW>;
1070 clock-names = "bus", "mod";
1071 resets = <&ccu RST_BUS_HDMI0>;
1072 reset-names = "phy";
1073 #phy-cells = <0>;
1074 };
1075
1076 r_intc: interrupt-controller@1f00c00 {
1077 compatible = "allwinner,sun8i-a83t-r-intc",
1078 "allwinner,sun6i-a31-r-intc";
1079 interrupt-controller;
1080 #interrupt-cells = <2>;
1081 reg = <0x01f00c00 0x400>;
1082 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
1083 };
1084
1085 r_ccu: clock@1f01400 {
1086 compatible = "allwinner,sun8i-a83t-r-ccu";
1087 reg = <0x01f01400 0x400>;
1088 clocks = <&osc24M>, <&osc16Md512>, <&osc16M>,
1089 <&ccu 6>;
1090 clock-names = "hosc", "losc", "iosc", "pll-periph";
1091 #clock-cells = <1>;
1092 #reset-cells = <1>;
1093 };
1094
1095 r_cpucfg@1f01c00 {
1096 compatible = "allwinner,sun8i-a83t-r-cpucfg";
1097 reg = <0x1f01c00 0x400>;
1098 };
1099
1100 r_cir: ir@1f02000 {
1101 compatible = "allwinner,sun8i-a83t-ir",
1102 "allwinner,sun6i-a31-ir";
1103 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
1104 clock-names = "apb", "ir";
1105 resets = <&r_ccu RST_APB0_IR>;
1106 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1107 reg = <0x01f02000 0x400>;
1108 pinctrl-names = "default";
1109 pinctrl-0 = <&r_cir_pin>;
1110 status = "disabled";
1111 };
1112
1113 r_lradc: lradc@1f03c00 {
1114 compatible = "allwinner,sun8i-a83t-r-lradc";
1115 reg = <0x01f03c00 0x100>;
1116 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
1117 status = "disabled";
1118 };
1119
1120 r_pio: pinctrl@1f02c00 {
1121 compatible = "allwinner,sun8i-a83t-r-pinctrl";
1122 reg = <0x01f02c00 0x400>;
1123 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
1124 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
1125 <&osc16Md512>;
1126 clock-names = "apb", "hosc", "losc";
1127 gpio-controller;
1128 #gpio-cells = <3>;
1129 interrupt-controller;
1130 #interrupt-cells = <3>;
1131
1132 r_cir_pin: r-cir-pin {
1133 pins = "PL12";
1134 function = "s_cir_rx";
1135 };
1136
1137 r_rsb_pins: r-rsb-pins {
1138 pins = "PL0", "PL1";
1139 function = "s_rsb";
1140 drive-strength = <20>;
1141 bias-pull-up;
1142 };
1143 };
1144
1145 r_rsb: rsb@1f03400 {
1146 compatible = "allwinner,sun8i-a83t-rsb",
1147 "allwinner,sun8i-a23-rsb";
1148 reg = <0x01f03400 0x400>;
1149 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1150 clocks = <&r_ccu CLK_APB0_RSB>;
1151 clock-frequency = <3000000>;
1152 resets = <&r_ccu RST_APB0_RSB>;
1153 pinctrl-names = "default";
1154 pinctrl-0 = <&r_rsb_pins>;
1155 status = "disabled";
1156 #address-cells = <1>;
1157 #size-cells = <0>;
1158 };
1159 };
1160};