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1/*
2 * DTS file for SPEAr320 SoC
3 *
4 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17 ahb {
18 #address-cells = <1>;
19 #size-cells = <1>;
20 compatible = "simple-bus";
21 ranges = <0x40000000 0x40000000 0x80000000
22 0xd0000000 0xd0000000 0x30000000>;
23
24 pinmux: pinmux@b3000000 {
25 compatible = "st,spear320-pinmux";
26 reg = <0xb3000000 0x1000>;
27 #gpio-range-cells = <3>;
28 };
29
30 clcd@90000000 {
31 compatible = "arm,pl110", "arm,primecell";
32 reg = <0x90000000 0x1000>;
33 interrupts = <8>;
34 interrupt-parent = <&shirq>;
35 status = "disabled";
36 };
37
38 fsmc: flash@4c000000 {
39 compatible = "st,spear600-fsmc-nand";
40 #address-cells = <1>;
41 #size-cells = <1>;
42 reg = <0x4c000000 0x1000 /* FSMC Register */
43 0x50000000 0x0010 /* NAND Base DATA */
44 0x50020000 0x0010 /* NAND Base ADDR */
45 0x50010000 0x0010>; /* NAND Base CMD */
46 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
47 status = "disabled";
48 };
49
50 sdhci@70000000 {
51 compatible = "st,sdhci-spear";
52 reg = <0x70000000 0x100>;
53 interrupts = <10>;
54 interrupt-parent = <&shirq>;
55 status = "disabled";
56 };
57
58 shirq: interrupt-controller@0xb3000000 {
59 compatible = "st,spear320-shirq";
60 reg = <0xb3000000 0x1000>;
61 interrupts = <30 28 29 1>;
62 #interrupt-cells = <1>;
63 interrupt-controller;
64 };
65
66 spi1: spi@a5000000 {
67 compatible = "arm,pl022", "arm,primecell";
68 reg = <0xa5000000 0x1000>;
69 interrupts = <15>;
70 interrupt-parent = <&shirq>;
71 #address-cells = <1>;
72 #size-cells = <0>;
73 status = "disabled";
74 };
75
76 spi2: spi@a6000000 {
77 compatible = "arm,pl022", "arm,primecell";
78 reg = <0xa6000000 0x1000>;
79 interrupts = <16>;
80 interrupt-parent = <&shirq>;
81 #address-cells = <1>;
82 #size-cells = <0>;
83 status = "disabled";
84 };
85
86 pwm: pwm@a8000000 {
87 compatible ="st,spear-pwm";
88 reg = <0xa8000000 0x1000>;
89 #pwm-cells = <2>;
90 status = "disabled";
91 };
92
93 apb {
94 #address-cells = <1>;
95 #size-cells = <1>;
96 compatible = "simple-bus";
97 ranges = <0xa0000000 0xa0000000 0x20000000
98 0xd0000000 0xd0000000 0x30000000>;
99
100 i2c1: i2c@a7000000 {
101 #address-cells = <1>;
102 #size-cells = <0>;
103 compatible = "snps,designware-i2c";
104 reg = <0xa7000000 0x1000>;
105 interrupts = <21>;
106 interrupt-parent = <&shirq>;
107 status = "disabled";
108 };
109
110 serial@a3000000 {
111 compatible = "arm,pl011", "arm,primecell";
112 reg = <0xa3000000 0x1000>;
113 interrupts = <13>;
114 interrupt-parent = <&shirq>;
115 status = "disabled";
116 };
117
118 serial@a4000000 {
119 compatible = "arm,pl011", "arm,primecell";
120 reg = <0xa4000000 0x1000>;
121 interrupts = <14>;
122 interrupt-parent = <&shirq>;
123 status = "disabled";
124 };
125
126 gpiopinctrl: gpio@b3000000 {
127 compatible = "st,spear-plgpio";
128 reg = <0xb3000000 0x1000>;
129 #interrupt-cells = <1>;
130 interrupt-controller;
131 gpio-controller;
132 #gpio-cells = <2>;
133 gpio-ranges = <&pinmux 0 0 102>;
134 status = "disabled";
135
136 st-plgpio,ngpio = <102>;
137 st-plgpio,enb-reg = <0x24>;
138 st-plgpio,wdata-reg = <0x34>;
139 st-plgpio,dir-reg = <0x44>;
140 st-plgpio,ie-reg = <0x64>;
141 st-plgpio,rdata-reg = <0x54>;
142 st-plgpio,mis-reg = <0x84>;
143 st-plgpio,eit-reg = <0x94>;
144 };
145 };
146 };
147};
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * DTS file for SPEAr320 SoC
4 *
5 * Copyright 2012 Viresh Kumar <vireshk@kernel.org>
6 */
7
8/include/ "spear3xx.dtsi"
9
10/ {
11 ahb {
12 #address-cells = <1>;
13 #size-cells = <1>;
14 compatible = "simple-bus";
15 ranges = <0x40000000 0x40000000 0x80000000
16 0xd0000000 0xd0000000 0x30000000>;
17
18 pinmux: pinmux@b3000000 {
19 compatible = "st,spear320-pinmux";
20 reg = <0xb3000000 0x1000>;
21 #gpio-range-cells = <3>;
22 };
23
24 clcd@90000000 {
25 compatible = "arm,pl110", "arm,primecell";
26 reg = <0x90000000 0x1000>;
27 interrupts = <8>;
28 interrupt-parent = <&shirq>;
29 status = "disabled";
30 };
31
32 fsmc: flash@4c000000 {
33 compatible = "st,spear600-fsmc-nand";
34 #address-cells = <1>;
35 #size-cells = <1>;
36 reg = <0x4c000000 0x1000 /* FSMC Register */
37 0x50000000 0x0010 /* NAND Base DATA */
38 0x50020000 0x0010 /* NAND Base ADDR */
39 0x50010000 0x0010>; /* NAND Base CMD */
40 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
41 status = "disabled";
42 };
43
44 sdhci@70000000 {
45 compatible = "st,sdhci-spear";
46 reg = <0x70000000 0x100>;
47 interrupts = <10>;
48 interrupt-parent = <&shirq>;
49 status = "disabled";
50 };
51
52 shirq: interrupt-controller@0xb3000000 {
53 compatible = "st,spear320-shirq";
54 reg = <0xb3000000 0x1000>;
55 interrupts = <30 28 29 1>;
56 #interrupt-cells = <1>;
57 interrupt-controller;
58 };
59
60 spi1: spi@a5000000 {
61 compatible = "arm,pl022", "arm,primecell";
62 reg = <0xa5000000 0x1000>;
63 interrupts = <15>;
64 interrupt-parent = <&shirq>;
65 #address-cells = <1>;
66 #size-cells = <0>;
67 status = "disabled";
68 };
69
70 spi2: spi@a6000000 {
71 compatible = "arm,pl022", "arm,primecell";
72 reg = <0xa6000000 0x1000>;
73 interrupts = <16>;
74 interrupt-parent = <&shirq>;
75 #address-cells = <1>;
76 #size-cells = <0>;
77 status = "disabled";
78 };
79
80 pwm: pwm@a8000000 {
81 compatible ="st,spear-pwm";
82 reg = <0xa8000000 0x1000>;
83 #pwm-cells = <2>;
84 status = "disabled";
85 };
86
87 apb {
88 #address-cells = <1>;
89 #size-cells = <1>;
90 compatible = "simple-bus";
91 ranges = <0xa0000000 0xa0000000 0x20000000
92 0xd0000000 0xd0000000 0x30000000>;
93
94 i2c1: i2c@a7000000 {
95 #address-cells = <1>;
96 #size-cells = <0>;
97 compatible = "snps,designware-i2c";
98 reg = <0xa7000000 0x1000>;
99 interrupts = <21>;
100 interrupt-parent = <&shirq>;
101 status = "disabled";
102 };
103
104 serial@a3000000 {
105 compatible = "arm,pl011", "arm,primecell";
106 reg = <0xa3000000 0x1000>;
107 interrupts = <13>;
108 interrupt-parent = <&shirq>;
109 status = "disabled";
110 };
111
112 serial@a4000000 {
113 compatible = "arm,pl011", "arm,primecell";
114 reg = <0xa4000000 0x1000>;
115 interrupts = <14>;
116 interrupt-parent = <&shirq>;
117 status = "disabled";
118 };
119
120 gpiopinctrl: gpio@b3000000 {
121 compatible = "st,spear-plgpio";
122 reg = <0xb3000000 0x1000>;
123 #interrupt-cells = <1>;
124 interrupt-controller;
125 gpio-controller;
126 #gpio-cells = <2>;
127 gpio-ranges = <&pinmux 0 0 102>;
128 status = "disabled";
129
130 st-plgpio,ngpio = <102>;
131 st-plgpio,enb-reg = <0x24>;
132 st-plgpio,wdata-reg = <0x34>;
133 st-plgpio,dir-reg = <0x44>;
134 st-plgpio,ie-reg = <0x64>;
135 st-plgpio,rdata-reg = <0x54>;
136 st-plgpio,mis-reg = <0x84>;
137 st-plgpio,eit-reg = <0x94>;
138 };
139 };
140 };
141};