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1/*
2 * Copyright (C) 2011 Picochip, Jamie Iles
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14/ {
15 model = "Picochip picoXcell PC3X2";
16 compatible = "picochip,pc3x2";
17 #address-cells = <1>;
18 #size-cells = <1>;
19
20 cpus {
21 #address-cells = <0>;
22 #size-cells = <0>;
23
24 cpu {
25 compatible = "arm,arm1176jz-s";
26 device_type = "cpu";
27 clock-frequency = <400000000>;
28 d-cache-line-size = <32>;
29 d-cache-size = <32768>;
30 i-cache-line-size = <32>;
31 i-cache-size = <32768>;
32 };
33 };
34
35 clocks {
36 #address-cells = <1>;
37 #size-cells = <1>;
38 ranges;
39
40 pclk: clock@0 {
41 compatible = "fixed-clock";
42 clock-outputs = "bus", "pclk";
43 clock-frequency = <200000000>;
44 ref-clock = <&ref_clk>, "ref";
45 };
46 };
47
48 paxi {
49 compatible = "simple-bus";
50 #address-cells = <1>;
51 #size-cells = <1>;
52 ranges = <0 0x80000000 0x400000>;
53
54 emac: gem@30000 {
55 compatible = "cadence,gem";
56 reg = <0x30000 0x10000>;
57 interrupts = <31>;
58 };
59
60 dmac1: dmac@40000 {
61 compatible = "snps,dw-dmac";
62 reg = <0x40000 0x10000>;
63 interrupts = <25>;
64 };
65
66 dmac2: dmac@50000 {
67 compatible = "snps,dw-dmac";
68 reg = <0x50000 0x10000>;
69 interrupts = <26>;
70 };
71
72 vic0: interrupt-controller@60000 {
73 compatible = "arm,pl192-vic";
74 interrupt-controller;
75 reg = <0x60000 0x1000>;
76 #interrupt-cells = <1>;
77 };
78
79 vic1: interrupt-controller@64000 {
80 compatible = "arm,pl192-vic";
81 interrupt-controller;
82 reg = <0x64000 0x1000>;
83 #interrupt-cells = <1>;
84 };
85
86 fuse: picoxcell-fuse@80000 {
87 compatible = "picoxcell,fuse-pc3x2";
88 reg = <0x80000 0x10000>;
89 };
90
91 ssi: picoxcell-spi@90000 {
92 compatible = "picoxcell,spi";
93 reg = <0x90000 0x10000>;
94 interrupt-parent = <&vic0>;
95 interrupts = <10>;
96 };
97
98 ipsec: spacc@100000 {
99 compatible = "picochip,spacc-ipsec";
100 reg = <0x100000 0x10000>;
101 interrupt-parent = <&vic0>;
102 interrupts = <24>;
103 ref-clock = <&pclk>, "ref";
104 };
105
106 srtp: spacc@140000 {
107 compatible = "picochip,spacc-srtp";
108 reg = <0x140000 0x10000>;
109 interrupt-parent = <&vic0>;
110 interrupts = <23>;
111 };
112
113 l2_engine: spacc@180000 {
114 compatible = "picochip,spacc-l2";
115 reg = <0x180000 0x10000>;
116 interrupt-parent = <&vic0>;
117 interrupts = <22>;
118 ref-clock = <&pclk>, "ref";
119 };
120
121 apb {
122 compatible = "simple-bus";
123 #address-cells = <1>;
124 #size-cells = <1>;
125 ranges = <0 0x200000 0x80000>;
126
127 rtc0: rtc@0 {
128 compatible = "picochip,pc3x2-rtc";
129 clock-freq = <200000000>;
130 reg = <0x00000 0xf>;
131 interrupt-parent = <&vic1>;
132 interrupts = <8>;
133 };
134
135 timer0: timer@10000 {
136 compatible = "picochip,pc3x2-timer";
137 interrupt-parent = <&vic0>;
138 interrupts = <4>;
139 clock-freq = <200000000>;
140 reg = <0x10000 0x14>;
141 };
142
143 timer1: timer@10014 {
144 compatible = "picochip,pc3x2-timer";
145 interrupt-parent = <&vic0>;
146 interrupts = <5>;
147 clock-freq = <200000000>;
148 reg = <0x10014 0x14>;
149 };
150
151 timer2: timer@10028 {
152 compatible = "picochip,pc3x2-timer";
153 interrupt-parent = <&vic0>;
154 interrupts = <6>;
155 clock-freq = <200000000>;
156 reg = <0x10028 0x14>;
157 };
158
159 timer3: timer@1003c {
160 compatible = "picochip,pc3x2-timer";
161 interrupt-parent = <&vic0>;
162 interrupts = <7>;
163 clock-freq = <200000000>;
164 reg = <0x1003c 0x14>;
165 };
166
167 gpio: gpio@20000 {
168 compatible = "snps,dw-apb-gpio";
169 reg = <0x20000 0x1000>;
170 #address-cells = <1>;
171 #size-cells = <0>;
172 reg-io-width = <4>;
173
174 banka: gpio-controller@0 {
175 compatible = "snps,dw-apb-gpio-bank";
176 gpio-controller;
177 #gpio-cells = <2>;
178 gpio-generic,nr-gpio = <8>;
179
180 regoffset-dat = <0x50>;
181 regoffset-set = <0x00>;
182 regoffset-dirout = <0x04>;
183 };
184
185 bankb: gpio-controller@1 {
186 compatible = "snps,dw-apb-gpio-bank";
187 gpio-controller;
188 #gpio-cells = <2>;
189 gpio-generic,nr-gpio = <8>;
190
191 regoffset-dat = <0x54>;
192 regoffset-set = <0x0c>;
193 regoffset-dirout = <0x10>;
194 };
195 };
196
197 uart0: uart@30000 {
198 compatible = "snps,dw-apb-uart";
199 reg = <0x30000 0x1000>;
200 interrupt-parent = <&vic1>;
201 interrupts = <10>;
202 clock-frequency = <3686400>;
203 reg-shift = <2>;
204 reg-io-width = <4>;
205 };
206
207 uart1: uart@40000 {
208 compatible = "snps,dw-apb-uart";
209 reg = <0x40000 0x1000>;
210 interrupt-parent = <&vic1>;
211 interrupts = <9>;
212 clock-frequency = <3686400>;
213 reg-shift = <2>;
214 reg-io-width = <4>;
215 };
216
217 wdog: watchdog@50000 {
218 compatible = "snps,dw-apb-wdg";
219 reg = <0x50000 0x10000>;
220 interrupt-parent = <&vic0>;
221 interrupts = <11>;
222 bus-clock = <&pclk>, "bus";
223 };
224 };
225 };
226
227 rwid-axi {
228 #address-cells = <1>;
229 #size-cells = <1>;
230 compatible = "simple-bus";
231 ranges;
232
233 ebi@50000000 {
234 compatible = "simple-bus";
235 #address-cells = <2>;
236 #size-cells = <1>;
237 ranges = <0 0 0x40000000 0x08000000
238 1 0 0x48000000 0x08000000
239 2 0 0x50000000 0x08000000
240 3 0 0x58000000 0x08000000>;
241 };
242
243 axi2pico@c0000000 {
244 compatible = "picochip,axi2pico-pc3x2";
245 reg = <0xc0000000 0x10000>;
246 interrupts = <13 14 15 16 17 18 19 20 21>;
247 };
248 };
249};
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (C) 2011 Picochip, Jamie Iles
4 */
5/ {
6 model = "Picochip picoXcell PC3X2";
7 compatible = "picochip,pc3x2";
8 #address-cells = <1>;
9 #size-cells = <1>;
10
11 cpus {
12 #address-cells = <0>;
13 #size-cells = <0>;
14
15 cpu {
16 compatible = "arm,arm1176jz-s";
17 device_type = "cpu";
18 clock-frequency = <400000000>;
19 d-cache-line-size = <32>;
20 d-cache-size = <32768>;
21 i-cache-line-size = <32>;
22 i-cache-size = <32768>;
23 };
24 };
25
26 clocks {
27 #address-cells = <1>;
28 #size-cells = <1>;
29 ranges;
30
31 pclk: clock@0 {
32 compatible = "fixed-clock";
33 clock-outputs = "bus", "pclk";
34 clock-frequency = <200000000>;
35 ref-clock = <&ref_clk>, "ref";
36 };
37 };
38
39 paxi {
40 compatible = "simple-bus";
41 #address-cells = <1>;
42 #size-cells = <1>;
43 ranges = <0 0x80000000 0x400000>;
44
45 emac: gem@30000 {
46 compatible = "cadence,gem";
47 reg = <0x30000 0x10000>;
48 interrupts = <31>;
49 };
50
51 dmac1: dmac@40000 {
52 compatible = "snps,dw-dmac";
53 reg = <0x40000 0x10000>;
54 interrupts = <25>;
55 };
56
57 dmac2: dmac@50000 {
58 compatible = "snps,dw-dmac";
59 reg = <0x50000 0x10000>;
60 interrupts = <26>;
61 };
62
63 vic0: interrupt-controller@60000 {
64 compatible = "arm,pl192-vic";
65 interrupt-controller;
66 reg = <0x60000 0x1000>;
67 #interrupt-cells = <1>;
68 };
69
70 vic1: interrupt-controller@64000 {
71 compatible = "arm,pl192-vic";
72 interrupt-controller;
73 reg = <0x64000 0x1000>;
74 #interrupt-cells = <1>;
75 };
76
77 fuse: picoxcell-fuse@80000 {
78 compatible = "picoxcell,fuse-pc3x2";
79 reg = <0x80000 0x10000>;
80 };
81
82 ssi: picoxcell-spi@90000 {
83 compatible = "picoxcell,spi";
84 reg = <0x90000 0x10000>;
85 interrupt-parent = <&vic0>;
86 interrupts = <10>;
87 };
88
89 ipsec: spacc@100000 {
90 compatible = "picochip,spacc-ipsec";
91 reg = <0x100000 0x10000>;
92 interrupt-parent = <&vic0>;
93 interrupts = <24>;
94 ref-clock = <&pclk>, "ref";
95 };
96
97 srtp: spacc@140000 {
98 compatible = "picochip,spacc-srtp";
99 reg = <0x140000 0x10000>;
100 interrupt-parent = <&vic0>;
101 interrupts = <23>;
102 };
103
104 l2_engine: spacc@180000 {
105 compatible = "picochip,spacc-l2";
106 reg = <0x180000 0x10000>;
107 interrupt-parent = <&vic0>;
108 interrupts = <22>;
109 ref-clock = <&pclk>, "ref";
110 };
111
112 apb {
113 compatible = "simple-bus";
114 #address-cells = <1>;
115 #size-cells = <1>;
116 ranges = <0 0x200000 0x80000>;
117
118 rtc0: rtc@0 {
119 compatible = "picochip,pc3x2-rtc";
120 clock-freq = <200000000>;
121 reg = <0x00000 0xf>;
122 interrupt-parent = <&vic1>;
123 interrupts = <8>;
124 };
125
126 timer0: timer@10000 {
127 compatible = "picochip,pc3x2-timer";
128 interrupt-parent = <&vic0>;
129 interrupts = <4>;
130 clock-freq = <200000000>;
131 reg = <0x10000 0x14>;
132 };
133
134 timer1: timer@10014 {
135 compatible = "picochip,pc3x2-timer";
136 interrupt-parent = <&vic0>;
137 interrupts = <5>;
138 clock-freq = <200000000>;
139 reg = <0x10014 0x14>;
140 };
141
142 timer2: timer@10028 {
143 compatible = "picochip,pc3x2-timer";
144 interrupt-parent = <&vic0>;
145 interrupts = <6>;
146 clock-freq = <200000000>;
147 reg = <0x10028 0x14>;
148 };
149
150 timer3: timer@1003c {
151 compatible = "picochip,pc3x2-timer";
152 interrupt-parent = <&vic0>;
153 interrupts = <7>;
154 clock-freq = <200000000>;
155 reg = <0x1003c 0x14>;
156 };
157
158 gpio: gpio@20000 {
159 compatible = "snps,dw-apb-gpio";
160 reg = <0x20000 0x1000>;
161 #address-cells = <1>;
162 #size-cells = <0>;
163 reg-io-width = <4>;
164
165 banka: gpio-controller@0 {
166 compatible = "snps,dw-apb-gpio-bank";
167 gpio-controller;
168 #gpio-cells = <2>;
169 gpio-generic,nr-gpio = <8>;
170
171 regoffset-dat = <0x50>;
172 regoffset-set = <0x00>;
173 regoffset-dirout = <0x04>;
174 };
175
176 bankb: gpio-controller@1 {
177 compatible = "snps,dw-apb-gpio-bank";
178 gpio-controller;
179 #gpio-cells = <2>;
180 gpio-generic,nr-gpio = <8>;
181
182 regoffset-dat = <0x54>;
183 regoffset-set = <0x0c>;
184 regoffset-dirout = <0x10>;
185 };
186 };
187
188 uart0: uart@30000 {
189 compatible = "snps,dw-apb-uart";
190 reg = <0x30000 0x1000>;
191 interrupt-parent = <&vic1>;
192 interrupts = <10>;
193 clock-frequency = <3686400>;
194 reg-shift = <2>;
195 reg-io-width = <4>;
196 };
197
198 uart1: uart@40000 {
199 compatible = "snps,dw-apb-uart";
200 reg = <0x40000 0x1000>;
201 interrupt-parent = <&vic1>;
202 interrupts = <9>;
203 clock-frequency = <3686400>;
204 reg-shift = <2>;
205 reg-io-width = <4>;
206 };
207
208 wdog: watchdog@50000 {
209 compatible = "snps,dw-apb-wdg";
210 reg = <0x50000 0x10000>;
211 interrupt-parent = <&vic0>;
212 interrupts = <11>;
213 bus-clock = <&pclk>, "bus";
214 };
215 };
216 };
217
218 rwid-axi {
219 #address-cells = <1>;
220 #size-cells = <1>;
221 compatible = "simple-bus";
222 ranges;
223
224 ebi@50000000 {
225 compatible = "simple-bus";
226 #address-cells = <2>;
227 #size-cells = <1>;
228 ranges = <0 0 0x40000000 0x08000000
229 1 0 0x48000000 0x08000000
230 2 0 0x50000000 0x08000000
231 3 0 0x58000000 0x08000000>;
232 };
233
234 axi2pico@c0000000 {
235 compatible = "picochip,axi2pico-pc3x2";
236 reg = <0xc0000000 0x10000>;
237 interrupts = <13 14 15 16 17 18 19 20 21>;
238 };
239 };
240};