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1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for K2G EVM
4 *
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
6 */
7/dts-v1/;
8
9#include "keystone-k2g.dtsi"
10
11/ {
12 compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
13 model = "Texas Instruments K2G General Purpose EVM";
14
15 memory@800000000 {
16 device_type = "memory";
17 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
18 };
19
20 reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
23 ranges;
24
25 dsp_common_memory: dsp-common-memory@81f800000 {
26 compatible = "shared-dma-pool";
27 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
28 reusable;
29 status = "okay";
30 };
31 };
32
33 vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin {
34 compatible = "regulator-fixed";
35 regulator-name = "mmc0_fixed";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 regulator-always-on;
39 };
40};
41
42&k2g_pinctrl {
43 uart0_pins: pinmux_uart0_pins {
44 pinctrl-single,pins = <
45 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
46 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
47 >;
48 };
49
50 mmc0_pins: pinmux_mmc0_pins {
51 pinctrl-single,pins = <
52 K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */
53 K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */
54 K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */
55 K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */
56 K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */
57 K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */
58 K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */
59 >;
60 };
61
62 mmc1_pins: pinmux_mmc1_pins {
63 pinctrl-single,pins = <
64 K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */
65 K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */
66 K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */
67 K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */
68 K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
69 K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
70 K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
71 K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
72 K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
73 K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
74 >;
75 };
76
77 i2c0_pins: pinmux_i2c0_pins {
78 pinctrl-single,pins = <
79 K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
80 K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
81 >;
82 };
83
84 ecap0_pins: ecap0_pins {
85 pinctrl-single,pins = <
86 K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */
87 >;
88 };
89
90 spi1_pins: pinmux_spi1_pins {
91 pinctrl-single,pins = <
92 K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */
93 K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */
94 K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */
95 K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */
96 >;
97 };
98
99 qspi_pins: pinmux_qspi_pins {
100 pinctrl-single,pins = <
101 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
102 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
103 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
104 K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
105 K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
106 K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
107 K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
108 >;
109 };
110
111 uart2_pins: pinmux_uart2_pins {
112 pinctrl-single,pins = <
113 K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */
114 K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */
115 >;
116 };
117};
118
119&uart0 {
120 pinctrl-names = "default";
121 pinctrl-0 = <&uart0_pins>;
122 status = "okay";
123};
124
125&gpio1 {
126 status = "okay";
127};
128
129&mmc0 {
130 pinctrl-names = "default";
131 pinctrl-0 = <&mmc0_pins>;
132 vmmc-supply = <&vcc3v3_dcin_reg>;
133 cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
134 status = "okay";
135};
136
137&mmc1 {
138 pinctrl-names = "default";
139 pinctrl-0 = <&mmc1_pins>;
140 vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */
141 ti,non-removable;
142 status = "okay";
143};
144
145&dsp0 {
146 memory-region = <&dsp_common_memory>;
147 status = "okay";
148};
149
150&i2c0 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&i2c0_pins>;
153 status = "okay";
154
155 eeprom@50 {
156 compatible = "atmel,24c1024";
157 reg = <0x50>;
158 };
159};
160
161&keystone_usb0 {
162 status = "okay";
163};
164
165&usb0_phy {
166 status = "okay";
167};
168
169&usb0 {
170 dr_mode = "host";
171 status = "okay";
172};
173
174&keystone_usb1 {
175 status = "okay";
176};
177
178&usb1_phy {
179 status = "okay";
180};
181
182&usb1 {
183 dr_mode = "peripheral";
184 status = "okay";
185};
186
187&ecap0 {
188 status = "okay";
189 pinctrl-names = "default";
190 pinctrl-0 = <&ecap0_pins>;
191};
192
193&spi1 {
194 pinctrl-names = "default";
195 pinctrl-0 = <&spi1_pins>;
196 status = "okay";
197
198 spi_nor: flash@0 {
199 #address-cells = <1>;
200 #size-cells = <1>;
201 compatible = "jedec,spi-nor";
202 spi-max-frequency = <5000000>;
203 m25p,fast-read;
204 reg = <0>;
205
206 partition@0 {
207 label = "u-boot-spl";
208 reg = <0x0 0x100000>;
209 read-only;
210 };
211
212 partition@1 {
213 label = "misc";
214 reg = <0x100000 0xf00000>;
215 };
216 };
217};
218
219&qspi {
220 status = "okay";
221 pinctrl-names = "default";
222 pinctrl-0 = <&qspi_pins>;
223 cdns,rclk-en;
224
225 flash0: m25p80@0 {
226 compatible = "s25fl512s", "jedec,spi-nor";
227 reg = <0>;
228 spi-tx-bus-width = <1>;
229 spi-rx-bus-width = <4>;
230 spi-max-frequency = <96000000>;
231 #address-cells = <1>;
232 #size-cells = <1>;
233 cdns,read-delay = <5>;
234 cdns,tshsl-ns = <500>;
235 cdns,tsd2d-ns = <500>;
236 cdns,tchsh-ns = <119>;
237 cdns,tslch-ns = <119>;
238
239 partition@0 {
240 label = "QSPI.u-boot-spl-os";
241 reg = <0x00000000 0x00100000>;
242 };
243 partition@1 {
244 label = "QSPI.u-boot-env";
245 reg = <0x00100000 0x00040000>;
246 };
247 partition@2 {
248 label = "QSPI.skern";
249 reg = <0x00140000 0x0040000>;
250 };
251 partition@3 {
252 label = "QSPI.pmmc-firmware";
253 reg = <0x00180000 0x0040000>;
254 };
255 partition@4 {
256 label = "QSPI.kernel";
257 reg = <0x001C0000 0x0800000>;
258 };
259 partition@5 {
260 label = "QSPI.file-system";
261 reg = <0x009C0000 0x3640000>;
262 };
263 };
264};
265
266&uart2 {
267 pinctrl-names = "default";
268 pinctrl-0 = <&uart2_pins>;
269 status = "okay";
270};
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Device Tree Source for K2G EVM
4 *
5 * Copyright (C) 2016-2017 Texas Instruments Incorporated - http://www.ti.com/
6 */
7/dts-v1/;
8
9#include "keystone-k2g.dtsi"
10
11/ {
12 compatible = "ti,k2g-evm", "ti,k2g", "ti,keystone";
13 model = "Texas Instruments K2G General Purpose EVM";
14
15 memory@800000000 {
16 device_type = "memory";
17 reg = <0x00000008 0x00000000 0x00000000 0x80000000>;
18 };
19
20 reserved-memory {
21 #address-cells = <2>;
22 #size-cells = <2>;
23 ranges;
24
25 dsp_common_memory: dsp-common-memory@81f800000 {
26 compatible = "shared-dma-pool";
27 reg = <0x00000008 0x1f800000 0x00000000 0x800000>;
28 reusable;
29 status = "okay";
30 };
31 };
32
33 vcc3v3_dcin_reg: fixedregulator-vcc3v3-dcin {
34 compatible = "regulator-fixed";
35 regulator-name = "mmc0_fixed";
36 regulator-min-microvolt = <3300000>;
37 regulator-max-microvolt = <3300000>;
38 regulator-always-on;
39 };
40
41 vcc1v8_ldo1_reg: fixedregulator-vcc1v8-ldo1 {
42 compatible = "regulator-fixed";
43 regulator-name = "ldo1";
44 regulator-min-microvolt = <1800000>;
45 regulator-max-microvolt = <1800000>;
46 regulator-always-on;
47 };
48};
49
50&k2g_pinctrl {
51 uart0_pins: pinmux_uart0_pins {
52 pinctrl-single,pins = <
53 K2G_CORE_IOPAD(0x11cc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart0_rxd.uart0_rxd */
54 K2G_CORE_IOPAD(0x11d0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */
55 >;
56 };
57
58 mmc0_pins: pinmux_mmc0_pins {
59 pinctrl-single,pins = <
60 K2G_CORE_IOPAD(0x1300) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat3.mmc0_dat3 */
61 K2G_CORE_IOPAD(0x1304) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat2.mmc0_dat2 */
62 K2G_CORE_IOPAD(0x1308) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat1.mmc0_dat1 */
63 K2G_CORE_IOPAD(0x130c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_dat0.mmc0_dat0 */
64 K2G_CORE_IOPAD(0x1310) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_clk.mmc0_clk */
65 K2G_CORE_IOPAD(0x1314) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE2) /* mmc0_cmd.mmc0_cmd */
66 K2G_CORE_IOPAD(0x12ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE3) /* mmc0_sdcd.gpio1_12 */
67 >;
68 };
69
70 mmc1_pins: pinmux_mmc1_pins {
71 pinctrl-single,pins = <
72 K2G_CORE_IOPAD(0x10ec) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat7.mmc1_dat7 */
73 K2G_CORE_IOPAD(0x10f0) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat6.mmc1_dat6 */
74 K2G_CORE_IOPAD(0x10f4) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat5.mmc1_dat5 */
75 K2G_CORE_IOPAD(0x10f8) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat4.mmc1_dat4 */
76 K2G_CORE_IOPAD(0x10fc) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat3.mmc1_dat3 */
77 K2G_CORE_IOPAD(0x1100) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat2.mmc1_dat2 */
78 K2G_CORE_IOPAD(0x1104) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat1.mmc1_dat1 */
79 K2G_CORE_IOPAD(0x1108) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_dat0.mmc1_dat0 */
80 K2G_CORE_IOPAD(0x110c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_clk.mmc1_clk */
81 K2G_CORE_IOPAD(0x1110) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* mmc1_cmd.mmc1_cmd */
82 >;
83 };
84
85 i2c0_pins: pinmux_i2c0_pins {
86 pinctrl-single,pins = <
87 K2G_CORE_IOPAD(0x137c) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */
88 K2G_CORE_IOPAD(0x1380) (BUFFER_CLASS_B | PIN_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */
89 >;
90 };
91
92 ecap0_pins: ecap0_pins {
93 pinctrl-single,pins = <
94 K2G_CORE_IOPAD(0x1374) (BUFFER_CLASS_B | MUX_MODE4) /* pr1_mdio_data.ecap0_in_apwm0_out */
95 >;
96 };
97
98 spi1_pins: pinmux_spi1_pins {
99 pinctrl-single,pins = <
100 K2G_CORE_IOPAD(0x11a4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_scs0.spi1_scs0 */
101 K2G_CORE_IOPAD(0x11ac) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_clk.spi1_clk */
102 K2G_CORE_IOPAD(0x11b0) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_miso.spi1_miso */
103 K2G_CORE_IOPAD(0x11b4) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* spi1_mosi.spi1_mosi */
104 >;
105 };
106
107 qspi_pins: pinmux_qspi_pins {
108 pinctrl-single,pins = <
109 K2G_CORE_IOPAD(0x1204) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_clk.qspi_clk */
110 K2G_CORE_IOPAD(0x1208) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_rclk.qspi_rclk */
111 K2G_CORE_IOPAD(0x120c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d0.qspi_d0 */
112 K2G_CORE_IOPAD(0x1210) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d1.qspi_d1 */
113 K2G_CORE_IOPAD(0x1214) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d2.qspi_d2 */
114 K2G_CORE_IOPAD(0x1218) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_d3.qspi_d3 */
115 K2G_CORE_IOPAD(0x121c) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* qspi_csn0.qspi_csn0 */
116 >;
117 };
118
119 uart2_pins: pinmux_uart2_pins {
120 pinctrl-single,pins = <
121 K2G_CORE_IOPAD(0x11ec) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* uart2_rxd.uart2_rxd */
122 K2G_CORE_IOPAD(0x11f0) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* uart2_txd.uart2_txd */
123 >;
124 };
125
126 dcan0_pins: pinmux_dcan0_pins {
127 pinctrl-single,pins = <
128 K2G_CORE_IOPAD(0x11fc) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* dcan0tx.dcan0tx */
129 K2G_CORE_IOPAD(0x1200) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE0) /* dcan0rx.dcan0rx */
130 >;
131 };
132
133 dcan1_pins: pinmux_dcan1_pins {
134 pinctrl-single,pins = <
135 K2G_CORE_IOPAD(0x1224) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE1) /* qspicsn2.dcan1tx */
136 K2G_CORE_IOPAD(0x1228) (BUFFER_CLASS_B | PIN_PULLDOWN | MUX_MODE1) /* qspicsn3.dcan1rx */
137 >;
138 };
139
140 emac_pins: pinmux_emac_pins {
141 pinctrl-single,pins = <
142 K2G_CORE_IOPAD(0x113C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD1.RGMII_RXD1 */
143 K2G_CORE_IOPAD(0x1138) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD2.RGMII_RXD2 */
144 K2G_CORE_IOPAD(0x1134) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD3.RGMII_RXD3 */
145 K2G_CORE_IOPAD(0x1140) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXD0.RGMII_RXD0 */
146 K2G_CORE_IOPAD(0x1178) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD0.RGMII_TXD0 */
147 K2G_CORE_IOPAD(0x1174) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD1.RGMII_TXD1 */
148 K2G_CORE_IOPAD(0x1170) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD2.RGMII_TXD2 */
149 K2G_CORE_IOPAD(0x116C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXD3.RGMII_TXD3 */
150 K2G_CORE_IOPAD(0x1154) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXCLK.RGMII_TXC */
151 K2G_CORE_IOPAD(0x117C) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_TXEN.RGMII_TXCTL */
152 K2G_CORE_IOPAD(0x1120) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXCLK.RGMII_RXC */
153 K2G_CORE_IOPAD(0x1144) (BUFFER_CLASS_D | PULL_DISABLE | MUX_MODE1) /* MII_RXDV.RGMII_RXCTL */
154 >;
155 };
156
157 mdio_pins: pinmux_mdio_pins {
158 pinctrl-single,pins = <
159 K2G_CORE_IOPAD(0x118C) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_CLK.MDIO_CLK */
160 K2G_CORE_IOPAD(0x1188) (BUFFER_CLASS_B | PULL_DISABLE | MUX_MODE0) /* MDIO_DATA.MDIO_DATA */
161 >;
162 };
163};
164
165&uart0 {
166 pinctrl-names = "default";
167 pinctrl-0 = <&uart0_pins>;
168 status = "okay";
169};
170
171&gpio1 {
172 status = "okay";
173};
174
175&mmc0 {
176 pinctrl-names = "default";
177 pinctrl-0 = <&mmc0_pins>;
178 vmmc-supply = <&vcc3v3_dcin_reg>;
179 vqmmc-supply = <&vcc3v3_dcin_reg>;
180 cd-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
181 status = "okay";
182};
183
184&mmc1 {
185 pinctrl-names = "default";
186 pinctrl-0 = <&mmc1_pins>;
187 vmmc-supply = <&vcc3v3_dcin_reg>; /* VCC3V3_EMMC is connected to VCC3V3_DCIN */
188 vqmmc-supply = <&vcc1v8_ldo1_reg>;
189 ti,non-removable;
190 status = "okay";
191};
192
193&dsp0 {
194 memory-region = <&dsp_common_memory>;
195 status = "okay";
196};
197
198&i2c0 {
199 pinctrl-names = "default";
200 pinctrl-0 = <&i2c0_pins>;
201 status = "okay";
202
203 eeprom@50 {
204 compatible = "atmel,24c1024";
205 reg = <0x50>;
206 };
207};
208
209&keystone_usb0 {
210 status = "okay";
211};
212
213&usb0_phy {
214 status = "okay";
215};
216
217&usb0 {
218 dr_mode = "host";
219 status = "okay";
220};
221
222&keystone_usb1 {
223 status = "okay";
224};
225
226&usb1_phy {
227 status = "okay";
228};
229
230&usb1 {
231 dr_mode = "peripheral";
232 status = "okay";
233};
234
235&ecap0 {
236 status = "okay";
237 pinctrl-names = "default";
238 pinctrl-0 = <&ecap0_pins>;
239};
240
241&spi1 {
242 pinctrl-names = "default";
243 pinctrl-0 = <&spi1_pins>;
244 status = "okay";
245
246 spi_nor: flash@0 {
247 #address-cells = <1>;
248 #size-cells = <1>;
249 compatible = "jedec,spi-nor";
250 spi-max-frequency = <5000000>;
251 m25p,fast-read;
252 reg = <0>;
253
254 partition@0 {
255 label = "u-boot-spl";
256 reg = <0x0 0x100000>;
257 read-only;
258 };
259
260 partition@1 {
261 label = "misc";
262 reg = <0x100000 0xf00000>;
263 };
264 };
265};
266
267&qspi {
268 status = "okay";
269 pinctrl-names = "default";
270 pinctrl-0 = <&qspi_pins>;
271 cdns,rclk-en;
272
273 flash0: m25p80@0 {
274 compatible = "s25fl512s", "jedec,spi-nor";
275 reg = <0>;
276 spi-tx-bus-width = <1>;
277 spi-rx-bus-width = <4>;
278 spi-max-frequency = <96000000>;
279 #address-cells = <1>;
280 #size-cells = <1>;
281 cdns,read-delay = <5>;
282 cdns,tshsl-ns = <500>;
283 cdns,tsd2d-ns = <500>;
284 cdns,tchsh-ns = <119>;
285 cdns,tslch-ns = <119>;
286
287 partition@0 {
288 label = "QSPI.u-boot-spl-os";
289 reg = <0x00000000 0x00100000>;
290 };
291 partition@1 {
292 label = "QSPI.u-boot-env";
293 reg = <0x00100000 0x00040000>;
294 };
295 partition@2 {
296 label = "QSPI.skern";
297 reg = <0x00140000 0x0040000>;
298 };
299 partition@3 {
300 label = "QSPI.pmmc-firmware";
301 reg = <0x00180000 0x0040000>;
302 };
303 partition@4 {
304 label = "QSPI.kernel";
305 reg = <0x001C0000 0x0800000>;
306 };
307 partition@5 {
308 label = "QSPI.file-system";
309 reg = <0x009C0000 0x3640000>;
310 };
311 };
312};
313
314&uart2 {
315 pinctrl-names = "default";
316 pinctrl-0 = <&uart2_pins>;
317 status = "okay";
318};
319
320&dcan0 {
321 pinctrl-names = "default";
322 pinctrl-0 = <&dcan0_pins>;
323 status = "okay";
324};
325
326&dcan1 {
327 pinctrl-names = "default";
328 pinctrl-0 = <&dcan1_pins>;
329 status = "okay";
330};
331
332&qmss {
333 status = "okay";
334};
335
336&knav_dmas {
337 status = "okay";
338};
339
340&mdio {
341 pinctrl-names = "default";
342 pinctrl-0 = <&mdio_pins>;
343 status = "okay";
344 ethphy0: ethernet-phy@0 {
345 reg = <0>;
346 };
347};
348
349&gbe0 {
350 phy-handle = <ðphy0>;
351 phy-mode = "rgmii-id";
352 status = "okay";
353};
354
355&netcp {
356 pinctrl-names = "default";
357 pinctrl-0 = <&emac_pins>;
358 status = "okay";
359};