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1/*
2 * Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/gpio/gpio.h>
13#include "imx25-pinfunc.h"
14
15/ {
16 #address-cells = <1>;
17 #size-cells = <1>;
18 /*
19 * The decompressor and also some bootloaders rely on a
20 * pre-existing /chosen node to be available to insert the
21 * command line and merge other ATAGS info.
22 * Also for U-Boot there must be a pre-existing /memory node.
23 */
24 chosen {};
25 memory { device_type = "memory"; };
26
27 aliases {
28 ethernet0 = &fec;
29 gpio0 = &gpio1;
30 gpio1 = &gpio2;
31 gpio2 = &gpio3;
32 gpio3 = &gpio4;
33 i2c0 = &i2c1;
34 i2c1 = &i2c2;
35 i2c2 = &i2c3;
36 mmc0 = &esdhc1;
37 mmc1 = &esdhc2;
38 pwm0 = &pwm1;
39 pwm1 = &pwm2;
40 pwm2 = &pwm3;
41 pwm3 = &pwm4;
42 serial0 = &uart1;
43 serial1 = &uart2;
44 serial2 = &uart3;
45 serial3 = &uart4;
46 serial4 = &uart5;
47 spi0 = &spi1;
48 spi1 = &spi2;
49 spi2 = &spi3;
50 usb0 = &usbotg;
51 usb1 = &usbhost1;
52 };
53
54 cpus {
55 #address-cells = <1>;
56 #size-cells = <0>;
57
58 cpu@0 {
59 compatible = "arm,arm926ej-s";
60 device_type = "cpu";
61 reg = <0>;
62 };
63 };
64
65 asic: asic-interrupt-controller@68000000 {
66 compatible = "fsl,imx25-asic", "fsl,avic";
67 interrupt-controller;
68 #interrupt-cells = <1>;
69 reg = <0x68000000 0x8000000>;
70 };
71
72 clocks {
73 #address-cells = <1>;
74 #size-cells = <0>;
75
76 osc {
77 compatible = "fsl,imx-osc", "fixed-clock";
78 #clock-cells = <0>;
79 clock-frequency = <24000000>;
80 };
81 };
82
83 soc {
84 #address-cells = <1>;
85 #size-cells = <1>;
86 compatible = "simple-bus";
87 interrupt-parent = <&asic>;
88 ranges;
89
90 aips@43f00000 { /* AIPS1 */
91 compatible = "fsl,aips-bus", "simple-bus";
92 #address-cells = <1>;
93 #size-cells = <1>;
94 reg = <0x43f00000 0x100000>;
95 ranges;
96
97 aips1: bridge@43f00000 {
98 compatible = "fsl,imx25-aips";
99 reg = <0x43f00000 0x4000>;
100 };
101
102 i2c1: i2c@43f80000 {
103 #address-cells = <1>;
104 #size-cells = <0>;
105 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
106 reg = <0x43f80000 0x4000>;
107 clocks = <&clks 48>;
108 clock-names = "";
109 interrupts = <3>;
110 status = "disabled";
111 };
112
113 i2c3: i2c@43f84000 {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
117 reg = <0x43f84000 0x4000>;
118 clocks = <&clks 48>;
119 clock-names = "";
120 interrupts = <10>;
121 status = "disabled";
122 };
123
124 can1: can@43f88000 {
125 compatible = "fsl,imx25-flexcan";
126 reg = <0x43f88000 0x4000>;
127 interrupts = <43>;
128 clocks = <&clks 75>, <&clks 75>;
129 clock-names = "ipg", "per";
130 status = "disabled";
131 };
132
133 can2: can@43f8c000 {
134 compatible = "fsl,imx25-flexcan";
135 reg = <0x43f8c000 0x4000>;
136 interrupts = <44>;
137 clocks = <&clks 76>, <&clks 76>;
138 clock-names = "ipg", "per";
139 status = "disabled";
140 };
141
142 uart1: serial@43f90000 {
143 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
144 reg = <0x43f90000 0x4000>;
145 interrupts = <45>;
146 clocks = <&clks 120>, <&clks 57>;
147 clock-names = "ipg", "per";
148 status = "disabled";
149 };
150
151 uart2: serial@43f94000 {
152 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
153 reg = <0x43f94000 0x4000>;
154 interrupts = <32>;
155 clocks = <&clks 121>, <&clks 57>;
156 clock-names = "ipg", "per";
157 status = "disabled";
158 };
159
160 i2c2: i2c@43f98000 {
161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
164 reg = <0x43f98000 0x4000>;
165 clocks = <&clks 48>;
166 clock-names = "";
167 interrupts = <4>;
168 status = "disabled";
169 };
170
171 owire@43f9c000 {
172 #address-cells = <1>;
173 #size-cells = <0>;
174 reg = <0x43f9c000 0x4000>;
175 clocks = <&clks 51>;
176 clock-names = "";
177 interrupts = <2>;
178 status = "disabled";
179 };
180
181 spi1: cspi@43fa4000 {
182 #address-cells = <1>;
183 #size-cells = <0>;
184 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
185 reg = <0x43fa4000 0x4000>;
186 clocks = <&clks 78>, <&clks 78>;
187 clock-names = "ipg", "per";
188 interrupts = <14>;
189 status = "disabled";
190 };
191
192 kpp: kpp@43fa8000 {
193 #address-cells = <1>;
194 #size-cells = <0>;
195 compatible = "fsl,imx25-kpp", "fsl,imx21-kpp";
196 reg = <0x43fa8000 0x4000>;
197 clocks = <&clks 102>;
198 clock-names = "";
199 interrupts = <24>;
200 status = "disabled";
201 };
202
203 iomuxc: iomuxc@43fac000 {
204 compatible = "fsl,imx25-iomuxc";
205 reg = <0x43fac000 0x4000>;
206 };
207
208 audmux: audmux@43fb0000 {
209 compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
210 reg = <0x43fb0000 0x4000>;
211 status = "disabled";
212 };
213 };
214
215 spba@50000000 {
216 compatible = "fsl,spba-bus", "simple-bus";
217 #address-cells = <1>;
218 #size-cells = <1>;
219 reg = <0x50000000 0x40000>;
220 ranges;
221
222 spi3: cspi@50004000 {
223 #address-cells = <1>;
224 #size-cells = <0>;
225 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
226 reg = <0x50004000 0x4000>;
227 interrupts = <0>;
228 clocks = <&clks 80>, <&clks 80>;
229 clock-names = "ipg", "per";
230 status = "disabled";
231 };
232
233 uart4: serial@50008000 {
234 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
235 reg = <0x50008000 0x4000>;
236 interrupts = <5>;
237 clocks = <&clks 123>, <&clks 57>;
238 clock-names = "ipg", "per";
239 status = "disabled";
240 };
241
242 uart3: serial@5000c000 {
243 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
244 reg = <0x5000c000 0x4000>;
245 interrupts = <18>;
246 clocks = <&clks 122>, <&clks 57>;
247 clock-names = "ipg", "per";
248 status = "disabled";
249 };
250
251 spi2: cspi@50010000 {
252 #address-cells = <1>;
253 #size-cells = <0>;
254 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
255 reg = <0x50010000 0x4000>;
256 clocks = <&clks 79>, <&clks 79>;
257 clock-names = "ipg", "per";
258 interrupts = <13>;
259 status = "disabled";
260 };
261
262 ssi2: ssi@50014000 {
263 #sound-dai-cells = <0>;
264 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
265 reg = <0x50014000 0x4000>;
266 interrupts = <11>;
267 clocks = <&clks 118>;
268 clock-names = "ipg";
269 dmas = <&sdma 24 1 0>,
270 <&sdma 25 1 0>;
271 dma-names = "rx", "tx";
272 fsl,fifo-depth = <15>;
273 status = "disabled";
274 };
275
276 esai@50018000 {
277 reg = <0x50018000 0x4000>;
278 interrupts = <7>;
279 };
280
281 uart5: serial@5002c000 {
282 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
283 reg = <0x5002c000 0x4000>;
284 interrupts = <40>;
285 clocks = <&clks 124>, <&clks 57>;
286 clock-names = "ipg", "per";
287 status = "disabled";
288 };
289
290 tscadc: tscadc@50030000 {
291 compatible = "fsl,imx25-tsadc";
292 reg = <0x50030000 0xc>;
293 interrupts = <46>;
294 clocks = <&clks 119>;
295 clock-names = "ipg";
296 interrupt-controller;
297 #interrupt-cells = <1>;
298 #address-cells = <1>;
299 #size-cells = <1>;
300 status = "disabled";
301 ranges;
302
303 adc: adc@50030800 {
304 compatible = "fsl,imx25-gcq";
305 reg = <0x50030800 0x60>;
306 interrupt-parent = <&tscadc>;
307 interrupts = <1>;
308 #address-cells = <1>;
309 #size-cells = <0>;
310 status = "disabled";
311 };
312
313 tsc: tcq@50030400 {
314 compatible = "fsl,imx25-tcq";
315 reg = <0x50030400 0x60>;
316 interrupt-parent = <&tscadc>;
317 interrupts = <0>;
318 fsl,wires = <4>;
319 status = "disabled";
320 };
321 };
322
323 ssi1: ssi@50034000 {
324 #sound-dai-cells = <0>;
325 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
326 reg = <0x50034000 0x4000>;
327 interrupts = <12>;
328 clocks = <&clks 117>;
329 clock-names = "ipg";
330 dmas = <&sdma 28 1 0>,
331 <&sdma 29 1 0>;
332 dma-names = "rx", "tx";
333 fsl,fifo-depth = <15>;
334 status = "disabled";
335 };
336
337 fec: ethernet@50038000 {
338 compatible = "fsl,imx25-fec";
339 reg = <0x50038000 0x4000>;
340 interrupts = <57>;
341 clocks = <&clks 88>, <&clks 65>;
342 clock-names = "ipg", "ahb";
343 status = "disabled";
344 };
345 };
346
347 aips@53f00000 { /* AIPS2 */
348 compatible = "fsl,aips-bus", "simple-bus";
349 #address-cells = <1>;
350 #size-cells = <1>;
351 reg = <0x53f00000 0x100000>;
352 ranges;
353
354 aips2: bridge@53f00000 {
355 compatible = "fsl,imx25-aips";
356 reg = <0x53f00000 0x4000>;
357 };
358
359 clks: ccm@53f80000 {
360 compatible = "fsl,imx25-ccm";
361 reg = <0x53f80000 0x4000>;
362 interrupts = <31>;
363 #clock-cells = <1>;
364 };
365
366 gpt4: timer@53f84000 {
367 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
368 reg = <0x53f84000 0x4000>;
369 clocks = <&clks 95>, <&clks 47>;
370 clock-names = "ipg", "per";
371 interrupts = <1>;
372 };
373
374 gpt3: timer@53f88000 {
375 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
376 reg = <0x53f88000 0x4000>;
377 clocks = <&clks 94>, <&clks 47>;
378 clock-names = "ipg", "per";
379 interrupts = <29>;
380 };
381
382 gpt2: timer@53f8c000 {
383 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
384 reg = <0x53f8c000 0x4000>;
385 clocks = <&clks 93>, <&clks 47>;
386 clock-names = "ipg", "per";
387 interrupts = <53>;
388 };
389
390 gpt1: timer@53f90000 {
391 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
392 reg = <0x53f90000 0x4000>;
393 clocks = <&clks 92>, <&clks 47>;
394 clock-names = "ipg", "per";
395 interrupts = <54>;
396 };
397
398 epit1: timer@53f94000 {
399 compatible = "fsl,imx25-epit";
400 reg = <0x53f94000 0x4000>;
401 interrupts = <28>;
402 };
403
404 epit2: timer@53f98000 {
405 compatible = "fsl,imx25-epit";
406 reg = <0x53f98000 0x4000>;
407 interrupts = <27>;
408 };
409
410 gpio4: gpio@53f9c000 {
411 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
412 reg = <0x53f9c000 0x4000>;
413 interrupts = <23>;
414 gpio-controller;
415 #gpio-cells = <2>;
416 interrupt-controller;
417 #interrupt-cells = <2>;
418 };
419
420 pwm2: pwm@53fa0000 {
421 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
422 #pwm-cells = <2>;
423 reg = <0x53fa0000 0x4000>;
424 clocks = <&clks 106>, <&clks 52>;
425 clock-names = "ipg", "per";
426 interrupts = <36>;
427 };
428
429 gpio3: gpio@53fa4000 {
430 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
431 reg = <0x53fa4000 0x4000>;
432 interrupts = <16>;
433 gpio-controller;
434 #gpio-cells = <2>;
435 interrupt-controller;
436 #interrupt-cells = <2>;
437 };
438
439 pwm3: pwm@53fa8000 {
440 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
441 #pwm-cells = <2>;
442 reg = <0x53fa8000 0x4000>;
443 clocks = <&clks 107>, <&clks 52>;
444 clock-names = "ipg", "per";
445 interrupts = <41>;
446 };
447
448 scc: crypto@53fac000 {
449 compatible = "fsl,imx25-scc";
450 reg = <0x53fac000 0x4000>;
451 clocks = <&clks 111>;
452 clock-names = "ipg";
453 interrupts = <49>, <50>;
454 interrupt-names = "scm", "smn";
455 };
456
457 rngb: rngb@53fb0000 {
458 compatible = "fsl,imx25-rngb";
459 reg = <0x53fb0000 0x4000>;
460 clocks = <&clks 109>;
461 interrupts = <22>;
462 };
463
464 esdhc1: esdhc@53fb4000 {
465 compatible = "fsl,imx25-esdhc";
466 reg = <0x53fb4000 0x4000>;
467 interrupts = <9>;
468 clocks = <&clks 86>, <&clks 63>, <&clks 45>;
469 clock-names = "ipg", "ahb", "per";
470 status = "disabled";
471 };
472
473 esdhc2: esdhc@53fb8000 {
474 compatible = "fsl,imx25-esdhc";
475 reg = <0x53fb8000 0x4000>;
476 interrupts = <8>;
477 clocks = <&clks 87>, <&clks 64>, <&clks 46>;
478 clock-names = "ipg", "ahb", "per";
479 status = "disabled";
480 };
481
482 lcdc: lcdc@53fbc000 {
483 compatible = "fsl,imx25-fb", "fsl,imx21-fb";
484 reg = <0x53fbc000 0x4000>;
485 interrupts = <39>;
486 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
487 clock-names = "ipg", "ahb", "per";
488 status = "disabled";
489 };
490
491 slcdc@53fc0000 {
492 reg = <0x53fc0000 0x4000>;
493 interrupts = <38>;
494 status = "disabled";
495 };
496
497 pwm4: pwm@53fc8000 {
498 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
499 #pwm-cells = <2>;
500 reg = <0x53fc8000 0x4000>;
501 clocks = <&clks 108>, <&clks 52>;
502 clock-names = "ipg", "per";
503 interrupts = <42>;
504 };
505
506 gpio1: gpio@53fcc000 {
507 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
508 reg = <0x53fcc000 0x4000>;
509 interrupts = <52>;
510 gpio-controller;
511 #gpio-cells = <2>;
512 interrupt-controller;
513 #interrupt-cells = <2>;
514 };
515
516 gpio2: gpio@53fd0000 {
517 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
518 reg = <0x53fd0000 0x4000>;
519 interrupts = <51>;
520 gpio-controller;
521 #gpio-cells = <2>;
522 interrupt-controller;
523 #interrupt-cells = <2>;
524 };
525
526 sdma: sdma@53fd4000 {
527 compatible = "fsl,imx25-sdma";
528 reg = <0x53fd4000 0x4000>;
529 clocks = <&clks 112>, <&clks 68>;
530 clock-names = "ipg", "ahb";
531 #dma-cells = <3>;
532 interrupts = <34>;
533 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
534 };
535
536 wdog@53fdc000 {
537 compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
538 reg = <0x53fdc000 0x4000>;
539 clocks = <&clks 126>;
540 clock-names = "";
541 interrupts = <55>;
542 };
543
544 pwm1: pwm@53fe0000 {
545 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
546 #pwm-cells = <2>;
547 reg = <0x53fe0000 0x4000>;
548 clocks = <&clks 105>, <&clks 52>;
549 clock-names = "ipg", "per";
550 interrupts = <26>;
551 };
552
553 iim: iim@53ff0000 {
554 compatible = "fsl,imx25-iim", "fsl,imx27-iim";
555 reg = <0x53ff0000 0x4000>;
556 interrupts = <19>;
557 clocks = <&clks 99>;
558 };
559
560 usbotg: usb@53ff4000 {
561 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
562 reg = <0x53ff4000 0x0200>;
563 interrupts = <37>;
564 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
565 clock-names = "ipg", "ahb", "per";
566 fsl,usbmisc = <&usbmisc 0>;
567 fsl,usbphy = <&usbphy0>;
568 phy_type = "utmi";
569 dr_mode = "otg";
570 status = "disabled";
571 };
572
573 usbhost1: usb@53ff4400 {
574 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
575 reg = <0x53ff4400 0x0200>;
576 interrupts = <35>;
577 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
578 clock-names = "ipg", "ahb", "per";
579 fsl,usbmisc = <&usbmisc 1>;
580 fsl,usbphy = <&usbphy1>;
581 status = "disabled";
582 };
583
584 usbmisc: usbmisc@53ff4600 {
585 #index-cells = <1>;
586 compatible = "fsl,imx25-usbmisc";
587 reg = <0x53ff4600 0x00f>;
588 };
589
590 dryice@53ffc000 {
591 compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
592 reg = <0x53ffc000 0x4000>;
593 clocks = <&clks 81>;
594 clock-names = "ipg";
595 interrupts = <25 56>;
596 };
597 };
598
599 iram: sram@78000000 {
600 compatible = "mmio-sram";
601 reg = <0x78000000 0x20000>;
602 };
603
604 emi@80000000 {
605 compatible = "fsl,emi-bus", "simple-bus";
606 #address-cells = <1>;
607 #size-cells = <1>;
608 reg = <0x80000000 0x3b002000>;
609 ranges;
610
611 nfc: nand@bb000000 {
612 #address-cells = <1>;
613 #size-cells = <1>;
614
615 compatible = "fsl,imx25-nand";
616 reg = <0xbb000000 0x2000>;
617 clocks = <&clks 50>;
618 clock-names = "";
619 interrupts = <33>;
620 status = "disabled";
621 };
622 };
623 };
624
625 usbphy {
626 compatible = "simple-bus";
627 #address-cells = <1>;
628 #size-cells = <0>;
629
630 usbphy0: usb-phy@0 {
631 reg = <0>;
632 compatible = "usb-nop-xceiv";
633 #phy-cells = <0>;
634 };
635
636 usbphy1: usb-phy@1 {
637 reg = <1>;
638 compatible = "usb-nop-xceiv";
639 #phy-cells = <0>;
640 };
641 };
642};
1// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2012 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
4
5#include <dt-bindings/gpio/gpio.h>
6#include "imx25-pinfunc.h"
7
8/ {
9 #address-cells = <1>;
10 #size-cells = <1>;
11 /*
12 * The decompressor and also some bootloaders rely on a
13 * pre-existing /chosen node to be available to insert the
14 * command line and merge other ATAGS info.
15 */
16 chosen {};
17
18 aliases {
19 ethernet0 = &fec;
20 gpio0 = &gpio1;
21 gpio1 = &gpio2;
22 gpio2 = &gpio3;
23 gpio3 = &gpio4;
24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 mmc0 = &esdhc1;
28 mmc1 = &esdhc2;
29 pwm0 = &pwm1;
30 pwm1 = &pwm2;
31 pwm2 = &pwm3;
32 pwm3 = &pwm4;
33 serial0 = &uart1;
34 serial1 = &uart2;
35 serial2 = &uart3;
36 serial3 = &uart4;
37 serial4 = &uart5;
38 spi0 = &spi1;
39 spi1 = &spi2;
40 spi2 = &spi3;
41 usb0 = &usbotg;
42 usb1 = &usbhost1;
43 };
44
45 cpus {
46 #address-cells = <1>;
47 #size-cells = <0>;
48
49 cpu@0 {
50 compatible = "arm,arm926ej-s";
51 device_type = "cpu";
52 reg = <0>;
53 };
54 };
55
56 asic: asic-interrupt-controller@68000000 {
57 compatible = "fsl,imx25-asic", "fsl,avic";
58 interrupt-controller;
59 #interrupt-cells = <1>;
60 reg = <0x68000000 0x8000000>;
61 };
62
63 clocks {
64 osc {
65 compatible = "fsl,imx-osc", "fixed-clock";
66 #clock-cells = <0>;
67 clock-frequency = <24000000>;
68 };
69 };
70
71 soc {
72 #address-cells = <1>;
73 #size-cells = <1>;
74 compatible = "simple-bus";
75 interrupt-parent = <&asic>;
76 ranges;
77
78 aips@43f00000 { /* AIPS1 */
79 compatible = "fsl,aips-bus", "simple-bus";
80 #address-cells = <1>;
81 #size-cells = <1>;
82 reg = <0x43f00000 0x100000>;
83 ranges;
84
85 aips1: bridge@43f00000 {
86 compatible = "fsl,imx25-aips";
87 reg = <0x43f00000 0x4000>;
88 };
89
90 i2c1: i2c@43f80000 {
91 #address-cells = <1>;
92 #size-cells = <0>;
93 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
94 reg = <0x43f80000 0x4000>;
95 clocks = <&clks 48>;
96 clock-names = "";
97 interrupts = <3>;
98 status = "disabled";
99 };
100
101 i2c3: i2c@43f84000 {
102 #address-cells = <1>;
103 #size-cells = <0>;
104 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
105 reg = <0x43f84000 0x4000>;
106 clocks = <&clks 48>;
107 clock-names = "";
108 interrupts = <10>;
109 status = "disabled";
110 };
111
112 can1: can@43f88000 {
113 compatible = "fsl,imx25-flexcan";
114 reg = <0x43f88000 0x4000>;
115 interrupts = <43>;
116 clocks = <&clks 75>, <&clks 75>;
117 clock-names = "ipg", "per";
118 status = "disabled";
119 };
120
121 can2: can@43f8c000 {
122 compatible = "fsl,imx25-flexcan";
123 reg = <0x43f8c000 0x4000>;
124 interrupts = <44>;
125 clocks = <&clks 76>, <&clks 76>;
126 clock-names = "ipg", "per";
127 status = "disabled";
128 };
129
130 uart1: serial@43f90000 {
131 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
132 reg = <0x43f90000 0x4000>;
133 interrupts = <45>;
134 clocks = <&clks 120>, <&clks 57>;
135 clock-names = "ipg", "per";
136 status = "disabled";
137 };
138
139 uart2: serial@43f94000 {
140 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
141 reg = <0x43f94000 0x4000>;
142 interrupts = <32>;
143 clocks = <&clks 121>, <&clks 57>;
144 clock-names = "ipg", "per";
145 status = "disabled";
146 };
147
148 i2c2: i2c@43f98000 {
149 #address-cells = <1>;
150 #size-cells = <0>;
151 compatible = "fsl,imx25-i2c", "fsl,imx21-i2c";
152 reg = <0x43f98000 0x4000>;
153 clocks = <&clks 48>;
154 clock-names = "";
155 interrupts = <4>;
156 status = "disabled";
157 };
158
159 owire@43f9c000 {
160 #address-cells = <1>;
161 #size-cells = <0>;
162 reg = <0x43f9c000 0x4000>;
163 clocks = <&clks 51>;
164 clock-names = "";
165 interrupts = <2>;
166 status = "disabled";
167 };
168
169 spi1: spi@43fa4000 {
170 #address-cells = <1>;
171 #size-cells = <0>;
172 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
173 reg = <0x43fa4000 0x4000>;
174 clocks = <&clks 78>, <&clks 78>;
175 clock-names = "ipg", "per";
176 interrupts = <14>;
177 status = "disabled";
178 };
179
180 kpp: kpp@43fa8000 {
181 #address-cells = <1>;
182 #size-cells = <0>;
183 compatible = "fsl,imx25-kpp", "fsl,imx21-kpp";
184 reg = <0x43fa8000 0x4000>;
185 clocks = <&clks 102>;
186 clock-names = "";
187 interrupts = <24>;
188 status = "disabled";
189 };
190
191 iomuxc: iomuxc@43fac000 {
192 compatible = "fsl,imx25-iomuxc";
193 reg = <0x43fac000 0x4000>;
194 };
195
196 audmux: audmux@43fb0000 {
197 compatible = "fsl,imx25-audmux", "fsl,imx31-audmux";
198 reg = <0x43fb0000 0x4000>;
199 status = "disabled";
200 };
201 };
202
203 spba@50000000 {
204 compatible = "fsl,spba-bus", "simple-bus";
205 #address-cells = <1>;
206 #size-cells = <1>;
207 reg = <0x50000000 0x40000>;
208 ranges;
209
210 spi3: spi@50004000 {
211 #address-cells = <1>;
212 #size-cells = <0>;
213 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
214 reg = <0x50004000 0x4000>;
215 interrupts = <0>;
216 clocks = <&clks 80>, <&clks 80>;
217 clock-names = "ipg", "per";
218 status = "disabled";
219 };
220
221 uart4: serial@50008000 {
222 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
223 reg = <0x50008000 0x4000>;
224 interrupts = <5>;
225 clocks = <&clks 123>, <&clks 57>;
226 clock-names = "ipg", "per";
227 status = "disabled";
228 };
229
230 uart3: serial@5000c000 {
231 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
232 reg = <0x5000c000 0x4000>;
233 interrupts = <18>;
234 clocks = <&clks 122>, <&clks 57>;
235 clock-names = "ipg", "per";
236 status = "disabled";
237 };
238
239 spi2: spi@50010000 {
240 #address-cells = <1>;
241 #size-cells = <0>;
242 compatible = "fsl,imx25-cspi", "fsl,imx35-cspi";
243 reg = <0x50010000 0x4000>;
244 clocks = <&clks 79>, <&clks 79>;
245 clock-names = "ipg", "per";
246 interrupts = <13>;
247 status = "disabled";
248 };
249
250 ssi2: ssi@50014000 {
251 #sound-dai-cells = <0>;
252 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
253 reg = <0x50014000 0x4000>;
254 interrupts = <11>;
255 clocks = <&clks 118>;
256 clock-names = "ipg";
257 dmas = <&sdma 24 1 0>,
258 <&sdma 25 1 0>;
259 dma-names = "rx", "tx";
260 fsl,fifo-depth = <15>;
261 status = "disabled";
262 };
263
264 esai@50018000 {
265 reg = <0x50018000 0x4000>;
266 interrupts = <7>;
267 };
268
269 uart5: serial@5002c000 {
270 compatible = "fsl,imx25-uart", "fsl,imx21-uart";
271 reg = <0x5002c000 0x4000>;
272 interrupts = <40>;
273 clocks = <&clks 124>, <&clks 57>;
274 clock-names = "ipg", "per";
275 status = "disabled";
276 };
277
278 tscadc: tscadc@50030000 {
279 compatible = "fsl,imx25-tsadc";
280 reg = <0x50030000 0xc>;
281 interrupts = <46>;
282 clocks = <&clks 119>;
283 clock-names = "ipg";
284 interrupt-controller;
285 #interrupt-cells = <1>;
286 #address-cells = <1>;
287 #size-cells = <1>;
288 status = "disabled";
289 ranges;
290
291 adc: adc@50030800 {
292 compatible = "fsl,imx25-gcq";
293 reg = <0x50030800 0x60>;
294 interrupt-parent = <&tscadc>;
295 interrupts = <1>;
296 #address-cells = <1>;
297 #size-cells = <0>;
298 status = "disabled";
299 };
300
301 tsc: tcq@50030400 {
302 compatible = "fsl,imx25-tcq";
303 reg = <0x50030400 0x60>;
304 interrupt-parent = <&tscadc>;
305 interrupts = <0>;
306 fsl,wires = <4>;
307 status = "disabled";
308 };
309 };
310
311 ssi1: ssi@50034000 {
312 #sound-dai-cells = <0>;
313 compatible = "fsl,imx25-ssi", "fsl,imx21-ssi";
314 reg = <0x50034000 0x4000>;
315 interrupts = <12>;
316 clocks = <&clks 117>;
317 clock-names = "ipg";
318 dmas = <&sdma 28 1 0>,
319 <&sdma 29 1 0>;
320 dma-names = "rx", "tx";
321 fsl,fifo-depth = <15>;
322 status = "disabled";
323 };
324
325 fec: ethernet@50038000 {
326 compatible = "fsl,imx25-fec";
327 reg = <0x50038000 0x4000>;
328 interrupts = <57>;
329 clocks = <&clks 88>, <&clks 65>;
330 clock-names = "ipg", "ahb";
331 status = "disabled";
332 };
333 };
334
335 aips@53f00000 { /* AIPS2 */
336 compatible = "fsl,aips-bus", "simple-bus";
337 #address-cells = <1>;
338 #size-cells = <1>;
339 reg = <0x53f00000 0x100000>;
340 ranges;
341
342 aips2: bridge@53f00000 {
343 compatible = "fsl,imx25-aips";
344 reg = <0x53f00000 0x4000>;
345 };
346
347 clks: ccm@53f80000 {
348 compatible = "fsl,imx25-ccm";
349 reg = <0x53f80000 0x4000>;
350 interrupts = <31>;
351 #clock-cells = <1>;
352 };
353
354 gpt4: timer@53f84000 {
355 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
356 reg = <0x53f84000 0x4000>;
357 clocks = <&clks 95>, <&clks 47>;
358 clock-names = "ipg", "per";
359 interrupts = <1>;
360 };
361
362 gpt3: timer@53f88000 {
363 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
364 reg = <0x53f88000 0x4000>;
365 clocks = <&clks 94>, <&clks 47>;
366 clock-names = "ipg", "per";
367 interrupts = <29>;
368 };
369
370 gpt2: timer@53f8c000 {
371 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
372 reg = <0x53f8c000 0x4000>;
373 clocks = <&clks 93>, <&clks 47>;
374 clock-names = "ipg", "per";
375 interrupts = <53>;
376 };
377
378 gpt1: timer@53f90000 {
379 compatible = "fsl,imx25-gpt", "fsl,imx31-gpt";
380 reg = <0x53f90000 0x4000>;
381 clocks = <&clks 92>, <&clks 47>;
382 clock-names = "ipg", "per";
383 interrupts = <54>;
384 };
385
386 epit1: timer@53f94000 {
387 compatible = "fsl,imx25-epit";
388 reg = <0x53f94000 0x4000>;
389 clocks = <&clks 83>, <&clks 43>;
390 clock-names = "ipg", "per";
391 interrupts = <28>;
392 };
393
394 epit2: timer@53f98000 {
395 compatible = "fsl,imx25-epit";
396 reg = <0x53f98000 0x4000>;
397 clocks = <&clks 84>, <&clks 43>;
398 clock-names = "ipg", "per";
399 interrupts = <27>;
400 };
401
402 gpio4: gpio@53f9c000 {
403 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
404 reg = <0x53f9c000 0x4000>;
405 interrupts = <23>;
406 gpio-controller;
407 #gpio-cells = <2>;
408 interrupt-controller;
409 #interrupt-cells = <2>;
410 };
411
412 pwm2: pwm@53fa0000 {
413 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
414 #pwm-cells = <2>;
415 reg = <0x53fa0000 0x4000>;
416 clocks = <&clks 106>, <&clks 52>;
417 clock-names = "ipg", "per";
418 interrupts = <36>;
419 };
420
421 gpio3: gpio@53fa4000 {
422 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
423 reg = <0x53fa4000 0x4000>;
424 interrupts = <16>;
425 gpio-controller;
426 #gpio-cells = <2>;
427 interrupt-controller;
428 #interrupt-cells = <2>;
429 };
430
431 pwm3: pwm@53fa8000 {
432 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
433 #pwm-cells = <2>;
434 reg = <0x53fa8000 0x4000>;
435 clocks = <&clks 107>, <&clks 52>;
436 clock-names = "ipg", "per";
437 interrupts = <41>;
438 };
439
440 scc: crypto@53fac000 {
441 compatible = "fsl,imx25-scc";
442 reg = <0x53fac000 0x4000>;
443 clocks = <&clks 111>;
444 clock-names = "ipg";
445 interrupts = <49>, <50>;
446 interrupt-names = "scm", "smn";
447 };
448
449 rngb: rngb@53fb0000 {
450 compatible = "fsl,imx25-rngb";
451 reg = <0x53fb0000 0x4000>;
452 clocks = <&clks 109>;
453 interrupts = <22>;
454 };
455
456 esdhc1: esdhc@53fb4000 {
457 compatible = "fsl,imx25-esdhc";
458 reg = <0x53fb4000 0x4000>;
459 interrupts = <9>;
460 clocks = <&clks 86>, <&clks 63>, <&clks 45>;
461 clock-names = "ipg", "ahb", "per";
462 status = "disabled";
463 };
464
465 esdhc2: esdhc@53fb8000 {
466 compatible = "fsl,imx25-esdhc";
467 reg = <0x53fb8000 0x4000>;
468 interrupts = <8>;
469 clocks = <&clks 87>, <&clks 64>, <&clks 46>;
470 clock-names = "ipg", "ahb", "per";
471 status = "disabled";
472 };
473
474 lcdc: lcdc@53fbc000 {
475 compatible = "fsl,imx25-fb", "fsl,imx21-fb";
476 reg = <0x53fbc000 0x4000>;
477 interrupts = <39>;
478 clocks = <&clks 103>, <&clks 66>, <&clks 49>;
479 clock-names = "ipg", "ahb", "per";
480 status = "disabled";
481 };
482
483 slcdc@53fc0000 {
484 reg = <0x53fc0000 0x4000>;
485 interrupts = <38>;
486 status = "disabled";
487 };
488
489 pwm4: pwm@53fc8000 {
490 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
491 #pwm-cells = <2>;
492 reg = <0x53fc8000 0x4000>;
493 clocks = <&clks 108>, <&clks 52>;
494 clock-names = "ipg", "per";
495 interrupts = <42>;
496 };
497
498 gpio1: gpio@53fcc000 {
499 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
500 reg = <0x53fcc000 0x4000>;
501 interrupts = <52>;
502 gpio-controller;
503 #gpio-cells = <2>;
504 interrupt-controller;
505 #interrupt-cells = <2>;
506 };
507
508 gpio2: gpio@53fd0000 {
509 compatible = "fsl,imx25-gpio", "fsl,imx35-gpio";
510 reg = <0x53fd0000 0x4000>;
511 interrupts = <51>;
512 gpio-controller;
513 #gpio-cells = <2>;
514 interrupt-controller;
515 #interrupt-cells = <2>;
516 };
517
518 sdma: sdma@53fd4000 {
519 compatible = "fsl,imx25-sdma";
520 reg = <0x53fd4000 0x4000>;
521 clocks = <&clks 112>, <&clks 68>;
522 clock-names = "ipg", "ahb";
523 #dma-cells = <3>;
524 interrupts = <34>;
525 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx25.bin";
526 };
527
528 wdog@53fdc000 {
529 compatible = "fsl,imx25-wdt", "fsl,imx21-wdt";
530 reg = <0x53fdc000 0x4000>;
531 clocks = <&clks 126>;
532 clock-names = "";
533 interrupts = <55>;
534 };
535
536 pwm1: pwm@53fe0000 {
537 compatible = "fsl,imx25-pwm", "fsl,imx27-pwm";
538 #pwm-cells = <2>;
539 reg = <0x53fe0000 0x4000>;
540 clocks = <&clks 105>, <&clks 52>;
541 clock-names = "ipg", "per";
542 interrupts = <26>;
543 };
544
545 iim: iim@53ff0000 {
546 compatible = "fsl,imx25-iim", "fsl,imx27-iim";
547 reg = <0x53ff0000 0x4000>;
548 interrupts = <19>;
549 clocks = <&clks 99>;
550 };
551
552 usbotg: usb@53ff4000 {
553 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
554 reg = <0x53ff4000 0x0200>;
555 interrupts = <37>;
556 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
557 clock-names = "ipg", "ahb", "per";
558 fsl,usbmisc = <&usbmisc 0>;
559 fsl,usbphy = <&usbphy0>;
560 phy_type = "utmi";
561 dr_mode = "otg";
562 status = "disabled";
563 };
564
565 usbhost1: usb@53ff4400 {
566 compatible = "fsl,imx25-usb", "fsl,imx27-usb";
567 reg = <0x53ff4400 0x0200>;
568 interrupts = <35>;
569 clocks = <&clks 9>, <&clks 70>, <&clks 8>;
570 clock-names = "ipg", "ahb", "per";
571 fsl,usbmisc = <&usbmisc 1>;
572 fsl,usbphy = <&usbphy1>;
573 status = "disabled";
574 };
575
576 usbmisc: usbmisc@53ff4600 {
577 #index-cells = <1>;
578 compatible = "fsl,imx25-usbmisc";
579 reg = <0x53ff4600 0x00f>;
580 };
581
582 dryice@53ffc000 {
583 compatible = "fsl,imx25-dryice", "fsl,imx25-rtc";
584 reg = <0x53ffc000 0x4000>;
585 clocks = <&clks 81>;
586 clock-names = "ipg";
587 interrupts = <25 56>;
588 };
589 };
590
591 iram: sram@78000000 {
592 compatible = "mmio-sram";
593 reg = <0x78000000 0x20000>;
594 };
595
596 emi@80000000 {
597 compatible = "fsl,emi-bus", "simple-bus";
598 #address-cells = <1>;
599 #size-cells = <1>;
600 reg = <0x80000000 0x3b002000>;
601 ranges;
602
603 nfc: nand@bb000000 {
604 #address-cells = <1>;
605 #size-cells = <1>;
606
607 compatible = "fsl,imx25-nand";
608 reg = <0xbb000000 0x2000>;
609 clocks = <&clks 50>;
610 clock-names = "";
611 interrupts = <33>;
612 status = "disabled";
613 };
614 };
615 };
616
617 usbphy {
618 compatible = "simple-bus";
619 #address-cells = <1>;
620 #size-cells = <0>;
621
622 usbphy0: usb-phy@0 {
623 reg = <0>;
624 compatible = "usb-nop-xceiv";
625 #phy-cells = <0>;
626 };
627
628 usbphy1: usb-phy@1 {
629 reg = <1>;
630 compatible = "usb-nop-xceiv";
631 #phy-cells = <0>;
632 };
633 };
634};