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v4.17
 
   1/*
   2 * Device Tree Source for DRA7xx clock data
   3 *
   4 * Copyright (C) 2013 Texas Instruments, Inc.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10&cm_core_aon_clocks {
  11	atl_clkin0_ck: atl_clkin0_ck {
  12		#clock-cells = <0>;
  13		compatible = "ti,dra7-atl-clock";
  14		clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
  15	};
  16
  17	atl_clkin1_ck: atl_clkin1_ck {
  18		#clock-cells = <0>;
  19		compatible = "ti,dra7-atl-clock";
  20		clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
  21	};
  22
  23	atl_clkin2_ck: atl_clkin2_ck {
  24		#clock-cells = <0>;
  25		compatible = "ti,dra7-atl-clock";
  26		clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
  27	};
  28
  29	atl_clkin3_ck: atl_clkin3_ck {
  30		#clock-cells = <0>;
  31		compatible = "ti,dra7-atl-clock";
  32		clocks = <&atl_clkctrl DRA7_ATL_CLKCTRL 26>;
  33	};
  34
  35	hdmi_clkin_ck: hdmi_clkin_ck {
  36		#clock-cells = <0>;
  37		compatible = "fixed-clock";
  38		clock-frequency = <0>;
  39	};
  40
  41	mlb_clkin_ck: mlb_clkin_ck {
  42		#clock-cells = <0>;
  43		compatible = "fixed-clock";
  44		clock-frequency = <0>;
  45	};
  46
  47	mlbp_clkin_ck: mlbp_clkin_ck {
  48		#clock-cells = <0>;
  49		compatible = "fixed-clock";
  50		clock-frequency = <0>;
  51	};
  52
  53	pciesref_acs_clk_ck: pciesref_acs_clk_ck {
  54		#clock-cells = <0>;
  55		compatible = "fixed-clock";
  56		clock-frequency = <100000000>;
  57	};
  58
  59	ref_clkin0_ck: ref_clkin0_ck {
  60		#clock-cells = <0>;
  61		compatible = "fixed-clock";
  62		clock-frequency = <0>;
  63	};
  64
  65	ref_clkin1_ck: ref_clkin1_ck {
  66		#clock-cells = <0>;
  67		compatible = "fixed-clock";
  68		clock-frequency = <0>;
  69	};
  70
  71	ref_clkin2_ck: ref_clkin2_ck {
  72		#clock-cells = <0>;
  73		compatible = "fixed-clock";
  74		clock-frequency = <0>;
  75	};
  76
  77	ref_clkin3_ck: ref_clkin3_ck {
  78		#clock-cells = <0>;
  79		compatible = "fixed-clock";
  80		clock-frequency = <0>;
  81	};
  82
  83	rmii_clk_ck: rmii_clk_ck {
  84		#clock-cells = <0>;
  85		compatible = "fixed-clock";
  86		clock-frequency = <0>;
  87	};
  88
  89	sdvenc_clkin_ck: sdvenc_clkin_ck {
  90		#clock-cells = <0>;
  91		compatible = "fixed-clock";
  92		clock-frequency = <0>;
  93	};
  94
  95	secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  96		#clock-cells = <0>;
  97		compatible = "fixed-clock";
  98		clock-frequency = <32768>;
  99	};
 100
 101	sys_clk32_crystal_ck: sys_clk32_crystal_ck {
 102		#clock-cells = <0>;
 103		compatible = "fixed-clock";
 104		clock-frequency = <32768>;
 105	};
 106
 107	sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
 108		#clock-cells = <0>;
 109		compatible = "fixed-factor-clock";
 110		clocks = <&sys_clkin1>;
 111		clock-mult = <1>;
 112		clock-div = <610>;
 113	};
 114
 115	virt_12000000_ck: virt_12000000_ck {
 116		#clock-cells = <0>;
 117		compatible = "fixed-clock";
 118		clock-frequency = <12000000>;
 119	};
 120
 121	virt_13000000_ck: virt_13000000_ck {
 122		#clock-cells = <0>;
 123		compatible = "fixed-clock";
 124		clock-frequency = <13000000>;
 125	};
 126
 127	virt_16800000_ck: virt_16800000_ck {
 128		#clock-cells = <0>;
 129		compatible = "fixed-clock";
 130		clock-frequency = <16800000>;
 131	};
 132
 133	virt_19200000_ck: virt_19200000_ck {
 134		#clock-cells = <0>;
 135		compatible = "fixed-clock";
 136		clock-frequency = <19200000>;
 137	};
 138
 139	virt_20000000_ck: virt_20000000_ck {
 140		#clock-cells = <0>;
 141		compatible = "fixed-clock";
 142		clock-frequency = <20000000>;
 143	};
 144
 145	virt_26000000_ck: virt_26000000_ck {
 146		#clock-cells = <0>;
 147		compatible = "fixed-clock";
 148		clock-frequency = <26000000>;
 149	};
 150
 151	virt_27000000_ck: virt_27000000_ck {
 152		#clock-cells = <0>;
 153		compatible = "fixed-clock";
 154		clock-frequency = <27000000>;
 155	};
 156
 157	virt_38400000_ck: virt_38400000_ck {
 158		#clock-cells = <0>;
 159		compatible = "fixed-clock";
 160		clock-frequency = <38400000>;
 161	};
 162
 163	sys_clkin2: sys_clkin2 {
 164		#clock-cells = <0>;
 165		compatible = "fixed-clock";
 166		clock-frequency = <22579200>;
 167	};
 168
 169	usb_otg_clkin_ck: usb_otg_clkin_ck {
 170		#clock-cells = <0>;
 171		compatible = "fixed-clock";
 172		clock-frequency = <0>;
 173	};
 174
 175	video1_clkin_ck: video1_clkin_ck {
 176		#clock-cells = <0>;
 177		compatible = "fixed-clock";
 178		clock-frequency = <0>;
 179	};
 180
 181	video1_m2_clkin_ck: video1_m2_clkin_ck {
 182		#clock-cells = <0>;
 183		compatible = "fixed-clock";
 184		clock-frequency = <0>;
 185	};
 186
 187	video2_clkin_ck: video2_clkin_ck {
 188		#clock-cells = <0>;
 189		compatible = "fixed-clock";
 190		clock-frequency = <0>;
 191	};
 192
 193	video2_m2_clkin_ck: video2_m2_clkin_ck {
 194		#clock-cells = <0>;
 195		compatible = "fixed-clock";
 196		clock-frequency = <0>;
 197	};
 198
 199	dpll_abe_ck: dpll_abe_ck@1e0 {
 200		#clock-cells = <0>;
 201		compatible = "ti,omap4-dpll-m4xen-clock";
 202		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 203		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 204	};
 205
 206	dpll_abe_x2_ck: dpll_abe_x2_ck {
 207		#clock-cells = <0>;
 208		compatible = "ti,omap4-dpll-x2-clock";
 209		clocks = <&dpll_abe_ck>;
 210	};
 211
 212	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 213		#clock-cells = <0>;
 214		compatible = "ti,divider-clock";
 215		clocks = <&dpll_abe_x2_ck>;
 216		ti,max-div = <31>;
 217		ti,autoidle-shift = <8>;
 218		reg = <0x01f0>;
 219		ti,index-starts-at-one;
 220		ti,invert-autoidle-bit;
 221	};
 222
 223	abe_clk: abe_clk@108 {
 224		#clock-cells = <0>;
 225		compatible = "ti,divider-clock";
 226		clocks = <&dpll_abe_m2x2_ck>;
 227		ti,max-div = <4>;
 228		reg = <0x0108>;
 229		ti,index-power-of-two;
 230	};
 231
 232	dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
 233		#clock-cells = <0>;
 234		compatible = "ti,divider-clock";
 235		clocks = <&dpll_abe_ck>;
 236		ti,max-div = <31>;
 237		ti,autoidle-shift = <8>;
 238		reg = <0x01f0>;
 239		ti,index-starts-at-one;
 240		ti,invert-autoidle-bit;
 241	};
 242
 243	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 244		#clock-cells = <0>;
 245		compatible = "ti,divider-clock";
 246		clocks = <&dpll_abe_x2_ck>;
 247		ti,max-div = <31>;
 248		ti,autoidle-shift = <8>;
 249		reg = <0x01f4>;
 250		ti,index-starts-at-one;
 251		ti,invert-autoidle-bit;
 252	};
 253
 254	dpll_core_byp_mux: dpll_core_byp_mux@12c {
 255		#clock-cells = <0>;
 256		compatible = "ti,mux-clock";
 257		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 258		ti,bit-shift = <23>;
 259		reg = <0x012c>;
 260	};
 261
 262	dpll_core_ck: dpll_core_ck@120 {
 263		#clock-cells = <0>;
 264		compatible = "ti,omap4-dpll-core-clock";
 265		clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
 266		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 267	};
 268
 269	dpll_core_x2_ck: dpll_core_x2_ck {
 270		#clock-cells = <0>;
 271		compatible = "ti,omap4-dpll-x2-clock";
 272		clocks = <&dpll_core_ck>;
 273	};
 274
 275	dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
 276		#clock-cells = <0>;
 277		compatible = "ti,divider-clock";
 278		clocks = <&dpll_core_x2_ck>;
 279		ti,max-div = <63>;
 280		ti,autoidle-shift = <8>;
 281		reg = <0x013c>;
 282		ti,index-starts-at-one;
 283		ti,invert-autoidle-bit;
 284	};
 285
 286	mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
 287		#clock-cells = <0>;
 288		compatible = "fixed-factor-clock";
 289		clocks = <&dpll_core_h12x2_ck>;
 290		clock-mult = <1>;
 291		clock-div = <1>;
 292	};
 293
 294	dpll_mpu_ck: dpll_mpu_ck@160 {
 295		#clock-cells = <0>;
 296		compatible = "ti,omap5-mpu-dpll-clock";
 297		clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
 298		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 299	};
 300
 301	dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 302		#clock-cells = <0>;
 303		compatible = "ti,divider-clock";
 304		clocks = <&dpll_mpu_ck>;
 305		ti,max-div = <31>;
 306		ti,autoidle-shift = <8>;
 307		reg = <0x0170>;
 308		ti,index-starts-at-one;
 309		ti,invert-autoidle-bit;
 310	};
 311
 312	mpu_dclk_div: mpu_dclk_div {
 313		#clock-cells = <0>;
 314		compatible = "fixed-factor-clock";
 315		clocks = <&dpll_mpu_m2_ck>;
 316		clock-mult = <1>;
 317		clock-div = <1>;
 318	};
 319
 320	dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
 321		#clock-cells = <0>;
 322		compatible = "fixed-factor-clock";
 323		clocks = <&dpll_core_h12x2_ck>;
 324		clock-mult = <1>;
 325		clock-div = <1>;
 326	};
 327
 328	dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
 329		#clock-cells = <0>;
 330		compatible = "ti,mux-clock";
 331		clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
 332		ti,bit-shift = <23>;
 333		reg = <0x0240>;
 334	};
 335
 336	dpll_dsp_ck: dpll_dsp_ck@234 {
 337		#clock-cells = <0>;
 338		compatible = "ti,omap4-dpll-clock";
 339		clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
 340		reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
 341		assigned-clocks = <&dpll_dsp_ck>;
 342		assigned-clock-rates = <600000000>;
 343	};
 344
 345	dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
 346		#clock-cells = <0>;
 347		compatible = "ti,divider-clock";
 348		clocks = <&dpll_dsp_ck>;
 349		ti,max-div = <31>;
 350		ti,autoidle-shift = <8>;
 351		reg = <0x0244>;
 352		ti,index-starts-at-one;
 353		ti,invert-autoidle-bit;
 354		assigned-clocks = <&dpll_dsp_m2_ck>;
 355		assigned-clock-rates = <600000000>;
 356	};
 357
 358	iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
 359		#clock-cells = <0>;
 360		compatible = "fixed-factor-clock";
 361		clocks = <&dpll_core_h12x2_ck>;
 362		clock-mult = <1>;
 363		clock-div = <1>;
 364	};
 365
 366	dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
 367		#clock-cells = <0>;
 368		compatible = "ti,mux-clock";
 369		clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
 370		ti,bit-shift = <23>;
 371		reg = <0x01ac>;
 372	};
 373
 374	dpll_iva_ck: dpll_iva_ck@1a0 {
 375		#clock-cells = <0>;
 376		compatible = "ti,omap4-dpll-clock";
 377		clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
 378		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 379		assigned-clocks = <&dpll_iva_ck>;
 380		assigned-clock-rates = <1165000000>;
 381	};
 382
 383	dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
 384		#clock-cells = <0>;
 385		compatible = "ti,divider-clock";
 386		clocks = <&dpll_iva_ck>;
 387		ti,max-div = <31>;
 388		ti,autoidle-shift = <8>;
 389		reg = <0x01b0>;
 390		ti,index-starts-at-one;
 391		ti,invert-autoidle-bit;
 392		assigned-clocks = <&dpll_iva_m2_ck>;
 393		assigned-clock-rates = <388333334>;
 394	};
 395
 396	iva_dclk: iva_dclk {
 397		#clock-cells = <0>;
 398		compatible = "fixed-factor-clock";
 399		clocks = <&dpll_iva_m2_ck>;
 400		clock-mult = <1>;
 401		clock-div = <1>;
 402	};
 403
 404	dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
 405		#clock-cells = <0>;
 406		compatible = "ti,mux-clock";
 407		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 408		ti,bit-shift = <23>;
 409		reg = <0x02e4>;
 410	};
 411
 412	dpll_gpu_ck: dpll_gpu_ck@2d8 {
 413		#clock-cells = <0>;
 414		compatible = "ti,omap4-dpll-clock";
 415		clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
 416		reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
 417		assigned-clocks = <&dpll_gpu_ck>;
 418		assigned-clock-rates = <1277000000>;
 419	};
 420
 421	dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
 422		#clock-cells = <0>;
 423		compatible = "ti,divider-clock";
 424		clocks = <&dpll_gpu_ck>;
 425		ti,max-div = <31>;
 426		ti,autoidle-shift = <8>;
 427		reg = <0x02e8>;
 428		ti,index-starts-at-one;
 429		ti,invert-autoidle-bit;
 430		assigned-clocks = <&dpll_gpu_m2_ck>;
 431		assigned-clock-rates = <425666667>;
 432	};
 433
 434	dpll_core_m2_ck: dpll_core_m2_ck@130 {
 435		#clock-cells = <0>;
 436		compatible = "ti,divider-clock";
 437		clocks = <&dpll_core_ck>;
 438		ti,max-div = <31>;
 439		ti,autoidle-shift = <8>;
 440		reg = <0x0130>;
 441		ti,index-starts-at-one;
 442		ti,invert-autoidle-bit;
 443	};
 444
 445	core_dpll_out_dclk_div: core_dpll_out_dclk_div {
 446		#clock-cells = <0>;
 447		compatible = "fixed-factor-clock";
 448		clocks = <&dpll_core_m2_ck>;
 449		clock-mult = <1>;
 450		clock-div = <1>;
 451	};
 452
 453	dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
 454		#clock-cells = <0>;
 455		compatible = "ti,mux-clock";
 456		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 457		ti,bit-shift = <23>;
 458		reg = <0x021c>;
 459	};
 460
 461	dpll_ddr_ck: dpll_ddr_ck@210 {
 462		#clock-cells = <0>;
 463		compatible = "ti,omap4-dpll-clock";
 464		clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
 465		reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 466	};
 467
 468	dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
 469		#clock-cells = <0>;
 470		compatible = "ti,divider-clock";
 471		clocks = <&dpll_ddr_ck>;
 472		ti,max-div = <31>;
 473		ti,autoidle-shift = <8>;
 474		reg = <0x0220>;
 475		ti,index-starts-at-one;
 476		ti,invert-autoidle-bit;
 477	};
 478
 479	dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
 480		#clock-cells = <0>;
 481		compatible = "ti,mux-clock";
 482		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 483		ti,bit-shift = <23>;
 484		reg = <0x02b4>;
 485	};
 486
 487	dpll_gmac_ck: dpll_gmac_ck@2a8 {
 488		#clock-cells = <0>;
 489		compatible = "ti,omap4-dpll-clock";
 490		clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
 491		reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 492	};
 493
 494	dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
 495		#clock-cells = <0>;
 496		compatible = "ti,divider-clock";
 497		clocks = <&dpll_gmac_ck>;
 498		ti,max-div = <31>;
 499		ti,autoidle-shift = <8>;
 500		reg = <0x02b8>;
 501		ti,index-starts-at-one;
 502		ti,invert-autoidle-bit;
 503	};
 504
 505	video2_dclk_div: video2_dclk_div {
 506		#clock-cells = <0>;
 507		compatible = "fixed-factor-clock";
 508		clocks = <&video2_m2_clkin_ck>;
 509		clock-mult = <1>;
 510		clock-div = <1>;
 511	};
 512
 513	video1_dclk_div: video1_dclk_div {
 514		#clock-cells = <0>;
 515		compatible = "fixed-factor-clock";
 516		clocks = <&video1_m2_clkin_ck>;
 517		clock-mult = <1>;
 518		clock-div = <1>;
 519	};
 520
 521	hdmi_dclk_div: hdmi_dclk_div {
 522		#clock-cells = <0>;
 523		compatible = "fixed-factor-clock";
 524		clocks = <&hdmi_clkin_ck>;
 525		clock-mult = <1>;
 526		clock-div = <1>;
 527	};
 528
 529	per_dpll_hs_clk_div: per_dpll_hs_clk_div {
 530		#clock-cells = <0>;
 531		compatible = "fixed-factor-clock";
 532		clocks = <&dpll_abe_m3x2_ck>;
 533		clock-mult = <1>;
 534		clock-div = <2>;
 535	};
 536
 537	usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
 538		#clock-cells = <0>;
 539		compatible = "fixed-factor-clock";
 540		clocks = <&dpll_abe_m3x2_ck>;
 541		clock-mult = <1>;
 542		clock-div = <3>;
 543	};
 544
 545	eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
 546		#clock-cells = <0>;
 547		compatible = "fixed-factor-clock";
 548		clocks = <&dpll_core_h12x2_ck>;
 549		clock-mult = <1>;
 550		clock-div = <1>;
 551	};
 552
 553	dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
 554		#clock-cells = <0>;
 555		compatible = "ti,mux-clock";
 556		clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
 557		ti,bit-shift = <23>;
 558		reg = <0x0290>;
 559	};
 560
 561	dpll_eve_ck: dpll_eve_ck@284 {
 562		#clock-cells = <0>;
 563		compatible = "ti,omap4-dpll-clock";
 564		clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
 565		reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 566	};
 567
 568	dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
 569		#clock-cells = <0>;
 570		compatible = "ti,divider-clock";
 571		clocks = <&dpll_eve_ck>;
 572		ti,max-div = <31>;
 573		ti,autoidle-shift = <8>;
 574		reg = <0x0294>;
 575		ti,index-starts-at-one;
 576		ti,invert-autoidle-bit;
 577	};
 578
 579	eve_dclk_div: eve_dclk_div {
 580		#clock-cells = <0>;
 581		compatible = "fixed-factor-clock";
 582		clocks = <&dpll_eve_m2_ck>;
 583		clock-mult = <1>;
 584		clock-div = <1>;
 585	};
 586
 587	dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
 588		#clock-cells = <0>;
 589		compatible = "ti,divider-clock";
 590		clocks = <&dpll_core_x2_ck>;
 591		ti,max-div = <63>;
 592		ti,autoidle-shift = <8>;
 593		reg = <0x0140>;
 594		ti,index-starts-at-one;
 595		ti,invert-autoidle-bit;
 596	};
 597
 598	dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
 599		#clock-cells = <0>;
 600		compatible = "ti,divider-clock";
 601		clocks = <&dpll_core_x2_ck>;
 602		ti,max-div = <63>;
 603		ti,autoidle-shift = <8>;
 604		reg = <0x0144>;
 605		ti,index-starts-at-one;
 606		ti,invert-autoidle-bit;
 607	};
 608
 609	dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
 610		#clock-cells = <0>;
 611		compatible = "ti,divider-clock";
 612		clocks = <&dpll_core_x2_ck>;
 613		ti,max-div = <63>;
 614		ti,autoidle-shift = <8>;
 615		reg = <0x0154>;
 616		ti,index-starts-at-one;
 617		ti,invert-autoidle-bit;
 618	};
 619
 620	dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
 621		#clock-cells = <0>;
 622		compatible = "ti,divider-clock";
 623		clocks = <&dpll_core_x2_ck>;
 624		ti,max-div = <63>;
 625		ti,autoidle-shift = <8>;
 626		reg = <0x0158>;
 627		ti,index-starts-at-one;
 628		ti,invert-autoidle-bit;
 629	};
 630
 631	dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
 632		#clock-cells = <0>;
 633		compatible = "ti,divider-clock";
 634		clocks = <&dpll_core_x2_ck>;
 635		ti,max-div = <63>;
 636		ti,autoidle-shift = <8>;
 637		reg = <0x015c>;
 638		ti,index-starts-at-one;
 639		ti,invert-autoidle-bit;
 640	};
 641
 642	dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 643		#clock-cells = <0>;
 644		compatible = "ti,omap4-dpll-x2-clock";
 645		clocks = <&dpll_ddr_ck>;
 646	};
 647
 648	dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
 649		#clock-cells = <0>;
 650		compatible = "ti,divider-clock";
 651		clocks = <&dpll_ddr_x2_ck>;
 652		ti,max-div = <63>;
 653		ti,autoidle-shift = <8>;
 654		reg = <0x0228>;
 655		ti,index-starts-at-one;
 656		ti,invert-autoidle-bit;
 657	};
 658
 659	dpll_dsp_x2_ck: dpll_dsp_x2_ck {
 660		#clock-cells = <0>;
 661		compatible = "ti,omap4-dpll-x2-clock";
 662		clocks = <&dpll_dsp_ck>;
 663	};
 664
 665	dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
 666		#clock-cells = <0>;
 667		compatible = "ti,divider-clock";
 668		clocks = <&dpll_dsp_x2_ck>;
 669		ti,max-div = <31>;
 670		ti,autoidle-shift = <8>;
 671		reg = <0x0248>;
 672		ti,index-starts-at-one;
 673		ti,invert-autoidle-bit;
 674		assigned-clocks = <&dpll_dsp_m3x2_ck>;
 675		assigned-clock-rates = <400000000>;
 676	};
 677
 678	dpll_gmac_x2_ck: dpll_gmac_x2_ck {
 679		#clock-cells = <0>;
 680		compatible = "ti,omap4-dpll-x2-clock";
 681		clocks = <&dpll_gmac_ck>;
 682	};
 683
 684	dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
 685		#clock-cells = <0>;
 686		compatible = "ti,divider-clock";
 687		clocks = <&dpll_gmac_x2_ck>;
 688		ti,max-div = <63>;
 689		ti,autoidle-shift = <8>;
 690		reg = <0x02c0>;
 691		ti,index-starts-at-one;
 692		ti,invert-autoidle-bit;
 693	};
 694
 695	dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
 696		#clock-cells = <0>;
 697		compatible = "ti,divider-clock";
 698		clocks = <&dpll_gmac_x2_ck>;
 699		ti,max-div = <63>;
 700		ti,autoidle-shift = <8>;
 701		reg = <0x02c4>;
 702		ti,index-starts-at-one;
 703		ti,invert-autoidle-bit;
 704	};
 705
 706	dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
 707		#clock-cells = <0>;
 708		compatible = "ti,divider-clock";
 709		clocks = <&dpll_gmac_x2_ck>;
 710		ti,max-div = <63>;
 711		ti,autoidle-shift = <8>;
 712		reg = <0x02c8>;
 713		ti,index-starts-at-one;
 714		ti,invert-autoidle-bit;
 715	};
 716
 717	dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
 718		#clock-cells = <0>;
 719		compatible = "ti,divider-clock";
 720		clocks = <&dpll_gmac_x2_ck>;
 721		ti,max-div = <31>;
 722		ti,autoidle-shift = <8>;
 723		reg = <0x02bc>;
 724		ti,index-starts-at-one;
 725		ti,invert-autoidle-bit;
 726	};
 727
 728	gmii_m_clk_div: gmii_m_clk_div {
 729		#clock-cells = <0>;
 730		compatible = "fixed-factor-clock";
 731		clocks = <&dpll_gmac_h11x2_ck>;
 732		clock-mult = <1>;
 733		clock-div = <2>;
 734	};
 735
 736	hdmi_clk2_div: hdmi_clk2_div {
 737		#clock-cells = <0>;
 738		compatible = "fixed-factor-clock";
 739		clocks = <&hdmi_clkin_ck>;
 740		clock-mult = <1>;
 741		clock-div = <1>;
 742	};
 743
 744	hdmi_div_clk: hdmi_div_clk {
 745		#clock-cells = <0>;
 746		compatible = "fixed-factor-clock";
 747		clocks = <&hdmi_clkin_ck>;
 748		clock-mult = <1>;
 749		clock-div = <1>;
 750	};
 751
 752	l3_iclk_div: l3_iclk_div@100 {
 753		#clock-cells = <0>;
 754		compatible = "ti,divider-clock";
 755		ti,max-div = <2>;
 756		ti,bit-shift = <4>;
 757		reg = <0x0100>;
 758		clocks = <&dpll_core_h12x2_ck>;
 759		ti,index-power-of-two;
 760	};
 761
 762	l4_root_clk_div: l4_root_clk_div {
 763		#clock-cells = <0>;
 764		compatible = "fixed-factor-clock";
 765		clocks = <&l3_iclk_div>;
 766		clock-mult = <1>;
 767		clock-div = <2>;
 768	};
 769
 770	video1_clk2_div: video1_clk2_div {
 771		#clock-cells = <0>;
 772		compatible = "fixed-factor-clock";
 773		clocks = <&video1_clkin_ck>;
 774		clock-mult = <1>;
 775		clock-div = <1>;
 776	};
 777
 778	video1_div_clk: video1_div_clk {
 779		#clock-cells = <0>;
 780		compatible = "fixed-factor-clock";
 781		clocks = <&video1_clkin_ck>;
 782		clock-mult = <1>;
 783		clock-div = <1>;
 784	};
 785
 786	video2_clk2_div: video2_clk2_div {
 787		#clock-cells = <0>;
 788		compatible = "fixed-factor-clock";
 789		clocks = <&video2_clkin_ck>;
 790		clock-mult = <1>;
 791		clock-div = <1>;
 792	};
 793
 794	video2_div_clk: video2_div_clk {
 795		#clock-cells = <0>;
 796		compatible = "fixed-factor-clock";
 797		clocks = <&video2_clkin_ck>;
 798		clock-mult = <1>;
 799		clock-div = <1>;
 800	};
 801
 802	ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
 803		#clock-cells = <0>;
 804		compatible = "ti,mux-clock";
 805		clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
 806		ti,bit-shift = <24>;
 807		reg = <0x0520>;
 808		assigned-clocks = <&ipu1_gfclk_mux>;
 809		assigned-clock-parents = <&dpll_core_h22x2_ck>;
 810	};
 811
 812	dummy_ck: dummy_ck {
 813		#clock-cells = <0>;
 814		compatible = "fixed-clock";
 815		clock-frequency = <0>;
 816	};
 817};
 818&prm_clocks {
 819	sys_clkin1: sys_clkin1@110 {
 820		#clock-cells = <0>;
 821		compatible = "ti,mux-clock";
 822		clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 823		reg = <0x0110>;
 824		ti,index-starts-at-one;
 825	};
 826
 827	abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
 828		#clock-cells = <0>;
 829		compatible = "ti,mux-clock";
 830		clocks = <&sys_clkin1>, <&sys_clkin2>;
 831		reg = <0x0118>;
 832	};
 833
 834	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
 835		#clock-cells = <0>;
 836		compatible = "ti,mux-clock";
 837		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 838		reg = <0x0114>;
 839	};
 840
 841	abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
 842		#clock-cells = <0>;
 843		compatible = "ti,mux-clock";
 844		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 845		reg = <0x010c>;
 846	};
 847
 848	abe_24m_fclk: abe_24m_fclk@11c {
 849		#clock-cells = <0>;
 850		compatible = "ti,divider-clock";
 851		clocks = <&dpll_abe_m2x2_ck>;
 852		reg = <0x011c>;
 853		ti,dividers = <8>, <16>;
 854	};
 855
 856	aess_fclk: aess_fclk@178 {
 857		#clock-cells = <0>;
 858		compatible = "ti,divider-clock";
 859		clocks = <&abe_clk>;
 860		reg = <0x0178>;
 861		ti,max-div = <2>;
 862	};
 863
 864	abe_giclk_div: abe_giclk_div@174 {
 865		#clock-cells = <0>;
 866		compatible = "ti,divider-clock";
 867		clocks = <&aess_fclk>;
 868		reg = <0x0174>;
 869		ti,max-div = <2>;
 870	};
 871
 872	abe_lp_clk_div: abe_lp_clk_div@1d8 {
 873		#clock-cells = <0>;
 874		compatible = "ti,divider-clock";
 875		clocks = <&dpll_abe_m2x2_ck>;
 876		reg = <0x01d8>;
 877		ti,dividers = <16>, <32>;
 878	};
 879
 880	abe_sys_clk_div: abe_sys_clk_div@120 {
 881		#clock-cells = <0>;
 882		compatible = "ti,divider-clock";
 883		clocks = <&sys_clkin1>;
 884		reg = <0x0120>;
 885		ti,max-div = <2>;
 886	};
 887
 888	adc_gfclk_mux: adc_gfclk_mux@1dc {
 889		#clock-cells = <0>;
 890		compatible = "ti,mux-clock";
 891		clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
 892		reg = <0x01dc>;
 893	};
 894
 895	sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
 896		#clock-cells = <0>;
 897		compatible = "ti,divider-clock";
 898		clocks = <&sys_clkin1>;
 899		ti,max-div = <64>;
 900		reg = <0x01c8>;
 901		ti,index-power-of-two;
 902	};
 903
 904	sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
 905		#clock-cells = <0>;
 906		compatible = "ti,divider-clock";
 907		clocks = <&sys_clkin2>;
 908		ti,max-div = <64>;
 909		reg = <0x01cc>;
 910		ti,index-power-of-two;
 911	};
 912
 913	per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
 914		#clock-cells = <0>;
 915		compatible = "ti,divider-clock";
 916		clocks = <&dpll_abe_m2_ck>;
 917		ti,max-div = <64>;
 918		reg = <0x01bc>;
 919		ti,index-power-of-two;
 920	};
 921
 922	dsp_gclk_div: dsp_gclk_div@18c {
 923		#clock-cells = <0>;
 924		compatible = "ti,divider-clock";
 925		clocks = <&dpll_dsp_m2_ck>;
 926		ti,max-div = <64>;
 927		reg = <0x018c>;
 928		ti,index-power-of-two;
 929	};
 930
 931	gpu_dclk: gpu_dclk@1a0 {
 932		#clock-cells = <0>;
 933		compatible = "ti,divider-clock";
 934		clocks = <&dpll_gpu_m2_ck>;
 935		ti,max-div = <64>;
 936		reg = <0x01a0>;
 937		ti,index-power-of-two;
 938	};
 939
 940	emif_phy_dclk_div: emif_phy_dclk_div@190 {
 941		#clock-cells = <0>;
 942		compatible = "ti,divider-clock";
 943		clocks = <&dpll_ddr_m2_ck>;
 944		ti,max-div = <64>;
 945		reg = <0x0190>;
 946		ti,index-power-of-two;
 947	};
 948
 949	gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
 950		#clock-cells = <0>;
 951		compatible = "ti,divider-clock";
 952		clocks = <&dpll_gmac_m2_ck>;
 953		ti,max-div = <64>;
 954		reg = <0x019c>;
 955		ti,index-power-of-two;
 956	};
 957
 958	gmac_main_clk: gmac_main_clk {
 959		#clock-cells = <0>;
 960		compatible = "fixed-factor-clock";
 961		clocks = <&gmac_250m_dclk_div>;
 962		clock-mult = <1>;
 963		clock-div = <2>;
 964	};
 965
 966	l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
 967		#clock-cells = <0>;
 968		compatible = "ti,divider-clock";
 969		clocks = <&dpll_usb_m2_ck>;
 970		ti,max-div = <64>;
 971		reg = <0x01ac>;
 972		ti,index-power-of-two;
 973	};
 974
 975	usb_otg_dclk_div: usb_otg_dclk_div@184 {
 976		#clock-cells = <0>;
 977		compatible = "ti,divider-clock";
 978		clocks = <&usb_otg_clkin_ck>;
 979		ti,max-div = <64>;
 980		reg = <0x0184>;
 981		ti,index-power-of-two;
 982	};
 983
 984	sata_dclk_div: sata_dclk_div@1c0 {
 985		#clock-cells = <0>;
 986		compatible = "ti,divider-clock";
 987		clocks = <&sys_clkin1>;
 988		ti,max-div = <64>;
 989		reg = <0x01c0>;
 990		ti,index-power-of-two;
 991	};
 992
 993	pcie2_dclk_div: pcie2_dclk_div@1b8 {
 994		#clock-cells = <0>;
 995		compatible = "ti,divider-clock";
 996		clocks = <&dpll_pcie_ref_m2_ck>;
 997		ti,max-div = <64>;
 998		reg = <0x01b8>;
 999		ti,index-power-of-two;
1000	};
1001
1002	pcie_dclk_div: pcie_dclk_div@1b4 {
1003		#clock-cells = <0>;
1004		compatible = "ti,divider-clock";
1005		clocks = <&apll_pcie_m2_ck>;
1006		ti,max-div = <64>;
1007		reg = <0x01b4>;
1008		ti,index-power-of-two;
1009	};
1010
1011	emu_dclk_div: emu_dclk_div@194 {
1012		#clock-cells = <0>;
1013		compatible = "ti,divider-clock";
1014		clocks = <&sys_clkin1>;
1015		ti,max-div = <64>;
1016		reg = <0x0194>;
1017		ti,index-power-of-two;
1018	};
1019
1020	secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
1021		#clock-cells = <0>;
1022		compatible = "ti,divider-clock";
1023		clocks = <&secure_32k_clk_src_ck>;
1024		ti,max-div = <64>;
1025		reg = <0x01c4>;
1026		ti,index-power-of-two;
1027	};
1028
1029	clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
1030		#clock-cells = <0>;
1031		compatible = "ti,mux-clock";
1032		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1033		reg = <0x0158>;
1034	};
1035
1036	clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
1037		#clock-cells = <0>;
1038		compatible = "ti,mux-clock";
1039		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1040		reg = <0x015c>;
1041	};
1042
1043	clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
1044		#clock-cells = <0>;
1045		compatible = "ti,mux-clock";
1046		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1047		reg = <0x0160>;
1048	};
1049
1050	custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1051		#clock-cells = <0>;
1052		compatible = "fixed-factor-clock";
1053		clocks = <&sys_clkin1>;
1054		clock-mult = <1>;
1055		clock-div = <2>;
1056	};
1057
1058	eve_clk: eve_clk@180 {
1059		#clock-cells = <0>;
1060		compatible = "ti,mux-clock";
1061		clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1062		reg = <0x0180>;
1063	};
1064
1065	hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
1066		#clock-cells = <0>;
1067		compatible = "ti,mux-clock";
1068		clocks = <&sys_clkin1>, <&sys_clkin2>;
1069		reg = <0x0164>;
1070	};
1071
1072	mlb_clk: mlb_clk@134 {
1073		#clock-cells = <0>;
1074		compatible = "ti,divider-clock";
1075		clocks = <&mlb_clkin_ck>;
1076		ti,max-div = <64>;
1077		reg = <0x0134>;
1078		ti,index-power-of-two;
1079	};
1080
1081	mlbp_clk: mlbp_clk@130 {
1082		#clock-cells = <0>;
1083		compatible = "ti,divider-clock";
1084		clocks = <&mlbp_clkin_ck>;
1085		ti,max-div = <64>;
1086		reg = <0x0130>;
1087		ti,index-power-of-two;
1088	};
1089
1090	per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
1091		#clock-cells = <0>;
1092		compatible = "ti,divider-clock";
1093		clocks = <&dpll_abe_m2_ck>;
1094		ti,max-div = <64>;
1095		reg = <0x0138>;
1096		ti,index-power-of-two;
1097	};
1098
1099	timer_sys_clk_div: timer_sys_clk_div@144 {
1100		#clock-cells = <0>;
1101		compatible = "ti,divider-clock";
1102		clocks = <&sys_clkin1>;
1103		reg = <0x0144>;
1104		ti,max-div = <2>;
1105	};
1106
1107	video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
1108		#clock-cells = <0>;
1109		compatible = "ti,mux-clock";
1110		clocks = <&sys_clkin1>, <&sys_clkin2>;
1111		reg = <0x0168>;
1112	};
1113
1114	video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
1115		#clock-cells = <0>;
1116		compatible = "ti,mux-clock";
1117		clocks = <&sys_clkin1>, <&sys_clkin2>;
1118		reg = <0x016c>;
1119	};
1120
1121	wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
1122		#clock-cells = <0>;
1123		compatible = "ti,mux-clock";
1124		clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1125		reg = <0x0108>;
1126	};
1127};
1128
1129&cm_core_clocks {
1130	dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
1131		#clock-cells = <0>;
1132		compatible = "ti,omap4-dpll-clock";
1133		clocks = <&sys_clkin1>, <&sys_clkin1>;
1134		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1135	};
1136
1137	dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
1138		#clock-cells = <0>;
1139		compatible = "ti,divider-clock";
1140		clocks = <&dpll_pcie_ref_ck>;
1141		ti,max-div = <31>;
1142		ti,autoidle-shift = <8>;
1143		reg = <0x0210>;
1144		ti,index-starts-at-one;
1145		ti,invert-autoidle-bit;
1146	};
1147
1148	apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1149		compatible = "ti,mux-clock";
1150		clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1151		#clock-cells = <0>;
1152		reg = <0x021c 0x4>;
1153		ti,bit-shift = <7>;
1154	};
1155
1156	apll_pcie_ck: apll_pcie_ck@21c {
1157		#clock-cells = <0>;
1158		compatible = "ti,dra7-apll-clock";
1159		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1160		reg = <0x021c>, <0x0220>;
1161	};
1162
1163	optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1164		compatible = "ti,divider-clock";
1165		clocks = <&apll_pcie_ck>;
1166		#clock-cells = <0>;
1167		reg = <0x021c>;
1168		ti,dividers = <2>, <1>;
1169		ti,bit-shift = <8>;
1170		ti,max-div = <2>;
1171	};
1172
1173	apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1174		#clock-cells = <0>;
1175		compatible = "fixed-factor-clock";
1176		clocks = <&apll_pcie_ck>;
1177		clock-mult = <1>;
1178		clock-div = <1>;
1179	};
1180
1181	apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1182		#clock-cells = <0>;
1183		compatible = "fixed-factor-clock";
1184		clocks = <&apll_pcie_ck>;
1185		clock-mult = <1>;
1186		clock-div = <1>;
1187	};
1188
1189	apll_pcie_m2_ck: apll_pcie_m2_ck {
1190		#clock-cells = <0>;
1191		compatible = "fixed-factor-clock";
1192		clocks = <&apll_pcie_ck>;
1193		clock-mult = <1>;
1194		clock-div = <1>;
1195	};
1196
1197	dpll_per_byp_mux: dpll_per_byp_mux@14c {
1198		#clock-cells = <0>;
1199		compatible = "ti,mux-clock";
1200		clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1201		ti,bit-shift = <23>;
1202		reg = <0x014c>;
1203	};
1204
1205	dpll_per_ck: dpll_per_ck@140 {
1206		#clock-cells = <0>;
1207		compatible = "ti,omap4-dpll-clock";
1208		clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1209		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1210	};
1211
1212	dpll_per_m2_ck: dpll_per_m2_ck@150 {
1213		#clock-cells = <0>;
1214		compatible = "ti,divider-clock";
1215		clocks = <&dpll_per_ck>;
1216		ti,max-div = <31>;
1217		ti,autoidle-shift = <8>;
1218		reg = <0x0150>;
1219		ti,index-starts-at-one;
1220		ti,invert-autoidle-bit;
1221	};
1222
1223	func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1224		#clock-cells = <0>;
1225		compatible = "fixed-factor-clock";
1226		clocks = <&dpll_per_m2_ck>;
1227		clock-mult = <1>;
1228		clock-div = <1>;
1229	};
1230
1231	dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
1232		#clock-cells = <0>;
1233		compatible = "ti,mux-clock";
1234		clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1235		ti,bit-shift = <23>;
1236		reg = <0x018c>;
1237	};
1238
1239	dpll_usb_ck: dpll_usb_ck@180 {
1240		#clock-cells = <0>;
1241		compatible = "ti,omap4-dpll-j-type-clock";
1242		clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1243		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1244	};
1245
1246	dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
1247		#clock-cells = <0>;
1248		compatible = "ti,divider-clock";
1249		clocks = <&dpll_usb_ck>;
1250		ti,max-div = <127>;
1251		ti,autoidle-shift = <8>;
1252		reg = <0x0190>;
1253		ti,index-starts-at-one;
1254		ti,invert-autoidle-bit;
1255	};
1256
1257	dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
1258		#clock-cells = <0>;
1259		compatible = "ti,divider-clock";
1260		clocks = <&dpll_pcie_ref_ck>;
1261		ti,max-div = <127>;
1262		ti,autoidle-shift = <8>;
1263		reg = <0x0210>;
1264		ti,index-starts-at-one;
1265		ti,invert-autoidle-bit;
1266	};
1267
1268	dpll_per_x2_ck: dpll_per_x2_ck {
1269		#clock-cells = <0>;
1270		compatible = "ti,omap4-dpll-x2-clock";
1271		clocks = <&dpll_per_ck>;
1272	};
1273
1274	dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
1275		#clock-cells = <0>;
1276		compatible = "ti,divider-clock";
1277		clocks = <&dpll_per_x2_ck>;
1278		ti,max-div = <63>;
1279		ti,autoidle-shift = <8>;
1280		reg = <0x0158>;
1281		ti,index-starts-at-one;
1282		ti,invert-autoidle-bit;
1283	};
1284
1285	dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
1286		#clock-cells = <0>;
1287		compatible = "ti,divider-clock";
1288		clocks = <&dpll_per_x2_ck>;
1289		ti,max-div = <63>;
1290		ti,autoidle-shift = <8>;
1291		reg = <0x015c>;
1292		ti,index-starts-at-one;
1293		ti,invert-autoidle-bit;
1294	};
1295
1296	dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
1297		#clock-cells = <0>;
1298		compatible = "ti,divider-clock";
1299		clocks = <&dpll_per_x2_ck>;
1300		ti,max-div = <63>;
1301		ti,autoidle-shift = <8>;
1302		reg = <0x0160>;
1303		ti,index-starts-at-one;
1304		ti,invert-autoidle-bit;
1305	};
1306
1307	dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
1308		#clock-cells = <0>;
1309		compatible = "ti,divider-clock";
1310		clocks = <&dpll_per_x2_ck>;
1311		ti,max-div = <63>;
1312		ti,autoidle-shift = <8>;
1313		reg = <0x0164>;
1314		ti,index-starts-at-one;
1315		ti,invert-autoidle-bit;
1316	};
1317
1318	dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
1319		#clock-cells = <0>;
1320		compatible = "ti,divider-clock";
1321		clocks = <&dpll_per_x2_ck>;
1322		ti,max-div = <31>;
1323		ti,autoidle-shift = <8>;
1324		reg = <0x0150>;
1325		ti,index-starts-at-one;
1326		ti,invert-autoidle-bit;
1327	};
1328
1329	dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1330		#clock-cells = <0>;
1331		compatible = "fixed-factor-clock";
1332		clocks = <&dpll_usb_ck>;
1333		clock-mult = <1>;
1334		clock-div = <1>;
1335	};
1336
1337	func_128m_clk: func_128m_clk {
1338		#clock-cells = <0>;
1339		compatible = "fixed-factor-clock";
1340		clocks = <&dpll_per_h11x2_ck>;
1341		clock-mult = <1>;
1342		clock-div = <2>;
1343	};
1344
1345	func_12m_fclk: func_12m_fclk {
1346		#clock-cells = <0>;
1347		compatible = "fixed-factor-clock";
1348		clocks = <&dpll_per_m2x2_ck>;
1349		clock-mult = <1>;
1350		clock-div = <16>;
1351	};
1352
1353	func_24m_clk: func_24m_clk {
1354		#clock-cells = <0>;
1355		compatible = "fixed-factor-clock";
1356		clocks = <&dpll_per_m2_ck>;
1357		clock-mult = <1>;
1358		clock-div = <4>;
1359	};
1360
1361	func_48m_fclk: func_48m_fclk {
1362		#clock-cells = <0>;
1363		compatible = "fixed-factor-clock";
1364		clocks = <&dpll_per_m2x2_ck>;
1365		clock-mult = <1>;
1366		clock-div = <4>;
1367	};
1368
1369	func_96m_fclk: func_96m_fclk {
1370		#clock-cells = <0>;
1371		compatible = "fixed-factor-clock";
1372		clocks = <&dpll_per_m2x2_ck>;
1373		clock-mult = <1>;
1374		clock-div = <2>;
1375	};
1376
1377	l3init_60m_fclk: l3init_60m_fclk@104 {
1378		#clock-cells = <0>;
1379		compatible = "ti,divider-clock";
1380		clocks = <&dpll_usb_m2_ck>;
1381		reg = <0x0104>;
1382		ti,dividers = <1>, <8>;
1383	};
1384
1385	clkout2_clk: clkout2_clk@6b0 {
1386		#clock-cells = <0>;
1387		compatible = "ti,gate-clock";
1388		clocks = <&clkoutmux2_clk_mux>;
1389		ti,bit-shift = <8>;
1390		reg = <0x06b0>;
1391	};
1392
1393	l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
1394		#clock-cells = <0>;
1395		compatible = "ti,gate-clock";
1396		clocks = <&dpll_usb_clkdcoldo>;
1397		ti,bit-shift = <8>;
1398		reg = <0x06c0>;
1399	};
1400
1401	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
1402		#clock-cells = <0>;
1403		compatible = "ti,gate-clock";
1404		clocks = <&sys_32k_ck>;
1405		ti,bit-shift = <8>;
1406		reg = <0x0640>;
1407	};
1408
1409	usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
1410		#clock-cells = <0>;
1411		compatible = "ti,gate-clock";
1412		clocks = <&sys_32k_ck>;
1413		ti,bit-shift = <8>;
1414		reg = <0x0688>;
1415	};
1416
1417	usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
1418		#clock-cells = <0>;
1419		compatible = "ti,gate-clock";
1420		clocks = <&sys_32k_ck>;
1421		ti,bit-shift = <8>;
1422		reg = <0x0698>;
1423	};
1424
1425	gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
1426		#clock-cells = <0>;
1427		compatible = "ti,mux-clock";
1428		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1429		ti,bit-shift = <24>;
1430		reg = <0x1220>;
1431		assigned-clocks = <&gpu_core_gclk_mux>;
1432		assigned-clock-parents = <&dpll_gpu_m2_ck>;
1433	};
1434
1435	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
1436		#clock-cells = <0>;
1437		compatible = "ti,mux-clock";
1438		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1439		ti,bit-shift = <26>;
1440		reg = <0x1220>;
1441		assigned-clocks = <&gpu_hyd_gclk_mux>;
1442		assigned-clock-parents = <&dpll_gpu_m2_ck>;
1443	};
1444
1445	l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
1446		#clock-cells = <0>;
1447		compatible = "ti,divider-clock";
1448		clocks = <&wkupaon_iclk_mux>;
1449		ti,bit-shift = <24>;
1450		reg = <0x0e50>;
1451		ti,dividers = <8>, <16>, <32>;
1452	};
1453
1454	vip1_gclk_mux: vip1_gclk_mux@1020 {
1455		#clock-cells = <0>;
1456		compatible = "ti,mux-clock";
1457		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1458		ti,bit-shift = <24>;
1459		reg = <0x1020>;
1460	};
1461
1462	vip2_gclk_mux: vip2_gclk_mux@1028 {
1463		#clock-cells = <0>;
1464		compatible = "ti,mux-clock";
1465		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1466		ti,bit-shift = <24>;
1467		reg = <0x1028>;
1468	};
1469
1470	vip3_gclk_mux: vip3_gclk_mux@1030 {
1471		#clock-cells = <0>;
1472		compatible = "ti,mux-clock";
1473		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1474		ti,bit-shift = <24>;
1475		reg = <0x1030>;
1476	};
1477};
1478
1479&cm_core_clockdomains {
1480	coreaon_clkdm: coreaon_clkdm {
1481		compatible = "ti,clockdomain";
1482		clocks = <&dpll_usb_ck>;
1483	};
1484};
1485
1486&scm_conf_clocks {
1487	dss_deshdcp_clk: dss_deshdcp_clk@558 {
1488		#clock-cells = <0>;
1489		compatible = "ti,gate-clock";
1490		clocks = <&l3_iclk_div>;
1491		ti,bit-shift = <0>;
1492		reg = <0x558>;
1493	};
1494
1495       ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
1496		#clock-cells = <0>;
1497		compatible = "ti,gate-clock";
1498		clocks = <&l4_root_clk_div>;
1499		ti,bit-shift = <20>;
1500		reg = <0x0558>;
1501	};
1502
1503	ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
1504		#clock-cells = <0>;
1505		compatible = "ti,gate-clock";
1506		clocks = <&l4_root_clk_div>;
1507		ti,bit-shift = <21>;
1508		reg = <0x0558>;
1509	};
1510
1511	ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
1512		#clock-cells = <0>;
1513		compatible = "ti,gate-clock";
1514		clocks = <&l4_root_clk_div>;
1515		ti,bit-shift = <22>;
1516		reg = <0x0558>;
1517	};
1518
1519	sys_32k_ck: sys_32k_ck {
1520		#clock-cells = <0>;
1521		compatible = "ti,mux-clock";
1522		clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
1523		ti,bit-shift = <8>;
1524		reg = <0x6c4>;
1525	};
1526};
1527
1528&cm_core_aon {
1529	mpu_cm: mpu_cm@300 {
1530		compatible = "ti,omap4-cm";
1531		reg = <0x300 0x100>;
1532		#address-cells = <1>;
1533		#size-cells = <1>;
1534		ranges = <0 0x300 0x100>;
1535
1536		mpu_clkctrl: clk@20 {
1537			compatible = "ti,clkctrl";
1538			reg = <0x20 0x4>;
1539			#clock-cells = <2>;
1540		};
 
1541	};
1542
1543	ipu_cm: ipu_cm@500 {
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1544		compatible = "ti,omap4-cm";
1545		reg = <0x500 0x100>;
1546		#address-cells = <1>;
1547		#size-cells = <1>;
1548		ranges = <0 0x500 0x100>;
1549
1550		ipu_clkctrl: clk@40 {
1551			compatible = "ti,clkctrl";
1552			reg = <0x40 0x44>;
1553			#clock-cells = <2>;
1554		};
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1555	};
1556
1557	rtc_cm: rtc_cm@700 {
1558		compatible = "ti,omap4-cm";
1559		reg = <0x700 0x100>;
1560		#address-cells = <1>;
1561		#size-cells = <1>;
1562		ranges = <0 0x700 0x100>;
1563
1564		rtc_clkctrl: clk@40 {
1565			compatible = "ti,clkctrl";
1566			reg = <0x40 0x8>;
1567			#clock-cells = <2>;
1568		};
1569	};
1570
1571};
1572
1573&cm_core {
1574	coreaon_cm: coreaon_cm@600 {
1575		compatible = "ti,omap4-cm";
1576		reg = <0x600 0x100>;
1577		#address-cells = <1>;
1578		#size-cells = <1>;
1579		ranges = <0 0x600 0x100>;
1580
1581		coreaon_clkctrl: clk@20 {
1582			compatible = "ti,clkctrl";
1583			reg = <0x20 0x1c>;
1584			#clock-cells = <2>;
1585		};
1586	};
1587
1588	l3main1_cm: l3main1_cm@700 {
1589		compatible = "ti,omap4-cm";
1590		reg = <0x700 0x100>;
1591		#address-cells = <1>;
1592		#size-cells = <1>;
1593		ranges = <0 0x700 0x100>;
1594
1595		l3main1_clkctrl: clk@20 {
1596			compatible = "ti,clkctrl";
1597			reg = <0x20 0x74>;
1598			#clock-cells = <2>;
1599		};
 
1600	};
1601
1602	dma_cm: dma_cm@a00 {
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1603		compatible = "ti,omap4-cm";
1604		reg = <0xa00 0x100>;
1605		#address-cells = <1>;
1606		#size-cells = <1>;
1607		ranges = <0 0xa00 0x100>;
1608
1609		dma_clkctrl: clk@20 {
1610			compatible = "ti,clkctrl";
1611			reg = <0x20 0x4>;
1612			#clock-cells = <2>;
1613		};
1614	};
1615
1616	emif_cm: emif_cm@b00 {
1617		compatible = "ti,omap4-cm";
1618		reg = <0xb00 0x100>;
1619		#address-cells = <1>;
1620		#size-cells = <1>;
1621		ranges = <0 0xb00 0x100>;
1622
1623		emif_clkctrl: clk@20 {
1624			compatible = "ti,clkctrl";
1625			reg = <0x20 0x4>;
1626			#clock-cells = <2>;
1627		};
1628	};
1629
1630	atl_cm: atl_cm@c00 {
1631		compatible = "ti,omap4-cm";
1632		reg = <0xc00 0x100>;
1633		#address-cells = <1>;
1634		#size-cells = <1>;
1635		ranges = <0 0xc00 0x100>;
1636
1637		atl_clkctrl: clk@0 {
1638			compatible = "ti,clkctrl";
1639			reg = <0x0 0x4>;
1640			#clock-cells = <2>;
1641		};
1642	};
1643
1644	l4cfg_cm: l4cfg_cm@d00 {
1645		compatible = "ti,omap4-cm";
1646		reg = <0xd00 0x100>;
1647		#address-cells = <1>;
1648		#size-cells = <1>;
1649		ranges = <0 0xd00 0x100>;
1650
1651		l4cfg_clkctrl: clk@20 {
1652			compatible = "ti,clkctrl";
1653			reg = <0x20 0x84>;
1654			#clock-cells = <2>;
1655		};
1656	};
1657
1658	l3instr_cm: l3instr_cm@e00 {
1659		compatible = "ti,omap4-cm";
1660		reg = <0xe00 0x100>;
1661		#address-cells = <1>;
1662		#size-cells = <1>;
1663		ranges = <0 0xe00 0x100>;
1664
1665		l3instr_clkctrl: clk@20 {
1666			compatible = "ti,clkctrl";
1667			reg = <0x20 0xc>;
1668			#clock-cells = <2>;
1669		};
1670	};
1671
1672	dss_cm: dss_cm@1100 {
1673		compatible = "ti,omap4-cm";
1674		reg = <0x1100 0x100>;
1675		#address-cells = <1>;
1676		#size-cells = <1>;
1677		ranges = <0 0x1100 0x100>;
1678
1679		dss_clkctrl: clk@20 {
1680			compatible = "ti,clkctrl";
1681			reg = <0x20 0x14>;
1682			#clock-cells = <2>;
1683		};
1684	};
1685
1686	l3init_cm: l3init_cm@1300 {
1687		compatible = "ti,omap4-cm";
1688		reg = <0x1300 0x100>;
1689		#address-cells = <1>;
1690		#size-cells = <1>;
1691		ranges = <0 0x1300 0x100>;
1692
1693		l3init_clkctrl: clk@20 {
 
 
 
 
 
 
 
 
 
 
 
 
1694			compatible = "ti,clkctrl";
1695			reg = <0x20 0xd4>;
1696			#clock-cells = <2>;
1697		};
 
1698	};
1699
1700	l4per_cm: l4per_cm@1700 {
1701		compatible = "ti,omap4-cm";
1702		reg = <0x1700 0x300>;
1703		#address-cells = <1>;
1704		#size-cells = <1>;
1705		ranges = <0 0x1700 0x300>;
1706
1707		l4per_clkctrl: clk@0 {
1708			compatible = "ti,clkctrl";
1709			reg = <0x0 0x20c>;
1710			#clock-cells = <2>;
1711
1712			assigned-clocks = <&l4per_clkctrl DRA7_MCASP3_CLKCTRL 24>;
1713			assigned-clock-parents = <&abe_24m_fclk>;
1714		};
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
1715	};
1716
1717};
1718
1719&prm {
1720	wkupaon_cm: wkupaon_cm@1800 {
1721		compatible = "ti,omap4-cm";
1722		reg = <0x1800 0x100>;
1723		#address-cells = <1>;
1724		#size-cells = <1>;
1725		ranges = <0 0x1800 0x100>;
1726
1727		wkupaon_clkctrl: clk@20 {
1728			compatible = "ti,clkctrl";
1729			reg = <0x20 0x6c>;
1730			#clock-cells = <2>;
1731		};
1732	};
1733};
v5.4
   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Device Tree Source for DRA7xx clock data
   4 *
   5 * Copyright (C) 2013 Texas Instruments, Inc.
 
 
 
 
   6 */
   7&cm_core_aon_clocks {
   8	atl_clkin0_ck: atl_clkin0_ck {
   9		#clock-cells = <0>;
  10		compatible = "ti,dra7-atl-clock";
  11		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  12	};
  13
  14	atl_clkin1_ck: atl_clkin1_ck {
  15		#clock-cells = <0>;
  16		compatible = "ti,dra7-atl-clock";
  17		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  18	};
  19
  20	atl_clkin2_ck: atl_clkin2_ck {
  21		#clock-cells = <0>;
  22		compatible = "ti,dra7-atl-clock";
  23		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  24	};
  25
  26	atl_clkin3_ck: atl_clkin3_ck {
  27		#clock-cells = <0>;
  28		compatible = "ti,dra7-atl-clock";
  29		clocks = <&atl_clkctrl DRA7_ATL_ATL_CLKCTRL 26>;
  30	};
  31
  32	hdmi_clkin_ck: hdmi_clkin_ck {
  33		#clock-cells = <0>;
  34		compatible = "fixed-clock";
  35		clock-frequency = <0>;
  36	};
  37
  38	mlb_clkin_ck: mlb_clkin_ck {
  39		#clock-cells = <0>;
  40		compatible = "fixed-clock";
  41		clock-frequency = <0>;
  42	};
  43
  44	mlbp_clkin_ck: mlbp_clkin_ck {
  45		#clock-cells = <0>;
  46		compatible = "fixed-clock";
  47		clock-frequency = <0>;
  48	};
  49
  50	pciesref_acs_clk_ck: pciesref_acs_clk_ck {
  51		#clock-cells = <0>;
  52		compatible = "fixed-clock";
  53		clock-frequency = <100000000>;
  54	};
  55
  56	ref_clkin0_ck: ref_clkin0_ck {
  57		#clock-cells = <0>;
  58		compatible = "fixed-clock";
  59		clock-frequency = <0>;
  60	};
  61
  62	ref_clkin1_ck: ref_clkin1_ck {
  63		#clock-cells = <0>;
  64		compatible = "fixed-clock";
  65		clock-frequency = <0>;
  66	};
  67
  68	ref_clkin2_ck: ref_clkin2_ck {
  69		#clock-cells = <0>;
  70		compatible = "fixed-clock";
  71		clock-frequency = <0>;
  72	};
  73
  74	ref_clkin3_ck: ref_clkin3_ck {
  75		#clock-cells = <0>;
  76		compatible = "fixed-clock";
  77		clock-frequency = <0>;
  78	};
  79
  80	rmii_clk_ck: rmii_clk_ck {
  81		#clock-cells = <0>;
  82		compatible = "fixed-clock";
  83		clock-frequency = <0>;
  84	};
  85
  86	sdvenc_clkin_ck: sdvenc_clkin_ck {
  87		#clock-cells = <0>;
  88		compatible = "fixed-clock";
  89		clock-frequency = <0>;
  90	};
  91
  92	secure_32k_clk_src_ck: secure_32k_clk_src_ck {
  93		#clock-cells = <0>;
  94		compatible = "fixed-clock";
  95		clock-frequency = <32768>;
  96	};
  97
  98	sys_clk32_crystal_ck: sys_clk32_crystal_ck {
  99		#clock-cells = <0>;
 100		compatible = "fixed-clock";
 101		clock-frequency = <32768>;
 102	};
 103
 104	sys_clk32_pseudo_ck: sys_clk32_pseudo_ck {
 105		#clock-cells = <0>;
 106		compatible = "fixed-factor-clock";
 107		clocks = <&sys_clkin1>;
 108		clock-mult = <1>;
 109		clock-div = <610>;
 110	};
 111
 112	virt_12000000_ck: virt_12000000_ck {
 113		#clock-cells = <0>;
 114		compatible = "fixed-clock";
 115		clock-frequency = <12000000>;
 116	};
 117
 118	virt_13000000_ck: virt_13000000_ck {
 119		#clock-cells = <0>;
 120		compatible = "fixed-clock";
 121		clock-frequency = <13000000>;
 122	};
 123
 124	virt_16800000_ck: virt_16800000_ck {
 125		#clock-cells = <0>;
 126		compatible = "fixed-clock";
 127		clock-frequency = <16800000>;
 128	};
 129
 130	virt_19200000_ck: virt_19200000_ck {
 131		#clock-cells = <0>;
 132		compatible = "fixed-clock";
 133		clock-frequency = <19200000>;
 134	};
 135
 136	virt_20000000_ck: virt_20000000_ck {
 137		#clock-cells = <0>;
 138		compatible = "fixed-clock";
 139		clock-frequency = <20000000>;
 140	};
 141
 142	virt_26000000_ck: virt_26000000_ck {
 143		#clock-cells = <0>;
 144		compatible = "fixed-clock";
 145		clock-frequency = <26000000>;
 146	};
 147
 148	virt_27000000_ck: virt_27000000_ck {
 149		#clock-cells = <0>;
 150		compatible = "fixed-clock";
 151		clock-frequency = <27000000>;
 152	};
 153
 154	virt_38400000_ck: virt_38400000_ck {
 155		#clock-cells = <0>;
 156		compatible = "fixed-clock";
 157		clock-frequency = <38400000>;
 158	};
 159
 160	sys_clkin2: sys_clkin2 {
 161		#clock-cells = <0>;
 162		compatible = "fixed-clock";
 163		clock-frequency = <22579200>;
 164	};
 165
 166	usb_otg_clkin_ck: usb_otg_clkin_ck {
 167		#clock-cells = <0>;
 168		compatible = "fixed-clock";
 169		clock-frequency = <0>;
 170	};
 171
 172	video1_clkin_ck: video1_clkin_ck {
 173		#clock-cells = <0>;
 174		compatible = "fixed-clock";
 175		clock-frequency = <0>;
 176	};
 177
 178	video1_m2_clkin_ck: video1_m2_clkin_ck {
 179		#clock-cells = <0>;
 180		compatible = "fixed-clock";
 181		clock-frequency = <0>;
 182	};
 183
 184	video2_clkin_ck: video2_clkin_ck {
 185		#clock-cells = <0>;
 186		compatible = "fixed-clock";
 187		clock-frequency = <0>;
 188	};
 189
 190	video2_m2_clkin_ck: video2_m2_clkin_ck {
 191		#clock-cells = <0>;
 192		compatible = "fixed-clock";
 193		clock-frequency = <0>;
 194	};
 195
 196	dpll_abe_ck: dpll_abe_ck@1e0 {
 197		#clock-cells = <0>;
 198		compatible = "ti,omap4-dpll-m4xen-clock";
 199		clocks = <&abe_dpll_clk_mux>, <&abe_dpll_bypass_clk_mux>;
 200		reg = <0x01e0>, <0x01e4>, <0x01ec>, <0x01e8>;
 201	};
 202
 203	dpll_abe_x2_ck: dpll_abe_x2_ck {
 204		#clock-cells = <0>;
 205		compatible = "ti,omap4-dpll-x2-clock";
 206		clocks = <&dpll_abe_ck>;
 207	};
 208
 209	dpll_abe_m2x2_ck: dpll_abe_m2x2_ck@1f0 {
 210		#clock-cells = <0>;
 211		compatible = "ti,divider-clock";
 212		clocks = <&dpll_abe_x2_ck>;
 213		ti,max-div = <31>;
 214		ti,autoidle-shift = <8>;
 215		reg = <0x01f0>;
 216		ti,index-starts-at-one;
 217		ti,invert-autoidle-bit;
 218	};
 219
 220	abe_clk: abe_clk@108 {
 221		#clock-cells = <0>;
 222		compatible = "ti,divider-clock";
 223		clocks = <&dpll_abe_m2x2_ck>;
 224		ti,max-div = <4>;
 225		reg = <0x0108>;
 226		ti,index-power-of-two;
 227	};
 228
 229	dpll_abe_m2_ck: dpll_abe_m2_ck@1f0 {
 230		#clock-cells = <0>;
 231		compatible = "ti,divider-clock";
 232		clocks = <&dpll_abe_ck>;
 233		ti,max-div = <31>;
 234		ti,autoidle-shift = <8>;
 235		reg = <0x01f0>;
 236		ti,index-starts-at-one;
 237		ti,invert-autoidle-bit;
 238	};
 239
 240	dpll_abe_m3x2_ck: dpll_abe_m3x2_ck@1f4 {
 241		#clock-cells = <0>;
 242		compatible = "ti,divider-clock";
 243		clocks = <&dpll_abe_x2_ck>;
 244		ti,max-div = <31>;
 245		ti,autoidle-shift = <8>;
 246		reg = <0x01f4>;
 247		ti,index-starts-at-one;
 248		ti,invert-autoidle-bit;
 249	};
 250
 251	dpll_core_byp_mux: dpll_core_byp_mux@12c {
 252		#clock-cells = <0>;
 253		compatible = "ti,mux-clock";
 254		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 255		ti,bit-shift = <23>;
 256		reg = <0x012c>;
 257	};
 258
 259	dpll_core_ck: dpll_core_ck@120 {
 260		#clock-cells = <0>;
 261		compatible = "ti,omap4-dpll-core-clock";
 262		clocks = <&sys_clkin1>, <&dpll_core_byp_mux>;
 263		reg = <0x0120>, <0x0124>, <0x012c>, <0x0128>;
 264	};
 265
 266	dpll_core_x2_ck: dpll_core_x2_ck {
 267		#clock-cells = <0>;
 268		compatible = "ti,omap4-dpll-x2-clock";
 269		clocks = <&dpll_core_ck>;
 270	};
 271
 272	dpll_core_h12x2_ck: dpll_core_h12x2_ck@13c {
 273		#clock-cells = <0>;
 274		compatible = "ti,divider-clock";
 275		clocks = <&dpll_core_x2_ck>;
 276		ti,max-div = <63>;
 277		ti,autoidle-shift = <8>;
 278		reg = <0x013c>;
 279		ti,index-starts-at-one;
 280		ti,invert-autoidle-bit;
 281	};
 282
 283	mpu_dpll_hs_clk_div: mpu_dpll_hs_clk_div {
 284		#clock-cells = <0>;
 285		compatible = "fixed-factor-clock";
 286		clocks = <&dpll_core_h12x2_ck>;
 287		clock-mult = <1>;
 288		clock-div = <1>;
 289	};
 290
 291	dpll_mpu_ck: dpll_mpu_ck@160 {
 292		#clock-cells = <0>;
 293		compatible = "ti,omap5-mpu-dpll-clock";
 294		clocks = <&sys_clkin1>, <&mpu_dpll_hs_clk_div>;
 295		reg = <0x0160>, <0x0164>, <0x016c>, <0x0168>;
 296	};
 297
 298	dpll_mpu_m2_ck: dpll_mpu_m2_ck@170 {
 299		#clock-cells = <0>;
 300		compatible = "ti,divider-clock";
 301		clocks = <&dpll_mpu_ck>;
 302		ti,max-div = <31>;
 303		ti,autoidle-shift = <8>;
 304		reg = <0x0170>;
 305		ti,index-starts-at-one;
 306		ti,invert-autoidle-bit;
 307	};
 308
 309	mpu_dclk_div: mpu_dclk_div {
 310		#clock-cells = <0>;
 311		compatible = "fixed-factor-clock";
 312		clocks = <&dpll_mpu_m2_ck>;
 313		clock-mult = <1>;
 314		clock-div = <1>;
 315	};
 316
 317	dsp_dpll_hs_clk_div: dsp_dpll_hs_clk_div {
 318		#clock-cells = <0>;
 319		compatible = "fixed-factor-clock";
 320		clocks = <&dpll_core_h12x2_ck>;
 321		clock-mult = <1>;
 322		clock-div = <1>;
 323	};
 324
 325	dpll_dsp_byp_mux: dpll_dsp_byp_mux@240 {
 326		#clock-cells = <0>;
 327		compatible = "ti,mux-clock";
 328		clocks = <&sys_clkin1>, <&dsp_dpll_hs_clk_div>;
 329		ti,bit-shift = <23>;
 330		reg = <0x0240>;
 331	};
 332
 333	dpll_dsp_ck: dpll_dsp_ck@234 {
 334		#clock-cells = <0>;
 335		compatible = "ti,omap4-dpll-clock";
 336		clocks = <&sys_clkin1>, <&dpll_dsp_byp_mux>;
 337		reg = <0x0234>, <0x0238>, <0x0240>, <0x023c>;
 338		assigned-clocks = <&dpll_dsp_ck>;
 339		assigned-clock-rates = <600000000>;
 340	};
 341
 342	dpll_dsp_m2_ck: dpll_dsp_m2_ck@244 {
 343		#clock-cells = <0>;
 344		compatible = "ti,divider-clock";
 345		clocks = <&dpll_dsp_ck>;
 346		ti,max-div = <31>;
 347		ti,autoidle-shift = <8>;
 348		reg = <0x0244>;
 349		ti,index-starts-at-one;
 350		ti,invert-autoidle-bit;
 351		assigned-clocks = <&dpll_dsp_m2_ck>;
 352		assigned-clock-rates = <600000000>;
 353	};
 354
 355	iva_dpll_hs_clk_div: iva_dpll_hs_clk_div {
 356		#clock-cells = <0>;
 357		compatible = "fixed-factor-clock";
 358		clocks = <&dpll_core_h12x2_ck>;
 359		clock-mult = <1>;
 360		clock-div = <1>;
 361	};
 362
 363	dpll_iva_byp_mux: dpll_iva_byp_mux@1ac {
 364		#clock-cells = <0>;
 365		compatible = "ti,mux-clock";
 366		clocks = <&sys_clkin1>, <&iva_dpll_hs_clk_div>;
 367		ti,bit-shift = <23>;
 368		reg = <0x01ac>;
 369	};
 370
 371	dpll_iva_ck: dpll_iva_ck@1a0 {
 372		#clock-cells = <0>;
 373		compatible = "ti,omap4-dpll-clock";
 374		clocks = <&sys_clkin1>, <&dpll_iva_byp_mux>;
 375		reg = <0x01a0>, <0x01a4>, <0x01ac>, <0x01a8>;
 376		assigned-clocks = <&dpll_iva_ck>;
 377		assigned-clock-rates = <1165000000>;
 378	};
 379
 380	dpll_iva_m2_ck: dpll_iva_m2_ck@1b0 {
 381		#clock-cells = <0>;
 382		compatible = "ti,divider-clock";
 383		clocks = <&dpll_iva_ck>;
 384		ti,max-div = <31>;
 385		ti,autoidle-shift = <8>;
 386		reg = <0x01b0>;
 387		ti,index-starts-at-one;
 388		ti,invert-autoidle-bit;
 389		assigned-clocks = <&dpll_iva_m2_ck>;
 390		assigned-clock-rates = <388333334>;
 391	};
 392
 393	iva_dclk: iva_dclk {
 394		#clock-cells = <0>;
 395		compatible = "fixed-factor-clock";
 396		clocks = <&dpll_iva_m2_ck>;
 397		clock-mult = <1>;
 398		clock-div = <1>;
 399	};
 400
 401	dpll_gpu_byp_mux: dpll_gpu_byp_mux@2e4 {
 402		#clock-cells = <0>;
 403		compatible = "ti,mux-clock";
 404		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 405		ti,bit-shift = <23>;
 406		reg = <0x02e4>;
 407	};
 408
 409	dpll_gpu_ck: dpll_gpu_ck@2d8 {
 410		#clock-cells = <0>;
 411		compatible = "ti,omap4-dpll-clock";
 412		clocks = <&sys_clkin1>, <&dpll_gpu_byp_mux>;
 413		reg = <0x02d8>, <0x02dc>, <0x02e4>, <0x02e0>;
 414		assigned-clocks = <&dpll_gpu_ck>;
 415		assigned-clock-rates = <1277000000>;
 416	};
 417
 418	dpll_gpu_m2_ck: dpll_gpu_m2_ck@2e8 {
 419		#clock-cells = <0>;
 420		compatible = "ti,divider-clock";
 421		clocks = <&dpll_gpu_ck>;
 422		ti,max-div = <31>;
 423		ti,autoidle-shift = <8>;
 424		reg = <0x02e8>;
 425		ti,index-starts-at-one;
 426		ti,invert-autoidle-bit;
 427		assigned-clocks = <&dpll_gpu_m2_ck>;
 428		assigned-clock-rates = <425666667>;
 429	};
 430
 431	dpll_core_m2_ck: dpll_core_m2_ck@130 {
 432		#clock-cells = <0>;
 433		compatible = "ti,divider-clock";
 434		clocks = <&dpll_core_ck>;
 435		ti,max-div = <31>;
 436		ti,autoidle-shift = <8>;
 437		reg = <0x0130>;
 438		ti,index-starts-at-one;
 439		ti,invert-autoidle-bit;
 440	};
 441
 442	core_dpll_out_dclk_div: core_dpll_out_dclk_div {
 443		#clock-cells = <0>;
 444		compatible = "fixed-factor-clock";
 445		clocks = <&dpll_core_m2_ck>;
 446		clock-mult = <1>;
 447		clock-div = <1>;
 448	};
 449
 450	dpll_ddr_byp_mux: dpll_ddr_byp_mux@21c {
 451		#clock-cells = <0>;
 452		compatible = "ti,mux-clock";
 453		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 454		ti,bit-shift = <23>;
 455		reg = <0x021c>;
 456	};
 457
 458	dpll_ddr_ck: dpll_ddr_ck@210 {
 459		#clock-cells = <0>;
 460		compatible = "ti,omap4-dpll-clock";
 461		clocks = <&sys_clkin1>, <&dpll_ddr_byp_mux>;
 462		reg = <0x0210>, <0x0214>, <0x021c>, <0x0218>;
 463	};
 464
 465	dpll_ddr_m2_ck: dpll_ddr_m2_ck@220 {
 466		#clock-cells = <0>;
 467		compatible = "ti,divider-clock";
 468		clocks = <&dpll_ddr_ck>;
 469		ti,max-div = <31>;
 470		ti,autoidle-shift = <8>;
 471		reg = <0x0220>;
 472		ti,index-starts-at-one;
 473		ti,invert-autoidle-bit;
 474	};
 475
 476	dpll_gmac_byp_mux: dpll_gmac_byp_mux@2b4 {
 477		#clock-cells = <0>;
 478		compatible = "ti,mux-clock";
 479		clocks = <&sys_clkin1>, <&dpll_abe_m3x2_ck>;
 480		ti,bit-shift = <23>;
 481		reg = <0x02b4>;
 482	};
 483
 484	dpll_gmac_ck: dpll_gmac_ck@2a8 {
 485		#clock-cells = <0>;
 486		compatible = "ti,omap4-dpll-clock";
 487		clocks = <&sys_clkin1>, <&dpll_gmac_byp_mux>;
 488		reg = <0x02a8>, <0x02ac>, <0x02b4>, <0x02b0>;
 489	};
 490
 491	dpll_gmac_m2_ck: dpll_gmac_m2_ck@2b8 {
 492		#clock-cells = <0>;
 493		compatible = "ti,divider-clock";
 494		clocks = <&dpll_gmac_ck>;
 495		ti,max-div = <31>;
 496		ti,autoidle-shift = <8>;
 497		reg = <0x02b8>;
 498		ti,index-starts-at-one;
 499		ti,invert-autoidle-bit;
 500	};
 501
 502	video2_dclk_div: video2_dclk_div {
 503		#clock-cells = <0>;
 504		compatible = "fixed-factor-clock";
 505		clocks = <&video2_m2_clkin_ck>;
 506		clock-mult = <1>;
 507		clock-div = <1>;
 508	};
 509
 510	video1_dclk_div: video1_dclk_div {
 511		#clock-cells = <0>;
 512		compatible = "fixed-factor-clock";
 513		clocks = <&video1_m2_clkin_ck>;
 514		clock-mult = <1>;
 515		clock-div = <1>;
 516	};
 517
 518	hdmi_dclk_div: hdmi_dclk_div {
 519		#clock-cells = <0>;
 520		compatible = "fixed-factor-clock";
 521		clocks = <&hdmi_clkin_ck>;
 522		clock-mult = <1>;
 523		clock-div = <1>;
 524	};
 525
 526	per_dpll_hs_clk_div: per_dpll_hs_clk_div {
 527		#clock-cells = <0>;
 528		compatible = "fixed-factor-clock";
 529		clocks = <&dpll_abe_m3x2_ck>;
 530		clock-mult = <1>;
 531		clock-div = <2>;
 532	};
 533
 534	usb_dpll_hs_clk_div: usb_dpll_hs_clk_div {
 535		#clock-cells = <0>;
 536		compatible = "fixed-factor-clock";
 537		clocks = <&dpll_abe_m3x2_ck>;
 538		clock-mult = <1>;
 539		clock-div = <3>;
 540	};
 541
 542	eve_dpll_hs_clk_div: eve_dpll_hs_clk_div {
 543		#clock-cells = <0>;
 544		compatible = "fixed-factor-clock";
 545		clocks = <&dpll_core_h12x2_ck>;
 546		clock-mult = <1>;
 547		clock-div = <1>;
 548	};
 549
 550	dpll_eve_byp_mux: dpll_eve_byp_mux@290 {
 551		#clock-cells = <0>;
 552		compatible = "ti,mux-clock";
 553		clocks = <&sys_clkin1>, <&eve_dpll_hs_clk_div>;
 554		ti,bit-shift = <23>;
 555		reg = <0x0290>;
 556	};
 557
 558	dpll_eve_ck: dpll_eve_ck@284 {
 559		#clock-cells = <0>;
 560		compatible = "ti,omap4-dpll-clock";
 561		clocks = <&sys_clkin1>, <&dpll_eve_byp_mux>;
 562		reg = <0x0284>, <0x0288>, <0x0290>, <0x028c>;
 563	};
 564
 565	dpll_eve_m2_ck: dpll_eve_m2_ck@294 {
 566		#clock-cells = <0>;
 567		compatible = "ti,divider-clock";
 568		clocks = <&dpll_eve_ck>;
 569		ti,max-div = <31>;
 570		ti,autoidle-shift = <8>;
 571		reg = <0x0294>;
 572		ti,index-starts-at-one;
 573		ti,invert-autoidle-bit;
 574	};
 575
 576	eve_dclk_div: eve_dclk_div {
 577		#clock-cells = <0>;
 578		compatible = "fixed-factor-clock";
 579		clocks = <&dpll_eve_m2_ck>;
 580		clock-mult = <1>;
 581		clock-div = <1>;
 582	};
 583
 584	dpll_core_h13x2_ck: dpll_core_h13x2_ck@140 {
 585		#clock-cells = <0>;
 586		compatible = "ti,divider-clock";
 587		clocks = <&dpll_core_x2_ck>;
 588		ti,max-div = <63>;
 589		ti,autoidle-shift = <8>;
 590		reg = <0x0140>;
 591		ti,index-starts-at-one;
 592		ti,invert-autoidle-bit;
 593	};
 594
 595	dpll_core_h14x2_ck: dpll_core_h14x2_ck@144 {
 596		#clock-cells = <0>;
 597		compatible = "ti,divider-clock";
 598		clocks = <&dpll_core_x2_ck>;
 599		ti,max-div = <63>;
 600		ti,autoidle-shift = <8>;
 601		reg = <0x0144>;
 602		ti,index-starts-at-one;
 603		ti,invert-autoidle-bit;
 604	};
 605
 606	dpll_core_h22x2_ck: dpll_core_h22x2_ck@154 {
 607		#clock-cells = <0>;
 608		compatible = "ti,divider-clock";
 609		clocks = <&dpll_core_x2_ck>;
 610		ti,max-div = <63>;
 611		ti,autoidle-shift = <8>;
 612		reg = <0x0154>;
 613		ti,index-starts-at-one;
 614		ti,invert-autoidle-bit;
 615	};
 616
 617	dpll_core_h23x2_ck: dpll_core_h23x2_ck@158 {
 618		#clock-cells = <0>;
 619		compatible = "ti,divider-clock";
 620		clocks = <&dpll_core_x2_ck>;
 621		ti,max-div = <63>;
 622		ti,autoidle-shift = <8>;
 623		reg = <0x0158>;
 624		ti,index-starts-at-one;
 625		ti,invert-autoidle-bit;
 626	};
 627
 628	dpll_core_h24x2_ck: dpll_core_h24x2_ck@15c {
 629		#clock-cells = <0>;
 630		compatible = "ti,divider-clock";
 631		clocks = <&dpll_core_x2_ck>;
 632		ti,max-div = <63>;
 633		ti,autoidle-shift = <8>;
 634		reg = <0x015c>;
 635		ti,index-starts-at-one;
 636		ti,invert-autoidle-bit;
 637	};
 638
 639	dpll_ddr_x2_ck: dpll_ddr_x2_ck {
 640		#clock-cells = <0>;
 641		compatible = "ti,omap4-dpll-x2-clock";
 642		clocks = <&dpll_ddr_ck>;
 643	};
 644
 645	dpll_ddr_h11x2_ck: dpll_ddr_h11x2_ck@228 {
 646		#clock-cells = <0>;
 647		compatible = "ti,divider-clock";
 648		clocks = <&dpll_ddr_x2_ck>;
 649		ti,max-div = <63>;
 650		ti,autoidle-shift = <8>;
 651		reg = <0x0228>;
 652		ti,index-starts-at-one;
 653		ti,invert-autoidle-bit;
 654	};
 655
 656	dpll_dsp_x2_ck: dpll_dsp_x2_ck {
 657		#clock-cells = <0>;
 658		compatible = "ti,omap4-dpll-x2-clock";
 659		clocks = <&dpll_dsp_ck>;
 660	};
 661
 662	dpll_dsp_m3x2_ck: dpll_dsp_m3x2_ck@248 {
 663		#clock-cells = <0>;
 664		compatible = "ti,divider-clock";
 665		clocks = <&dpll_dsp_x2_ck>;
 666		ti,max-div = <31>;
 667		ti,autoidle-shift = <8>;
 668		reg = <0x0248>;
 669		ti,index-starts-at-one;
 670		ti,invert-autoidle-bit;
 671		assigned-clocks = <&dpll_dsp_m3x2_ck>;
 672		assigned-clock-rates = <400000000>;
 673	};
 674
 675	dpll_gmac_x2_ck: dpll_gmac_x2_ck {
 676		#clock-cells = <0>;
 677		compatible = "ti,omap4-dpll-x2-clock";
 678		clocks = <&dpll_gmac_ck>;
 679	};
 680
 681	dpll_gmac_h11x2_ck: dpll_gmac_h11x2_ck@2c0 {
 682		#clock-cells = <0>;
 683		compatible = "ti,divider-clock";
 684		clocks = <&dpll_gmac_x2_ck>;
 685		ti,max-div = <63>;
 686		ti,autoidle-shift = <8>;
 687		reg = <0x02c0>;
 688		ti,index-starts-at-one;
 689		ti,invert-autoidle-bit;
 690	};
 691
 692	dpll_gmac_h12x2_ck: dpll_gmac_h12x2_ck@2c4 {
 693		#clock-cells = <0>;
 694		compatible = "ti,divider-clock";
 695		clocks = <&dpll_gmac_x2_ck>;
 696		ti,max-div = <63>;
 697		ti,autoidle-shift = <8>;
 698		reg = <0x02c4>;
 699		ti,index-starts-at-one;
 700		ti,invert-autoidle-bit;
 701	};
 702
 703	dpll_gmac_h13x2_ck: dpll_gmac_h13x2_ck@2c8 {
 704		#clock-cells = <0>;
 705		compatible = "ti,divider-clock";
 706		clocks = <&dpll_gmac_x2_ck>;
 707		ti,max-div = <63>;
 708		ti,autoidle-shift = <8>;
 709		reg = <0x02c8>;
 710		ti,index-starts-at-one;
 711		ti,invert-autoidle-bit;
 712	};
 713
 714	dpll_gmac_m3x2_ck: dpll_gmac_m3x2_ck@2bc {
 715		#clock-cells = <0>;
 716		compatible = "ti,divider-clock";
 717		clocks = <&dpll_gmac_x2_ck>;
 718		ti,max-div = <31>;
 719		ti,autoidle-shift = <8>;
 720		reg = <0x02bc>;
 721		ti,index-starts-at-one;
 722		ti,invert-autoidle-bit;
 723	};
 724
 725	gmii_m_clk_div: gmii_m_clk_div {
 726		#clock-cells = <0>;
 727		compatible = "fixed-factor-clock";
 728		clocks = <&dpll_gmac_h11x2_ck>;
 729		clock-mult = <1>;
 730		clock-div = <2>;
 731	};
 732
 733	hdmi_clk2_div: hdmi_clk2_div {
 734		#clock-cells = <0>;
 735		compatible = "fixed-factor-clock";
 736		clocks = <&hdmi_clkin_ck>;
 737		clock-mult = <1>;
 738		clock-div = <1>;
 739	};
 740
 741	hdmi_div_clk: hdmi_div_clk {
 742		#clock-cells = <0>;
 743		compatible = "fixed-factor-clock";
 744		clocks = <&hdmi_clkin_ck>;
 745		clock-mult = <1>;
 746		clock-div = <1>;
 747	};
 748
 749	l3_iclk_div: l3_iclk_div@100 {
 750		#clock-cells = <0>;
 751		compatible = "ti,divider-clock";
 752		ti,max-div = <2>;
 753		ti,bit-shift = <4>;
 754		reg = <0x0100>;
 755		clocks = <&dpll_core_h12x2_ck>;
 756		ti,index-power-of-two;
 757	};
 758
 759	l4_root_clk_div: l4_root_clk_div {
 760		#clock-cells = <0>;
 761		compatible = "fixed-factor-clock";
 762		clocks = <&l3_iclk_div>;
 763		clock-mult = <1>;
 764		clock-div = <2>;
 765	};
 766
 767	video1_clk2_div: video1_clk2_div {
 768		#clock-cells = <0>;
 769		compatible = "fixed-factor-clock";
 770		clocks = <&video1_clkin_ck>;
 771		clock-mult = <1>;
 772		clock-div = <1>;
 773	};
 774
 775	video1_div_clk: video1_div_clk {
 776		#clock-cells = <0>;
 777		compatible = "fixed-factor-clock";
 778		clocks = <&video1_clkin_ck>;
 779		clock-mult = <1>;
 780		clock-div = <1>;
 781	};
 782
 783	video2_clk2_div: video2_clk2_div {
 784		#clock-cells = <0>;
 785		compatible = "fixed-factor-clock";
 786		clocks = <&video2_clkin_ck>;
 787		clock-mult = <1>;
 788		clock-div = <1>;
 789	};
 790
 791	video2_div_clk: video2_div_clk {
 792		#clock-cells = <0>;
 793		compatible = "fixed-factor-clock";
 794		clocks = <&video2_clkin_ck>;
 795		clock-mult = <1>;
 796		clock-div = <1>;
 797	};
 798
 799	ipu1_gfclk_mux: ipu1_gfclk_mux@520 {
 800		#clock-cells = <0>;
 801		compatible = "ti,mux-clock";
 802		clocks = <&dpll_abe_m2x2_ck>, <&dpll_core_h22x2_ck>;
 803		ti,bit-shift = <24>;
 804		reg = <0x0520>;
 805		assigned-clocks = <&ipu1_gfclk_mux>;
 806		assigned-clock-parents = <&dpll_core_h22x2_ck>;
 807	};
 808
 809	dummy_ck: dummy_ck {
 810		#clock-cells = <0>;
 811		compatible = "fixed-clock";
 812		clock-frequency = <0>;
 813	};
 814};
 815&prm_clocks {
 816	sys_clkin1: sys_clkin1@110 {
 817		#clock-cells = <0>;
 818		compatible = "ti,mux-clock";
 819		clocks = <&virt_12000000_ck>, <&virt_20000000_ck>, <&virt_16800000_ck>, <&virt_19200000_ck>, <&virt_26000000_ck>, <&virt_27000000_ck>, <&virt_38400000_ck>;
 820		reg = <0x0110>;
 821		ti,index-starts-at-one;
 822	};
 823
 824	abe_dpll_sys_clk_mux: abe_dpll_sys_clk_mux@118 {
 825		#clock-cells = <0>;
 826		compatible = "ti,mux-clock";
 827		clocks = <&sys_clkin1>, <&sys_clkin2>;
 828		reg = <0x0118>;
 829	};
 830
 831	abe_dpll_bypass_clk_mux: abe_dpll_bypass_clk_mux@114 {
 832		#clock-cells = <0>;
 833		compatible = "ti,mux-clock";
 834		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 835		reg = <0x0114>;
 836	};
 837
 838	abe_dpll_clk_mux: abe_dpll_clk_mux@10c {
 839		#clock-cells = <0>;
 840		compatible = "ti,mux-clock";
 841		clocks = <&abe_dpll_sys_clk_mux>, <&sys_32k_ck>;
 842		reg = <0x010c>;
 843	};
 844
 845	abe_24m_fclk: abe_24m_fclk@11c {
 846		#clock-cells = <0>;
 847		compatible = "ti,divider-clock";
 848		clocks = <&dpll_abe_m2x2_ck>;
 849		reg = <0x011c>;
 850		ti,dividers = <8>, <16>;
 851	};
 852
 853	aess_fclk: aess_fclk@178 {
 854		#clock-cells = <0>;
 855		compatible = "ti,divider-clock";
 856		clocks = <&abe_clk>;
 857		reg = <0x0178>;
 858		ti,max-div = <2>;
 859	};
 860
 861	abe_giclk_div: abe_giclk_div@174 {
 862		#clock-cells = <0>;
 863		compatible = "ti,divider-clock";
 864		clocks = <&aess_fclk>;
 865		reg = <0x0174>;
 866		ti,max-div = <2>;
 867	};
 868
 869	abe_lp_clk_div: abe_lp_clk_div@1d8 {
 870		#clock-cells = <0>;
 871		compatible = "ti,divider-clock";
 872		clocks = <&dpll_abe_m2x2_ck>;
 873		reg = <0x01d8>;
 874		ti,dividers = <16>, <32>;
 875	};
 876
 877	abe_sys_clk_div: abe_sys_clk_div@120 {
 878		#clock-cells = <0>;
 879		compatible = "ti,divider-clock";
 880		clocks = <&sys_clkin1>;
 881		reg = <0x0120>;
 882		ti,max-div = <2>;
 883	};
 884
 885	adc_gfclk_mux: adc_gfclk_mux@1dc {
 886		#clock-cells = <0>;
 887		compatible = "ti,mux-clock";
 888		clocks = <&sys_clkin1>, <&sys_clkin2>, <&sys_32k_ck>;
 889		reg = <0x01dc>;
 890	};
 891
 892	sys_clk1_dclk_div: sys_clk1_dclk_div@1c8 {
 893		#clock-cells = <0>;
 894		compatible = "ti,divider-clock";
 895		clocks = <&sys_clkin1>;
 896		ti,max-div = <64>;
 897		reg = <0x01c8>;
 898		ti,index-power-of-two;
 899	};
 900
 901	sys_clk2_dclk_div: sys_clk2_dclk_div@1cc {
 902		#clock-cells = <0>;
 903		compatible = "ti,divider-clock";
 904		clocks = <&sys_clkin2>;
 905		ti,max-div = <64>;
 906		reg = <0x01cc>;
 907		ti,index-power-of-two;
 908	};
 909
 910	per_abe_x1_dclk_div: per_abe_x1_dclk_div@1bc {
 911		#clock-cells = <0>;
 912		compatible = "ti,divider-clock";
 913		clocks = <&dpll_abe_m2_ck>;
 914		ti,max-div = <64>;
 915		reg = <0x01bc>;
 916		ti,index-power-of-two;
 917	};
 918
 919	dsp_gclk_div: dsp_gclk_div@18c {
 920		#clock-cells = <0>;
 921		compatible = "ti,divider-clock";
 922		clocks = <&dpll_dsp_m2_ck>;
 923		ti,max-div = <64>;
 924		reg = <0x018c>;
 925		ti,index-power-of-two;
 926	};
 927
 928	gpu_dclk: gpu_dclk@1a0 {
 929		#clock-cells = <0>;
 930		compatible = "ti,divider-clock";
 931		clocks = <&dpll_gpu_m2_ck>;
 932		ti,max-div = <64>;
 933		reg = <0x01a0>;
 934		ti,index-power-of-two;
 935	};
 936
 937	emif_phy_dclk_div: emif_phy_dclk_div@190 {
 938		#clock-cells = <0>;
 939		compatible = "ti,divider-clock";
 940		clocks = <&dpll_ddr_m2_ck>;
 941		ti,max-div = <64>;
 942		reg = <0x0190>;
 943		ti,index-power-of-two;
 944	};
 945
 946	gmac_250m_dclk_div: gmac_250m_dclk_div@19c {
 947		#clock-cells = <0>;
 948		compatible = "ti,divider-clock";
 949		clocks = <&dpll_gmac_m2_ck>;
 950		ti,max-div = <64>;
 951		reg = <0x019c>;
 952		ti,index-power-of-two;
 953	};
 954
 955	gmac_main_clk: gmac_main_clk {
 956		#clock-cells = <0>;
 957		compatible = "fixed-factor-clock";
 958		clocks = <&gmac_250m_dclk_div>;
 959		clock-mult = <1>;
 960		clock-div = <2>;
 961	};
 962
 963	l3init_480m_dclk_div: l3init_480m_dclk_div@1ac {
 964		#clock-cells = <0>;
 965		compatible = "ti,divider-clock";
 966		clocks = <&dpll_usb_m2_ck>;
 967		ti,max-div = <64>;
 968		reg = <0x01ac>;
 969		ti,index-power-of-two;
 970	};
 971
 972	usb_otg_dclk_div: usb_otg_dclk_div@184 {
 973		#clock-cells = <0>;
 974		compatible = "ti,divider-clock";
 975		clocks = <&usb_otg_clkin_ck>;
 976		ti,max-div = <64>;
 977		reg = <0x0184>;
 978		ti,index-power-of-two;
 979	};
 980
 981	sata_dclk_div: sata_dclk_div@1c0 {
 982		#clock-cells = <0>;
 983		compatible = "ti,divider-clock";
 984		clocks = <&sys_clkin1>;
 985		ti,max-div = <64>;
 986		reg = <0x01c0>;
 987		ti,index-power-of-two;
 988	};
 989
 990	pcie2_dclk_div: pcie2_dclk_div@1b8 {
 991		#clock-cells = <0>;
 992		compatible = "ti,divider-clock";
 993		clocks = <&dpll_pcie_ref_m2_ck>;
 994		ti,max-div = <64>;
 995		reg = <0x01b8>;
 996		ti,index-power-of-two;
 997	};
 998
 999	pcie_dclk_div: pcie_dclk_div@1b4 {
1000		#clock-cells = <0>;
1001		compatible = "ti,divider-clock";
1002		clocks = <&apll_pcie_m2_ck>;
1003		ti,max-div = <64>;
1004		reg = <0x01b4>;
1005		ti,index-power-of-two;
1006	};
1007
1008	emu_dclk_div: emu_dclk_div@194 {
1009		#clock-cells = <0>;
1010		compatible = "ti,divider-clock";
1011		clocks = <&sys_clkin1>;
1012		ti,max-div = <64>;
1013		reg = <0x0194>;
1014		ti,index-power-of-two;
1015	};
1016
1017	secure_32k_dclk_div: secure_32k_dclk_div@1c4 {
1018		#clock-cells = <0>;
1019		compatible = "ti,divider-clock";
1020		clocks = <&secure_32k_clk_src_ck>;
1021		ti,max-div = <64>;
1022		reg = <0x01c4>;
1023		ti,index-power-of-two;
1024	};
1025
1026	clkoutmux0_clk_mux: clkoutmux0_clk_mux@158 {
1027		#clock-cells = <0>;
1028		compatible = "ti,mux-clock";
1029		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1030		reg = <0x0158>;
1031	};
1032
1033	clkoutmux1_clk_mux: clkoutmux1_clk_mux@15c {
1034		#clock-cells = <0>;
1035		compatible = "ti,mux-clock";
1036		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1037		reg = <0x015c>;
1038	};
1039
1040	clkoutmux2_clk_mux: clkoutmux2_clk_mux@160 {
1041		#clock-cells = <0>;
1042		compatible = "ti,mux-clock";
1043		clocks = <&sys_clk1_dclk_div>, <&sys_clk2_dclk_div>, <&per_abe_x1_dclk_div>, <&mpu_dclk_div>, <&dsp_gclk_div>, <&iva_dclk>, <&gpu_dclk>, <&core_dpll_out_dclk_div>, <&emif_phy_dclk_div>, <&gmac_250m_dclk_div>, <&video2_dclk_div>, <&video1_dclk_div>, <&hdmi_dclk_div>, <&func_96m_aon_dclk_div>, <&l3init_480m_dclk_div>, <&usb_otg_dclk_div>, <&sata_dclk_div>, <&pcie2_dclk_div>, <&pcie_dclk_div>, <&emu_dclk_div>, <&secure_32k_dclk_div>, <&eve_dclk_div>;
1044		reg = <0x0160>;
1045	};
1046
1047	custefuse_sys_gfclk_div: custefuse_sys_gfclk_div {
1048		#clock-cells = <0>;
1049		compatible = "fixed-factor-clock";
1050		clocks = <&sys_clkin1>;
1051		clock-mult = <1>;
1052		clock-div = <2>;
1053	};
1054
1055	eve_clk: eve_clk@180 {
1056		#clock-cells = <0>;
1057		compatible = "ti,mux-clock";
1058		clocks = <&dpll_eve_m2_ck>, <&dpll_dsp_m3x2_ck>;
1059		reg = <0x0180>;
1060	};
1061
1062	hdmi_dpll_clk_mux: hdmi_dpll_clk_mux@164 {
1063		#clock-cells = <0>;
1064		compatible = "ti,mux-clock";
1065		clocks = <&sys_clkin1>, <&sys_clkin2>;
1066		reg = <0x0164>;
1067	};
1068
1069	mlb_clk: mlb_clk@134 {
1070		#clock-cells = <0>;
1071		compatible = "ti,divider-clock";
1072		clocks = <&mlb_clkin_ck>;
1073		ti,max-div = <64>;
1074		reg = <0x0134>;
1075		ti,index-power-of-two;
1076	};
1077
1078	mlbp_clk: mlbp_clk@130 {
1079		#clock-cells = <0>;
1080		compatible = "ti,divider-clock";
1081		clocks = <&mlbp_clkin_ck>;
1082		ti,max-div = <64>;
1083		reg = <0x0130>;
1084		ti,index-power-of-two;
1085	};
1086
1087	per_abe_x1_gfclk2_div: per_abe_x1_gfclk2_div@138 {
1088		#clock-cells = <0>;
1089		compatible = "ti,divider-clock";
1090		clocks = <&dpll_abe_m2_ck>;
1091		ti,max-div = <64>;
1092		reg = <0x0138>;
1093		ti,index-power-of-two;
1094	};
1095
1096	timer_sys_clk_div: timer_sys_clk_div@144 {
1097		#clock-cells = <0>;
1098		compatible = "ti,divider-clock";
1099		clocks = <&sys_clkin1>;
1100		reg = <0x0144>;
1101		ti,max-div = <2>;
1102	};
1103
1104	video1_dpll_clk_mux: video1_dpll_clk_mux@168 {
1105		#clock-cells = <0>;
1106		compatible = "ti,mux-clock";
1107		clocks = <&sys_clkin1>, <&sys_clkin2>;
1108		reg = <0x0168>;
1109	};
1110
1111	video2_dpll_clk_mux: video2_dpll_clk_mux@16c {
1112		#clock-cells = <0>;
1113		compatible = "ti,mux-clock";
1114		clocks = <&sys_clkin1>, <&sys_clkin2>;
1115		reg = <0x016c>;
1116	};
1117
1118	wkupaon_iclk_mux: wkupaon_iclk_mux@108 {
1119		#clock-cells = <0>;
1120		compatible = "ti,mux-clock";
1121		clocks = <&sys_clkin1>, <&abe_lp_clk_div>;
1122		reg = <0x0108>;
1123	};
1124};
1125
1126&cm_core_clocks {
1127	dpll_pcie_ref_ck: dpll_pcie_ref_ck@200 {
1128		#clock-cells = <0>;
1129		compatible = "ti,omap4-dpll-clock";
1130		clocks = <&sys_clkin1>, <&sys_clkin1>;
1131		reg = <0x0200>, <0x0204>, <0x020c>, <0x0208>;
1132	};
1133
1134	dpll_pcie_ref_m2ldo_ck: dpll_pcie_ref_m2ldo_ck@210 {
1135		#clock-cells = <0>;
1136		compatible = "ti,divider-clock";
1137		clocks = <&dpll_pcie_ref_ck>;
1138		ti,max-div = <31>;
1139		ti,autoidle-shift = <8>;
1140		reg = <0x0210>;
1141		ti,index-starts-at-one;
1142		ti,invert-autoidle-bit;
1143	};
1144
1145	apll_pcie_in_clk_mux: apll_pcie_in_clk_mux@4ae06118 {
1146		compatible = "ti,mux-clock";
1147		clocks = <&dpll_pcie_ref_m2ldo_ck>, <&pciesref_acs_clk_ck>;
1148		#clock-cells = <0>;
1149		reg = <0x021c 0x4>;
1150		ti,bit-shift = <7>;
1151	};
1152
1153	apll_pcie_ck: apll_pcie_ck@21c {
1154		#clock-cells = <0>;
1155		compatible = "ti,dra7-apll-clock";
1156		clocks = <&apll_pcie_in_clk_mux>, <&dpll_pcie_ref_ck>;
1157		reg = <0x021c>, <0x0220>;
1158	};
1159
1160	optfclk_pciephy_div: optfclk_pciephy_div@4a00821c {
1161		compatible = "ti,divider-clock";
1162		clocks = <&apll_pcie_ck>;
1163		#clock-cells = <0>;
1164		reg = <0x021c>;
1165		ti,dividers = <2>, <1>;
1166		ti,bit-shift = <8>;
1167		ti,max-div = <2>;
1168	};
1169
1170	apll_pcie_clkvcoldo: apll_pcie_clkvcoldo {
1171		#clock-cells = <0>;
1172		compatible = "fixed-factor-clock";
1173		clocks = <&apll_pcie_ck>;
1174		clock-mult = <1>;
1175		clock-div = <1>;
1176	};
1177
1178	apll_pcie_clkvcoldo_div: apll_pcie_clkvcoldo_div {
1179		#clock-cells = <0>;
1180		compatible = "fixed-factor-clock";
1181		clocks = <&apll_pcie_ck>;
1182		clock-mult = <1>;
1183		clock-div = <1>;
1184	};
1185
1186	apll_pcie_m2_ck: apll_pcie_m2_ck {
1187		#clock-cells = <0>;
1188		compatible = "fixed-factor-clock";
1189		clocks = <&apll_pcie_ck>;
1190		clock-mult = <1>;
1191		clock-div = <1>;
1192	};
1193
1194	dpll_per_byp_mux: dpll_per_byp_mux@14c {
1195		#clock-cells = <0>;
1196		compatible = "ti,mux-clock";
1197		clocks = <&sys_clkin1>, <&per_dpll_hs_clk_div>;
1198		ti,bit-shift = <23>;
1199		reg = <0x014c>;
1200	};
1201
1202	dpll_per_ck: dpll_per_ck@140 {
1203		#clock-cells = <0>;
1204		compatible = "ti,omap4-dpll-clock";
1205		clocks = <&sys_clkin1>, <&dpll_per_byp_mux>;
1206		reg = <0x0140>, <0x0144>, <0x014c>, <0x0148>;
1207	};
1208
1209	dpll_per_m2_ck: dpll_per_m2_ck@150 {
1210		#clock-cells = <0>;
1211		compatible = "ti,divider-clock";
1212		clocks = <&dpll_per_ck>;
1213		ti,max-div = <31>;
1214		ti,autoidle-shift = <8>;
1215		reg = <0x0150>;
1216		ti,index-starts-at-one;
1217		ti,invert-autoidle-bit;
1218	};
1219
1220	func_96m_aon_dclk_div: func_96m_aon_dclk_div {
1221		#clock-cells = <0>;
1222		compatible = "fixed-factor-clock";
1223		clocks = <&dpll_per_m2_ck>;
1224		clock-mult = <1>;
1225		clock-div = <1>;
1226	};
1227
1228	dpll_usb_byp_mux: dpll_usb_byp_mux@18c {
1229		#clock-cells = <0>;
1230		compatible = "ti,mux-clock";
1231		clocks = <&sys_clkin1>, <&usb_dpll_hs_clk_div>;
1232		ti,bit-shift = <23>;
1233		reg = <0x018c>;
1234	};
1235
1236	dpll_usb_ck: dpll_usb_ck@180 {
1237		#clock-cells = <0>;
1238		compatible = "ti,omap4-dpll-j-type-clock";
1239		clocks = <&sys_clkin1>, <&dpll_usb_byp_mux>;
1240		reg = <0x0180>, <0x0184>, <0x018c>, <0x0188>;
1241	};
1242
1243	dpll_usb_m2_ck: dpll_usb_m2_ck@190 {
1244		#clock-cells = <0>;
1245		compatible = "ti,divider-clock";
1246		clocks = <&dpll_usb_ck>;
1247		ti,max-div = <127>;
1248		ti,autoidle-shift = <8>;
1249		reg = <0x0190>;
1250		ti,index-starts-at-one;
1251		ti,invert-autoidle-bit;
1252	};
1253
1254	dpll_pcie_ref_m2_ck: dpll_pcie_ref_m2_ck@210 {
1255		#clock-cells = <0>;
1256		compatible = "ti,divider-clock";
1257		clocks = <&dpll_pcie_ref_ck>;
1258		ti,max-div = <127>;
1259		ti,autoidle-shift = <8>;
1260		reg = <0x0210>;
1261		ti,index-starts-at-one;
1262		ti,invert-autoidle-bit;
1263	};
1264
1265	dpll_per_x2_ck: dpll_per_x2_ck {
1266		#clock-cells = <0>;
1267		compatible = "ti,omap4-dpll-x2-clock";
1268		clocks = <&dpll_per_ck>;
1269	};
1270
1271	dpll_per_h11x2_ck: dpll_per_h11x2_ck@158 {
1272		#clock-cells = <0>;
1273		compatible = "ti,divider-clock";
1274		clocks = <&dpll_per_x2_ck>;
1275		ti,max-div = <63>;
1276		ti,autoidle-shift = <8>;
1277		reg = <0x0158>;
1278		ti,index-starts-at-one;
1279		ti,invert-autoidle-bit;
1280	};
1281
1282	dpll_per_h12x2_ck: dpll_per_h12x2_ck@15c {
1283		#clock-cells = <0>;
1284		compatible = "ti,divider-clock";
1285		clocks = <&dpll_per_x2_ck>;
1286		ti,max-div = <63>;
1287		ti,autoidle-shift = <8>;
1288		reg = <0x015c>;
1289		ti,index-starts-at-one;
1290		ti,invert-autoidle-bit;
1291	};
1292
1293	dpll_per_h13x2_ck: dpll_per_h13x2_ck@160 {
1294		#clock-cells = <0>;
1295		compatible = "ti,divider-clock";
1296		clocks = <&dpll_per_x2_ck>;
1297		ti,max-div = <63>;
1298		ti,autoidle-shift = <8>;
1299		reg = <0x0160>;
1300		ti,index-starts-at-one;
1301		ti,invert-autoidle-bit;
1302	};
1303
1304	dpll_per_h14x2_ck: dpll_per_h14x2_ck@164 {
1305		#clock-cells = <0>;
1306		compatible = "ti,divider-clock";
1307		clocks = <&dpll_per_x2_ck>;
1308		ti,max-div = <63>;
1309		ti,autoidle-shift = <8>;
1310		reg = <0x0164>;
1311		ti,index-starts-at-one;
1312		ti,invert-autoidle-bit;
1313	};
1314
1315	dpll_per_m2x2_ck: dpll_per_m2x2_ck@150 {
1316		#clock-cells = <0>;
1317		compatible = "ti,divider-clock";
1318		clocks = <&dpll_per_x2_ck>;
1319		ti,max-div = <31>;
1320		ti,autoidle-shift = <8>;
1321		reg = <0x0150>;
1322		ti,index-starts-at-one;
1323		ti,invert-autoidle-bit;
1324	};
1325
1326	dpll_usb_clkdcoldo: dpll_usb_clkdcoldo {
1327		#clock-cells = <0>;
1328		compatible = "fixed-factor-clock";
1329		clocks = <&dpll_usb_ck>;
1330		clock-mult = <1>;
1331		clock-div = <1>;
1332	};
1333
1334	func_128m_clk: func_128m_clk {
1335		#clock-cells = <0>;
1336		compatible = "fixed-factor-clock";
1337		clocks = <&dpll_per_h11x2_ck>;
1338		clock-mult = <1>;
1339		clock-div = <2>;
1340	};
1341
1342	func_12m_fclk: func_12m_fclk {
1343		#clock-cells = <0>;
1344		compatible = "fixed-factor-clock";
1345		clocks = <&dpll_per_m2x2_ck>;
1346		clock-mult = <1>;
1347		clock-div = <16>;
1348	};
1349
1350	func_24m_clk: func_24m_clk {
1351		#clock-cells = <0>;
1352		compatible = "fixed-factor-clock";
1353		clocks = <&dpll_per_m2_ck>;
1354		clock-mult = <1>;
1355		clock-div = <4>;
1356	};
1357
1358	func_48m_fclk: func_48m_fclk {
1359		#clock-cells = <0>;
1360		compatible = "fixed-factor-clock";
1361		clocks = <&dpll_per_m2x2_ck>;
1362		clock-mult = <1>;
1363		clock-div = <4>;
1364	};
1365
1366	func_96m_fclk: func_96m_fclk {
1367		#clock-cells = <0>;
1368		compatible = "fixed-factor-clock";
1369		clocks = <&dpll_per_m2x2_ck>;
1370		clock-mult = <1>;
1371		clock-div = <2>;
1372	};
1373
1374	l3init_60m_fclk: l3init_60m_fclk@104 {
1375		#clock-cells = <0>;
1376		compatible = "ti,divider-clock";
1377		clocks = <&dpll_usb_m2_ck>;
1378		reg = <0x0104>;
1379		ti,dividers = <1>, <8>;
1380	};
1381
1382	clkout2_clk: clkout2_clk@6b0 {
1383		#clock-cells = <0>;
1384		compatible = "ti,gate-clock";
1385		clocks = <&clkoutmux2_clk_mux>;
1386		ti,bit-shift = <8>;
1387		reg = <0x06b0>;
1388	};
1389
1390	l3init_960m_gfclk: l3init_960m_gfclk@6c0 {
1391		#clock-cells = <0>;
1392		compatible = "ti,gate-clock";
1393		clocks = <&dpll_usb_clkdcoldo>;
1394		ti,bit-shift = <8>;
1395		reg = <0x06c0>;
1396	};
1397
1398	usb_phy1_always_on_clk32k: usb_phy1_always_on_clk32k@640 {
1399		#clock-cells = <0>;
1400		compatible = "ti,gate-clock";
1401		clocks = <&sys_32k_ck>;
1402		ti,bit-shift = <8>;
1403		reg = <0x0640>;
1404	};
1405
1406	usb_phy2_always_on_clk32k: usb_phy2_always_on_clk32k@688 {
1407		#clock-cells = <0>;
1408		compatible = "ti,gate-clock";
1409		clocks = <&sys_32k_ck>;
1410		ti,bit-shift = <8>;
1411		reg = <0x0688>;
1412	};
1413
1414	usb_phy3_always_on_clk32k: usb_phy3_always_on_clk32k@698 {
1415		#clock-cells = <0>;
1416		compatible = "ti,gate-clock";
1417		clocks = <&sys_32k_ck>;
1418		ti,bit-shift = <8>;
1419		reg = <0x0698>;
1420	};
1421
1422	gpu_core_gclk_mux: gpu_core_gclk_mux@1220 {
1423		#clock-cells = <0>;
1424		compatible = "ti,mux-clock";
1425		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1426		ti,bit-shift = <24>;
1427		reg = <0x1220>;
1428		assigned-clocks = <&gpu_core_gclk_mux>;
1429		assigned-clock-parents = <&dpll_gpu_m2_ck>;
1430	};
1431
1432	gpu_hyd_gclk_mux: gpu_hyd_gclk_mux@1220 {
1433		#clock-cells = <0>;
1434		compatible = "ti,mux-clock";
1435		clocks = <&dpll_core_h14x2_ck>, <&dpll_per_h14x2_ck>, <&dpll_gpu_m2_ck>;
1436		ti,bit-shift = <26>;
1437		reg = <0x1220>;
1438		assigned-clocks = <&gpu_hyd_gclk_mux>;
1439		assigned-clock-parents = <&dpll_gpu_m2_ck>;
1440	};
1441
1442	l3instr_ts_gclk_div: l3instr_ts_gclk_div@e50 {
1443		#clock-cells = <0>;
1444		compatible = "ti,divider-clock";
1445		clocks = <&wkupaon_iclk_mux>;
1446		ti,bit-shift = <24>;
1447		reg = <0x0e50>;
1448		ti,dividers = <8>, <16>, <32>;
1449	};
1450
1451	vip1_gclk_mux: vip1_gclk_mux@1020 {
1452		#clock-cells = <0>;
1453		compatible = "ti,mux-clock";
1454		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1455		ti,bit-shift = <24>;
1456		reg = <0x1020>;
1457	};
1458
1459	vip2_gclk_mux: vip2_gclk_mux@1028 {
1460		#clock-cells = <0>;
1461		compatible = "ti,mux-clock";
1462		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1463		ti,bit-shift = <24>;
1464		reg = <0x1028>;
1465	};
1466
1467	vip3_gclk_mux: vip3_gclk_mux@1030 {
1468		#clock-cells = <0>;
1469		compatible = "ti,mux-clock";
1470		clocks = <&l3_iclk_div>, <&dpll_core_h23x2_ck>;
1471		ti,bit-shift = <24>;
1472		reg = <0x1030>;
1473	};
1474};
1475
1476&cm_core_clockdomains {
1477	coreaon_clkdm: coreaon_clkdm {
1478		compatible = "ti,clockdomain";
1479		clocks = <&dpll_usb_ck>;
1480	};
1481};
1482
1483&scm_conf_clocks {
1484	dss_deshdcp_clk: dss_deshdcp_clk@558 {
1485		#clock-cells = <0>;
1486		compatible = "ti,gate-clock";
1487		clocks = <&l3_iclk_div>;
1488		ti,bit-shift = <0>;
1489		reg = <0x558>;
1490	};
1491
1492       ehrpwm0_tbclk: ehrpwm0_tbclk@558 {
1493		#clock-cells = <0>;
1494		compatible = "ti,gate-clock";
1495		clocks = <&l4_root_clk_div>;
1496		ti,bit-shift = <20>;
1497		reg = <0x0558>;
1498	};
1499
1500	ehrpwm1_tbclk: ehrpwm1_tbclk@558 {
1501		#clock-cells = <0>;
1502		compatible = "ti,gate-clock";
1503		clocks = <&l4_root_clk_div>;
1504		ti,bit-shift = <21>;
1505		reg = <0x0558>;
1506	};
1507
1508	ehrpwm2_tbclk: ehrpwm2_tbclk@558 {
1509		#clock-cells = <0>;
1510		compatible = "ti,gate-clock";
1511		clocks = <&l4_root_clk_div>;
1512		ti,bit-shift = <22>;
1513		reg = <0x0558>;
1514	};
1515
1516	sys_32k_ck: sys_32k_ck {
1517		#clock-cells = <0>;
1518		compatible = "ti,mux-clock";
1519		clocks = <&sys_clk32_crystal_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>, <&sys_clk32_pseudo_ck>;
1520		ti,bit-shift = <8>;
1521		reg = <0x6c4>;
1522	};
1523};
1524
1525&cm_core_aon {
1526	mpu_cm: mpu-cm@300 {
1527		compatible = "ti,omap4-cm";
1528		reg = <0x300 0x100>;
1529		#address-cells = <1>;
1530		#size-cells = <1>;
1531		ranges = <0 0x300 0x100>;
1532
1533		mpu_clkctrl: mpu-clkctrl@20 {
1534			compatible = "ti,clkctrl";
1535			reg = <0x20 0x4>;
1536			#clock-cells = <2>;
1537		};
1538
1539	};
1540
1541	dsp1_cm: dsp1-cm@400 {
1542		compatible = "ti,omap4-cm";
1543		reg = <0x400 0x100>;
1544		#address-cells = <1>;
1545		#size-cells = <1>;
1546		ranges = <0 0x400 0x100>;
1547
1548		dsp1_clkctrl: dsp1-clkctrl@20 {
1549			compatible = "ti,clkctrl";
1550			reg = <0x20 0x4>;
1551			#clock-cells = <2>;
1552		};
1553
1554	};
1555
1556	ipu_cm: ipu-cm@500 {
1557		compatible = "ti,omap4-cm";
1558		reg = <0x500 0x100>;
1559		#address-cells = <1>;
1560		#size-cells = <1>;
1561		ranges = <0 0x500 0x100>;
1562
1563		ipu1_clkctrl: ipu1-clkctrl@20 {
1564			compatible = "ti,clkctrl";
1565			reg = <0x20 0x4>;
1566			#clock-cells = <2>;
1567		};
1568
1569		ipu_clkctrl: ipu-clkctrl@50 {
1570			compatible = "ti,clkctrl";
1571			reg = <0x50 0x34>;
1572			#clock-cells = <2>;
1573		};
1574
1575	};
1576
1577	dsp2_cm: dsp2-cm@600 {
1578		compatible = "ti,omap4-cm";
1579		reg = <0x600 0x100>;
1580		#address-cells = <1>;
1581		#size-cells = <1>;
1582		ranges = <0 0x600 0x100>;
1583
1584		dsp2_clkctrl: dsp2-clkctrl@20 {
1585			compatible = "ti,clkctrl";
1586			reg = <0x20 0x4>;
1587			#clock-cells = <2>;
1588		};
1589
1590	};
1591
1592	rtc_cm: rtc-cm@700 {
1593		compatible = "ti,omap4-cm";
1594		reg = <0x700 0x100>;
1595		#address-cells = <1>;
1596		#size-cells = <1>;
1597		ranges = <0 0x700 0x100>;
1598
1599		rtc_clkctrl: rtc-clkctrl@20 {
1600			compatible = "ti,clkctrl";
1601			reg = <0x20 0x28>;
1602			#clock-cells = <2>;
1603		};
1604	};
1605
1606};
1607
1608&cm_core {
1609	coreaon_cm: coreaon-cm@600 {
1610		compatible = "ti,omap4-cm";
1611		reg = <0x600 0x100>;
1612		#address-cells = <1>;
1613		#size-cells = <1>;
1614		ranges = <0 0x600 0x100>;
1615
1616		coreaon_clkctrl: coreaon-clkctrl@20 {
1617			compatible = "ti,clkctrl";
1618			reg = <0x20 0x1c>;
1619			#clock-cells = <2>;
1620		};
1621	};
1622
1623	l3main1_cm: l3main1-cm@700 {
1624		compatible = "ti,omap4-cm";
1625		reg = <0x700 0x100>;
1626		#address-cells = <1>;
1627		#size-cells = <1>;
1628		ranges = <0 0x700 0x100>;
1629
1630		l3main1_clkctrl: l3main1-clkctrl@20 {
1631			compatible = "ti,clkctrl";
1632			reg = <0x20 0x74>;
1633			#clock-cells = <2>;
1634		};
1635
1636	};
1637
1638	ipu2_cm: ipu2-cm@900 {
1639		compatible = "ti,omap4-cm";
1640		reg = <0x900 0x100>;
1641		#address-cells = <1>;
1642		#size-cells = <1>;
1643		ranges = <0 0x900 0x100>;
1644
1645		ipu2_clkctrl: ipu2-clkctrl@20 {
1646			compatible = "ti,clkctrl";
1647			reg = <0x20 0x4>;
1648			#clock-cells = <2>;
1649		};
1650
1651	};
1652
1653	dma_cm: dma-cm@a00 {
1654		compatible = "ti,omap4-cm";
1655		reg = <0xa00 0x100>;
1656		#address-cells = <1>;
1657		#size-cells = <1>;
1658		ranges = <0 0xa00 0x100>;
1659
1660		dma_clkctrl: dma-clkctrl@20 {
1661			compatible = "ti,clkctrl";
1662			reg = <0x20 0x4>;
1663			#clock-cells = <2>;
1664		};
1665	};
1666
1667	emif_cm: emif-cm@b00 {
1668		compatible = "ti,omap4-cm";
1669		reg = <0xb00 0x100>;
1670		#address-cells = <1>;
1671		#size-cells = <1>;
1672		ranges = <0 0xb00 0x100>;
1673
1674		emif_clkctrl: emif-clkctrl@20 {
1675			compatible = "ti,clkctrl";
1676			reg = <0x20 0x4>;
1677			#clock-cells = <2>;
1678		};
1679	};
1680
1681	atl_cm: atl-cm@c00 {
1682		compatible = "ti,omap4-cm";
1683		reg = <0xc00 0x100>;
1684		#address-cells = <1>;
1685		#size-cells = <1>;
1686		ranges = <0 0xc00 0x100>;
1687
1688		atl_clkctrl: atl-clkctrl@0 {
1689			compatible = "ti,clkctrl";
1690			reg = <0x0 0x4>;
1691			#clock-cells = <2>;
1692		};
1693	};
1694
1695	l4cfg_cm: l4cfg-cm@d00 {
1696		compatible = "ti,omap4-cm";
1697		reg = <0xd00 0x100>;
1698		#address-cells = <1>;
1699		#size-cells = <1>;
1700		ranges = <0 0xd00 0x100>;
1701
1702		l4cfg_clkctrl: l4cfg-clkctrl@20 {
1703			compatible = "ti,clkctrl";
1704			reg = <0x20 0x84>;
1705			#clock-cells = <2>;
1706		};
1707	};
1708
1709	l3instr_cm: l3instr-cm@e00 {
1710		compatible = "ti,omap4-cm";
1711		reg = <0xe00 0x100>;
1712		#address-cells = <1>;
1713		#size-cells = <1>;
1714		ranges = <0 0xe00 0x100>;
1715
1716		l3instr_clkctrl: l3instr-clkctrl@20 {
1717			compatible = "ti,clkctrl";
1718			reg = <0x20 0xc>;
1719			#clock-cells = <2>;
1720		};
1721	};
1722
1723	dss_cm: dss-cm@1100 {
1724		compatible = "ti,omap4-cm";
1725		reg = <0x1100 0x100>;
1726		#address-cells = <1>;
1727		#size-cells = <1>;
1728		ranges = <0 0x1100 0x100>;
1729
1730		dss_clkctrl: dss-clkctrl@20 {
1731			compatible = "ti,clkctrl";
1732			reg = <0x20 0x14>;
1733			#clock-cells = <2>;
1734		};
1735	};
1736
1737	l3init_cm: l3init-cm@1300 {
1738		compatible = "ti,omap4-cm";
1739		reg = <0x1300 0x100>;
1740		#address-cells = <1>;
1741		#size-cells = <1>;
1742		ranges = <0 0x1300 0x100>;
1743
1744		l3init_clkctrl: l3init-clkctrl@20 {
1745			compatible = "ti,clkctrl";
1746			reg = <0x20 0x6c>, <0xe0 0x14>;
1747			#clock-cells = <2>;
1748		};
1749
1750		pcie_clkctrl: pcie-clkctrl@b0 {
1751			compatible = "ti,clkctrl";
1752			reg = <0xb0 0xc>;
1753			#clock-cells = <2>;
1754		};
1755
1756		gmac_clkctrl: gmac-clkctrl@d0 {
1757			compatible = "ti,clkctrl";
1758			reg = <0xd0 0x4>;
1759			#clock-cells = <2>;
1760		};
1761
1762	};
1763
1764	l4per_cm: l4per-cm@1700 {
1765		compatible = "ti,omap4-cm";
1766		reg = <0x1700 0x300>;
1767		#address-cells = <1>;
1768		#size-cells = <1>;
1769		ranges = <0 0x1700 0x300>;
1770
1771		l4per_clkctrl: l4per-clkctrl@28 {
1772			compatible = "ti,clkctrl";
1773			reg = <0x28 0x64>, <0xa0 0x24>, <0xf0 0x3c>, <0x140 0x1c>, <0x170 0x4>;
1774			#clock-cells = <2>;
1775
1776			assigned-clocks = <&l4per2_clkctrl DRA7_L4PER2_MCASP3_CLKCTRL 24>;
1777			assigned-clock-parents = <&abe_24m_fclk>;
1778		};
1779
1780		l4sec_clkctrl: l4sec-clkctrl@1a0 {
1781			compatible = "ti,clkctrl";
1782			reg = <0x1a0 0x2c>;
1783			#clock-cells = <2>;
1784		};
1785
1786		l4per2_clkctrl: l4per2-clkctrl@c {
1787			compatible = "ti,clkctrl";
1788			reg = <0xc 0x4>, <0x18 0xc>, <0x90 0xc>, <0xc4 0x4>, <0x138 0x4>, <0x160 0xc>, <0x178 0x24>, <0x1d0 0x3c>;
1789			#clock-cells = <2>;
1790		};
1791
1792		l4per3_clkctrl: l4per3-clkctrl@14 {
1793			compatible = "ti,clkctrl";
1794			reg = <0x14 0x4>, <0xc8 0x14>, <0x130 0x4>;
1795			#clock-cells = <2>;
1796		};
1797	};
1798
1799};
1800
1801&prm {
1802	wkupaon_cm: wkupaon-cm@1800 {
1803		compatible = "ti,omap4-cm";
1804		reg = <0x1800 0x100>;
1805		#address-cells = <1>;
1806		#size-cells = <1>;
1807		ranges = <0 0x1800 0x100>;
1808
1809		wkupaon_clkctrl: wkupaon-clkctrl@20 {
1810			compatible = "ti,clkctrl";
1811			reg = <0x20 0x6c>;
1812			#clock-cells = <2>;
1813		};
1814	};
1815};